1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
13
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-pll.h"
17 #include "clk-rcg.h"
18 #include "clk-regmap.h"
19 #include "clk-regmap-divider.h"
20 #include "clk-regmap-mux.h"
21 #include "common.h"
22 #include "gdsc.h"
23 #include "reset.h"
24
25 enum {
26 DT_BI_TCXO,
27 DT_GPLL0,
28 DT_DSI0_PHY_PLL_OUT_BYTECLK,
29 DT_DSI0_PHY_PLL_OUT_DSICLK,
30 DT_DSI1_PHY_PLL_OUT_DSICLK,
31 DT_DP_PHY_PLL_LINK_CLK,
32 DT_DP_PHY_PLL_VCO_DIV_CLK,
33 };
34
35 enum {
36 P_BI_TCXO,
37 P_DISP_CC_PLL0_OUT_MAIN,
38 P_DP_PHY_PLL_LINK_CLK,
39 P_DP_PHY_PLL_VCO_DIV_CLK,
40 P_DSI0_PHY_PLL_OUT_BYTECLK,
41 P_DSI0_PHY_PLL_OUT_DSICLK,
42 P_DSI1_PHY_PLL_OUT_DSICLK,
43 P_GPLL0_OUT_MAIN,
44 };
45
46 static const struct pll_vco disp_cc_pll_vco[] = {
47 { 500000000, 1000000000, 2 },
48 };
49
50 /* 576MHz configuration VCO - 2 */
51 static struct alpha_pll_config disp_cc_pll0_config = {
52 .l = 0x1e,
53 .vco_val = BIT(21),
54 .vco_mask = GENMASK(21, 20),
55 .main_output_mask = BIT(0),
56 .config_ctl_val = 0x4001055b,
57 .test_ctl_hi_val = 0x1,
58 .test_ctl_hi_mask = 0x1,
59 };
60
61 static struct clk_alpha_pll disp_cc_pll0 = {
62 .offset = 0x0,
63 .config = &disp_cc_pll0_config,
64 .vco_table = disp_cc_pll_vco,
65 .num_vco = ARRAY_SIZE(disp_cc_pll_vco),
66 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
67 .clkr = {
68 .hw.init = &(const struct clk_init_data) {
69 .name = "disp_cc_pll0",
70 .parent_data = &(const struct clk_parent_data) {
71 .index = DT_BI_TCXO,
72 },
73 .num_parents = 1,
74 .ops = &clk_alpha_pll_slew_ops,
75 },
76 },
77 };
78
79 static const struct parent_map disp_cc_parent_map_0[] = {
80 { P_BI_TCXO, 0 },
81 { P_DP_PHY_PLL_LINK_CLK, 1 },
82 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
83 };
84
85 static const struct clk_parent_data disp_cc_parent_data_0[] = {
86 { .index = DT_BI_TCXO },
87 { .index = DT_DP_PHY_PLL_LINK_CLK },
88 { .index = DT_DP_PHY_PLL_VCO_DIV_CLK },
89 };
90
91 static const struct parent_map disp_cc_parent_map_1[] = {
92 { P_BI_TCXO, 0 },
93 };
94
95 static const struct clk_parent_data disp_cc_parent_data_1[] = {
96 { .index = DT_BI_TCXO },
97 };
98
99 static const struct parent_map disp_cc_parent_map_2[] = {
100 { P_BI_TCXO, 0 },
101 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
102 };
103
104 static const struct clk_parent_data disp_cc_parent_data_2[] = {
105 { .index = DT_BI_TCXO },
106 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
107 };
108
109 static const struct parent_map disp_cc_parent_map_3[] = {
110 { P_BI_TCXO, 0 },
111 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
112 { P_GPLL0_OUT_MAIN, 4 },
113 };
114
115 static const struct clk_parent_data disp_cc_parent_data_3[] = {
116 { .index = DT_BI_TCXO },
117 { .hw = &disp_cc_pll0.clkr.hw },
118 { .index = DT_GPLL0 },
119 };
120
121 static const struct parent_map disp_cc_parent_map_4[] = {
122 { P_BI_TCXO, 0 },
123 { P_GPLL0_OUT_MAIN, 4 },
124 };
125
126 static const struct clk_parent_data disp_cc_parent_data_4[] = {
127 { .index = DT_BI_TCXO },
128 { .index = DT_GPLL0 },
129 };
130
131 static const struct parent_map disp_cc_parent_map_5[] = {
132 { P_BI_TCXO, 0 },
133 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
134 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
135 };
136
137 static const struct clk_parent_data disp_cc_parent_data_5[] = {
138 { .index = DT_BI_TCXO },
139 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
140 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
141 };
142
143 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
144 F(19200000, P_BI_TCXO, 1, 0, 0),
145 F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
146 F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
147 { }
148 };
149
150 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
151 .cmd_rcgr = 0x2170,
152 .mnd_width = 0,
153 .hid_width = 5,
154 .parent_map = disp_cc_parent_map_4,
155 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
156 .clkr.hw.init = &(const struct clk_init_data) {
157 .name = "disp_cc_mdss_ahb_clk_src",
158 .parent_data = disp_cc_parent_data_4,
159 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
160 .ops = &clk_rcg2_shared_ops,
161 },
162 };
163
164 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
165 .cmd_rcgr = 0x20c0,
166 .mnd_width = 0,
167 .hid_width = 5,
168 .parent_map = disp_cc_parent_map_2,
169 .clkr.hw.init = &(const struct clk_init_data) {
170 .name = "disp_cc_mdss_byte0_clk_src",
171 .parent_data = disp_cc_parent_data_2,
172 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
173 .flags = CLK_SET_RATE_PARENT,
174 .ops = &clk_byte2_ops,
175 },
176 };
177
178 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] = {
179 F(19200000, P_BI_TCXO, 1, 0, 0),
180 { }
181 };
182
183 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
184 .cmd_rcgr = 0x2158,
185 .mnd_width = 0,
186 .hid_width = 5,
187 .parent_map = disp_cc_parent_map_1,
188 .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
189 .clkr.hw.init = &(struct clk_init_data){
190 .name = "disp_cc_mdss_dp_aux_clk_src",
191 .parent_data = disp_cc_parent_data_1,
192 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
193 .ops = &clk_rcg2_shared_ops,
194 },
195 };
196
197 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
198 .cmd_rcgr = 0x2110,
199 .mnd_width = 0,
200 .hid_width = 5,
201 .parent_map = disp_cc_parent_map_0,
202 .clkr.hw.init = &(const struct clk_init_data) {
203 .name = "disp_cc_mdss_dp_crypto_clk_src",
204 .parent_data = disp_cc_parent_data_0,
205 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
206 .ops = &clk_byte2_ops,
207 },
208 };
209
210 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
211 .cmd_rcgr = 0x20f4,
212 .mnd_width = 0,
213 .hid_width = 5,
214 .parent_map = disp_cc_parent_map_0,
215 .clkr.hw.init = &(const struct clk_init_data) {
216 .name = "disp_cc_mdss_dp_link_clk_src",
217 .parent_data = disp_cc_parent_data_0,
218 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
219 .flags = CLK_SET_RATE_PARENT,
220 .ops = &clk_byte2_ops,
221 },
222 };
223
224 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
225 .cmd_rcgr = 0x2140,
226 .mnd_width = 16,
227 .hid_width = 5,
228 .parent_map = disp_cc_parent_map_0,
229 .clkr.hw.init = &(const struct clk_init_data) {
230 .name = "disp_cc_mdss_dp_pixel1_clk_src",
231 .parent_data = disp_cc_parent_data_0,
232 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
233 .flags = CLK_SET_RATE_PARENT,
234 .ops = &clk_dp_ops,
235 },
236 };
237
238 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
239 .cmd_rcgr = 0x2128,
240 .mnd_width = 16,
241 .hid_width = 5,
242 .parent_map = disp_cc_parent_map_0,
243 .clkr.hw.init = &(const struct clk_init_data) {
244 .name = "disp_cc_mdss_dp_pixel_clk_src",
245 .parent_data = disp_cc_parent_data_0,
246 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
247 .flags = CLK_SET_RATE_PARENT,
248 .ops = &clk_dp_ops,
249 },
250 };
251
252 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
253 .cmd_rcgr = 0x20dc,
254 .mnd_width = 0,
255 .hid_width = 5,
256 .parent_map = disp_cc_parent_map_2,
257 .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
258 .clkr.hw.init = &(struct clk_init_data){
259 .name = "disp_cc_mdss_esc0_clk_src",
260 .parent_data = disp_cc_parent_data_2,
261 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
262 .ops = &clk_rcg2_ops,
263 },
264 };
265
266 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
267 F(19200000, P_BI_TCXO, 1, 0, 0),
268 F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
269 F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
270 F(307000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
271 { }
272 };
273
274 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
275 .cmd_rcgr = 0x2078,
276 .mnd_width = 0,
277 .hid_width = 5,
278 .parent_map = disp_cc_parent_map_3,
279 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
280 .clkr.hw.init = &(const struct clk_init_data) {
281 .name = "disp_cc_mdss_mdp_clk_src",
282 .parent_data = disp_cc_parent_data_3,
283 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
284 .flags = CLK_SET_RATE_PARENT,
285 .ops = &clk_rcg2_shared_ops,
286 },
287 };
288
289 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
290 .cmd_rcgr = 0x2060,
291 .mnd_width = 8,
292 .hid_width = 5,
293 .parent_map = disp_cc_parent_map_5,
294 .clkr.hw.init = &(const struct clk_init_data) {
295 .name = "disp_cc_mdss_pclk0_clk_src",
296 .parent_data = disp_cc_parent_data_5,
297 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
298 .flags = CLK_SET_RATE_PARENT,
299 .ops = &clk_pixel_ops,
300 },
301 };
302
303 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
304 .cmd_rcgr = 0x2090,
305 .mnd_width = 0,
306 .hid_width = 5,
307 .parent_map = disp_cc_parent_map_3,
308 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
309 .clkr.hw.init = &(const struct clk_init_data) {
310 .name = "disp_cc_mdss_rot_clk_src",
311 .parent_data = disp_cc_parent_data_3,
312 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
313 .flags = CLK_SET_RATE_PARENT,
314 .ops = &clk_rcg2_shared_ops,
315 },
316 };
317
318 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
319 .cmd_rcgr = 0x20a8,
320 .mnd_width = 0,
321 .hid_width = 5,
322 .parent_map = disp_cc_parent_map_1,
323 .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
324 .clkr.hw.init = &(struct clk_init_data){
325 .name = "disp_cc_mdss_vsync_clk_src",
326 .parent_data = disp_cc_parent_data_1,
327 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
328 .ops = &clk_rcg2_shared_ops,
329 },
330 };
331
332 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
333 .reg = 0x20d8,
334 .shift = 0,
335 .width = 2,
336 .clkr.hw.init = &(const struct clk_init_data) {
337 .name = "disp_cc_mdss_byte0_div_clk_src",
338 .parent_hws = (const struct clk_hw*[]) {
339 &disp_cc_mdss_byte0_clk_src.clkr.hw,
340 },
341 .num_parents = 1,
342 .ops = &clk_regmap_div_ro_ops,
343 },
344 };
345
346 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
347 .reg = 0x210c,
348 .shift = 0,
349 .width = 2,
350 .clkr.hw.init = &(const struct clk_init_data) {
351 .name = "disp_cc_mdss_dp_link_div_clk_src",
352 .parent_hws = (const struct clk_hw*[]) {
353 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
354 },
355 .num_parents = 1,
356 .flags = CLK_SET_RATE_PARENT,
357 .ops = &clk_regmap_div_ro_ops,
358 },
359 };
360
361 static struct clk_branch disp_cc_mdss_ahb_clk = {
362 .halt_reg = 0x2048,
363 .halt_check = BRANCH_HALT,
364 .clkr = {
365 .enable_reg = 0x2048,
366 .enable_mask = BIT(0),
367 .hw.init = &(const struct clk_init_data) {
368 .name = "disp_cc_mdss_ahb_clk",
369 .parent_hws = (const struct clk_hw*[]) {
370 &disp_cc_mdss_ahb_clk_src.clkr.hw,
371 },
372 .num_parents = 1,
373 .flags = CLK_SET_RATE_PARENT,
374 .ops = &clk_branch2_ops,
375 },
376 },
377 };
378
379 static struct clk_branch disp_cc_mdss_byte0_clk = {
380 .halt_reg = 0x2024,
381 .halt_check = BRANCH_HALT,
382 .clkr = {
383 .enable_reg = 0x2024,
384 .enable_mask = BIT(0),
385 .hw.init = &(const struct clk_init_data) {
386 .name = "disp_cc_mdss_byte0_clk",
387 .parent_hws = (const struct clk_hw*[]) {
388 &disp_cc_mdss_byte0_clk_src.clkr.hw,
389 },
390 .num_parents = 1,
391 .flags = CLK_SET_RATE_PARENT,
392 .ops = &clk_branch2_ops,
393 },
394 },
395 };
396
397 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
398 .halt_reg = 0x2028,
399 .halt_check = BRANCH_HALT,
400 .clkr = {
401 .enable_reg = 0x2028,
402 .enable_mask = BIT(0),
403 .hw.init = &(const struct clk_init_data) {
404 .name = "disp_cc_mdss_byte0_intf_clk",
405 .parent_hws = (const struct clk_hw*[]) {
406 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
407 },
408 .num_parents = 1,
409 .flags = CLK_SET_RATE_PARENT,
410 .ops = &clk_branch2_ops,
411 },
412 },
413 };
414
415 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
416 .halt_reg = 0x2044,
417 .halt_check = BRANCH_HALT,
418 .clkr = {
419 .enable_reg = 0x2044,
420 .enable_mask = BIT(0),
421 .hw.init = &(const struct clk_init_data) {
422 .name = "disp_cc_mdss_dp_aux_clk",
423 .parent_hws = (const struct clk_hw*[]) {
424 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
425 },
426 .num_parents = 1,
427 .flags = CLK_SET_RATE_PARENT,
428 .ops = &clk_branch2_ops,
429 },
430 },
431 };
432
433 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
434 .halt_reg = 0x2038,
435 .halt_check = BRANCH_HALT,
436 .clkr = {
437 .enable_reg = 0x2038,
438 .enable_mask = BIT(0),
439 .hw.init = &(const struct clk_init_data) {
440 .name = "disp_cc_mdss_dp_crypto_clk",
441 .parent_hws = (const struct clk_hw*[]) {
442 &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
443 },
444 .num_parents = 1,
445 .flags = CLK_SET_RATE_PARENT,
446 .ops = &clk_branch2_ops,
447 },
448 },
449 };
450
451 static struct clk_branch disp_cc_mdss_dp_link_clk = {
452 .halt_reg = 0x2030,
453 .halt_check = BRANCH_HALT,
454 .clkr = {
455 .enable_reg = 0x2030,
456 .enable_mask = BIT(0),
457 .hw.init = &(const struct clk_init_data) {
458 .name = "disp_cc_mdss_dp_link_clk",
459 .parent_hws = (const struct clk_hw*[]) {
460 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
461 },
462 .num_parents = 1,
463 .flags = CLK_SET_RATE_PARENT,
464 .ops = &clk_branch2_ops,
465 },
466 },
467 };
468
469 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
470 .halt_reg = 0x2034,
471 .halt_check = BRANCH_HALT,
472 .clkr = {
473 .enable_reg = 0x2034,
474 .enable_mask = BIT(0),
475 .hw.init = &(const struct clk_init_data) {
476 .name = "disp_cc_mdss_dp_link_intf_clk",
477 .parent_hws = (const struct clk_hw*[]) {
478 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
479 },
480 .num_parents = 1,
481 .flags = CLK_SET_RATE_PARENT,
482 .ops = &clk_branch2_ops,
483 },
484 },
485 };
486
487 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
488 .halt_reg = 0x2040,
489 .halt_check = BRANCH_HALT,
490 .clkr = {
491 .enable_reg = 0x2040,
492 .enable_mask = BIT(0),
493 .hw.init = &(const struct clk_init_data) {
494 .name = "disp_cc_mdss_dp_pixel1_clk",
495 .parent_hws = (const struct clk_hw*[]) {
496 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
497 },
498 .num_parents = 1,
499 .flags = CLK_SET_RATE_PARENT,
500 .ops = &clk_branch2_ops,
501 },
502 },
503 };
504
505 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
506 .halt_reg = 0x203c,
507 .halt_check = BRANCH_HALT,
508 .clkr = {
509 .enable_reg = 0x203c,
510 .enable_mask = BIT(0),
511 .hw.init = &(const struct clk_init_data) {
512 .name = "disp_cc_mdss_dp_pixel_clk",
513 .parent_hws = (const struct clk_hw*[]) {
514 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
515 },
516 .num_parents = 1,
517 .flags = CLK_SET_RATE_PARENT,
518 .ops = &clk_branch2_ops,
519 },
520 },
521 };
522
523 static struct clk_branch disp_cc_mdss_esc0_clk = {
524 .halt_reg = 0x202c,
525 .halt_check = BRANCH_HALT,
526 .clkr = {
527 .enable_reg = 0x202c,
528 .enable_mask = BIT(0),
529 .hw.init = &(const struct clk_init_data) {
530 .name = "disp_cc_mdss_esc0_clk",
531 .parent_hws = (const struct clk_hw*[]) {
532 &disp_cc_mdss_esc0_clk_src.clkr.hw,
533 },
534 .num_parents = 1,
535 .flags = CLK_SET_RATE_PARENT,
536 .ops = &clk_branch2_ops,
537 },
538 },
539 };
540
541 static struct clk_branch disp_cc_mdss_mdp_clk = {
542 .halt_reg = 0x2008,
543 .halt_check = BRANCH_HALT,
544 .clkr = {
545 .enable_reg = 0x2008,
546 .enable_mask = BIT(0),
547 .hw.init = &(const struct clk_init_data) {
548 .name = "disp_cc_mdss_mdp_clk",
549 .parent_hws = (const struct clk_hw*[]) {
550 &disp_cc_mdss_mdp_clk_src.clkr.hw,
551 },
552 .num_parents = 1,
553 .flags = CLK_SET_RATE_PARENT,
554 .ops = &clk_branch2_ops,
555 },
556 },
557 };
558
559 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
560 .halt_reg = 0x2018,
561 .halt_check = BRANCH_HALT,
562 .clkr = {
563 .enable_reg = 0x2018,
564 .enable_mask = BIT(0),
565 .hw.init = &(const struct clk_init_data) {
566 .name = "disp_cc_mdss_mdp_lut_clk",
567 .parent_hws = (const struct clk_hw*[]) {
568 &disp_cc_mdss_mdp_clk_src.clkr.hw,
569 },
570 .num_parents = 1,
571 .flags = CLK_SET_RATE_PARENT,
572 .ops = &clk_branch2_ops,
573 },
574 },
575 };
576
577 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
578 .halt_reg = 0x4004,
579 .halt_check = BRANCH_HALT_VOTED,
580 .clkr = {
581 .enable_reg = 0x4004,
582 .enable_mask = BIT(0),
583 .hw.init = &(const struct clk_init_data) {
584 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
585 .parent_hws = (const struct clk_hw*[]) {
586 &disp_cc_mdss_ahb_clk_src.clkr.hw,
587 },
588 .num_parents = 1,
589 .flags = CLK_SET_RATE_PARENT,
590 .ops = &clk_branch2_ops,
591 },
592 },
593 };
594
595 static struct clk_branch disp_cc_mdss_pclk0_clk = {
596 .halt_reg = 0x2004,
597 .halt_check = BRANCH_HALT,
598 .clkr = {
599 .enable_reg = 0x2004,
600 .enable_mask = BIT(0),
601 .hw.init = &(const struct clk_init_data) {
602 .name = "disp_cc_mdss_pclk0_clk",
603 .parent_hws = (const struct clk_hw*[]) {
604 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
605 },
606 .num_parents = 1,
607 .flags = CLK_SET_RATE_PARENT,
608 .ops = &clk_branch2_ops,
609 },
610 },
611 };
612
613 static struct clk_branch disp_cc_mdss_rot_clk = {
614 .halt_reg = 0x2010,
615 .halt_check = BRANCH_HALT,
616 .clkr = {
617 .enable_reg = 0x2010,
618 .enable_mask = BIT(0),
619 .hw.init = &(const struct clk_init_data) {
620 .name = "disp_cc_mdss_rot_clk",
621 .parent_hws = (const struct clk_hw*[]) {
622 &disp_cc_mdss_rot_clk_src.clkr.hw,
623 },
624 .num_parents = 1,
625 .flags = CLK_SET_RATE_PARENT,
626 .ops = &clk_branch2_ops,
627 },
628 },
629 };
630
631 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
632 .halt_reg = 0x400c,
633 .halt_check = BRANCH_HALT,
634 .clkr = {
635 .enable_reg = 0x400c,
636 .enable_mask = BIT(0),
637 .hw.init = &(const struct clk_init_data) {
638 .name = "disp_cc_mdss_rscc_ahb_clk",
639 .parent_hws = (const struct clk_hw*[]) {
640 &disp_cc_mdss_ahb_clk_src.clkr.hw,
641 },
642 .num_parents = 1,
643 .flags = CLK_SET_RATE_PARENT,
644 .ops = &clk_branch2_ops,
645 },
646 },
647 };
648
649 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
650 .halt_reg = 0x4008,
651 .halt_check = BRANCH_HALT,
652 .clkr = {
653 .enable_reg = 0x4008,
654 .enable_mask = BIT(0),
655 .hw.init = &(const struct clk_init_data) {
656 .name = "disp_cc_mdss_rscc_vsync_clk",
657 .parent_hws = (const struct clk_hw*[]) {
658 &disp_cc_mdss_vsync_clk_src.clkr.hw,
659 },
660 .num_parents = 1,
661 .flags = CLK_SET_RATE_PARENT,
662 .ops = &clk_branch2_ops,
663 },
664 },
665 };
666
667 static struct clk_branch disp_cc_mdss_vsync_clk = {
668 .halt_reg = 0x2020,
669 .halt_check = BRANCH_HALT,
670 .clkr = {
671 .enable_reg = 0x2020,
672 .enable_mask = BIT(0),
673 .hw.init = &(const struct clk_init_data) {
674 .name = "disp_cc_mdss_vsync_clk",
675 .parent_hws = (const struct clk_hw*[]) {
676 &disp_cc_mdss_vsync_clk_src.clkr.hw,
677 },
678 .num_parents = 1,
679 .flags = CLK_SET_RATE_PARENT,
680 .ops = &clk_branch2_ops,
681 },
682 },
683 };
684
685 static struct gdsc mdss_core_gdsc = {
686 .gdscr = 0x3000,
687 .en_rest_wait_val = 0x2,
688 .en_few_wait_val = 0x2,
689 .clk_dis_wait_val = 0xf,
690 .pd = {
691 .name = "mdss_core_gdsc",
692 },
693 .pwrsts = PWRSTS_OFF_ON,
694 .flags = HW_CTRL | POLL_CFG_GDSCR,
695 };
696
697 static struct clk_regmap *disp_cc_qcs615_clocks[] = {
698 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
699 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
700 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
701 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
702 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
703 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
704 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
705 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
706 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
707 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
708 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
709 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
710 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
711 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
712 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
713 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
714 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
715 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
716 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
717 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
718 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
719 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
720 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
721 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
722 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
723 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
724 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
725 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
726 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
727 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
728 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
729 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
730 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
731 };
732
733 static struct gdsc *disp_cc_qcs615_gdscs[] = {
734 [MDSS_CORE_GDSC] = &mdss_core_gdsc,
735 };
736
737 static struct clk_alpha_pll *disp_cc_qcs615_plls[] = {
738 &disp_cc_pll0,
739 };
740
741 static const u32 disp_cc_qcs615_critical_cbcrs[] = {
742 0x6054, /* DISP_CC_XO_CLK */
743 };
744
745 static const struct regmap_config disp_cc_qcs615_regmap_config = {
746 .reg_bits = 32,
747 .reg_stride = 4,
748 .val_bits = 32,
749 .max_register = 0x10000,
750 .fast_io = true,
751 };
752
753 static const struct qcom_cc_driver_data disp_cc_qcs615_driver_data = {
754 .alpha_plls = disp_cc_qcs615_plls,
755 .num_alpha_plls = ARRAY_SIZE(disp_cc_qcs615_plls),
756 .clk_cbcrs = disp_cc_qcs615_critical_cbcrs,
757 .num_clk_cbcrs = ARRAY_SIZE(disp_cc_qcs615_critical_cbcrs),
758 };
759
760 static const struct qcom_cc_desc disp_cc_qcs615_desc = {
761 .config = &disp_cc_qcs615_regmap_config,
762 .clks = disp_cc_qcs615_clocks,
763 .num_clks = ARRAY_SIZE(disp_cc_qcs615_clocks),
764 .gdscs = disp_cc_qcs615_gdscs,
765 .num_gdscs = ARRAY_SIZE(disp_cc_qcs615_gdscs),
766 .driver_data = &disp_cc_qcs615_driver_data,
767 };
768
769 static const struct of_device_id disp_cc_qcs615_match_table[] = {
770 { .compatible = "qcom,qcs615-dispcc" },
771 { }
772 };
773 MODULE_DEVICE_TABLE(of, disp_cc_qcs615_match_table);
774
disp_cc_qcs615_probe(struct platform_device * pdev)775 static int disp_cc_qcs615_probe(struct platform_device *pdev)
776 {
777 return qcom_cc_probe(pdev, &disp_cc_qcs615_desc);
778 }
779
780 static struct platform_driver disp_cc_qcs615_driver = {
781 .probe = disp_cc_qcs615_probe,
782 .driver = {
783 .name = "dispcc-qcs615",
784 .of_match_table = disp_cc_qcs615_match_table,
785 },
786 };
787
788 module_platform_driver(disp_cc_qcs615_driver);
789
790 MODULE_DESCRIPTION("QTI DISPCC QCS615 Driver");
791 MODULE_LICENSE("GPL");
792