1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/cleanup.h> 5 #include <linux/clk.h> 6 #include <linux/clk-provider.h> 7 #include <linux/interrupt.h> 8 #include <linux/kernel.h> 9 #include <linux/mfd/wcd934x/registers.h> 10 #include <linux/mfd/wcd934x/wcd934x.h> 11 #include <linux/module.h> 12 #include <linux/mutex.h> 13 #include <linux/of_clk.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/slimbus.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <sound/tlv.h> 23 #include "wcd-clsh-v2.h" 24 #include "wcd-common.h" 25 #include "wcd-mbhc-v2.h" 26 27 #include <dt-bindings/sound/qcom,wcd934x.h> 28 29 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 30 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 31 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 32 /* Fractional Rates */ 33 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 34 SNDRV_PCM_RATE_176400) 35 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 36 SNDRV_PCM_FMTBIT_S24_LE) 37 38 /* slave port water mark level 39 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 40 */ 41 #define SLAVE_PORT_WATER_MARK_6BYTES 0 42 #define SLAVE_PORT_WATER_MARK_9BYTES 1 43 #define SLAVE_PORT_WATER_MARK_12BYTES 2 44 #define SLAVE_PORT_WATER_MARK_15BYTES 3 45 #define SLAVE_PORT_WATER_MARK_SHIFT 1 46 #define SLAVE_PORT_ENABLE 1 47 #define SLAVE_PORT_DISABLE 0 48 #define WCD934X_SLIM_WATER_MARK_VAL \ 49 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 50 (SLAVE_PORT_ENABLE)) 51 52 #define WCD934X_SLIM_NUM_PORT_REG 3 53 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2) 54 #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0) 55 #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1) 56 #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2) 57 58 #define WCD934X_MCLK_CLK_12P288MHZ 12288000 59 #define WCD934X_MCLK_CLK_9P6MHZ 9600000 60 61 /* Only valid for 9.6 MHz mclk */ 62 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000 63 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000 64 65 /* Only valid for 12.288 MHz mclk */ 66 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000 67 68 #define WCD934X_DMIC_CLK_DIV_2 0x0 69 #define WCD934X_DMIC_CLK_DIV_3 0x1 70 #define WCD934X_DMIC_CLK_DIV_4 0x2 71 #define WCD934X_DMIC_CLK_DIV_6 0x3 72 #define WCD934X_DMIC_CLK_DIV_8 0x4 73 #define WCD934X_DMIC_CLK_DIV_16 0x5 74 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02 75 76 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 77 #define CF_MIN_3DB_4HZ 0x0 78 #define CF_MIN_3DB_75HZ 0x1 79 #define CF_MIN_3DB_150HZ 0x2 80 81 #define WCD934X_RX_START 16 82 #define WCD934X_NUM_INTERPOLATORS 9 83 #define WCD934X_RX_PATH_CTL_OFFSET 20 84 #define WCD934X_MAX_VALID_ADC_MUX 13 85 #define WCD934X_INVALID_ADC_MUX 9 86 87 #define WCD934X_SLIM_RX_CH(p) \ 88 {.port = p + WCD934X_RX_START, .shift = p,} 89 90 #define WCD934X_SLIM_TX_CH(p) \ 91 {.port = p, .shift = p,} 92 93 /* Feature masks to distinguish codec version */ 94 #define DSD_DISABLED_MASK 0 95 #define SLNQ_DISABLED_MASK 1 96 97 #define DSD_DISABLED BIT(DSD_DISABLED_MASK) 98 #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK) 99 100 /* As fine version info cannot be retrieved before wcd probe. 101 * Define three coarse versions for possible future use before wcd probe. 102 */ 103 #define WCD_VERSION_WCD9340_1_0 0x400 104 #define WCD_VERSION_WCD9341_1_0 0x410 105 #define WCD_VERSION_WCD9340_1_1 0x401 106 #define WCD_VERSION_WCD9341_1_1 0x411 107 #define WCD934X_AMIC_PWR_LEVEL_LP 0 108 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1 109 #define WCD934X_AMIC_PWR_LEVEL_HP 2 110 #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3 111 #define WCD934X_AMIC_PWR_LVL_MASK 0x60 112 #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5 113 114 #define WCD934X_DEC_PWR_LVL_MASK 0x06 115 #define WCD934X_DEC_PWR_LVL_LP 0x02 116 #define WCD934X_DEC_PWR_LVL_HP 0x04 117 #define WCD934X_DEC_PWR_LVL_DF 0x00 118 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF 119 120 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 121 122 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \ 123 { \ 124 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 125 .info = wcd934x_iir_filter_info, \ 126 .get = wcd934x_get_iir_band_audio_mixer, \ 127 .put = wcd934x_put_iir_band_audio_mixer, \ 128 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 129 .iir_idx = iidx, \ 130 .band_idx = bidx, \ 131 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \ 132 } \ 133 } 134 135 /* Z value defined in milliohm */ 136 #define WCD934X_ZDET_VAL_32 32000 137 #define WCD934X_ZDET_VAL_400 400000 138 #define WCD934X_ZDET_VAL_1200 1200000 139 #define WCD934X_ZDET_VAL_100K 100000000 140 /* Z floating defined in ohms */ 141 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE 142 143 #define WCD934X_ZDET_NUM_MEASUREMENTS 900 144 #define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 145 #define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF) 146 /* Z value compared in milliOhm */ 147 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 148 #define WCD934X_MBHC_ZDET_CONST (86 * 16384) 149 #define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM 150 #define WCD934X_MBHC_MAX_BUTTONS (8) 151 #define WCD_MBHC_HS_V_MAX 1600 152 153 #define WCD934X_INTERPOLATOR_PATH(id) \ 154 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 155 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 156 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 157 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 158 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 159 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 160 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 161 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 162 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \ 163 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \ 164 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 165 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 166 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 167 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 168 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 169 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 170 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 171 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 172 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \ 173 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \ 174 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 175 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 176 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 177 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 178 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 179 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 180 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 181 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 182 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \ 183 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \ 184 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 185 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 186 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 187 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 188 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 189 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 190 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 191 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 192 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 193 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 194 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 195 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \ 196 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \ 197 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \ 198 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \ 199 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \ 200 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \ 201 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \ 202 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"} 203 204 #define WCD934X_INTERPOLATOR_MIX2(id) \ 205 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 206 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"} 207 208 #define WCD934X_SLIM_RX_AIF_PATH(id) \ 209 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \ 210 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \ 211 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \ 212 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \ 213 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"} 214 215 #define WCD934X_ADC_MUX(id) \ 216 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \ 217 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \ 218 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 219 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 220 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 221 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 222 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 223 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 224 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 225 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 226 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 227 {"AMIC MUX" #id, "ADC4", "ADC4"} 228 229 #define WCD934X_IIR_INP_MUX(id) \ 230 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \ 231 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \ 232 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \ 233 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \ 234 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \ 235 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \ 236 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \ 237 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \ 238 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \ 239 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \ 240 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \ 241 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \ 242 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \ 243 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \ 244 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \ 245 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \ 246 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \ 247 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \ 248 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \ 249 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \ 250 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \ 251 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \ 252 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \ 253 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \ 254 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \ 255 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \ 256 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \ 257 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \ 258 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \ 259 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \ 260 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \ 261 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \ 262 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \ 263 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \ 264 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \ 265 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \ 266 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \ 267 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \ 268 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \ 269 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \ 270 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \ 271 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \ 272 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \ 273 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \ 274 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \ 275 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \ 276 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \ 277 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \ 278 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \ 279 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \ 280 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \ 281 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \ 282 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \ 283 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \ 284 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \ 285 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \ 286 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \ 287 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \ 288 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \ 289 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \ 290 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \ 291 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \ 292 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \ 293 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \ 294 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \ 295 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \ 296 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \ 297 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \ 298 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \ 299 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \ 300 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \ 301 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"} 302 303 #define WCD934X_SLIM_TX_AIF_PATH(id) \ 304 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 305 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 306 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 307 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"} 308 309 #define WCD934X_MAX_MICBIAS MIC_BIAS_4 310 #define NUM_CODEC_DAIS 9 311 312 enum { 313 SIDO_SOURCE_INTERNAL, 314 SIDO_SOURCE_RCO_BG, 315 }; 316 317 enum { 318 INTERP_EAR = 0, 319 INTERP_HPHL, 320 INTERP_HPHR, 321 INTERP_LO1, 322 INTERP_LO2, 323 INTERP_LO3_NA, /* LO3 not avalible in Tavil */ 324 INTERP_LO4_NA, 325 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */ 326 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */ 327 INTERP_MAX, 328 }; 329 330 enum { 331 WCD934X_RX0 = 0, 332 WCD934X_RX1, 333 WCD934X_RX2, 334 WCD934X_RX3, 335 WCD934X_RX4, 336 WCD934X_RX5, 337 WCD934X_RX6, 338 WCD934X_RX7, 339 WCD934X_RX8, 340 WCD934X_RX9, 341 WCD934X_RX10, 342 WCD934X_RX11, 343 WCD934X_RX12, 344 WCD934X_RX_MAX, 345 }; 346 347 enum { 348 WCD934X_TX0 = 0, 349 WCD934X_TX1, 350 WCD934X_TX2, 351 WCD934X_TX3, 352 WCD934X_TX4, 353 WCD934X_TX5, 354 WCD934X_TX6, 355 WCD934X_TX7, 356 WCD934X_TX8, 357 WCD934X_TX9, 358 WCD934X_TX10, 359 WCD934X_TX11, 360 WCD934X_TX12, 361 WCD934X_TX13, 362 WCD934X_TX14, 363 WCD934X_TX15, 364 WCD934X_TX_MAX, 365 }; 366 367 struct wcd934x_slim_ch { 368 u32 ch_num; 369 u16 port; 370 u16 shift; 371 struct list_head list; 372 }; 373 374 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = { 375 WCD934X_SLIM_TX_CH(0), 376 WCD934X_SLIM_TX_CH(1), 377 WCD934X_SLIM_TX_CH(2), 378 WCD934X_SLIM_TX_CH(3), 379 WCD934X_SLIM_TX_CH(4), 380 WCD934X_SLIM_TX_CH(5), 381 WCD934X_SLIM_TX_CH(6), 382 WCD934X_SLIM_TX_CH(7), 383 WCD934X_SLIM_TX_CH(8), 384 WCD934X_SLIM_TX_CH(9), 385 WCD934X_SLIM_TX_CH(10), 386 WCD934X_SLIM_TX_CH(11), 387 WCD934X_SLIM_TX_CH(12), 388 WCD934X_SLIM_TX_CH(13), 389 WCD934X_SLIM_TX_CH(14), 390 WCD934X_SLIM_TX_CH(15), 391 }; 392 393 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = { 394 WCD934X_SLIM_RX_CH(0), /* 16 */ 395 WCD934X_SLIM_RX_CH(1), /* 17 */ 396 WCD934X_SLIM_RX_CH(2), 397 WCD934X_SLIM_RX_CH(3), 398 WCD934X_SLIM_RX_CH(4), 399 WCD934X_SLIM_RX_CH(5), 400 WCD934X_SLIM_RX_CH(6), 401 WCD934X_SLIM_RX_CH(7), 402 WCD934X_SLIM_RX_CH(8), 403 WCD934X_SLIM_RX_CH(9), 404 WCD934X_SLIM_RX_CH(10), 405 WCD934X_SLIM_RX_CH(11), 406 WCD934X_SLIM_RX_CH(12), 407 }; 408 409 /* Codec supports 2 IIR filters */ 410 enum { 411 IIR0 = 0, 412 IIR1, 413 IIR_MAX, 414 }; 415 416 /* Each IIR has 5 Filter Stages */ 417 enum { 418 BAND1 = 0, 419 BAND2, 420 BAND3, 421 BAND4, 422 BAND5, 423 BAND_MAX, 424 }; 425 426 enum { 427 COMPANDER_1, /* HPH_L */ 428 COMPANDER_2, /* HPH_R */ 429 COMPANDER_3, /* LO1_DIFF */ 430 COMPANDER_4, /* LO2_DIFF */ 431 COMPANDER_5, /* LO3_SE - not used in Tavil */ 432 COMPANDER_6, /* LO4_SE - not used in Tavil */ 433 COMPANDER_7, /* SWR SPK CH1 */ 434 COMPANDER_8, /* SWR SPK CH2 */ 435 COMPANDER_MAX, 436 }; 437 438 enum { 439 INTn_1_INP_SEL_ZERO = 0, 440 INTn_1_INP_SEL_DEC0, 441 INTn_1_INP_SEL_DEC1, 442 INTn_1_INP_SEL_IIR0, 443 INTn_1_INP_SEL_IIR1, 444 INTn_1_INP_SEL_RX0, 445 INTn_1_INP_SEL_RX1, 446 INTn_1_INP_SEL_RX2, 447 INTn_1_INP_SEL_RX3, 448 INTn_1_INP_SEL_RX4, 449 INTn_1_INP_SEL_RX5, 450 INTn_1_INP_SEL_RX6, 451 INTn_1_INP_SEL_RX7, 452 }; 453 454 enum { 455 INTn_2_INP_SEL_ZERO = 0, 456 INTn_2_INP_SEL_RX0, 457 INTn_2_INP_SEL_RX1, 458 INTn_2_INP_SEL_RX2, 459 INTn_2_INP_SEL_RX3, 460 INTn_2_INP_SEL_RX4, 461 INTn_2_INP_SEL_RX5, 462 INTn_2_INP_SEL_RX6, 463 INTn_2_INP_SEL_RX7, 464 INTn_2_INP_SEL_PROXIMITY, 465 }; 466 467 struct interp_sample_rate { 468 int sample_rate; 469 int rate_val; 470 }; 471 472 static const struct interp_sample_rate sr_val_tbl[] = { 473 {8000, 0x0}, 474 {16000, 0x1}, 475 {32000, 0x3}, 476 {48000, 0x4}, 477 {96000, 0x5}, 478 {192000, 0x6}, 479 {384000, 0x7}, 480 {44100, 0x9}, 481 {88200, 0xA}, 482 {176400, 0xB}, 483 {352800, 0xC}, 484 }; 485 486 struct wcd934x_mbhc_zdet_param { 487 u16 ldo_ctl; 488 u16 noff; 489 u16 nshift; 490 u16 btn5; 491 u16 btn6; 492 u16 btn7; 493 }; 494 495 struct wcd_slim_codec_dai_data { 496 struct list_head slim_ch_list; 497 struct slim_stream_config sconfig; 498 struct slim_stream_runtime *sruntime; 499 }; 500 501 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = { 502 { 503 .name = "WCD9335-IFC-DEV", 504 .range_min = 0x0, 505 .range_max = 0xffff, 506 .selector_reg = 0x800, 507 .selector_mask = 0xfff, 508 .selector_shift = 0, 509 .window_start = 0x800, 510 .window_len = 0x400, 511 }, 512 }; 513 514 static const struct regmap_config wcd934x_ifc_regmap_config = { 515 .reg_bits = 16, 516 .val_bits = 8, 517 .max_register = 0xffff, 518 .ranges = wcd934x_ifc_ranges, 519 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges), 520 }; 521 522 struct wcd934x_codec { 523 struct device *dev; 524 struct clk_hw hw; 525 struct clk *extclk; 526 struct regmap *regmap; 527 struct regmap *if_regmap; 528 struct slim_device *sdev; 529 struct slim_device *sidev; 530 struct wcd_clsh_ctrl *clsh_ctrl; 531 struct wcd_common common; 532 struct snd_soc_component *component; 533 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX]; 534 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX]; 535 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 536 int rate; 537 u32 version; 538 u32 hph_mode; 539 u32 tx_port_value[WCD934X_TX_MAX]; 540 u32 rx_port_value[WCD934X_RX_MAX]; 541 int sido_input_src; 542 int dmic_0_1_clk_cnt; 543 int dmic_2_3_clk_cnt; 544 int dmic_4_5_clk_cnt; 545 int dmic_sample_rate; 546 int comp_enabled[COMPANDER_MAX]; 547 int sysclk_users; 548 struct mutex sysclk_mutex; 549 /* mbhc module */ 550 struct wcd_mbhc *mbhc; 551 struct wcd_mbhc_config mbhc_cfg; 552 struct wcd_mbhc_intr intr_ids; 553 bool mbhc_started; 554 struct mutex micb_lock; 555 u32 micb_ref[WCD934X_MAX_MICBIAS]; 556 u32 pullup_ref[WCD934X_MAX_MICBIAS]; 557 }; 558 559 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw) 560 561 struct wcd_iir_filter_ctl { 562 unsigned int iir_idx; 563 unsigned int band_idx; 564 struct soc_bytes_ext bytes_ext; 565 }; 566 567 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 568 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 569 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 570 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 571 572 /* Cutoff frequency for high pass filter */ 573 static const char * const cf_text[] = { 574 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 575 }; 576 577 static const char * const rx_cf_text[] = { 578 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 579 "CF_NEG_3DB_0P48HZ" 580 }; 581 582 static const char * const rx_hph_mode_mux_text[] = { 583 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 584 "Class-H Hi-Fi Low Power" 585 }; 586 587 static const char *const slim_rx_mux_text[] = { 588 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 589 }; 590 591 static const char * const rx_int0_7_mix_mux_text[] = { 592 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 593 "RX6", "RX7", "PROXIMITY" 594 }; 595 596 static const char * const rx_int_mix_mux_text[] = { 597 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 598 "RX6", "RX7" 599 }; 600 601 static const char * const rx_prim_mix_text[] = { 602 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 603 "RX3", "RX4", "RX5", "RX6", "RX7" 604 }; 605 606 static const char * const rx_sidetone_mix_text[] = { 607 "ZERO", "SRC0", "SRC1", "SRC_SUM" 608 }; 609 610 static const char * const iir_inp_mux_text[] = { 611 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", 612 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7" 613 }; 614 615 static const char * const rx_int_dem_inp_mux_text[] = { 616 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 617 }; 618 619 static const char * const rx_int0_1_interp_mux_text[] = { 620 "ZERO", "RX INT0_1 MIX1", 621 }; 622 623 static const char * const rx_int1_1_interp_mux_text[] = { 624 "ZERO", "RX INT1_1 MIX1", 625 }; 626 627 static const char * const rx_int2_1_interp_mux_text[] = { 628 "ZERO", "RX INT2_1 MIX1", 629 }; 630 631 static const char * const rx_int3_1_interp_mux_text[] = { 632 "ZERO", "RX INT3_1 MIX1", 633 }; 634 635 static const char * const rx_int4_1_interp_mux_text[] = { 636 "ZERO", "RX INT4_1 MIX1", 637 }; 638 639 static const char * const rx_int7_1_interp_mux_text[] = { 640 "ZERO", "RX INT7_1 MIX1", 641 }; 642 643 static const char * const rx_int8_1_interp_mux_text[] = { 644 "ZERO", "RX INT8_1 MIX1", 645 }; 646 647 static const char * const rx_int0_2_interp_mux_text[] = { 648 "ZERO", "RX INT0_2 MUX", 649 }; 650 651 static const char * const rx_int1_2_interp_mux_text[] = { 652 "ZERO", "RX INT1_2 MUX", 653 }; 654 655 static const char * const rx_int2_2_interp_mux_text[] = { 656 "ZERO", "RX INT2_2 MUX", 657 }; 658 659 static const char * const rx_int3_2_interp_mux_text[] = { 660 "ZERO", "RX INT3_2 MUX", 661 }; 662 663 static const char * const rx_int4_2_interp_mux_text[] = { 664 "ZERO", "RX INT4_2 MUX", 665 }; 666 667 static const char * const rx_int7_2_interp_mux_text[] = { 668 "ZERO", "RX INT7_2 MUX", 669 }; 670 671 static const char * const rx_int8_2_interp_mux_text[] = { 672 "ZERO", "RX INT8_2 MUX", 673 }; 674 675 static const char * const dmic_mux_text[] = { 676 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5" 677 }; 678 679 static const char * const amic_mux_text[] = { 680 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4" 681 }; 682 683 static const char * const amic4_5_sel_text[] = { 684 "AMIC4", "AMIC5" 685 }; 686 687 static const char * const adc_mux_text[] = { 688 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 689 }; 690 691 static const char * const cdc_if_tx0_mux_text[] = { 692 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 693 }; 694 695 static const char * const cdc_if_tx1_mux_text[] = { 696 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 697 }; 698 699 static const char * const cdc_if_tx2_mux_text[] = { 700 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 701 }; 702 703 static const char * const cdc_if_tx3_mux_text[] = { 704 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 705 }; 706 707 static const char * const cdc_if_tx4_mux_text[] = { 708 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 709 }; 710 711 static const char * const cdc_if_tx5_mux_text[] = { 712 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 713 }; 714 715 static const char * const cdc_if_tx6_mux_text[] = { 716 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 717 }; 718 719 static const char * const cdc_if_tx7_mux_text[] = { 720 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 721 }; 722 723 static const char * const cdc_if_tx8_mux_text[] = { 724 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 725 }; 726 727 static const char * const cdc_if_tx9_mux_text[] = { 728 "ZERO", "DEC7", "DEC7_192" 729 }; 730 731 static const char * const cdc_if_tx10_mux_text[] = { 732 "ZERO", "DEC6", "DEC6_192" 733 }; 734 735 static const char * const cdc_if_tx11_mux_text[] = { 736 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST" 737 }; 738 739 static const char * const cdc_if_tx11_inp1_mux_text[] = { 740 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", 741 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12" 742 }; 743 744 static const char * const cdc_if_tx13_mux_text[] = { 745 "CDC_DEC_5", "MAD_BRDCST" 746 }; 747 748 static const char * const cdc_if_tx13_inp1_mux_text[] = { 749 "ZERO", "DEC5", "DEC5_192" 750 }; 751 752 static const struct soc_enum cf_dec0_enum = 753 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 754 755 static const struct soc_enum cf_dec1_enum = 756 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 757 758 static const struct soc_enum cf_dec2_enum = 759 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 760 761 static const struct soc_enum cf_dec3_enum = 762 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 763 764 static const struct soc_enum cf_dec4_enum = 765 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 766 767 static const struct soc_enum cf_dec5_enum = 768 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 769 770 static const struct soc_enum cf_dec6_enum = 771 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 772 773 static const struct soc_enum cf_dec7_enum = 774 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 775 776 static const struct soc_enum cf_dec8_enum = 777 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 778 779 static const struct soc_enum cf_int0_1_enum = 780 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 781 782 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2, 783 rx_cf_text); 784 785 static const struct soc_enum cf_int1_1_enum = 786 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 787 788 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2, 789 rx_cf_text); 790 791 static const struct soc_enum cf_int2_1_enum = 792 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 793 794 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2, 795 rx_cf_text); 796 797 static const struct soc_enum cf_int3_1_enum = 798 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 799 800 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2, 801 rx_cf_text); 802 803 static const struct soc_enum cf_int4_1_enum = 804 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 805 806 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2, 807 rx_cf_text); 808 809 static const struct soc_enum cf_int7_1_enum = 810 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 811 812 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2, 813 rx_cf_text); 814 815 static const struct soc_enum cf_int8_1_enum = 816 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 817 818 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2, 819 rx_cf_text); 820 821 static const struct soc_enum rx_hph_mode_mux_enum = 822 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 823 rx_hph_mode_mux_text); 824 825 static const struct soc_enum slim_rx_mux_enum = 826 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 827 828 static const struct soc_enum rx_int0_2_mux_chain_enum = 829 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 830 rx_int0_7_mix_mux_text); 831 832 static const struct soc_enum rx_int1_2_mux_chain_enum = 833 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 834 rx_int_mix_mux_text); 835 836 static const struct soc_enum rx_int2_2_mux_chain_enum = 837 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 838 rx_int_mix_mux_text); 839 840 static const struct soc_enum rx_int3_2_mux_chain_enum = 841 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 842 rx_int_mix_mux_text); 843 844 static const struct soc_enum rx_int4_2_mux_chain_enum = 845 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 846 rx_int_mix_mux_text); 847 848 static const struct soc_enum rx_int7_2_mux_chain_enum = 849 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 850 rx_int0_7_mix_mux_text); 851 852 static const struct soc_enum rx_int8_2_mux_chain_enum = 853 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 854 rx_int_mix_mux_text); 855 856 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 857 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 858 rx_prim_mix_text); 859 860 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 861 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 862 rx_prim_mix_text); 863 864 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 865 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 866 rx_prim_mix_text); 867 868 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 869 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 870 rx_prim_mix_text); 871 872 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 873 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 874 rx_prim_mix_text); 875 876 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 877 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 878 rx_prim_mix_text); 879 880 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 881 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 882 rx_prim_mix_text); 883 884 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 885 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 886 rx_prim_mix_text); 887 888 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 889 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 890 rx_prim_mix_text); 891 892 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 893 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 894 rx_prim_mix_text); 895 896 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 897 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 898 rx_prim_mix_text); 899 900 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 901 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 902 rx_prim_mix_text); 903 904 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 905 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 906 rx_prim_mix_text); 907 908 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 909 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 910 rx_prim_mix_text); 911 912 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 913 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 914 rx_prim_mix_text); 915 916 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 917 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 918 rx_prim_mix_text); 919 920 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 921 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 922 rx_prim_mix_text); 923 924 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 925 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 926 rx_prim_mix_text); 927 928 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 929 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 930 rx_prim_mix_text); 931 932 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 933 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 934 rx_prim_mix_text); 935 936 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 937 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 938 rx_prim_mix_text); 939 940 static const struct soc_enum rx_int0_mix2_inp_mux_enum = 941 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4, 942 rx_sidetone_mix_text); 943 944 static const struct soc_enum rx_int1_mix2_inp_mux_enum = 945 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4, 946 rx_sidetone_mix_text); 947 948 static const struct soc_enum rx_int2_mix2_inp_mux_enum = 949 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4, 950 rx_sidetone_mix_text); 951 952 static const struct soc_enum rx_int3_mix2_inp_mux_enum = 953 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4, 954 rx_sidetone_mix_text); 955 956 static const struct soc_enum rx_int4_mix2_inp_mux_enum = 957 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4, 958 rx_sidetone_mix_text); 959 960 static const struct soc_enum rx_int7_mix2_inp_mux_enum = 961 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4, 962 rx_sidetone_mix_text); 963 964 static const struct soc_enum iir0_inp0_mux_enum = 965 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 966 0, 18, iir_inp_mux_text); 967 968 static const struct soc_enum iir0_inp1_mux_enum = 969 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 970 0, 18, iir_inp_mux_text); 971 972 static const struct soc_enum iir0_inp2_mux_enum = 973 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 974 0, 18, iir_inp_mux_text); 975 976 static const struct soc_enum iir0_inp3_mux_enum = 977 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 978 0, 18, iir_inp_mux_text); 979 980 static const struct soc_enum iir1_inp0_mux_enum = 981 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 982 0, 18, iir_inp_mux_text); 983 984 static const struct soc_enum iir1_inp1_mux_enum = 985 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 986 0, 18, iir_inp_mux_text); 987 988 static const struct soc_enum iir1_inp2_mux_enum = 989 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 990 0, 18, iir_inp_mux_text); 991 992 static const struct soc_enum iir1_inp3_mux_enum = 993 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 994 0, 18, iir_inp_mux_text); 995 996 static const struct soc_enum rx_int0_dem_inp_mux_enum = 997 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0, 998 ARRAY_SIZE(rx_int_dem_inp_mux_text), 999 rx_int_dem_inp_mux_text); 1000 1001 static const struct soc_enum rx_int1_dem_inp_mux_enum = 1002 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0, 1003 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1004 rx_int_dem_inp_mux_text); 1005 1006 static const struct soc_enum rx_int2_dem_inp_mux_enum = 1007 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0, 1008 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1009 rx_int_dem_inp_mux_text); 1010 1011 static const struct soc_enum tx_adc_mux0_enum = 1012 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 1013 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1014 static const struct soc_enum tx_adc_mux1_enum = 1015 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 1016 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1017 static const struct soc_enum tx_adc_mux2_enum = 1018 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 1019 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1020 static const struct soc_enum tx_adc_mux3_enum = 1021 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 1022 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1023 static const struct soc_enum tx_adc_mux4_enum = 1024 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2, 1025 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1026 static const struct soc_enum tx_adc_mux5_enum = 1027 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2, 1028 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1029 static const struct soc_enum tx_adc_mux6_enum = 1030 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2, 1031 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1032 static const struct soc_enum tx_adc_mux7_enum = 1033 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2, 1034 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1035 static const struct soc_enum tx_adc_mux8_enum = 1036 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4, 1037 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1038 1039 static const struct soc_enum rx_int0_1_interp_mux_enum = 1040 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1041 rx_int0_1_interp_mux_text); 1042 1043 static const struct soc_enum rx_int1_1_interp_mux_enum = 1044 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1045 rx_int1_1_interp_mux_text); 1046 1047 static const struct soc_enum rx_int2_1_interp_mux_enum = 1048 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1049 rx_int2_1_interp_mux_text); 1050 1051 static const struct soc_enum rx_int3_1_interp_mux_enum = 1052 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text); 1053 1054 static const struct soc_enum rx_int4_1_interp_mux_enum = 1055 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text); 1056 1057 static const struct soc_enum rx_int7_1_interp_mux_enum = 1058 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text); 1059 1060 static const struct soc_enum rx_int8_1_interp_mux_enum = 1061 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text); 1062 1063 static const struct soc_enum rx_int0_2_interp_mux_enum = 1064 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text); 1065 1066 static const struct soc_enum rx_int1_2_interp_mux_enum = 1067 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text); 1068 1069 static const struct soc_enum rx_int2_2_interp_mux_enum = 1070 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text); 1071 1072 static const struct soc_enum rx_int3_2_interp_mux_enum = 1073 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text); 1074 1075 static const struct soc_enum rx_int4_2_interp_mux_enum = 1076 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text); 1077 1078 static const struct soc_enum rx_int7_2_interp_mux_enum = 1079 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text); 1080 1081 static const struct soc_enum rx_int8_2_interp_mux_enum = 1082 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text); 1083 1084 static const struct soc_enum tx_dmic_mux0_enum = 1085 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7, 1086 dmic_mux_text); 1087 1088 static const struct soc_enum tx_dmic_mux1_enum = 1089 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7, 1090 dmic_mux_text); 1091 1092 static const struct soc_enum tx_dmic_mux2_enum = 1093 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7, 1094 dmic_mux_text); 1095 1096 static const struct soc_enum tx_dmic_mux3_enum = 1097 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7, 1098 dmic_mux_text); 1099 1100 static const struct soc_enum tx_dmic_mux4_enum = 1101 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 1102 dmic_mux_text); 1103 1104 static const struct soc_enum tx_dmic_mux5_enum = 1105 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 1106 dmic_mux_text); 1107 1108 static const struct soc_enum tx_dmic_mux6_enum = 1109 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 1110 dmic_mux_text); 1111 1112 static const struct soc_enum tx_dmic_mux7_enum = 1113 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 1114 dmic_mux_text); 1115 1116 static const struct soc_enum tx_dmic_mux8_enum = 1117 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 1118 dmic_mux_text); 1119 1120 static const struct soc_enum tx_amic_mux0_enum = 1121 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5, 1122 amic_mux_text); 1123 static const struct soc_enum tx_amic_mux1_enum = 1124 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5, 1125 amic_mux_text); 1126 static const struct soc_enum tx_amic_mux2_enum = 1127 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5, 1128 amic_mux_text); 1129 static const struct soc_enum tx_amic_mux3_enum = 1130 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5, 1131 amic_mux_text); 1132 static const struct soc_enum tx_amic_mux4_enum = 1133 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5, 1134 amic_mux_text); 1135 static const struct soc_enum tx_amic_mux5_enum = 1136 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5, 1137 amic_mux_text); 1138 static const struct soc_enum tx_amic_mux6_enum = 1139 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5, 1140 amic_mux_text); 1141 static const struct soc_enum tx_amic_mux7_enum = 1142 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5, 1143 amic_mux_text); 1144 static const struct soc_enum tx_amic_mux8_enum = 1145 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5, 1146 amic_mux_text); 1147 1148 static const struct soc_enum tx_amic4_5_enum = 1149 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text); 1150 1151 static const struct soc_enum cdc_if_tx0_mux_enum = 1152 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 1153 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text); 1154 static const struct soc_enum cdc_if_tx1_mux_enum = 1155 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 1156 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text); 1157 static const struct soc_enum cdc_if_tx2_mux_enum = 1158 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 1159 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text); 1160 static const struct soc_enum cdc_if_tx3_mux_enum = 1161 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 1162 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text); 1163 static const struct soc_enum cdc_if_tx4_mux_enum = 1164 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 1165 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text); 1166 static const struct soc_enum cdc_if_tx5_mux_enum = 1167 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 1168 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text); 1169 static const struct soc_enum cdc_if_tx6_mux_enum = 1170 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 1171 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text); 1172 static const struct soc_enum cdc_if_tx7_mux_enum = 1173 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 1174 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text); 1175 static const struct soc_enum cdc_if_tx8_mux_enum = 1176 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 1177 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text); 1178 static const struct soc_enum cdc_if_tx9_mux_enum = 1179 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2, 1180 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text); 1181 static const struct soc_enum cdc_if_tx10_mux_enum = 1182 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4, 1183 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text); 1184 static const struct soc_enum cdc_if_tx11_inp1_mux_enum = 1185 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0, 1186 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text), 1187 cdc_if_tx11_inp1_mux_text); 1188 static const struct soc_enum cdc_if_tx11_mux_enum = 1189 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0, 1190 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text); 1191 static const struct soc_enum cdc_if_tx13_inp1_mux_enum = 1192 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4, 1193 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text), 1194 cdc_if_tx13_inp1_mux_text); 1195 static const struct soc_enum cdc_if_tx13_mux_enum = 1196 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0, 1197 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text); 1198 1199 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 1200 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80), 1201 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40), 1202 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20), 1203 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 1204 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08), 1205 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0), 1206 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04), 1207 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10), 1208 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08), 1209 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01), 1210 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06), 1211 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80), 1212 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 1213 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03), 1214 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03), 1215 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08), 1216 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1217 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20), 1218 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80), 1219 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40), 1220 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10), 1221 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07), 1222 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70), 1223 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF), 1224 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0), 1225 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF), 1226 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40), 1227 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80), 1228 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0), 1229 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1230 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02), 1231 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01), 1232 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70), 1233 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20), 1234 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40), 1235 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10), 1236 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01), 1237 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01), 1238 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04), 1239 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08), 1240 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08), 1241 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40), 1242 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80), 1243 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF), 1244 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F), 1245 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10), 1246 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04), 1247 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02), 1248 }; 1249 1250 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src) 1251 { 1252 if (sido_src == wcd->sido_input_src) 1253 return 0; 1254 1255 if (sido_src == SIDO_SOURCE_RCO_BG) { 1256 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO, 1257 WCD934X_ANA_RCO_BG_EN_MASK, 1258 WCD934X_ANA_RCO_BG_ENABLE); 1259 usleep_range(100, 110); 1260 } 1261 wcd->sido_input_src = sido_src; 1262 1263 return 0; 1264 } 1265 1266 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd) 1267 { 1268 scoped_guard(mutex, &wcd->sysclk_mutex) { 1269 if (++wcd->sysclk_users != 1) 1270 return 0; 1271 } 1272 1273 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1274 WCD934X_ANA_BIAS_EN_MASK, 1275 WCD934X_ANA_BIAS_EN); 1276 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1277 WCD934X_ANA_PRECHRG_EN_MASK, 1278 WCD934X_ANA_PRECHRG_EN); 1279 /* 1280 * 1ms delay is required after pre-charge is enabled 1281 * as per HW requirement 1282 */ 1283 usleep_range(1000, 1100); 1284 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1285 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1286 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1287 WCD934X_ANA_PRECHRG_MODE_MASK, 0); 1288 1289 /* 1290 * In data clock contrl register is changed 1291 * to CLK_SYS_MCLK_PRG 1292 */ 1293 1294 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1295 WCD934X_EXT_CLK_BUF_EN_MASK, 1296 WCD934X_EXT_CLK_BUF_EN); 1297 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1298 WCD934X_EXT_CLK_DIV_RATIO_MASK, 1299 WCD934X_EXT_CLK_DIV_BY_2); 1300 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1301 WCD934X_MCLK_SRC_MASK, 1302 WCD934X_MCLK_SRC_EXT_CLK); 1303 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1304 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN); 1305 regmap_update_bits(wcd->regmap, 1306 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 1307 WCD934X_CDC_FS_MCLK_CNT_EN_MASK, 1308 WCD934X_CDC_FS_MCLK_CNT_ENABLE); 1309 regmap_update_bits(wcd->regmap, 1310 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL, 1311 WCD934X_MCLK_EN_MASK, 1312 WCD934X_MCLK_EN); 1313 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE, 1314 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0); 1315 /* 1316 * 10us sleep is required after clock is enabled 1317 * as per HW requirement 1318 */ 1319 usleep_range(10, 15); 1320 1321 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1322 1323 return 0; 1324 } 1325 1326 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd) 1327 { 1328 scoped_guard(mutex, &wcd->sysclk_mutex) { 1329 if (--wcd->sysclk_users != 0) 1330 return 0; 1331 } 1332 1333 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1334 WCD934X_EXT_CLK_BUF_EN_MASK | 1335 WCD934X_MCLK_EN_MASK, 0x0); 1336 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1337 WCD934X_ANA_BIAS_EN_MASK, 0); 1338 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1339 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1340 1341 return 0; 1342 } 1343 1344 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable) 1345 { 1346 int ret = 0; 1347 1348 if (enable) { 1349 ret = clk_prepare_enable(wcd->extclk); 1350 1351 if (ret) { 1352 dev_err(wcd->dev, "%s: ext clk enable failed\n", 1353 __func__); 1354 return ret; 1355 } 1356 ret = wcd934x_enable_ana_bias_and_sysclk(wcd); 1357 } else { 1358 int val; 1359 1360 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1361 &val); 1362 1363 /* Don't disable clock if soundwire using it.*/ 1364 if (val & WCD934X_CDC_SWR_CLK_EN_MASK) 1365 return 0; 1366 1367 wcd934x_disable_ana_bias_and_syclk(wcd); 1368 clk_disable_unprepare(wcd->extclk); 1369 } 1370 1371 return ret; 1372 } 1373 1374 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w, 1375 struct snd_kcontrol *kc, int event) 1376 { 1377 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 1378 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1379 1380 switch (event) { 1381 case SND_SOC_DAPM_PRE_PMU: 1382 return __wcd934x_cdc_mclk_enable(wcd, true); 1383 case SND_SOC_DAPM_POST_PMD: 1384 return __wcd934x_cdc_mclk_enable(wcd, false); 1385 } 1386 1387 return 0; 1388 } 1389 1390 static int wcd934x_get_version(struct wcd934x_codec *wcd) 1391 { 1392 int val1, val2, ver, ret; 1393 struct regmap *regmap; 1394 u16 id_minor; 1395 u32 version_mask = 0; 1396 1397 regmap = wcd->regmap; 1398 ver = 0; 1399 1400 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 1401 (u8 *)&id_minor, sizeof(u16)); 1402 1403 if (ret) 1404 return ret; 1405 1406 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1); 1407 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2); 1408 1409 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK; 1410 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK; 1411 1412 switch (version_mask) { 1413 case DSD_DISABLED | SLNQ_DISABLED: 1414 if (id_minor == 0) 1415 ver = WCD_VERSION_WCD9340_1_0; 1416 else if (id_minor == 0x01) 1417 ver = WCD_VERSION_WCD9340_1_1; 1418 break; 1419 case SLNQ_DISABLED: 1420 if (id_minor == 0) 1421 ver = WCD_VERSION_WCD9341_1_0; 1422 else if (id_minor == 0x01) 1423 ver = WCD_VERSION_WCD9341_1_1; 1424 break; 1425 } 1426 1427 wcd->version = ver; 1428 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver); 1429 1430 return 0; 1431 } 1432 1433 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd) 1434 { 1435 int rc, val; 1436 1437 __wcd934x_cdc_mclk_enable(wcd, true); 1438 1439 regmap_update_bits(wcd->regmap, 1440 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1441 WCD934X_EFUSE_SENSE_STATE_MASK, 1442 WCD934X_EFUSE_SENSE_STATE_DEF); 1443 regmap_update_bits(wcd->regmap, 1444 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1445 WCD934X_EFUSE_SENSE_EN_MASK, 1446 WCD934X_EFUSE_SENSE_ENABLE); 1447 /* 1448 * 5ms sleep required after enabling efuse control 1449 * before checking the status. 1450 */ 1451 usleep_range(5000, 5500); 1452 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1453 1454 rc = regmap_read(wcd->regmap, 1455 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val); 1456 if (rc || (!(val & 0x01))) 1457 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n", 1458 __func__, val, rc); 1459 1460 __wcd934x_cdc_mclk_enable(wcd, false); 1461 } 1462 1463 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable) 1464 { 1465 if (enable) { 1466 __wcd934x_cdc_mclk_enable(wcd, true); 1467 regmap_update_bits(wcd->regmap, 1468 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1469 WCD934X_CDC_SWR_CLK_EN_MASK, 1470 WCD934X_CDC_SWR_CLK_ENABLE); 1471 } else { 1472 regmap_update_bits(wcd->regmap, 1473 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1474 WCD934X_CDC_SWR_CLK_EN_MASK, 0); 1475 __wcd934x_cdc_mclk_enable(wcd, false); 1476 } 1477 1478 return 0; 1479 } 1480 1481 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1482 u8 rate_val, u32 rate) 1483 { 1484 struct snd_soc_component *comp = dai->component; 1485 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1486 struct wcd934x_slim_ch *ch; 1487 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1488 int inp, j; 1489 1490 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1491 inp = ch->shift + INTn_1_INP_SEL_RX0; 1492 /* 1493 * Loop through all interpolator MUX inputs and find out 1494 * to which interpolator input, the slim rx port 1495 * is connected 1496 */ 1497 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1498 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1499 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1500 continue; 1501 1502 cfg0 = snd_soc_component_read(comp, 1503 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1504 cfg1 = snd_soc_component_read(comp, 1505 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1506 1507 inp0_sel = cfg0 & 1508 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1509 inp1_sel = (cfg0 >> 4) & 1510 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1511 inp2_sel = (cfg1 >> 4) & 1512 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1513 1514 if ((inp0_sel == inp) || (inp1_sel == inp) || 1515 (inp2_sel == inp)) { 1516 /* rate is in Hz */ 1517 /* 1518 * Ear and speaker primary path does not support 1519 * native sample rates 1520 */ 1521 if ((j == INTERP_EAR || j == INTERP_SPKR1 || 1522 j == INTERP_SPKR2) && rate == 44100) 1523 dev_err(wcd->dev, 1524 "Cannot set 44.1KHz on INT%d\n", 1525 j); 1526 else 1527 snd_soc_component_update_bits(comp, 1528 WCD934X_CDC_RX_PATH_CTL(j), 1529 WCD934X_CDC_MIX_PCM_RATE_MASK, 1530 rate_val); 1531 } 1532 } 1533 } 1534 1535 return 0; 1536 } 1537 1538 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1539 int rate_val, u32 rate) 1540 { 1541 struct snd_soc_component *component = dai->component; 1542 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 1543 struct wcd934x_slim_ch *ch; 1544 int val, j; 1545 1546 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1547 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1548 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1549 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1550 continue; 1551 val = snd_soc_component_read(component, 1552 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1553 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1554 1555 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) { 1556 /* 1557 * Ear mix path supports only 48, 96, 192, 1558 * 384KHz only 1559 */ 1560 if ((j == INTERP_EAR) && 1561 (rate_val < 0x4 || 1562 rate_val > 0x7)) { 1563 dev_err(component->dev, 1564 "Invalid rate for AIF_PB DAI(%d)\n", 1565 dai->id); 1566 return -EINVAL; 1567 } 1568 1569 snd_soc_component_update_bits(component, 1570 WCD934X_CDC_RX_PATH_MIX_CTL(j), 1571 WCD934X_CDC_MIX_PCM_RATE_MASK, 1572 rate_val); 1573 } 1574 } 1575 } 1576 1577 return 0; 1578 } 1579 1580 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai, 1581 u32 sample_rate) 1582 { 1583 int rate_val = 0; 1584 int i, ret; 1585 1586 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) { 1587 if (sample_rate == sr_val_tbl[i].sample_rate) { 1588 rate_val = sr_val_tbl[i].rate_val; 1589 break; 1590 } 1591 } 1592 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) { 1593 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate); 1594 return -EINVAL; 1595 } 1596 1597 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val, 1598 sample_rate); 1599 if (ret) 1600 return ret; 1601 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val, 1602 sample_rate); 1603 1604 return ret; 1605 } 1606 1607 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai, 1608 u8 rate_val, u32 rate) 1609 { 1610 struct snd_soc_component *comp = dai->component; 1611 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 1612 u8 shift = 0, shift_val = 0, tx_mux_sel; 1613 struct wcd934x_slim_ch *ch; 1614 int tx_port, tx_port_reg; 1615 int decimator = -1; 1616 1617 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1618 tx_port = ch->port; 1619 /* Find the SB TX MUX input - which decimator is connected */ 1620 switch (tx_port) { 1621 case 0 ... 3: 1622 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0; 1623 shift = (tx_port << 1); 1624 shift_val = 0x03; 1625 break; 1626 case 4 ... 7: 1627 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1; 1628 shift = ((tx_port - 4) << 1); 1629 shift_val = 0x03; 1630 break; 1631 case 8 ... 10: 1632 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2; 1633 shift = ((tx_port - 8) << 1); 1634 shift_val = 0x03; 1635 break; 1636 case 11: 1637 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1638 shift = 0; 1639 shift_val = 0x0F; 1640 break; 1641 case 13: 1642 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1643 shift = 4; 1644 shift_val = 0x03; 1645 break; 1646 default: 1647 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1648 tx_port, dai->id); 1649 return -EINVAL; 1650 } 1651 1652 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1653 (shift_val << shift); 1654 1655 tx_mux_sel = tx_mux_sel >> shift; 1656 switch (tx_port) { 1657 case 0 ... 8: 1658 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1659 decimator = tx_port; 1660 break; 1661 case 9 ... 10: 1662 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1663 decimator = ((tx_port == 9) ? 7 : 6); 1664 break; 1665 case 11: 1666 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1667 decimator = tx_mux_sel - 1; 1668 break; 1669 case 13: 1670 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1671 decimator = 5; 1672 break; 1673 default: 1674 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n", 1675 tx_port); 1676 return -EINVAL; 1677 } 1678 1679 snd_soc_component_update_bits(comp, 1680 WCD934X_CDC_TX_PATH_CTL(decimator), 1681 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1682 rate_val); 1683 } 1684 1685 return 0; 1686 } 1687 1688 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd, 1689 struct wcd_slim_codec_dai_data *dai_data, 1690 int direction) 1691 { 1692 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1693 struct slim_stream_config *cfg = &dai_data->sconfig; 1694 struct wcd934x_slim_ch *ch; 1695 u16 payload = 0; 1696 int ret, i; 1697 1698 cfg->ch_count = 0; 1699 cfg->direction = direction; 1700 cfg->port_mask = 0; 1701 1702 /* Configure slave interface device */ 1703 list_for_each_entry(ch, slim_ch_list, list) { 1704 cfg->ch_count++; 1705 payload |= 1 << ch->shift; 1706 cfg->port_mask |= BIT(ch->port); 1707 } 1708 1709 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1710 if (!cfg->chs) 1711 return -ENOMEM; 1712 1713 i = 0; 1714 list_for_each_entry(ch, slim_ch_list, list) { 1715 cfg->chs[i++] = ch->ch_num; 1716 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1717 /* write to interface device */ 1718 ret = regmap_write(wcd->if_regmap, 1719 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1720 payload); 1721 1722 if (ret < 0) 1723 goto err; 1724 1725 /* configure the slave port for water mark and enable*/ 1726 ret = regmap_write(wcd->if_regmap, 1727 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port), 1728 WCD934X_SLIM_WATER_MARK_VAL); 1729 if (ret < 0) 1730 goto err; 1731 } else { 1732 ret = regmap_write(wcd->if_regmap, 1733 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1734 payload & 0x00FF); 1735 if (ret < 0) 1736 goto err; 1737 1738 /* ports 8,9 */ 1739 ret = regmap_write(wcd->if_regmap, 1740 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1741 (payload & 0xFF00) >> 8); 1742 if (ret < 0) 1743 goto err; 1744 1745 /* configure the slave port for water mark and enable*/ 1746 ret = regmap_write(wcd->if_regmap, 1747 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port), 1748 WCD934X_SLIM_WATER_MARK_VAL); 1749 1750 if (ret < 0) 1751 goto err; 1752 } 1753 } 1754 1755 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM"); 1756 1757 return 0; 1758 1759 err: 1760 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1761 kfree(cfg->chs); 1762 cfg->chs = NULL; 1763 1764 return ret; 1765 } 1766 1767 static int wcd934x_hw_params(struct snd_pcm_substream *substream, 1768 struct snd_pcm_hw_params *params, 1769 struct snd_soc_dai *dai) 1770 { 1771 struct wcd934x_codec *wcd; 1772 int ret, tx_fs_rate = 0; 1773 1774 wcd = snd_soc_component_get_drvdata(dai->component); 1775 1776 switch (substream->stream) { 1777 case SNDRV_PCM_STREAM_PLAYBACK: 1778 ret = wcd934x_set_interpolator_rate(dai, params_rate(params)); 1779 if (ret) { 1780 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1781 params_rate(params)); 1782 return ret; 1783 } 1784 switch (params_width(params)) { 1785 case 16 ... 24: 1786 wcd->dai[dai->id].sconfig.bps = params_width(params); 1787 break; 1788 default: 1789 dev_err(wcd->dev, "Invalid format 0x%x\n", 1790 params_width(params)); 1791 return -EINVAL; 1792 } 1793 break; 1794 1795 case SNDRV_PCM_STREAM_CAPTURE: 1796 switch (params_rate(params)) { 1797 case 8000: 1798 tx_fs_rate = 0; 1799 break; 1800 case 16000: 1801 tx_fs_rate = 1; 1802 break; 1803 case 32000: 1804 tx_fs_rate = 3; 1805 break; 1806 case 48000: 1807 tx_fs_rate = 4; 1808 break; 1809 case 96000: 1810 tx_fs_rate = 5; 1811 break; 1812 case 192000: 1813 tx_fs_rate = 6; 1814 break; 1815 case 384000: 1816 tx_fs_rate = 7; 1817 break; 1818 default: 1819 dev_err(wcd->dev, "Invalid TX sample rate: %d\n", 1820 params_rate(params)); 1821 return -EINVAL; 1822 1823 } 1824 1825 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate, 1826 params_rate(params)); 1827 if (ret < 0) { 1828 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1829 return ret; 1830 } 1831 switch (params_width(params)) { 1832 case 16 ... 32: 1833 wcd->dai[dai->id].sconfig.bps = params_width(params); 1834 break; 1835 default: 1836 dev_err(wcd->dev, "Invalid format 0x%x\n", 1837 params_width(params)); 1838 return -EINVAL; 1839 } 1840 break; 1841 default: 1842 dev_err(wcd->dev, "Invalid stream type %d\n", 1843 substream->stream); 1844 return -EINVAL; 1845 } 1846 1847 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1848 1849 return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1850 } 1851 1852 static int wcd934x_hw_free(struct snd_pcm_substream *substream, 1853 struct snd_soc_dai *dai) 1854 { 1855 struct wcd_slim_codec_dai_data *dai_data; 1856 struct wcd934x_codec *wcd; 1857 1858 wcd = snd_soc_component_get_drvdata(dai->component); 1859 1860 dai_data = &wcd->dai[dai->id]; 1861 1862 kfree(dai_data->sconfig.chs); 1863 1864 return 0; 1865 } 1866 1867 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd, 1868 struct snd_soc_dai *dai) 1869 { 1870 struct wcd_slim_codec_dai_data *dai_data; 1871 struct wcd934x_codec *wcd; 1872 struct slim_stream_config *cfg; 1873 1874 wcd = snd_soc_component_get_drvdata(dai->component); 1875 1876 dai_data = &wcd->dai[dai->id]; 1877 1878 switch (cmd) { 1879 case SNDRV_PCM_TRIGGER_START: 1880 case SNDRV_PCM_TRIGGER_RESUME: 1881 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1882 cfg = &dai_data->sconfig; 1883 slim_stream_prepare(dai_data->sruntime, cfg); 1884 slim_stream_enable(dai_data->sruntime); 1885 break; 1886 case SNDRV_PCM_TRIGGER_STOP: 1887 case SNDRV_PCM_TRIGGER_SUSPEND: 1888 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1889 slim_stream_disable(dai_data->sruntime); 1890 slim_stream_unprepare(dai_data->sruntime); 1891 break; 1892 default: 1893 break; 1894 } 1895 1896 return 0; 1897 } 1898 1899 static int wcd934x_set_channel_map(struct snd_soc_dai *dai, 1900 unsigned int tx_num, 1901 const unsigned int *tx_slot, 1902 unsigned int rx_num, 1903 const unsigned int *rx_slot) 1904 { 1905 struct wcd934x_codec *wcd; 1906 int i; 1907 1908 wcd = snd_soc_component_get_drvdata(dai->component); 1909 1910 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) { 1911 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n", 1912 tx_num, rx_num); 1913 return -EINVAL; 1914 } 1915 1916 if (!tx_slot || !rx_slot) { 1917 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1918 tx_slot, rx_slot); 1919 return -EINVAL; 1920 } 1921 1922 for (i = 0; i < rx_num; i++) { 1923 wcd->rx_chs[i].ch_num = rx_slot[i]; 1924 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 1925 } 1926 1927 for (i = 0; i < tx_num; i++) { 1928 wcd->tx_chs[i].ch_num = tx_slot[i]; 1929 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 1930 } 1931 1932 return 0; 1933 } 1934 1935 static int wcd934x_get_channel_map(const struct snd_soc_dai *dai, 1936 unsigned int *tx_num, unsigned int *tx_slot, 1937 unsigned int *rx_num, unsigned int *rx_slot) 1938 { 1939 struct wcd934x_slim_ch *ch; 1940 struct wcd934x_codec *wcd; 1941 int i = 0; 1942 1943 wcd = snd_soc_component_get_drvdata(dai->component); 1944 1945 switch (dai->id) { 1946 case AIF1_PB: 1947 case AIF2_PB: 1948 case AIF3_PB: 1949 case AIF4_PB: 1950 if (!rx_slot || !rx_num) { 1951 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 1952 rx_slot, rx_num); 1953 return -EINVAL; 1954 } 1955 1956 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1957 rx_slot[i++] = ch->ch_num; 1958 1959 *rx_num = i; 1960 break; 1961 case AIF1_CAP: 1962 case AIF2_CAP: 1963 case AIF3_CAP: 1964 if (!tx_slot || !tx_num) { 1965 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 1966 tx_slot, tx_num); 1967 return -EINVAL; 1968 } 1969 1970 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1971 tx_slot[i++] = ch->ch_num; 1972 1973 *tx_num = i; 1974 break; 1975 default: 1976 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 1977 break; 1978 } 1979 1980 return 0; 1981 } 1982 1983 static const struct snd_soc_dai_ops wcd934x_dai_ops = { 1984 .hw_params = wcd934x_hw_params, 1985 .hw_free = wcd934x_hw_free, 1986 .trigger = wcd934x_trigger, 1987 .set_channel_map = wcd934x_set_channel_map, 1988 .get_channel_map = wcd934x_get_channel_map, 1989 }; 1990 1991 static struct snd_soc_dai_driver wcd934x_slim_dais[] = { 1992 [0] = { 1993 .name = "wcd934x_rx1", 1994 .id = AIF1_PB, 1995 .playback = { 1996 .stream_name = "AIF1 Playback", 1997 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 1998 .formats = WCD934X_FORMATS_S16_S24_LE, 1999 .rate_max = 192000, 2000 .rate_min = 8000, 2001 .channels_min = 1, 2002 .channels_max = 2, 2003 }, 2004 .ops = &wcd934x_dai_ops, 2005 }, 2006 [1] = { 2007 .name = "wcd934x_tx1", 2008 .id = AIF1_CAP, 2009 .capture = { 2010 .stream_name = "AIF1 Capture", 2011 .rates = WCD934X_RATES_MASK, 2012 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2013 .rate_min = 8000, 2014 .rate_max = 192000, 2015 .channels_min = 1, 2016 .channels_max = 4, 2017 }, 2018 .ops = &wcd934x_dai_ops, 2019 }, 2020 [2] = { 2021 .name = "wcd934x_rx2", 2022 .id = AIF2_PB, 2023 .playback = { 2024 .stream_name = "AIF2 Playback", 2025 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2026 .formats = WCD934X_FORMATS_S16_S24_LE, 2027 .rate_min = 8000, 2028 .rate_max = 192000, 2029 .channels_min = 1, 2030 .channels_max = 2, 2031 }, 2032 .ops = &wcd934x_dai_ops, 2033 }, 2034 [3] = { 2035 .name = "wcd934x_tx2", 2036 .id = AIF2_CAP, 2037 .capture = { 2038 .stream_name = "AIF2 Capture", 2039 .rates = WCD934X_RATES_MASK, 2040 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2041 .rate_min = 8000, 2042 .rate_max = 192000, 2043 .channels_min = 1, 2044 .channels_max = 4, 2045 }, 2046 .ops = &wcd934x_dai_ops, 2047 }, 2048 [4] = { 2049 .name = "wcd934x_rx3", 2050 .id = AIF3_PB, 2051 .playback = { 2052 .stream_name = "AIF3 Playback", 2053 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2054 .formats = WCD934X_FORMATS_S16_S24_LE, 2055 .rate_min = 8000, 2056 .rate_max = 192000, 2057 .channels_min = 1, 2058 .channels_max = 2, 2059 }, 2060 .ops = &wcd934x_dai_ops, 2061 }, 2062 [5] = { 2063 .name = "wcd934x_tx3", 2064 .id = AIF3_CAP, 2065 .capture = { 2066 .stream_name = "AIF3 Capture", 2067 .rates = WCD934X_RATES_MASK, 2068 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2069 .rate_min = 8000, 2070 .rate_max = 192000, 2071 .channels_min = 1, 2072 .channels_max = 4, 2073 }, 2074 .ops = &wcd934x_dai_ops, 2075 }, 2076 [6] = { 2077 .name = "wcd934x_rx4", 2078 .id = AIF4_PB, 2079 .playback = { 2080 .stream_name = "AIF4 Playback", 2081 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2082 .formats = WCD934X_FORMATS_S16_S24_LE, 2083 .rate_min = 8000, 2084 .rate_max = 192000, 2085 .channels_min = 1, 2086 .channels_max = 2, 2087 }, 2088 .ops = &wcd934x_dai_ops, 2089 }, 2090 }; 2091 2092 static int swclk_gate_enable(struct clk_hw *hw) 2093 { 2094 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true); 2095 } 2096 2097 static void swclk_gate_disable(struct clk_hw *hw) 2098 { 2099 wcd934x_swrm_clock(to_wcd934x_codec(hw), false); 2100 } 2101 2102 static int swclk_gate_is_enabled(struct clk_hw *hw) 2103 { 2104 struct wcd934x_codec *wcd = to_wcd934x_codec(hw); 2105 int ret, val; 2106 2107 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val); 2108 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK; 2109 2110 return ret; 2111 } 2112 2113 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2114 unsigned long parent_rate) 2115 { 2116 return parent_rate / 2; 2117 } 2118 2119 static const struct clk_ops swclk_gate_ops = { 2120 .prepare = swclk_gate_enable, 2121 .unprepare = swclk_gate_disable, 2122 .is_enabled = swclk_gate_is_enabled, 2123 .recalc_rate = swclk_recalc_rate, 2124 2125 }; 2126 2127 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd) 2128 { 2129 struct clk *parent = wcd->extclk; 2130 struct device *dev = wcd->dev; 2131 struct device_node *np = dev->parent->of_node; 2132 const char *parent_clk_name = NULL; 2133 const char *clk_name = "mclk"; 2134 struct clk_hw *hw; 2135 struct clk_init_data init; 2136 int ret; 2137 2138 if (of_property_read_u32(np, "clock-frequency", &wcd->rate)) 2139 return NULL; 2140 2141 parent_clk_name = __clk_get_name(parent); 2142 2143 of_property_read_string(np, "clock-output-names", &clk_name); 2144 2145 init.name = clk_name; 2146 init.ops = &swclk_gate_ops; 2147 init.flags = 0; 2148 init.parent_names = &parent_clk_name; 2149 init.num_parents = 1; 2150 wcd->hw.init = &init; 2151 2152 hw = &wcd->hw; 2153 ret = devm_clk_hw_register(wcd->dev->parent, hw); 2154 if (ret) 2155 return ERR_PTR(ret); 2156 2157 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2158 if (ret) 2159 return ERR_PTR(ret); 2160 2161 return NULL; 2162 } 2163 2164 static int wcd934x_init_dmic(struct snd_soc_component *comp) 2165 { 2166 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 2167 u32 def_dmic_rate, dmic_clk_drv; 2168 int ret; 2169 2170 ret = wcd_dt_parse_micbias_info(&wcd->common); 2171 if (ret) 2172 return ret; 2173 2174 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1, 2175 WCD934X_MICB_VAL_MASK, wcd->common.micb_vout[0]); 2176 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2, 2177 WCD934X_MICB_VAL_MASK, wcd->common.micb_vout[1]); 2178 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3, 2179 WCD934X_MICB_VAL_MASK, wcd->common.micb_vout[2]); 2180 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4, 2181 WCD934X_MICB_VAL_MASK, wcd->common.micb_vout[3]); 2182 2183 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ) 2184 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 2185 else 2186 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ; 2187 2188 wcd->dmic_sample_rate = def_dmic_rate; 2189 2190 dmic_clk_drv = 0; 2191 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0, 2192 0x0C, dmic_clk_drv << 2); 2193 2194 return 0; 2195 } 2196 2197 static void wcd934x_hw_init(struct wcd934x_codec *wcd) 2198 { 2199 struct regmap *rm = wcd->regmap; 2200 2201 /* set SPKR rate to FS_2P4_3P072 */ 2202 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08); 2203 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08); 2204 2205 /* Take DMICs out of reset */ 2206 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00); 2207 } 2208 2209 static int wcd934x_comp_init(struct snd_soc_component *component) 2210 { 2211 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2212 2213 wcd934x_hw_init(wcd); 2214 wcd934x_enable_efuse_sensing(wcd); 2215 wcd934x_get_version(wcd); 2216 2217 return 0; 2218 } 2219 2220 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data) 2221 { 2222 struct wcd934x_codec *wcd = data; 2223 unsigned long status = 0; 2224 unsigned int i, j, port_id; 2225 unsigned int val, int_val = 0; 2226 irqreturn_t ret = IRQ_NONE; 2227 bool tx; 2228 unsigned short reg = 0; 2229 2230 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 2231 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 2232 regmap_read(wcd->if_regmap, i, &val); 2233 status |= ((u32)val << (8 * j)); 2234 } 2235 2236 for_each_set_bit(j, &status, 32) { 2237 tx = false; 2238 port_id = j; 2239 2240 if (j >= 16) { 2241 tx = true; 2242 port_id = j - 16; 2243 } 2244 2245 regmap_read(wcd->if_regmap, 2246 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 2247 if (val) { 2248 if (!tx) 2249 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2250 (port_id / 8); 2251 else 2252 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2253 (port_id / 8); 2254 regmap_read(wcd->if_regmap, reg, &int_val); 2255 } 2256 2257 if (val & WCD934X_SLIM_IRQ_OVERFLOW) 2258 dev_err_ratelimited(wcd->dev, 2259 "overflow error on %s port %d, value %x\n", 2260 (tx ? "TX" : "RX"), port_id, val); 2261 2262 if (val & WCD934X_SLIM_IRQ_UNDERFLOW) 2263 dev_err_ratelimited(wcd->dev, 2264 "underflow error on %s port %d, value %x\n", 2265 (tx ? "TX" : "RX"), port_id, val); 2266 2267 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) || 2268 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) { 2269 if (!tx) 2270 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2271 (port_id / 8); 2272 else 2273 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2274 (port_id / 8); 2275 regmap_read( 2276 wcd->if_regmap, reg, &int_val); 2277 if (int_val & (1 << (port_id % 8))) { 2278 int_val = int_val ^ (1 << (port_id % 8)); 2279 regmap_write(wcd->if_regmap, 2280 reg, int_val); 2281 } 2282 } 2283 2284 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED) 2285 dev_err_ratelimited(wcd->dev, 2286 "Port Closed %s port %d, value %x\n", 2287 (tx ? "TX" : "RX"), port_id, val); 2288 2289 regmap_write(wcd->if_regmap, 2290 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 2291 BIT(j % 8)); 2292 ret = IRQ_HANDLED; 2293 } 2294 2295 return ret; 2296 } 2297 2298 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component, 2299 bool enable) 2300 { 2301 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1, 2302 WCD934X_MBHC_CTL_RCO_EN_MASK, enable); 2303 } 2304 2305 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2306 bool enable) 2307 { 2308 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT, 2309 WCD934X_ANA_MBHC_BIAS_EN, enable); 2310 } 2311 2312 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component, 2313 int *btn_low, int *btn_high, 2314 int num_btn, bool is_micbias) 2315 { 2316 int i, vth; 2317 2318 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2319 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2320 __func__, num_btn); 2321 return; 2322 } 2323 2324 for (i = 0; i < num_btn; i++) { 2325 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2326 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i, 2327 WCD934X_MBHC_BTN_VTH_MASK, vth); 2328 } 2329 } 2330 2331 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2332 { 2333 u8 val; 2334 2335 if (micb_num == MIC_BIAS_2) { 2336 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2, 2337 WCD934X_ANA_MICB2_ENABLE_MASK); 2338 if (val == WCD934X_MICB_ENABLE) 2339 return true; 2340 } 2341 return false; 2342 } 2343 2344 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2345 enum mbhc_hs_pullup_iref pull_up_cur) 2346 { 2347 /* Default pull up current to 2uA */ 2348 if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA || 2349 pull_up_cur == I_DEFAULT) 2350 pull_up_cur = I_2P0_UA; 2351 2352 2353 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 2354 WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur); 2355 } 2356 2357 static int wcd934x_micbias_control(struct snd_soc_component *component, 2358 int micb_num, int req, bool is_dapm) 2359 { 2360 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2361 int micb_index = micb_num - 1; 2362 u16 micb_reg; 2363 2364 switch (micb_num) { 2365 case MIC_BIAS_1: 2366 micb_reg = WCD934X_ANA_MICB1; 2367 break; 2368 case MIC_BIAS_2: 2369 micb_reg = WCD934X_ANA_MICB2; 2370 break; 2371 case MIC_BIAS_3: 2372 micb_reg = WCD934X_ANA_MICB3; 2373 break; 2374 case MIC_BIAS_4: 2375 micb_reg = WCD934X_ANA_MICB4; 2376 break; 2377 default: 2378 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2379 __func__, micb_num); 2380 return -EINVAL; 2381 } 2382 guard(mutex)(&wcd934x->micb_lock); 2383 2384 switch (req) { 2385 case MICB_PULLUP_ENABLE: 2386 wcd934x->pullup_ref[micb_index]++; 2387 if ((wcd934x->pullup_ref[micb_index] == 1) && 2388 (wcd934x->micb_ref[micb_index] == 0)) 2389 snd_soc_component_write_field(component, micb_reg, 2390 WCD934X_ANA_MICB_EN_MASK, 2391 WCD934X_MICB_PULL_UP); 2392 break; 2393 case MICB_PULLUP_DISABLE: 2394 if (wcd934x->pullup_ref[micb_index] > 0) 2395 wcd934x->pullup_ref[micb_index]--; 2396 2397 if ((wcd934x->pullup_ref[micb_index] == 0) && 2398 (wcd934x->micb_ref[micb_index] == 0)) 2399 snd_soc_component_write_field(component, micb_reg, 2400 WCD934X_ANA_MICB_EN_MASK, 0); 2401 break; 2402 case MICB_ENABLE: 2403 wcd934x->micb_ref[micb_index]++; 2404 if (wcd934x->micb_ref[micb_index] == 1) { 2405 snd_soc_component_write_field(component, micb_reg, 2406 WCD934X_ANA_MICB_EN_MASK, 2407 WCD934X_MICB_ENABLE); 2408 if (micb_num == MIC_BIAS_2) 2409 wcd_mbhc_event_notify(wcd934x->mbhc, 2410 WCD_EVENT_POST_MICBIAS_2_ON); 2411 } 2412 2413 if (micb_num == MIC_BIAS_2 && is_dapm) 2414 wcd_mbhc_event_notify(wcd934x->mbhc, 2415 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2416 break; 2417 case MICB_DISABLE: 2418 if (wcd934x->micb_ref[micb_index] > 0) 2419 wcd934x->micb_ref[micb_index]--; 2420 2421 if ((wcd934x->micb_ref[micb_index] == 0) && 2422 (wcd934x->pullup_ref[micb_index] > 0)) 2423 snd_soc_component_write_field(component, micb_reg, 2424 WCD934X_ANA_MICB_EN_MASK, 2425 WCD934X_MICB_PULL_UP); 2426 else if ((wcd934x->micb_ref[micb_index] == 0) && 2427 (wcd934x->pullup_ref[micb_index] == 0)) { 2428 if (micb_num == MIC_BIAS_2) 2429 wcd_mbhc_event_notify(wcd934x->mbhc, 2430 WCD_EVENT_PRE_MICBIAS_2_OFF); 2431 2432 snd_soc_component_write_field(component, micb_reg, 2433 WCD934X_ANA_MICB_EN_MASK, 0); 2434 if (micb_num == MIC_BIAS_2) 2435 wcd_mbhc_event_notify(wcd934x->mbhc, 2436 WCD_EVENT_POST_MICBIAS_2_OFF); 2437 } 2438 if (is_dapm && micb_num == MIC_BIAS_2) 2439 wcd_mbhc_event_notify(wcd934x->mbhc, 2440 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2441 break; 2442 } 2443 2444 return 0; 2445 } 2446 2447 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component, 2448 int micb_num, int req) 2449 { 2450 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2451 int ret; 2452 2453 if (req == MICB_ENABLE) 2454 __wcd934x_cdc_mclk_enable(wcd, true); 2455 2456 ret = wcd934x_micbias_control(component, micb_num, req, false); 2457 2458 if (req == MICB_DISABLE) 2459 __wcd934x_cdc_mclk_enable(wcd, false); 2460 2461 return ret; 2462 } 2463 2464 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2465 bool enable) 2466 { 2467 if (enable) { 2468 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2469 WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3); 2470 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2471 WCD934X_RAMP_EN_MASK, 1); 2472 } else { 2473 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2474 WCD934X_RAMP_EN_MASK, 0); 2475 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2476 WCD934X_RAMP_SHIFT_CTRL_MASK, 0); 2477 } 2478 } 2479 2480 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 2481 int req_volt, int micb_num) 2482 { 2483 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2484 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en; 2485 2486 switch (micb_num) { 2487 case MIC_BIAS_1: 2488 micb_reg = WCD934X_ANA_MICB1; 2489 break; 2490 case MIC_BIAS_2: 2491 micb_reg = WCD934X_ANA_MICB2; 2492 break; 2493 case MIC_BIAS_3: 2494 micb_reg = WCD934X_ANA_MICB3; 2495 break; 2496 case MIC_BIAS_4: 2497 micb_reg = WCD934X_ANA_MICB4; 2498 break; 2499 default: 2500 return -EINVAL; 2501 } 2502 guard(mutex)(&wcd934x->micb_lock); 2503 /* 2504 * If requested micbias voltage is same as current micbias 2505 * voltage, then just return. Otherwise, adjust voltage as 2506 * per requested value. If micbias is already enabled, then 2507 * to avoid slow micbias ramp-up or down enable pull-up 2508 * momentarily, change the micbias value and then re-enable 2509 * micbias. 2510 */ 2511 micb_en = snd_soc_component_read_field(component, micb_reg, 2512 WCD934X_ANA_MICB_EN_MASK); 2513 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2514 WCD934X_MICB_VAL_MASK); 2515 2516 req_vout_ctl = wcd_get_micb_vout_ctl_val(component->dev, req_volt); 2517 if (req_vout_ctl < 0) 2518 return -EINVAL; 2519 2520 if (cur_vout_ctl == req_vout_ctl) 2521 return 0; 2522 2523 if (micb_en == WCD934X_MICB_ENABLE) 2524 snd_soc_component_write_field(component, micb_reg, 2525 WCD934X_ANA_MICB_EN_MASK, 2526 WCD934X_MICB_PULL_UP); 2527 2528 snd_soc_component_write_field(component, micb_reg, 2529 WCD934X_MICB_VAL_MASK, 2530 req_vout_ctl); 2531 2532 if (micb_en == WCD934X_MICB_ENABLE) { 2533 snd_soc_component_write_field(component, micb_reg, 2534 WCD934X_ANA_MICB_EN_MASK, 2535 WCD934X_MICB_ENABLE); 2536 /* 2537 * Add 2ms delay as per HW requirement after enabling 2538 * micbias 2539 */ 2540 usleep_range(2000, 2100); 2541 } 2542 2543 return 0; 2544 } 2545 2546 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2547 int micb_num, bool req_en) 2548 { 2549 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2550 int rc, micb_mv; 2551 2552 if (micb_num != MIC_BIAS_2) 2553 return -EINVAL; 2554 /* 2555 * If device tree micbias level is already above the minimum 2556 * voltage needed to detect threshold microphone, then do 2557 * not change the micbias, just return. 2558 */ 2559 if (wcd934x->common.micb_mv[1] >= WCD_MBHC_THR_HS_MICB_MV) 2560 return 0; 2561 2562 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->common.micb_mv[1]; 2563 2564 rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2565 2566 return rc; 2567 } 2568 2569 static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x, 2570 s16 *d1_a, u16 noff, 2571 int32_t *zdet) 2572 { 2573 int i; 2574 int val, val1; 2575 s16 c1; 2576 s32 x1, d1; 2577 int32_t denom; 2578 static const int minCode_param[] = { 2579 3277, 1639, 820, 410, 205, 103, 52, 26 2580 }; 2581 2582 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20); 2583 for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) { 2584 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val); 2585 if (val & 0x80) 2586 break; 2587 } 2588 val = val << 0x8; 2589 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1); 2590 val |= val1; 2591 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00); 2592 x1 = WCD934X_MBHC_GET_X1(val); 2593 c1 = WCD934X_MBHC_GET_C1(val); 2594 /* If ramp is not complete, give additional 5ms */ 2595 if ((c1 < 2) && x1) 2596 usleep_range(5000, 5050); 2597 2598 if (!c1 || !x1) { 2599 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2600 __func__, c1, x1); 2601 goto ramp_down; 2602 } 2603 d1 = d1_a[c1]; 2604 denom = (x1 * d1) - (1 << (14 - noff)); 2605 if (denom > 0) 2606 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom; 2607 else if (x1 < minCode_param[noff]) 2608 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE; 2609 2610 dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n", 2611 __func__, d1, c1, x1, *zdet); 2612 ramp_down: 2613 i = 0; 2614 2615 while (x1) { 2616 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val); 2617 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1); 2618 val = val << 0x08; 2619 val |= val1; 2620 x1 = WCD934X_MBHC_GET_X1(val); 2621 i++; 2622 if (i == WCD934X_ZDET_NUM_MEASUREMENTS) 2623 break; 2624 } 2625 } 2626 2627 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component, 2628 struct wcd934x_mbhc_zdet_param *zdet_param, 2629 int32_t *zl, int32_t *zr, s16 *d1_a) 2630 { 2631 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2632 int32_t zdet = 0; 2633 2634 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2635 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2636 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5, 2637 WCD934X_VTH_MASK, zdet_param->btn5); 2638 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6, 2639 WCD934X_VTH_MASK, zdet_param->btn6); 2640 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7, 2641 WCD934X_VTH_MASK, zdet_param->btn7); 2642 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2643 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2644 snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL, 2645 0x0F, zdet_param->nshift); 2646 2647 if (!zl) 2648 goto z_right; 2649 /* Start impedance measurement for HPH_L */ 2650 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80); 2651 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2652 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00); 2653 2654 *zl = zdet; 2655 2656 z_right: 2657 if (!zr) 2658 return; 2659 /* Start impedance measurement for HPH_R */ 2660 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40); 2661 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2662 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00); 2663 2664 *zr = zdet; 2665 } 2666 2667 static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2668 int32_t *z_val, int flag_l_r) 2669 { 2670 s16 q1; 2671 int q1_cal; 2672 2673 if (*z_val < (WCD934X_ZDET_VAL_400/1000)) 2674 q1 = snd_soc_component_read(component, 2675 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r)); 2676 else 2677 q1 = snd_soc_component_read(component, 2678 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r)); 2679 if (q1 & 0x80) 2680 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2681 else 2682 q1_cal = (10000 + (q1 * 25)); 2683 if (q1_cal > 0) 2684 *z_val = ((*z_val) * 10000) / q1_cal; 2685 } 2686 2687 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2688 uint32_t *zl, uint32_t *zr) 2689 { 2690 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2691 s16 reg0, reg1, reg2, reg3, reg4; 2692 int32_t z1L, z1R, z1Ls; 2693 int zMono, z_diff1, z_diff2; 2694 bool is_fsm_disable = false; 2695 struct wcd934x_mbhc_zdet_param zdet_param[] = { 2696 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2697 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2698 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2699 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2700 }; 2701 struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL; 2702 s16 d1_a[][4] = { 2703 {0, 30, 90, 30}, 2704 {0, 30, 30, 5}, 2705 {0, 30, 30, 5}, 2706 {0, 30, 30, 5}, 2707 }; 2708 s16 *d1 = NULL; 2709 2710 reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5); 2711 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6); 2712 reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7); 2713 reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK); 2714 reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL); 2715 2716 if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) { 2717 is_fsm_disable = true; 2718 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00); 2719 } 2720 2721 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2722 if (wcd934x->mbhc_cfg.hphl_swh) 2723 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00); 2724 2725 /* Turn off 100k pull down on HPHL */ 2726 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00); 2727 2728 /* First get impedance on Left */ 2729 d1 = d1_a[1]; 2730 zdet_param_ptr = &zdet_param[1]; 2731 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2732 2733 if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2734 goto left_ch_impedance; 2735 2736 /* Second ramp for left ch */ 2737 if (z1L < WCD934X_ZDET_VAL_32) { 2738 zdet_param_ptr = &zdet_param[0]; 2739 d1 = d1_a[0]; 2740 } else if ((z1L > WCD934X_ZDET_VAL_400) && 2741 (z1L <= WCD934X_ZDET_VAL_1200)) { 2742 zdet_param_ptr = &zdet_param[2]; 2743 d1 = d1_a[2]; 2744 } else if (z1L > WCD934X_ZDET_VAL_1200) { 2745 zdet_param_ptr = &zdet_param[3]; 2746 d1 = d1_a[3]; 2747 } 2748 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2749 2750 left_ch_impedance: 2751 if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2752 (z1L > WCD934X_ZDET_VAL_100K)) { 2753 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE; 2754 zdet_param_ptr = &zdet_param[1]; 2755 d1 = d1_a[1]; 2756 } else { 2757 *zl = z1L/1000; 2758 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0); 2759 } 2760 dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2761 __func__, *zl); 2762 2763 /* Start of right impedance ramp and calculation */ 2764 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2765 if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2766 if (((z1R > WCD934X_ZDET_VAL_1200) && 2767 (zdet_param_ptr->noff == 0x6)) || 2768 ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE)) 2769 goto right_ch_impedance; 2770 /* Second ramp for right ch */ 2771 if (z1R < WCD934X_ZDET_VAL_32) { 2772 zdet_param_ptr = &zdet_param[0]; 2773 d1 = d1_a[0]; 2774 } else if ((z1R > WCD934X_ZDET_VAL_400) && 2775 (z1R <= WCD934X_ZDET_VAL_1200)) { 2776 zdet_param_ptr = &zdet_param[2]; 2777 d1 = d1_a[2]; 2778 } else if (z1R > WCD934X_ZDET_VAL_1200) { 2779 zdet_param_ptr = &zdet_param[3]; 2780 d1 = d1_a[3]; 2781 } 2782 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2783 } 2784 right_ch_impedance: 2785 if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2786 (z1R > WCD934X_ZDET_VAL_100K)) { 2787 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE; 2788 } else { 2789 *zr = z1R/1000; 2790 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1); 2791 } 2792 dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2793 __func__, *zr); 2794 2795 /* Mono/stereo detection */ 2796 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) && 2797 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) { 2798 dev_dbg(component->dev, 2799 "%s: plug type is invalid or extension cable\n", 2800 __func__); 2801 goto zdet_complete; 2802 } 2803 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2804 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2805 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2806 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2807 dev_dbg(component->dev, 2808 "%s: Mono plug type with one ch floating or shorted to GND\n", 2809 __func__); 2810 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2811 goto zdet_complete; 2812 } 2813 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2814 WCD934X_HPHPA_GND_OVR_MASK, 1); 2815 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2816 WCD934X_HPHPA_GND_R_MASK, 1); 2817 if (*zl < (WCD934X_ZDET_VAL_32/1000)) 2818 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2819 else 2820 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2821 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2822 WCD934X_HPHPA_GND_R_MASK, 0); 2823 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2824 WCD934X_HPHPA_GND_OVR_MASK, 0); 2825 z1Ls /= 1000; 2826 wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2827 /* Parallel of left Z and 9 ohm pull down resistor */ 2828 zMono = ((*zl) * 9) / ((*zl) + 9); 2829 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2830 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2831 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2832 dev_err(component->dev, "%s: stereo plug type detected\n", 2833 __func__); 2834 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO); 2835 } else { 2836 dev_err(component->dev, "%s: MONO plug type detected\n", 2837 __func__); 2838 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2839 } 2840 2841 zdet_complete: 2842 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0); 2843 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1); 2844 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2); 2845 /* Turn on 100k pull down on HPHL */ 2846 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01); 2847 2848 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2849 if (wcd934x->mbhc_cfg.hphl_swh) 2850 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80); 2851 2852 snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2853 snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3); 2854 if (is_fsm_disable) 2855 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80); 2856 } 2857 2858 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2859 bool enable) 2860 { 2861 if (enable) { 2862 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2863 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1); 2864 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2865 WCD934X_MBHC_GND_DET_EN_MASK, 1); 2866 } else { 2867 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2868 WCD934X_MBHC_GND_DET_EN_MASK, 0); 2869 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2870 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0); 2871 } 2872 } 2873 2874 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2875 bool enable) 2876 { 2877 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2878 WCD934X_HPHPA_GND_R_MASK, enable); 2879 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2880 WCD934X_HPHPA_GND_L_MASK, enable); 2881 } 2882 2883 static const struct wcd_mbhc_cb mbhc_cb = { 2884 .clk_setup = wcd934x_mbhc_clk_setup, 2885 .mbhc_bias = wcd934x_mbhc_mbhc_bias_control, 2886 .set_btn_thr = wcd934x_mbhc_program_btn_thr, 2887 .micbias_enable_status = wcd934x_mbhc_micb_en_status, 2888 .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control, 2889 .mbhc_micbias_control = wcd934x_mbhc_request_micbias, 2890 .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control, 2891 .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic, 2892 .compute_impedance = wcd934x_wcd_mbhc_calc_impedance, 2893 .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl, 2894 .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl, 2895 }; 2896 2897 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol, 2898 struct snd_ctl_elem_value *ucontrol) 2899 { 2900 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2901 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2902 2903 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc); 2904 2905 return 0; 2906 } 2907 2908 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2909 struct snd_ctl_elem_value *ucontrol) 2910 { 2911 uint32_t zl, zr; 2912 bool hphr; 2913 struct soc_mixer_control *mc; 2914 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2915 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2916 2917 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2918 hphr = mc->shift; 2919 wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr); 2920 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2921 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2922 2923 return 0; 2924 } 2925 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2926 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 2927 wcd934x_get_hph_type, NULL), 2928 }; 2929 2930 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2931 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2932 wcd934x_hph_impedance_get, NULL), 2933 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2934 wcd934x_hph_impedance_get, NULL), 2935 }; 2936 2937 static int wcd934x_mbhc_init(struct snd_soc_component *component) 2938 { 2939 struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent); 2940 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2941 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids; 2942 2943 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data, 2944 WCD934X_IRQ_MBHC_SW_DET); 2945 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data, 2946 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET); 2947 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data, 2948 WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET); 2949 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data, 2950 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2951 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data, 2952 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET); 2953 intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data, 2954 WCD934X_IRQ_HPH_PA_OCPL_FAULT); 2955 intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data, 2956 WCD934X_IRQ_HPH_PA_OCPR_FAULT); 2957 2958 wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2959 if (IS_ERR(wcd->mbhc)) { 2960 wcd->mbhc = NULL; 2961 return -EINVAL; 2962 } 2963 2964 snd_soc_add_component_controls(component, impedance_detect_controls, 2965 ARRAY_SIZE(impedance_detect_controls)); 2966 snd_soc_add_component_controls(component, hph_type_detect_controls, 2967 ARRAY_SIZE(hph_type_detect_controls)); 2968 2969 return 0; 2970 } 2971 2972 static void wcd934x_mbhc_deinit(struct snd_soc_component *component) 2973 { 2974 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2975 2976 if (!wcd->mbhc) 2977 return; 2978 2979 wcd_mbhc_deinit(wcd->mbhc); 2980 } 2981 2982 static int wcd934x_comp_probe(struct snd_soc_component *component) 2983 { 2984 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2985 int i, ret; 2986 2987 snd_soc_component_init_regmap(component, wcd->regmap); 2988 wcd->component = component; 2989 2990 /* Class-H Init*/ 2991 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version); 2992 if (IS_ERR(wcd->clsh_ctrl)) 2993 return PTR_ERR(wcd->clsh_ctrl); 2994 2995 /* Default HPH Mode to Class-H Low HiFi */ 2996 wcd->hph_mode = CLS_H_LOHIFI; 2997 2998 wcd934x_comp_init(component); 2999 3000 for (i = 0; i < NUM_CODEC_DAIS; i++) 3001 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 3002 3003 3004 ret = wcd934x_init_dmic(component); 3005 if (ret) { 3006 dev_err(component->dev, "Failed to Initialize micbias\n"); 3007 return ret; 3008 } 3009 3010 if (wcd934x_mbhc_init(component)) 3011 dev_err(component->dev, "Failed to Initialize MBHC\n"); 3012 3013 return 0; 3014 } 3015 3016 static void wcd934x_comp_remove(struct snd_soc_component *comp) 3017 { 3018 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3019 3020 wcd934x_mbhc_deinit(comp); 3021 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 3022 } 3023 3024 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp, 3025 int clk_id, int source, 3026 unsigned int freq, int dir) 3027 { 3028 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3029 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ; 3030 3031 wcd->rate = freq; 3032 3033 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ) 3034 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ; 3035 3036 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 3037 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 3038 val); 3039 3040 return clk_set_rate(wcd->extclk, freq); 3041 } 3042 3043 static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 3044 int iir_idx, int band_idx, int coeff_idx) 3045 { 3046 u32 value = 0; 3047 int reg, b2_reg; 3048 3049 /* Address does not automatically update if reading */ 3050 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3051 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3052 3053 snd_soc_component_write(component, reg, 3054 ((band_idx * BAND_MAX + coeff_idx) * 3055 sizeof(uint32_t)) & 0x7F); 3056 3057 value |= snd_soc_component_read(component, b2_reg); 3058 snd_soc_component_write(component, reg, 3059 ((band_idx * BAND_MAX + coeff_idx) 3060 * sizeof(uint32_t) + 1) & 0x7F); 3061 3062 value |= (snd_soc_component_read(component, b2_reg) << 8); 3063 snd_soc_component_write(component, reg, 3064 ((band_idx * BAND_MAX + coeff_idx) 3065 * sizeof(uint32_t) + 2) & 0x7F); 3066 3067 value |= (snd_soc_component_read(component, b2_reg) << 16); 3068 snd_soc_component_write(component, reg, 3069 ((band_idx * BAND_MAX + coeff_idx) 3070 * sizeof(uint32_t) + 3) & 0x7F); 3071 3072 /* Mask bits top 2 bits since they are reserved */ 3073 value |= (snd_soc_component_read(component, b2_reg) << 24); 3074 return value; 3075 } 3076 3077 static void set_iir_band_coeff(struct snd_soc_component *component, 3078 int iir_idx, int band_idx, uint32_t value) 3079 { 3080 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3081 3082 snd_soc_component_write(component, reg, (value & 0xFF)); 3083 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 3084 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 3085 /* Mask top 2 bits, 7-8 are reserved */ 3086 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 3087 } 3088 3089 static int wcd934x_put_iir_band_audio_mixer( 3090 struct snd_kcontrol *kcontrol, 3091 struct snd_ctl_elem_value *ucontrol) 3092 { 3093 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3094 struct wcd_iir_filter_ctl *ctl = 3095 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3096 struct soc_bytes_ext *params = &ctl->bytes_ext; 3097 int iir_idx = ctl->iir_idx; 3098 int band_idx = ctl->band_idx; 3099 u32 coeff[BAND_MAX]; 3100 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3101 3102 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 3103 3104 /* Mask top bit it is reserved */ 3105 /* Updates addr automatically for each B2 write */ 3106 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 3107 sizeof(uint32_t)) & 0x7F); 3108 3109 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 3110 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 3111 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 3112 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 3113 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 3114 3115 return 0; 3116 } 3117 3118 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 3119 struct snd_ctl_elem_value *ucontrol) 3120 { 3121 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3122 struct wcd_iir_filter_ctl *ctl = 3123 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3124 struct soc_bytes_ext *params = &ctl->bytes_ext; 3125 int iir_idx = ctl->iir_idx; 3126 int band_idx = ctl->band_idx; 3127 u32 coeff[BAND_MAX]; 3128 3129 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 3130 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 3131 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 3132 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 3133 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 3134 3135 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 3136 3137 return 0; 3138 } 3139 3140 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol, 3141 struct snd_ctl_elem_info *ucontrol) 3142 { 3143 struct wcd_iir_filter_ctl *ctl = 3144 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3145 struct soc_bytes_ext *params = &ctl->bytes_ext; 3146 3147 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 3148 ucontrol->count = params->max; 3149 3150 return 0; 3151 } 3152 3153 static int wcd934x_compander_get(struct snd_kcontrol *kc, 3154 struct snd_ctl_elem_value *ucontrol) 3155 { 3156 struct snd_soc_component *component = snd_kcontrol_chip(kc); 3157 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3158 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3159 3160 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 3161 3162 return 0; 3163 } 3164 3165 static int wcd934x_compander_set(struct snd_kcontrol *kc, 3166 struct snd_ctl_elem_value *ucontrol) 3167 { 3168 struct snd_soc_component *component = snd_kcontrol_chip(kc); 3169 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3170 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3171 int value = ucontrol->value.integer.value[0]; 3172 int sel; 3173 3174 if (wcd->comp_enabled[comp] == value) 3175 return 0; 3176 3177 wcd->comp_enabled[comp] = value; 3178 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER : 3179 WCD934X_HPH_GAIN_SRC_SEL_REGISTER; 3180 3181 /* Any specific register configuration for compander */ 3182 switch (comp) { 3183 case COMPANDER_1: 3184 /* Set Gain Source Select based on compander enable/disable */ 3185 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN, 3186 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3187 sel); 3188 break; 3189 case COMPANDER_2: 3190 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN, 3191 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3192 sel); 3193 break; 3194 case COMPANDER_3: 3195 case COMPANDER_4: 3196 case COMPANDER_7: 3197 case COMPANDER_8: 3198 break; 3199 default: 3200 return 0; 3201 } 3202 3203 return 1; 3204 } 3205 3206 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc, 3207 struct snd_ctl_elem_value *ucontrol) 3208 { 3209 struct snd_soc_component *component = snd_kcontrol_chip(kc); 3210 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3211 3212 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 3213 3214 return 0; 3215 } 3216 3217 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc, 3218 struct snd_ctl_elem_value *ucontrol) 3219 { 3220 struct snd_soc_component *component = snd_kcontrol_chip(kc); 3221 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3222 u32 mode_val; 3223 3224 mode_val = ucontrol->value.enumerated.item[0]; 3225 3226 if (mode_val == wcd->hph_mode) 3227 return 0; 3228 3229 if (mode_val == 0) { 3230 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 3231 mode_val = CLS_H_LOHIFI; 3232 } 3233 wcd->hph_mode = mode_val; 3234 3235 return 1; 3236 } 3237 3238 static int slim_rx_mux_get(struct snd_kcontrol *kc, 3239 struct snd_ctl_elem_value *ucontrol) 3240 { 3241 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kc); 3242 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_to_widget(kc); 3243 struct device *dev = snd_soc_dapm_to_dev(dapm); 3244 struct wcd934x_codec *wcd = dev_get_drvdata(dev); 3245 3246 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift]; 3247 3248 return 0; 3249 } 3250 3251 static int slim_rx_mux_to_dai_id(int mux) 3252 { 3253 int aif_id; 3254 3255 switch (mux) { 3256 case 1: 3257 aif_id = AIF1_PB; 3258 break; 3259 case 2: 3260 aif_id = AIF2_PB; 3261 break; 3262 case 3: 3263 aif_id = AIF3_PB; 3264 break; 3265 case 4: 3266 aif_id = AIF4_PB; 3267 break; 3268 default: 3269 aif_id = -1; 3270 break; 3271 } 3272 3273 return aif_id; 3274 } 3275 3276 static int slim_rx_mux_put(struct snd_kcontrol *kc, 3277 struct snd_ctl_elem_value *ucontrol) 3278 { 3279 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_to_widget(kc); 3280 struct device *dev = snd_soc_dapm_to_dev(w->dapm); 3281 struct wcd934x_codec *wcd = dev_get_drvdata(dev); 3282 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3283 struct snd_soc_dapm_update *update = NULL; 3284 struct wcd934x_slim_ch *ch, *c; 3285 u32 port_id = w->shift; 3286 bool found = false; 3287 int mux_idx; 3288 int prev_mux_idx = wcd->rx_port_value[port_id]; 3289 int aif_id; 3290 3291 mux_idx = ucontrol->value.enumerated.item[0]; 3292 3293 if (mux_idx == prev_mux_idx) 3294 return 0; 3295 3296 switch(mux_idx) { 3297 case 0: 3298 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx); 3299 if (aif_id < 0) 3300 return 0; 3301 3302 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) { 3303 if (ch->port == port_id + WCD934X_RX_START) { 3304 found = true; 3305 list_del_init(&ch->list); 3306 break; 3307 } 3308 } 3309 if (!found) 3310 return 0; 3311 3312 break; 3313 case 1 ... 4: 3314 aif_id = slim_rx_mux_to_dai_id(mux_idx); 3315 if (aif_id < 0) 3316 return 0; 3317 3318 if (list_empty(&wcd->rx_chs[port_id].list)) { 3319 list_add_tail(&wcd->rx_chs[port_id].list, 3320 &wcd->dai[aif_id].slim_ch_list); 3321 } else { 3322 dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id); 3323 return 0; 3324 } 3325 break; 3326 3327 default: 3328 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx); 3329 goto err; 3330 } 3331 3332 wcd->rx_port_value[port_id] = mux_idx; 3333 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 3334 e, update); 3335 3336 return 1; 3337 err: 3338 return -EINVAL; 3339 } 3340 3341 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc, 3342 struct snd_ctl_elem_value *ucontrol) 3343 { 3344 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3345 struct snd_soc_component *component; 3346 int reg, val; 3347 3348 component = snd_soc_dapm_kcontrol_to_component(kc); 3349 val = ucontrol->value.enumerated.item[0]; 3350 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0) 3351 reg = WCD934X_CDC_RX0_RX_PATH_CFG0; 3352 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0) 3353 reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 3354 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0) 3355 reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 3356 else 3357 return -EINVAL; 3358 3359 /* Set Look Ahead Delay */ 3360 if (val) 3361 snd_soc_component_update_bits(component, reg, 3362 WCD934X_RX_DLY_ZN_EN_MASK, 3363 WCD934X_RX_DLY_ZN_ENABLE); 3364 else 3365 snd_soc_component_update_bits(component, reg, 3366 WCD934X_RX_DLY_ZN_EN_MASK, 3367 WCD934X_RX_DLY_ZN_DISABLE); 3368 3369 return snd_soc_dapm_put_enum_double(kc, ucontrol); 3370 } 3371 3372 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol, 3373 struct snd_ctl_elem_value *ucontrol) 3374 { 3375 struct snd_soc_component *comp; 3376 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 3377 unsigned int val; 3378 u16 mic_sel_reg = 0; 3379 u8 mic_sel; 3380 3381 comp = snd_soc_dapm_kcontrol_to_component(kcontrol); 3382 3383 val = ucontrol->value.enumerated.item[0]; 3384 if (val > e->items - 1) 3385 return -EINVAL; 3386 3387 switch (e->reg) { 3388 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 3389 if (e->shift_l == 0) 3390 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0; 3391 else if (e->shift_l == 2) 3392 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0; 3393 else if (e->shift_l == 4) 3394 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0; 3395 break; 3396 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 3397 if (e->shift_l == 0) 3398 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0; 3399 else if (e->shift_l == 2) 3400 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0; 3401 break; 3402 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 3403 if (e->shift_l == 0) 3404 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0; 3405 else if (e->shift_l == 2) 3406 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0; 3407 break; 3408 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 3409 if (e->shift_l == 0) 3410 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0; 3411 else if (e->shift_l == 2) 3412 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0; 3413 break; 3414 default: 3415 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n", 3416 __func__, e->reg); 3417 return -EINVAL; 3418 } 3419 3420 /* ADC: 0, DMIC: 1 */ 3421 mic_sel = val ? 0x0 : 0x1; 3422 if (mic_sel_reg) 3423 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7), 3424 mic_sel << 7); 3425 3426 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 3427 } 3428 3429 static const struct snd_kcontrol_new rx_int0_2_mux = 3430 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 3431 3432 static const struct snd_kcontrol_new rx_int1_2_mux = 3433 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 3434 3435 static const struct snd_kcontrol_new rx_int2_2_mux = 3436 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 3437 3438 static const struct snd_kcontrol_new rx_int3_2_mux = 3439 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 3440 3441 static const struct snd_kcontrol_new rx_int4_2_mux = 3442 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 3443 3444 static const struct snd_kcontrol_new rx_int7_2_mux = 3445 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 3446 3447 static const struct snd_kcontrol_new rx_int8_2_mux = 3448 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 3449 3450 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 3451 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 3452 3453 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 3454 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 3455 3456 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 3457 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 3458 3459 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 3460 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 3461 3462 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 3463 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 3464 3465 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 3466 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 3467 3468 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 3469 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 3470 3471 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 3472 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 3473 3474 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 3475 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 3476 3477 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 3478 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 3479 3480 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 3481 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 3482 3483 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 3484 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 3485 3486 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 3487 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 3488 3489 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 3490 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 3491 3492 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 3493 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 3494 3495 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 3496 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 3497 3498 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 3499 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 3500 3501 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 3502 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 3503 3504 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 3505 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 3506 3507 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 3508 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 3509 3510 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 3511 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 3512 3513 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 3514 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum); 3515 3516 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 3517 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum); 3518 3519 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 3520 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum); 3521 3522 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux = 3523 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum); 3524 3525 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux = 3526 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum); 3527 3528 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux = 3529 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum); 3530 3531 static const struct snd_kcontrol_new iir0_inp0_mux = 3532 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum); 3533 static const struct snd_kcontrol_new iir0_inp1_mux = 3534 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum); 3535 static const struct snd_kcontrol_new iir0_inp2_mux = 3536 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum); 3537 static const struct snd_kcontrol_new iir0_inp3_mux = 3538 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum); 3539 3540 static const struct snd_kcontrol_new iir1_inp0_mux = 3541 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum); 3542 static const struct snd_kcontrol_new iir1_inp1_mux = 3543 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); 3544 static const struct snd_kcontrol_new iir1_inp2_mux = 3545 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum); 3546 static const struct snd_kcontrol_new iir1_inp3_mux = 3547 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum); 3548 3549 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = { 3550 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 3551 slim_rx_mux_get, slim_rx_mux_put), 3552 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 3553 slim_rx_mux_get, slim_rx_mux_put), 3554 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 3555 slim_rx_mux_get, slim_rx_mux_put), 3556 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 3557 slim_rx_mux_get, slim_rx_mux_put), 3558 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 3559 slim_rx_mux_get, slim_rx_mux_put), 3560 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 3561 slim_rx_mux_get, slim_rx_mux_put), 3562 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 3563 slim_rx_mux_get, slim_rx_mux_put), 3564 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 3565 slim_rx_mux_get, slim_rx_mux_put), 3566 }; 3567 3568 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = { 3569 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0), 3570 }; 3571 3572 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = { 3573 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0), 3574 }; 3575 3576 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = { 3577 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0), 3578 }; 3579 3580 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = { 3581 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0), 3582 }; 3583 3584 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 3585 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 3586 snd_soc_dapm_get_enum_double, 3587 wcd934x_int_dem_inp_mux_put); 3588 3589 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 3590 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 3591 snd_soc_dapm_get_enum_double, 3592 wcd934x_int_dem_inp_mux_put); 3593 3594 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 3595 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 3596 snd_soc_dapm_get_enum_double, 3597 wcd934x_int_dem_inp_mux_put); 3598 3599 static const struct snd_kcontrol_new rx_int0_1_interp_mux = 3600 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum); 3601 3602 static const struct snd_kcontrol_new rx_int1_1_interp_mux = 3603 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum); 3604 3605 static const struct snd_kcontrol_new rx_int2_1_interp_mux = 3606 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum); 3607 3608 static const struct snd_kcontrol_new rx_int3_1_interp_mux = 3609 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum); 3610 3611 static const struct snd_kcontrol_new rx_int4_1_interp_mux = 3612 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum); 3613 3614 static const struct snd_kcontrol_new rx_int7_1_interp_mux = 3615 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum); 3616 3617 static const struct snd_kcontrol_new rx_int8_1_interp_mux = 3618 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum); 3619 3620 static const struct snd_kcontrol_new rx_int0_2_interp_mux = 3621 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum); 3622 3623 static const struct snd_kcontrol_new rx_int1_2_interp_mux = 3624 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum); 3625 3626 static const struct snd_kcontrol_new rx_int2_2_interp_mux = 3627 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum); 3628 3629 static const struct snd_kcontrol_new rx_int3_2_interp_mux = 3630 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum); 3631 3632 static const struct snd_kcontrol_new rx_int4_2_interp_mux = 3633 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum); 3634 3635 static const struct snd_kcontrol_new rx_int7_2_interp_mux = 3636 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum); 3637 3638 static const struct snd_kcontrol_new rx_int8_2_interp_mux = 3639 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum); 3640 3641 static const struct snd_kcontrol_new tx_dmic_mux0 = 3642 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 3643 3644 static const struct snd_kcontrol_new tx_dmic_mux1 = 3645 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 3646 3647 static const struct snd_kcontrol_new tx_dmic_mux2 = 3648 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 3649 3650 static const struct snd_kcontrol_new tx_dmic_mux3 = 3651 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 3652 3653 static const struct snd_kcontrol_new tx_dmic_mux4 = 3654 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 3655 3656 static const struct snd_kcontrol_new tx_dmic_mux5 = 3657 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 3658 3659 static const struct snd_kcontrol_new tx_dmic_mux6 = 3660 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 3661 3662 static const struct snd_kcontrol_new tx_dmic_mux7 = 3663 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 3664 3665 static const struct snd_kcontrol_new tx_dmic_mux8 = 3666 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 3667 3668 static const struct snd_kcontrol_new tx_amic_mux0 = 3669 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 3670 3671 static const struct snd_kcontrol_new tx_amic_mux1 = 3672 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 3673 3674 static const struct snd_kcontrol_new tx_amic_mux2 = 3675 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 3676 3677 static const struct snd_kcontrol_new tx_amic_mux3 = 3678 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 3679 3680 static const struct snd_kcontrol_new tx_amic_mux4 = 3681 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 3682 3683 static const struct snd_kcontrol_new tx_amic_mux5 = 3684 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 3685 3686 static const struct snd_kcontrol_new tx_amic_mux6 = 3687 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 3688 3689 static const struct snd_kcontrol_new tx_amic_mux7 = 3690 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 3691 3692 static const struct snd_kcontrol_new tx_amic_mux8 = 3693 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 3694 3695 static const struct snd_kcontrol_new tx_amic4_5 = 3696 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum); 3697 3698 static const struct snd_kcontrol_new tx_adc_mux0_mux = 3699 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum, 3700 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3701 static const struct snd_kcontrol_new tx_adc_mux1_mux = 3702 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum, 3703 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3704 static const struct snd_kcontrol_new tx_adc_mux2_mux = 3705 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum, 3706 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3707 static const struct snd_kcontrol_new tx_adc_mux3_mux = 3708 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum, 3709 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3710 static const struct snd_kcontrol_new tx_adc_mux4_mux = 3711 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum, 3712 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3713 static const struct snd_kcontrol_new tx_adc_mux5_mux = 3714 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum, 3715 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3716 static const struct snd_kcontrol_new tx_adc_mux6_mux = 3717 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum, 3718 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3719 static const struct snd_kcontrol_new tx_adc_mux7_mux = 3720 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum, 3721 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3722 static const struct snd_kcontrol_new tx_adc_mux8_mux = 3723 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum, 3724 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3725 3726 static const struct snd_kcontrol_new cdc_if_tx0_mux = 3727 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum); 3728 static const struct snd_kcontrol_new cdc_if_tx1_mux = 3729 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum); 3730 static const struct snd_kcontrol_new cdc_if_tx2_mux = 3731 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum); 3732 static const struct snd_kcontrol_new cdc_if_tx3_mux = 3733 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum); 3734 static const struct snd_kcontrol_new cdc_if_tx4_mux = 3735 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum); 3736 static const struct snd_kcontrol_new cdc_if_tx5_mux = 3737 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum); 3738 static const struct snd_kcontrol_new cdc_if_tx6_mux = 3739 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum); 3740 static const struct snd_kcontrol_new cdc_if_tx7_mux = 3741 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum); 3742 static const struct snd_kcontrol_new cdc_if_tx8_mux = 3743 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum); 3744 static const struct snd_kcontrol_new cdc_if_tx9_mux = 3745 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum); 3746 static const struct snd_kcontrol_new cdc_if_tx10_mux = 3747 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum); 3748 static const struct snd_kcontrol_new cdc_if_tx11_mux = 3749 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum); 3750 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux = 3751 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum); 3752 static const struct snd_kcontrol_new cdc_if_tx13_mux = 3753 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum); 3754 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux = 3755 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum); 3756 3757 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 3758 struct snd_ctl_elem_value *ucontrol) 3759 { 3760 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kc); 3761 struct device *dev = snd_soc_dapm_to_dev(dapm); 3762 struct wcd934x_codec *wcd = dev_get_drvdata(dev); 3763 struct soc_mixer_control *mixer = 3764 (struct soc_mixer_control *)kc->private_value; 3765 int port_id = mixer->shift; 3766 3767 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id]; 3768 3769 return 0; 3770 } 3771 3772 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 3773 struct snd_ctl_elem_value *ucontrol) 3774 { 3775 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kc); 3776 struct device *dev = snd_soc_dapm_to_dev(widget->dapm); 3777 struct wcd934x_codec *wcd = dev_get_drvdata(dev); 3778 struct snd_soc_dapm_update *update = NULL; 3779 struct soc_mixer_control *mixer = 3780 (struct soc_mixer_control *)kc->private_value; 3781 int enable = ucontrol->value.integer.value[0]; 3782 struct wcd934x_slim_ch *ch, *c; 3783 int dai_id = widget->shift; 3784 int port_id = mixer->shift; 3785 3786 /* only add to the list if value not set */ 3787 if (enable == wcd->tx_port_value[port_id]) 3788 return 0; 3789 3790 if (enable) { 3791 if (list_empty(&wcd->tx_chs[port_id].list)) { 3792 list_add_tail(&wcd->tx_chs[port_id].list, 3793 &wcd->dai[dai_id].slim_ch_list); 3794 } else { 3795 dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id); 3796 return 0; 3797 } 3798 } else { 3799 bool found = false; 3800 3801 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) { 3802 if (ch->port == port_id) { 3803 found = true; 3804 list_del_init(&wcd->tx_chs[port_id].list); 3805 break; 3806 } 3807 } 3808 if (!found) 3809 return 0; 3810 } 3811 3812 wcd->tx_port_value[port_id] = enable; 3813 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 3814 3815 return 1; 3816 } 3817 3818 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = { 3819 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3820 slim_tx_mixer_get, slim_tx_mixer_put), 3821 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3822 slim_tx_mixer_get, slim_tx_mixer_put), 3823 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3824 slim_tx_mixer_get, slim_tx_mixer_put), 3825 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3826 slim_tx_mixer_get, slim_tx_mixer_put), 3827 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3828 slim_tx_mixer_get, slim_tx_mixer_put), 3829 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3830 slim_tx_mixer_get, slim_tx_mixer_put), 3831 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3832 slim_tx_mixer_get, slim_tx_mixer_put), 3833 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3834 slim_tx_mixer_get, slim_tx_mixer_put), 3835 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3836 slim_tx_mixer_get, slim_tx_mixer_put), 3837 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3838 slim_tx_mixer_get, slim_tx_mixer_put), 3839 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3840 slim_tx_mixer_get, slim_tx_mixer_put), 3841 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3842 slim_tx_mixer_get, slim_tx_mixer_put), 3843 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3844 slim_tx_mixer_get, slim_tx_mixer_put), 3845 }; 3846 3847 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = { 3848 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3849 slim_tx_mixer_get, slim_tx_mixer_put), 3850 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3851 slim_tx_mixer_get, slim_tx_mixer_put), 3852 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3853 slim_tx_mixer_get, slim_tx_mixer_put), 3854 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3855 slim_tx_mixer_get, slim_tx_mixer_put), 3856 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3857 slim_tx_mixer_get, slim_tx_mixer_put), 3858 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3859 slim_tx_mixer_get, slim_tx_mixer_put), 3860 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3861 slim_tx_mixer_get, slim_tx_mixer_put), 3862 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3863 slim_tx_mixer_get, slim_tx_mixer_put), 3864 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3865 slim_tx_mixer_get, slim_tx_mixer_put), 3866 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3867 slim_tx_mixer_get, slim_tx_mixer_put), 3868 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3869 slim_tx_mixer_get, slim_tx_mixer_put), 3870 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3871 slim_tx_mixer_get, slim_tx_mixer_put), 3872 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3873 slim_tx_mixer_get, slim_tx_mixer_put), 3874 }; 3875 3876 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = { 3877 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3878 slim_tx_mixer_get, slim_tx_mixer_put), 3879 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3880 slim_tx_mixer_get, slim_tx_mixer_put), 3881 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3882 slim_tx_mixer_get, slim_tx_mixer_put), 3883 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3884 slim_tx_mixer_get, slim_tx_mixer_put), 3885 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3886 slim_tx_mixer_get, slim_tx_mixer_put), 3887 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3888 slim_tx_mixer_get, slim_tx_mixer_put), 3889 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3890 slim_tx_mixer_get, slim_tx_mixer_put), 3891 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3892 slim_tx_mixer_get, slim_tx_mixer_put), 3893 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3894 slim_tx_mixer_get, slim_tx_mixer_put), 3895 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3896 slim_tx_mixer_get, slim_tx_mixer_put), 3897 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3898 slim_tx_mixer_get, slim_tx_mixer_put), 3899 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3900 slim_tx_mixer_get, slim_tx_mixer_put), 3901 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3902 slim_tx_mixer_get, slim_tx_mixer_put), 3903 }; 3904 3905 static const struct snd_kcontrol_new wcd934x_snd_controls[] = { 3906 /* Gain Controls */ 3907 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain), 3908 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain), 3909 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain), 3910 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER, 3911 3, 16, 1, line_gain), 3912 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER, 3913 3, 16, 1, line_gain), 3914 3915 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain), 3916 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain), 3917 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain), 3918 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain), 3919 3920 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL, 3921 -84, 40, digital_gain), /* -84dB min - 40dB max */ 3922 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL, 3923 -84, 40, digital_gain), 3924 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL, 3925 -84, 40, digital_gain), 3926 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL, 3927 -84, 40, digital_gain), 3928 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL, 3929 -84, 40, digital_gain), 3930 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL, 3931 -84, 40, digital_gain), 3932 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL, 3933 -84, 40, digital_gain), 3934 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", 3935 WCD934X_CDC_RX0_RX_VOL_MIX_CTL, 3936 -84, 40, digital_gain), 3937 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", 3938 WCD934X_CDC_RX1_RX_VOL_MIX_CTL, 3939 -84, 40, digital_gain), 3940 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", 3941 WCD934X_CDC_RX2_RX_VOL_MIX_CTL, 3942 -84, 40, digital_gain), 3943 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", 3944 WCD934X_CDC_RX3_RX_VOL_MIX_CTL, 3945 -84, 40, digital_gain), 3946 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", 3947 WCD934X_CDC_RX4_RX_VOL_MIX_CTL, 3948 -84, 40, digital_gain), 3949 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", 3950 WCD934X_CDC_RX7_RX_VOL_MIX_CTL, 3951 -84, 40, digital_gain), 3952 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", 3953 WCD934X_CDC_RX8_RX_VOL_MIX_CTL, 3954 -84, 40, digital_gain), 3955 3956 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL, 3957 -84, 40, digital_gain), 3958 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL, 3959 -84, 40, digital_gain), 3960 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL, 3961 -84, 40, digital_gain), 3962 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL, 3963 -84, 40, digital_gain), 3964 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL, 3965 -84, 40, digital_gain), 3966 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL, 3967 -84, 40, digital_gain), 3968 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL, 3969 -84, 40, digital_gain), 3970 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL, 3971 -84, 40, digital_gain), 3972 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL, 3973 -84, 40, digital_gain), 3974 3975 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 3976 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 3977 digital_gain), 3978 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 3979 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 3980 digital_gain), 3981 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 3982 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 3983 digital_gain), 3984 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 3985 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 3986 digital_gain), 3987 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 3988 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 3989 digital_gain), 3990 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 3991 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 3992 digital_gain), 3993 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 3994 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 3995 digital_gain), 3996 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 3997 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 3998 digital_gain), 3999 4000 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 4001 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 4002 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 4003 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 4004 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 4005 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 4006 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 4007 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 4008 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 4009 4010 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 4011 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 4012 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 4013 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 4014 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 4015 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 4016 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 4017 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 4018 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 4019 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 4020 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 4021 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 4022 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 4023 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 4024 4025 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 4026 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put), 4027 4028 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4029 0, 1, 0), 4030 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4031 1, 1, 0), 4032 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4033 2, 1, 0), 4034 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4035 3, 1, 0), 4036 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4037 4, 1, 0), 4038 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4039 0, 1, 0), 4040 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4041 1, 1, 0), 4042 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4043 2, 1, 0), 4044 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4045 3, 1, 0), 4046 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4047 4, 1, 0), 4048 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 4049 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 4050 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 4051 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 4052 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 4053 4054 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 4055 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 4056 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 4057 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 4058 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 4059 4060 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 4061 wcd934x_compander_get, wcd934x_compander_set), 4062 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 4063 wcd934x_compander_get, wcd934x_compander_set), 4064 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 4065 wcd934x_compander_get, wcd934x_compander_set), 4066 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 4067 wcd934x_compander_get, wcd934x_compander_set), 4068 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 4069 wcd934x_compander_get, wcd934x_compander_set), 4070 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 4071 wcd934x_compander_get, wcd934x_compander_set), 4072 }; 4073 4074 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 4075 struct snd_soc_component *component) 4076 { 4077 int port_num = 0; 4078 unsigned short reg = 0; 4079 unsigned int val = 0; 4080 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 4081 struct wcd934x_slim_ch *ch; 4082 4083 list_for_each_entry(ch, &dai->slim_ch_list, list) { 4084 if (ch->port >= WCD934X_RX_START) { 4085 port_num = ch->port - WCD934X_RX_START; 4086 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 4087 } else { 4088 port_num = ch->port; 4089 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 4090 } 4091 4092 regmap_read(wcd->if_regmap, reg, &val); 4093 if (!(val & BIT(port_num % 8))) 4094 regmap_write(wcd->if_regmap, reg, 4095 val | BIT(port_num % 8)); 4096 } 4097 } 4098 4099 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w, 4100 struct snd_kcontrol *kc, int event) 4101 { 4102 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4103 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4104 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 4105 4106 switch (event) { 4107 case SND_SOC_DAPM_POST_PMU: 4108 wcd934x_codec_enable_int_port(dai, comp); 4109 break; 4110 } 4111 4112 return 0; 4113 } 4114 4115 static void wcd934x_codec_hd2_control(struct snd_soc_component *component, 4116 u16 interp_idx, int event) 4117 { 4118 u16 hd2_scale_reg; 4119 u16 hd2_enable_reg = 0; 4120 4121 switch (interp_idx) { 4122 case INTERP_HPHL: 4123 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3; 4124 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 4125 break; 4126 case INTERP_HPHR: 4127 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3; 4128 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 4129 break; 4130 default: 4131 return; 4132 } 4133 4134 if (SND_SOC_DAPM_EVENT_ON(event)) { 4135 snd_soc_component_update_bits(component, hd2_scale_reg, 4136 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4137 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125); 4138 snd_soc_component_update_bits(component, hd2_enable_reg, 4139 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4140 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE); 4141 } 4142 4143 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4144 snd_soc_component_update_bits(component, hd2_enable_reg, 4145 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4146 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE); 4147 snd_soc_component_update_bits(component, hd2_scale_reg, 4148 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4149 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 4150 } 4151 } 4152 4153 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp, 4154 u16 interp_idx, int event) 4155 { 4156 u8 hph_dly_mask; 4157 u16 hph_lut_bypass_reg = 0; 4158 4159 switch (interp_idx) { 4160 case INTERP_HPHL: 4161 hph_dly_mask = 1; 4162 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT; 4163 break; 4164 case INTERP_HPHR: 4165 hph_dly_mask = 2; 4166 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT; 4167 break; 4168 default: 4169 return; 4170 } 4171 4172 if (SND_SOC_DAPM_EVENT_ON(event)) { 4173 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4174 hph_dly_mask, 0x0); 4175 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4176 WCD934X_HPH_LUT_BYPASS_MASK, 4177 WCD934X_HPH_LUT_BYPASS_ENABLE); 4178 } 4179 4180 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4181 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4182 hph_dly_mask, hph_dly_mask); 4183 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4184 WCD934X_HPH_LUT_BYPASS_MASK, 4185 WCD934X_HPH_LUT_BYPASS_DISABLE); 4186 } 4187 } 4188 4189 static int wcd934x_config_compander(struct snd_soc_component *comp, 4190 int interp_n, int event) 4191 { 4192 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4193 int compander; 4194 u16 comp_ctl0_reg, rx_path_cfg0_reg; 4195 4196 /* EAR does not have compander */ 4197 if (!interp_n) 4198 return 0; 4199 4200 compander = interp_n - 1; 4201 if (!wcd->comp_enabled[compander]) 4202 return 0; 4203 4204 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8); 4205 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20); 4206 4207 switch (event) { 4208 case SND_SOC_DAPM_PRE_PMU: 4209 /* Enable Compander Clock */ 4210 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4211 WCD934X_COMP_CLK_EN_MASK, 4212 WCD934X_COMP_CLK_ENABLE); 4213 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4214 WCD934X_COMP_SOFT_RST_MASK, 4215 WCD934X_COMP_SOFT_RST_ENABLE); 4216 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4217 WCD934X_COMP_SOFT_RST_MASK, 4218 WCD934X_COMP_SOFT_RST_DISABLE); 4219 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4220 WCD934X_HPH_CMP_EN_MASK, 4221 WCD934X_HPH_CMP_ENABLE); 4222 break; 4223 case SND_SOC_DAPM_POST_PMD: 4224 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4225 WCD934X_HPH_CMP_EN_MASK, 4226 WCD934X_HPH_CMP_DISABLE); 4227 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4228 WCD934X_COMP_HALT_MASK, 4229 WCD934X_COMP_HALT); 4230 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4231 WCD934X_COMP_SOFT_RST_MASK, 4232 WCD934X_COMP_SOFT_RST_ENABLE); 4233 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4234 WCD934X_COMP_SOFT_RST_MASK, 4235 WCD934X_COMP_SOFT_RST_DISABLE); 4236 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4237 WCD934X_COMP_CLK_EN_MASK, 0x0); 4238 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4239 WCD934X_COMP_SOFT_RST_MASK, 0x0); 4240 break; 4241 } 4242 4243 return 0; 4244 } 4245 4246 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w, 4247 struct snd_kcontrol *kc, int event) 4248 { 4249 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4250 int interp_idx = w->shift; 4251 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20); 4252 4253 switch (event) { 4254 case SND_SOC_DAPM_PRE_PMU: 4255 /* Clk enable */ 4256 snd_soc_component_update_bits(comp, main_reg, 4257 WCD934X_RX_CLK_EN_MASK, 4258 WCD934X_RX_CLK_ENABLE); 4259 wcd934x_codec_hd2_control(comp, interp_idx, event); 4260 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4261 wcd934x_config_compander(comp, interp_idx, event); 4262 break; 4263 case SND_SOC_DAPM_POST_PMD: 4264 wcd934x_config_compander(comp, interp_idx, event); 4265 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4266 wcd934x_codec_hd2_control(comp, interp_idx, event); 4267 /* Clk Disable */ 4268 snd_soc_component_update_bits(comp, main_reg, 4269 WCD934X_RX_CLK_EN_MASK, 0); 4270 /* Reset enable and disable */ 4271 snd_soc_component_update_bits(comp, main_reg, 4272 WCD934X_RX_RESET_MASK, 4273 WCD934X_RX_RESET_ENABLE); 4274 snd_soc_component_update_bits(comp, main_reg, 4275 WCD934X_RX_RESET_MASK, 4276 WCD934X_RX_RESET_DISABLE); 4277 /* Reset rate to 48K*/ 4278 snd_soc_component_update_bits(comp, main_reg, 4279 WCD934X_RX_PCM_RATE_MASK, 4280 WCD934X_RX_PCM_RATE_F_48K); 4281 break; 4282 } 4283 4284 return 0; 4285 } 4286 4287 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 4288 struct snd_kcontrol *kc, int event) 4289 { 4290 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4291 int offset_val = 0; 4292 u16 gain_reg, mix_reg; 4293 int val = 0; 4294 4295 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL + 4296 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4297 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL + 4298 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4299 4300 switch (event) { 4301 case SND_SOC_DAPM_PRE_PMU: 4302 /* Clk enable */ 4303 snd_soc_component_update_bits(comp, mix_reg, 4304 WCD934X_CDC_RX_MIX_CLK_EN_MASK, 4305 WCD934X_CDC_RX_MIX_CLK_ENABLE); 4306 break; 4307 4308 case SND_SOC_DAPM_POST_PMU: 4309 val = snd_soc_component_read(comp, gain_reg); 4310 val += offset_val; 4311 snd_soc_component_write(comp, gain_reg, val); 4312 break; 4313 } 4314 4315 return 0; 4316 } 4317 4318 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w, 4319 struct snd_kcontrol *kcontrol, int event) 4320 { 4321 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4322 int reg = w->reg; 4323 4324 switch (event) { 4325 case SND_SOC_DAPM_POST_PMU: 4326 /* B1 GAIN */ 4327 snd_soc_component_write(comp, reg, 4328 snd_soc_component_read(comp, reg)); 4329 /* B2 GAIN */ 4330 reg++; 4331 snd_soc_component_write(comp, reg, 4332 snd_soc_component_read(comp, reg)); 4333 /* B3 GAIN */ 4334 reg++; 4335 snd_soc_component_write(comp, reg, 4336 snd_soc_component_read(comp, reg)); 4337 /* B4 GAIN */ 4338 reg++; 4339 snd_soc_component_write(comp, reg, 4340 snd_soc_component_read(comp, reg)); 4341 /* B5 GAIN */ 4342 reg++; 4343 snd_soc_component_write(comp, reg, 4344 snd_soc_component_read(comp, reg)); 4345 break; 4346 default: 4347 break; 4348 } 4349 return 0; 4350 } 4351 4352 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w, 4353 struct snd_kcontrol *kcontrol, 4354 int event) 4355 { 4356 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4357 u16 gain_reg; 4358 4359 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift * 4360 WCD934X_RX_PATH_CTL_OFFSET); 4361 4362 switch (event) { 4363 case SND_SOC_DAPM_POST_PMU: 4364 snd_soc_component_write(comp, gain_reg, 4365 snd_soc_component_read(comp, gain_reg)); 4366 break; 4367 } 4368 4369 return 0; 4370 } 4371 4372 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 4373 struct snd_kcontrol *kc, int event) 4374 { 4375 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4376 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4377 4378 switch (event) { 4379 case SND_SOC_DAPM_PRE_PMU: 4380 /* Disable AutoChop timer during power up */ 4381 snd_soc_component_update_bits(comp, 4382 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4383 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4384 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4385 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4386 4387 break; 4388 case SND_SOC_DAPM_POST_PMD: 4389 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4390 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4391 break; 4392 } 4393 4394 return 0; 4395 } 4396 4397 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 4398 struct snd_kcontrol *kcontrol, 4399 int event) 4400 { 4401 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4402 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4403 int hph_mode = wcd->hph_mode; 4404 u8 dem_inp; 4405 4406 switch (event) { 4407 case SND_SOC_DAPM_PRE_PMU: 4408 /* Read DEM INP Select */ 4409 dem_inp = snd_soc_component_read(comp, 4410 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03; 4411 4412 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4413 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4414 return -EINVAL; 4415 } 4416 if (hph_mode != CLS_H_LP) 4417 /* Ripple freq control enable */ 4418 snd_soc_component_update_bits(comp, 4419 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4420 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4421 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4422 /* Disable AutoChop timer during power up */ 4423 snd_soc_component_update_bits(comp, 4424 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4425 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4426 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4427 WCD_CLSH_STATE_HPHL, hph_mode); 4428 4429 break; 4430 case SND_SOC_DAPM_POST_PMD: 4431 /* 1000us required as per HW requirement */ 4432 usleep_range(1000, 1100); 4433 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4434 WCD_CLSH_STATE_HPHL, hph_mode); 4435 if (hph_mode != CLS_H_LP) 4436 /* Ripple freq control disable */ 4437 snd_soc_component_update_bits(comp, 4438 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4439 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4440 4441 break; 4442 default: 4443 break; 4444 } 4445 4446 return 0; 4447 } 4448 4449 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 4450 struct snd_kcontrol *kcontrol, 4451 int event) 4452 { 4453 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4454 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4455 int hph_mode = wcd->hph_mode; 4456 u8 dem_inp; 4457 4458 switch (event) { 4459 case SND_SOC_DAPM_PRE_PMU: 4460 dem_inp = snd_soc_component_read(comp, 4461 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03; 4462 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4463 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4464 return -EINVAL; 4465 } 4466 if (hph_mode != CLS_H_LP) 4467 /* Ripple freq control enable */ 4468 snd_soc_component_update_bits(comp, 4469 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4470 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4471 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4472 /* Disable AutoChop timer during power up */ 4473 snd_soc_component_update_bits(comp, 4474 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4475 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4476 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4477 WCD_CLSH_STATE_HPHR, 4478 hph_mode); 4479 break; 4480 case SND_SOC_DAPM_POST_PMD: 4481 /* 1000us required as per HW requirement */ 4482 usleep_range(1000, 1100); 4483 4484 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4485 WCD_CLSH_STATE_HPHR, hph_mode); 4486 if (hph_mode != CLS_H_LP) 4487 /* Ripple freq control disable */ 4488 snd_soc_component_update_bits(comp, 4489 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4490 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4491 break; 4492 default: 4493 break; 4494 } 4495 4496 return 0; 4497 } 4498 4499 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 4500 struct snd_kcontrol *kc, int event) 4501 { 4502 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4503 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4504 4505 switch (event) { 4506 case SND_SOC_DAPM_PRE_PMU: 4507 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4508 WCD_CLSH_STATE_LO, CLS_AB); 4509 break; 4510 case SND_SOC_DAPM_POST_PMD: 4511 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4512 WCD_CLSH_STATE_LO, CLS_AB); 4513 break; 4514 } 4515 4516 return 0; 4517 } 4518 4519 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 4520 struct snd_kcontrol *kcontrol, 4521 int event) 4522 { 4523 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4524 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4525 4526 switch (event) { 4527 case SND_SOC_DAPM_POST_PMU: 4528 /* 4529 * 7ms sleep is required after PA is enabled as per 4530 * HW requirement. If compander is disabled, then 4531 * 20ms delay is needed. 4532 */ 4533 usleep_range(20000, 20100); 4534 4535 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4536 WCD934X_HPH_OCP_DET_MASK, 4537 WCD934X_HPH_OCP_DET_ENABLE); 4538 /* Remove Mute on primary path */ 4539 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4540 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4541 0); 4542 /* Enable GM3 boost */ 4543 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4544 WCD934X_HPH_GM3_BOOST_EN_MASK, 4545 WCD934X_HPH_GM3_BOOST_ENABLE); 4546 /* Enable AutoChop timer at the end of power up */ 4547 snd_soc_component_update_bits(comp, 4548 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4549 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4550 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4551 /* Remove mix path mute */ 4552 snd_soc_component_update_bits(comp, 4553 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4554 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00); 4555 break; 4556 case SND_SOC_DAPM_PRE_PMD: 4557 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4558 /* Enable DSD Mute before PA disable */ 4559 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4560 WCD934X_HPH_OCP_DET_MASK, 4561 WCD934X_HPH_OCP_DET_DISABLE); 4562 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4563 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4564 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4565 snd_soc_component_update_bits(comp, 4566 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4567 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4568 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4569 break; 4570 case SND_SOC_DAPM_POST_PMD: 4571 /* 4572 * 5ms sleep is required after PA disable. If compander is 4573 * disabled, then 20ms delay is needed after PA disable. 4574 */ 4575 usleep_range(20000, 20100); 4576 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4577 break; 4578 } 4579 4580 return 0; 4581 } 4582 4583 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 4584 struct snd_kcontrol *kcontrol, 4585 int event) 4586 { 4587 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4588 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4589 4590 switch (event) { 4591 case SND_SOC_DAPM_POST_PMU: 4592 /* 4593 * 7ms sleep is required after PA is enabled as per 4594 * HW requirement. If compander is disabled, then 4595 * 20ms delay is needed. 4596 */ 4597 usleep_range(20000, 20100); 4598 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4599 WCD934X_HPH_OCP_DET_MASK, 4600 WCD934X_HPH_OCP_DET_ENABLE); 4601 /* Remove mute */ 4602 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4603 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4604 0); 4605 /* Enable GM3 boost */ 4606 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4607 WCD934X_HPH_GM3_BOOST_EN_MASK, 4608 WCD934X_HPH_GM3_BOOST_ENABLE); 4609 /* Enable AutoChop timer at the end of power up */ 4610 snd_soc_component_update_bits(comp, 4611 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4612 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4613 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4614 /* Remove mix path mute if it is enabled */ 4615 if ((snd_soc_component_read(comp, 4616 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10) 4617 snd_soc_component_update_bits(comp, 4618 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4619 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4620 WCD934X_CDC_RX_PGA_MUTE_DISABLE); 4621 break; 4622 case SND_SOC_DAPM_PRE_PMD: 4623 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 4624 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4625 WCD934X_HPH_OCP_DET_MASK, 4626 WCD934X_HPH_OCP_DET_DISABLE); 4627 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4628 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4629 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4630 snd_soc_component_update_bits(comp, 4631 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4632 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4633 WCD934X_CDC_RX_PGA_MUTE_ENABLE); 4634 break; 4635 case SND_SOC_DAPM_POST_PMD: 4636 /* 4637 * 5ms sleep is required after PA disable. If compander is 4638 * disabled, then 20ms delay is needed after PA disable. 4639 */ 4640 usleep_range(20000, 20100); 4641 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 4642 break; 4643 } 4644 4645 return 0; 4646 } 4647 4648 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp, 4649 unsigned int dmic, 4650 struct wcd934x_codec *wcd) 4651 { 4652 u8 tx_stream_fs; 4653 u8 adc_mux_index = 0, adc_mux_sel = 0; 4654 bool dec_found = false; 4655 u16 adc_mux_ctl_reg, tx_fs_reg; 4656 u32 dmic_fs; 4657 4658 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) { 4659 if (adc_mux_index < 4) { 4660 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4661 (adc_mux_index * 2); 4662 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) { 4663 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4664 adc_mux_index - 4; 4665 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) { 4666 ++adc_mux_index; 4667 continue; 4668 } 4669 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg) 4670 & 0xF8) >> 3) - 1; 4671 4672 if (adc_mux_sel == dmic) { 4673 dec_found = true; 4674 break; 4675 } 4676 4677 ++adc_mux_index; 4678 } 4679 4680 if (dec_found && adc_mux_index <= 8) { 4681 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index); 4682 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F; 4683 if (tx_stream_fs <= 4) 4684 dmic_fs = min(wcd->dmic_sample_rate, WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ); 4685 else 4686 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 4687 } else { 4688 dmic_fs = wcd->dmic_sample_rate; 4689 } 4690 4691 return dmic_fs; 4692 } 4693 4694 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp, 4695 u32 mclk_rate, u32 dmic_clk_rate) 4696 { 4697 u32 div_factor; 4698 u8 dmic_ctl_val; 4699 4700 /* Default value to return in case of error */ 4701 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ) 4702 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4703 else 4704 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4705 4706 if (dmic_clk_rate == 0) { 4707 dev_err(comp->dev, 4708 "%s: dmic_sample_rate cannot be 0\n", 4709 __func__); 4710 goto done; 4711 } 4712 4713 div_factor = mclk_rate / dmic_clk_rate; 4714 switch (div_factor) { 4715 case 2: 4716 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4717 break; 4718 case 3: 4719 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4720 break; 4721 case 4: 4722 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4; 4723 break; 4724 case 6: 4725 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6; 4726 break; 4727 case 8: 4728 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8; 4729 break; 4730 case 16: 4731 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16; 4732 break; 4733 default: 4734 dev_err(comp->dev, 4735 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 4736 __func__, div_factor, mclk_rate, dmic_clk_rate); 4737 break; 4738 } 4739 4740 done: 4741 return dmic_ctl_val; 4742 } 4743 4744 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 4745 struct snd_kcontrol *kcontrol, int event) 4746 { 4747 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4748 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4749 u8 dmic_clk_en = 0x01; 4750 u16 dmic_clk_reg; 4751 s32 *dmic_clk_cnt; 4752 u8 dmic_rate_val, dmic_rate_shift = 1; 4753 unsigned int dmic; 4754 u32 dmic_sample_rate; 4755 int ret; 4756 char *wname; 4757 4758 wname = strpbrk(w->name, "012345"); 4759 if (!wname) { 4760 dev_err(comp->dev, "%s: widget not found\n", __func__); 4761 return -EINVAL; 4762 } 4763 4764 ret = kstrtouint(wname, 10, &dmic); 4765 if (ret < 0) { 4766 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 4767 __func__); 4768 return -EINVAL; 4769 } 4770 4771 switch (dmic) { 4772 case 0: 4773 case 1: 4774 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt; 4775 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL; 4776 break; 4777 case 2: 4778 case 3: 4779 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt; 4780 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL; 4781 break; 4782 case 4: 4783 case 5: 4784 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt; 4785 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL; 4786 break; 4787 default: 4788 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 4789 __func__); 4790 return -EINVAL; 4791 } 4792 4793 switch (event) { 4794 case SND_SOC_DAPM_PRE_PMU: 4795 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic, 4796 wcd); 4797 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate, 4798 dmic_sample_rate); 4799 (*dmic_clk_cnt)++; 4800 if (*dmic_clk_cnt == 1) { 4801 dmic_rate_val = dmic_rate_val << dmic_rate_shift; 4802 snd_soc_component_update_bits(comp, dmic_clk_reg, 4803 WCD934X_DMIC_RATE_MASK, 4804 dmic_rate_val); 4805 snd_soc_component_update_bits(comp, dmic_clk_reg, 4806 dmic_clk_en, dmic_clk_en); 4807 } 4808 4809 break; 4810 case SND_SOC_DAPM_POST_PMD: 4811 (*dmic_clk_cnt)--; 4812 if (*dmic_clk_cnt == 0) 4813 snd_soc_component_update_bits(comp, dmic_clk_reg, 4814 dmic_clk_en, 0); 4815 break; 4816 } 4817 4818 return 0; 4819 } 4820 4821 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp, 4822 int adc_mux_n) 4823 { 4824 u16 mask, shift, adc_mux_in_reg; 4825 u16 amic_mux_sel_reg; 4826 bool is_amic; 4827 4828 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX || 4829 adc_mux_n == WCD934X_INVALID_ADC_MUX) 4830 return 0; 4831 4832 if (adc_mux_n < 3) { 4833 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4834 adc_mux_n; 4835 mask = 0x03; 4836 shift = 0; 4837 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4838 2 * adc_mux_n; 4839 } else if (adc_mux_n < 4) { 4840 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4841 mask = 0x03; 4842 shift = 0; 4843 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4844 2 * adc_mux_n; 4845 } else if (adc_mux_n < 7) { 4846 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4847 (adc_mux_n - 4); 4848 mask = 0x0C; 4849 shift = 2; 4850 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4851 adc_mux_n - 4; 4852 } else if (adc_mux_n < 8) { 4853 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4854 mask = 0x0C; 4855 shift = 2; 4856 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4857 adc_mux_n - 4; 4858 } else if (adc_mux_n < 12) { 4859 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4860 ((adc_mux_n == 8) ? (adc_mux_n - 8) : 4861 (adc_mux_n - 9)); 4862 mask = 0x30; 4863 shift = 4; 4864 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4865 adc_mux_n - 4; 4866 } else if (adc_mux_n < 13) { 4867 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4868 mask = 0x30; 4869 shift = 4; 4870 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4871 adc_mux_n - 4; 4872 } else { 4873 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1; 4874 mask = 0xC0; 4875 shift = 6; 4876 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4877 adc_mux_n - 4; 4878 } 4879 4880 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg) 4881 & mask) >> shift) == 1); 4882 if (!is_amic) 4883 return 0; 4884 4885 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07; 4886 } 4887 4888 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 4889 int amic) 4890 { 4891 u16 pwr_level_reg = 0; 4892 4893 switch (amic) { 4894 case 1: 4895 case 2: 4896 pwr_level_reg = WCD934X_ANA_AMIC1; 4897 break; 4898 4899 case 3: 4900 case 4: 4901 pwr_level_reg = WCD934X_ANA_AMIC3; 4902 break; 4903 default: 4904 break; 4905 } 4906 4907 return pwr_level_reg; 4908 } 4909 4910 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w, 4911 struct snd_kcontrol *kcontrol, int event) 4912 { 4913 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4914 unsigned int decimator; 4915 char *dec_adc_mux_name = NULL; 4916 char *widget_name; 4917 int ret = 0, amic_n; 4918 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 4919 u16 tx_gain_ctl_reg; 4920 char *dec; 4921 u8 hpf_coff_freq; 4922 4923 char *wname __free(kfree) = kstrndup(w->name, 15, GFP_KERNEL); 4924 if (!wname) 4925 return -ENOMEM; 4926 4927 widget_name = wname; 4928 dec_adc_mux_name = strsep(&widget_name, " "); 4929 if (!dec_adc_mux_name) { 4930 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4931 __func__, w->name); 4932 return -EINVAL; 4933 } 4934 dec_adc_mux_name = widget_name; 4935 4936 dec = strpbrk(dec_adc_mux_name, "012345678"); 4937 if (!dec) { 4938 dev_err(comp->dev, "%s: decimator index not found\n", 4939 __func__); 4940 return -EINVAL; 4941 } 4942 4943 ret = kstrtouint(dec, 10, &decimator); 4944 if (ret < 0) { 4945 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4946 __func__, wname); 4947 return -EINVAL; 4948 } 4949 4950 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator; 4951 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 4952 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 4953 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator; 4954 4955 switch (event) { 4956 case SND_SOC_DAPM_PRE_PMU: 4957 amic_n = wcd934x_codec_find_amic_input(comp, decimator); 4958 if (amic_n) 4959 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp, 4960 amic_n); 4961 4962 if (!pwr_level_reg) 4963 break; 4964 4965 switch ((snd_soc_component_read(comp, pwr_level_reg) & 4966 WCD934X_AMIC_PWR_LVL_MASK) >> 4967 WCD934X_AMIC_PWR_LVL_SHIFT) { 4968 case WCD934X_AMIC_PWR_LEVEL_LP: 4969 snd_soc_component_update_bits(comp, dec_cfg_reg, 4970 WCD934X_DEC_PWR_LVL_MASK, 4971 WCD934X_DEC_PWR_LVL_LP); 4972 break; 4973 case WCD934X_AMIC_PWR_LEVEL_HP: 4974 snd_soc_component_update_bits(comp, dec_cfg_reg, 4975 WCD934X_DEC_PWR_LVL_MASK, 4976 WCD934X_DEC_PWR_LVL_HP); 4977 break; 4978 case WCD934X_AMIC_PWR_LEVEL_DEFAULT: 4979 case WCD934X_AMIC_PWR_LEVEL_HYBRID: 4980 default: 4981 snd_soc_component_update_bits(comp, dec_cfg_reg, 4982 WCD934X_DEC_PWR_LVL_MASK, 4983 WCD934X_DEC_PWR_LVL_DF); 4984 break; 4985 } 4986 break; 4987 case SND_SOC_DAPM_POST_PMU: 4988 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 4989 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 4990 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 4991 snd_soc_component_update_bits(comp, dec_cfg_reg, 4992 TX_HPF_CUT_OFF_FREQ_MASK, 4993 CF_MIN_3DB_150HZ << 5); 4994 snd_soc_component_update_bits(comp, hpf_gate_reg, 4995 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 4996 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 4997 /* 4998 * Minimum 1 clk cycle delay is required as per 4999 * HW spec. 5000 */ 5001 usleep_range(1000, 1010); 5002 snd_soc_component_update_bits(comp, hpf_gate_reg, 5003 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5004 0); 5005 } 5006 /* apply gain after decimator is enabled */ 5007 snd_soc_component_write(comp, tx_gain_ctl_reg, 5008 snd_soc_component_read(comp, 5009 tx_gain_ctl_reg)); 5010 break; 5011 case SND_SOC_DAPM_PRE_PMD: 5012 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5013 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5014 5015 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5016 snd_soc_component_update_bits(comp, dec_cfg_reg, 5017 TX_HPF_CUT_OFF_FREQ_MASK, 5018 hpf_coff_freq << 5); 5019 snd_soc_component_update_bits(comp, hpf_gate_reg, 5020 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5021 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5022 /* 5023 * Minimum 1 clk cycle delay is required as per 5024 * HW spec. 5025 */ 5026 usleep_range(1000, 1010); 5027 snd_soc_component_update_bits(comp, hpf_gate_reg, 5028 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5029 0); 5030 } 5031 break; 5032 case SND_SOC_DAPM_POST_PMD: 5033 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 5034 0x10, 0x00); 5035 snd_soc_component_update_bits(comp, dec_cfg_reg, 5036 WCD934X_DEC_PWR_LVL_MASK, 5037 WCD934X_DEC_PWR_LVL_DF); 5038 break; 5039 } 5040 5041 return ret; 5042 } 5043 5044 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp, 5045 u16 amic_reg, bool set) 5046 { 5047 u8 mask = 0x20; 5048 u8 val; 5049 5050 if (amic_reg == WCD934X_ANA_AMIC1 || 5051 amic_reg == WCD934X_ANA_AMIC3) 5052 mask = 0x40; 5053 5054 val = set ? mask : 0x00; 5055 5056 switch (amic_reg) { 5057 case WCD934X_ANA_AMIC1: 5058 case WCD934X_ANA_AMIC2: 5059 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2, 5060 mask, val); 5061 break; 5062 case WCD934X_ANA_AMIC3: 5063 case WCD934X_ANA_AMIC4: 5064 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4, 5065 mask, val); 5066 break; 5067 default: 5068 break; 5069 } 5070 } 5071 5072 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w, 5073 struct snd_kcontrol *kcontrol, int event) 5074 { 5075 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 5076 5077 switch (event) { 5078 case SND_SOC_DAPM_PRE_PMU: 5079 wcd934x_codec_set_tx_hold(comp, w->reg, true); 5080 break; 5081 default: 5082 break; 5083 } 5084 5085 return 0; 5086 } 5087 5088 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 5089 struct snd_kcontrol *kcontrol, 5090 int event) 5091 { 5092 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 5093 int micb_num = w->shift; 5094 5095 switch (event) { 5096 case SND_SOC_DAPM_PRE_PMU: 5097 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true); 5098 break; 5099 case SND_SOC_DAPM_POST_PMU: 5100 /* 1 msec delay as per HW requirement */ 5101 usleep_range(1000, 1100); 5102 break; 5103 case SND_SOC_DAPM_POST_PMD: 5104 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true); 5105 break; 5106 } 5107 5108 return 0; 5109 } 5110 5111 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = { 5112 /* Analog Outputs */ 5113 SND_SOC_DAPM_OUTPUT("EAR"), 5114 SND_SOC_DAPM_OUTPUT("HPHL"), 5115 SND_SOC_DAPM_OUTPUT("HPHR"), 5116 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 5117 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 5118 SND_SOC_DAPM_OUTPUT("SPK1 OUT"), 5119 SND_SOC_DAPM_OUTPUT("SPK2 OUT"), 5120 SND_SOC_DAPM_OUTPUT("ANC EAR"), 5121 SND_SOC_DAPM_OUTPUT("ANC HPHL"), 5122 SND_SOC_DAPM_OUTPUT("ANC HPHR"), 5123 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"), 5124 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"), 5125 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"), 5126 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 5127 AIF1_PB, 0, wcd934x_codec_enable_slim, 5128 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5129 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 5130 AIF2_PB, 0, wcd934x_codec_enable_slim, 5131 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5132 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 5133 AIF3_PB, 0, wcd934x_codec_enable_slim, 5134 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5135 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 5136 AIF4_PB, 0, wcd934x_codec_enable_slim, 5137 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5138 5139 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0, 5140 &slim_rx_mux[WCD934X_RX0]), 5141 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0, 5142 &slim_rx_mux[WCD934X_RX1]), 5143 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0, 5144 &slim_rx_mux[WCD934X_RX2]), 5145 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0, 5146 &slim_rx_mux[WCD934X_RX3]), 5147 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0, 5148 &slim_rx_mux[WCD934X_RX4]), 5149 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0, 5150 &slim_rx_mux[WCD934X_RX5]), 5151 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0, 5152 &slim_rx_mux[WCD934X_RX6]), 5153 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0, 5154 &slim_rx_mux[WCD934X_RX7]), 5155 5156 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5157 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5158 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5159 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5160 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5161 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5162 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5163 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5164 5165 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0, 5166 &rx_int0_2_mux, wcd934x_codec_enable_mix_path, 5167 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5168 SND_SOC_DAPM_POST_PMD), 5169 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 5170 &rx_int1_2_mux, wcd934x_codec_enable_mix_path, 5171 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5172 SND_SOC_DAPM_POST_PMD), 5173 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 5174 &rx_int2_2_mux, wcd934x_codec_enable_mix_path, 5175 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5176 SND_SOC_DAPM_POST_PMD), 5177 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0, 5178 &rx_int3_2_mux, wcd934x_codec_enable_mix_path, 5179 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5180 SND_SOC_DAPM_POST_PMD), 5181 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0, 5182 &rx_int4_2_mux, wcd934x_codec_enable_mix_path, 5183 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5184 SND_SOC_DAPM_POST_PMD), 5185 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0, 5186 &rx_int7_2_mux, wcd934x_codec_enable_mix_path, 5187 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5188 SND_SOC_DAPM_POST_PMD), 5189 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0, 5190 &rx_int8_2_mux, wcd934x_codec_enable_mix_path, 5191 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5192 SND_SOC_DAPM_POST_PMD), 5193 5194 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5195 &rx_int0_1_mix_inp0_mux), 5196 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5197 &rx_int0_1_mix_inp1_mux), 5198 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5199 &rx_int0_1_mix_inp2_mux), 5200 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5201 &rx_int1_1_mix_inp0_mux), 5202 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5203 &rx_int1_1_mix_inp1_mux), 5204 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5205 &rx_int1_1_mix_inp2_mux), 5206 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5207 &rx_int2_1_mix_inp0_mux), 5208 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5209 &rx_int2_1_mix_inp1_mux), 5210 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5211 &rx_int2_1_mix_inp2_mux), 5212 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5213 &rx_int3_1_mix_inp0_mux), 5214 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5215 &rx_int3_1_mix_inp1_mux), 5216 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5217 &rx_int3_1_mix_inp2_mux), 5218 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5219 &rx_int4_1_mix_inp0_mux), 5220 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5221 &rx_int4_1_mix_inp1_mux), 5222 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5223 &rx_int4_1_mix_inp2_mux), 5224 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5225 &rx_int7_1_mix_inp0_mux), 5226 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5227 &rx_int7_1_mix_inp1_mux), 5228 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5229 &rx_int7_1_mix_inp2_mux), 5230 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5231 &rx_int8_1_mix_inp0_mux), 5232 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5233 &rx_int8_1_mix_inp1_mux), 5234 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5235 &rx_int8_1_mix_inp2_mux), 5236 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5237 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5238 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5239 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, 5240 rx_int1_asrc_switch, 5241 ARRAY_SIZE(rx_int1_asrc_switch)), 5242 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5243 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, 5244 rx_int2_asrc_switch, 5245 ARRAY_SIZE(rx_int2_asrc_switch)), 5246 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5247 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, 5248 rx_int3_asrc_switch, 5249 ARRAY_SIZE(rx_int3_asrc_switch)), 5250 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5251 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, 5252 rx_int4_asrc_switch, 5253 ARRAY_SIZE(rx_int4_asrc_switch)), 5254 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5255 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5256 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5257 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5258 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5259 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5260 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5261 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5262 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5263 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5264 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5265 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5266 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5267 5268 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5269 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0, 5270 NULL, 0, NULL, 0), 5271 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0, 5272 NULL, 0, NULL, 0), 5273 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4, 5274 0, &rx_int0_mix2_inp_mux, NULL, 5275 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5276 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4, 5277 0, &rx_int1_mix2_inp_mux, NULL, 5278 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5279 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4, 5280 0, &rx_int2_mix2_inp_mux, NULL, 5281 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5282 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4, 5283 0, &rx_int3_mix2_inp_mux, NULL, 5284 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5285 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4, 5286 0, &rx_int4_mix2_inp_mux, NULL, 5287 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5288 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4, 5289 0, &rx_int7_mix2_inp_mux, NULL, 5290 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5291 5292 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 5293 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 5294 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 5295 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 5296 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 5297 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 5298 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 5299 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 5300 5301 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 5302 0, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5303 SND_SOC_DAPM_POST_PMU), 5304 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 5305 1, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5306 SND_SOC_DAPM_POST_PMU), 5307 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 5308 4, 0, NULL, 0), 5309 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 5310 4, 0, NULL, 0), 5311 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 5312 &rx_int0_dem_inp_mux), 5313 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 5314 &rx_int1_dem_inp_mux), 5315 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 5316 &rx_int2_dem_inp_mux), 5317 5318 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0, 5319 &rx_int0_1_interp_mux, 5320 wcd934x_codec_enable_main_path, 5321 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5322 SND_SOC_DAPM_POST_PMD), 5323 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 5324 &rx_int1_1_interp_mux, 5325 wcd934x_codec_enable_main_path, 5326 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5327 SND_SOC_DAPM_POST_PMD), 5328 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 5329 &rx_int2_1_interp_mux, 5330 wcd934x_codec_enable_main_path, 5331 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5332 SND_SOC_DAPM_POST_PMD), 5333 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0, 5334 &rx_int3_1_interp_mux, 5335 wcd934x_codec_enable_main_path, 5336 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5337 SND_SOC_DAPM_POST_PMD), 5338 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0, 5339 &rx_int4_1_interp_mux, 5340 wcd934x_codec_enable_main_path, 5341 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5342 SND_SOC_DAPM_POST_PMD), 5343 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0, 5344 &rx_int7_1_interp_mux, 5345 wcd934x_codec_enable_main_path, 5346 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5347 SND_SOC_DAPM_POST_PMD), 5348 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0, 5349 &rx_int8_1_interp_mux, 5350 wcd934x_codec_enable_main_path, 5351 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5352 SND_SOC_DAPM_POST_PMD), 5353 5354 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 5355 &rx_int0_2_interp_mux), 5356 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 5357 &rx_int1_2_interp_mux), 5358 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 5359 &rx_int2_2_interp_mux), 5360 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0, 5361 &rx_int3_2_interp_mux), 5362 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0, 5363 &rx_int4_2_interp_mux), 5364 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0, 5365 &rx_int7_2_interp_mux), 5366 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0, 5367 &rx_int8_2_interp_mux), 5368 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 5369 0, 0, wcd934x_codec_ear_dac_event, 5370 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5371 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5372 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH, 5373 5, 0, wcd934x_codec_hphl_dac_event, 5374 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5375 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5376 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH, 5377 4, 0, wcd934x_codec_hphr_dac_event, 5378 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5379 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5380 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 5381 0, 0, wcd934x_codec_lineout_dac_event, 5382 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5383 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 5384 0, 0, wcd934x_codec_lineout_dac_event, 5385 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5386 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0), 5387 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0, 5388 wcd934x_codec_enable_hphl_pa, 5389 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5390 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5391 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0, 5392 wcd934x_codec_enable_hphr_pa, 5393 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5394 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5395 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0, 5396 NULL, 0), 5397 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0, 5398 NULL, 0), 5399 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL, 5400 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5401 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1, 5402 0, 0, NULL, 0), 5403 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL, 5404 0, 0, NULL, 0), 5405 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1, 5406 0, 0, NULL, 0), 5407 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL, 5408 0, 0, NULL, 0), 5409 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0, 5410 wcd934x_codec_enable_interp_clk, 5411 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5412 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0, 5413 wcd934x_codec_enable_interp_clk, 5414 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5415 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0, 5416 wcd934x_codec_enable_interp_clk, 5417 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5418 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0, 5419 wcd934x_codec_enable_interp_clk, 5420 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5421 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0, 5422 wcd934x_codec_enable_interp_clk, 5423 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5424 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0, 5425 wcd934x_codec_enable_interp_clk, 5426 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5427 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0, 5428 wcd934x_codec_enable_interp_clk, 5429 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5430 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL, 5431 0, 0, NULL, 0), 5432 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL, 5433 0, 0, NULL, 0), 5434 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL, 5435 0, 0, NULL, 0), 5436 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL, 5437 0, 0, NULL, 0), 5438 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL, 5439 0, 0, NULL, 0), 5440 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL, 5441 0, 0, NULL, 0), 5442 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL, 5443 0, 0, NULL, 0), 5444 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 5445 wcd934x_codec_enable_mclk, 5446 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5447 5448 /* TX */ 5449 SND_SOC_DAPM_INPUT("AMIC1"), 5450 SND_SOC_DAPM_INPUT("AMIC2"), 5451 SND_SOC_DAPM_INPUT("AMIC3"), 5452 SND_SOC_DAPM_INPUT("AMIC4"), 5453 SND_SOC_DAPM_INPUT("AMIC5"), 5454 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 5455 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 5456 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 5457 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 5458 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 5459 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 5460 5461 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 5462 AIF1_CAP, 0, wcd934x_codec_enable_slim, 5463 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5464 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 5465 AIF2_CAP, 0, wcd934x_codec_enable_slim, 5466 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5467 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 5468 AIF3_CAP, 0, wcd934x_codec_enable_slim, 5469 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5470 5471 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5472 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5473 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5474 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5475 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5476 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5477 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5478 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5479 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0), 5480 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0), 5481 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0), 5482 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0), 5483 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0), 5484 5485 /* Digital Mic Inputs */ 5486 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 5487 wcd934x_codec_enable_dmic, 5488 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5489 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 5490 wcd934x_codec_enable_dmic, 5491 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5492 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 5493 wcd934x_codec_enable_dmic, 5494 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5495 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 5496 wcd934x_codec_enable_dmic, 5497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5498 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 5499 wcd934x_codec_enable_dmic, 5500 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5501 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 5502 wcd934x_codec_enable_dmic, 5503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5504 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0), 5505 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1), 5506 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2), 5507 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3), 5508 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4), 5509 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5), 5510 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6), 5511 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7), 5512 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8), 5513 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0), 5514 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1), 5515 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2), 5516 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3), 5517 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4), 5518 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5), 5519 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6), 5520 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7), 5521 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8), 5522 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0, 5523 &tx_adc_mux0_mux, wcd934x_codec_enable_dec, 5524 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5525 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5526 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0, 5527 &tx_adc_mux1_mux, wcd934x_codec_enable_dec, 5528 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5529 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5530 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0, 5531 &tx_adc_mux2_mux, wcd934x_codec_enable_dec, 5532 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5533 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5534 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0, 5535 &tx_adc_mux3_mux, wcd934x_codec_enable_dec, 5536 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5537 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5538 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0, 5539 &tx_adc_mux4_mux, wcd934x_codec_enable_dec, 5540 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5541 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5542 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0, 5543 &tx_adc_mux5_mux, wcd934x_codec_enable_dec, 5544 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5545 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5546 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0, 5547 &tx_adc_mux6_mux, wcd934x_codec_enable_dec, 5548 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5549 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5550 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0, 5551 &tx_adc_mux7_mux, wcd934x_codec_enable_dec, 5552 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5553 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5554 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0, 5555 &tx_adc_mux8_mux, wcd934x_codec_enable_dec, 5556 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5557 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5558 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0, 5559 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5560 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0, 5561 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5562 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0, 5563 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5564 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0, 5565 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5566 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 5567 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5568 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5569 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 5570 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5571 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5572 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 5573 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5574 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5575 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 5576 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5577 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5578 5579 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5), 5580 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0, 5581 &cdc_if_tx0_mux), 5582 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0, 5583 &cdc_if_tx1_mux), 5584 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0, 5585 &cdc_if_tx2_mux), 5586 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0, 5587 &cdc_if_tx3_mux), 5588 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0, 5589 &cdc_if_tx4_mux), 5590 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0, 5591 &cdc_if_tx5_mux), 5592 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0, 5593 &cdc_if_tx6_mux), 5594 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0, 5595 &cdc_if_tx7_mux), 5596 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0, 5597 &cdc_if_tx8_mux), 5598 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0, 5599 &cdc_if_tx9_mux), 5600 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0, 5601 &cdc_if_tx10_mux), 5602 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5603 &cdc_if_tx11_mux), 5604 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5605 &cdc_if_tx11_inp1_mux), 5606 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5607 &cdc_if_tx13_mux), 5608 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5609 &cdc_if_tx13_inp1_mux), 5610 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 5611 aif1_slim_cap_mixer, 5612 ARRAY_SIZE(aif1_slim_cap_mixer)), 5613 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 5614 aif2_slim_cap_mixer, 5615 ARRAY_SIZE(aif2_slim_cap_mixer)), 5616 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 5617 aif3_slim_cap_mixer, 5618 ARRAY_SIZE(aif3_slim_cap_mixer)), 5619 }; 5620 5621 static const struct snd_soc_dapm_route wcd934x_audio_map[] = { 5622 /* RX0-RX7 */ 5623 WCD934X_SLIM_RX_AIF_PATH(0), 5624 WCD934X_SLIM_RX_AIF_PATH(1), 5625 WCD934X_SLIM_RX_AIF_PATH(2), 5626 WCD934X_SLIM_RX_AIF_PATH(3), 5627 WCD934X_SLIM_RX_AIF_PATH(4), 5628 WCD934X_SLIM_RX_AIF_PATH(5), 5629 WCD934X_SLIM_RX_AIF_PATH(6), 5630 WCD934X_SLIM_RX_AIF_PATH(7), 5631 5632 /* RX0 Ear out */ 5633 WCD934X_INTERPOLATOR_PATH(0), 5634 WCD934X_INTERPOLATOR_MIX2(0), 5635 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 5636 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 5637 {"RX INT0 DAC", NULL, "RX_BIAS"}, 5638 {"EAR PA", NULL, "RX INT0 DAC"}, 5639 {"EAR", NULL, "EAR PA"}, 5640 5641 /* RX1 Headphone left */ 5642 WCD934X_INTERPOLATOR_PATH(1), 5643 WCD934X_INTERPOLATOR_MIX2(1), 5644 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"}, 5645 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"}, 5646 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 5647 {"RX INT1 DAC", NULL, "RX_BIAS"}, 5648 {"HPHL PA", NULL, "RX INT1 DAC"}, 5649 {"HPHL", NULL, "HPHL PA"}, 5650 5651 /* RX2 Headphone right */ 5652 WCD934X_INTERPOLATOR_PATH(2), 5653 WCD934X_INTERPOLATOR_MIX2(2), 5654 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"}, 5655 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"}, 5656 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 5657 {"RX INT2 DAC", NULL, "RX_BIAS"}, 5658 {"HPHR PA", NULL, "RX INT2 DAC"}, 5659 {"HPHR", NULL, "HPHR PA"}, 5660 5661 /* RX3 HIFi LineOut1 */ 5662 WCD934X_INTERPOLATOR_PATH(3), 5663 WCD934X_INTERPOLATOR_MIX2(3), 5664 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"}, 5665 {"RX INT3 DAC", NULL, "RX INT3 MIX3"}, 5666 {"RX INT3 DAC", NULL, "RX_BIAS"}, 5667 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 5668 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 5669 5670 /* RX4 HIFi LineOut2 */ 5671 WCD934X_INTERPOLATOR_PATH(4), 5672 WCD934X_INTERPOLATOR_MIX2(4), 5673 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"}, 5674 {"RX INT4 DAC", NULL, "RX INT4 MIX3"}, 5675 {"RX INT4 DAC", NULL, "RX_BIAS"}, 5676 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 5677 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 5678 5679 /* RX7 Speaker Left Out PA */ 5680 WCD934X_INTERPOLATOR_PATH(7), 5681 WCD934X_INTERPOLATOR_MIX2(7), 5682 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"}, 5683 {"RX INT7 CHAIN", NULL, "RX_BIAS"}, 5684 {"RX INT7 CHAIN", NULL, "SBOOST0"}, 5685 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"}, 5686 {"SPK1 OUT", NULL, "RX INT7 CHAIN"}, 5687 5688 /* RX8 Speaker Right Out PA */ 5689 WCD934X_INTERPOLATOR_PATH(8), 5690 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"}, 5691 {"RX INT8 CHAIN", NULL, "RX_BIAS"}, 5692 {"RX INT8 CHAIN", NULL, "SBOOST1"}, 5693 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"}, 5694 {"SPK2 OUT", NULL, "RX INT8 CHAIN"}, 5695 5696 /* Tx */ 5697 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 5698 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 5699 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 5700 5701 WCD934X_SLIM_TX_AIF_PATH(0), 5702 WCD934X_SLIM_TX_AIF_PATH(1), 5703 WCD934X_SLIM_TX_AIF_PATH(2), 5704 WCD934X_SLIM_TX_AIF_PATH(3), 5705 WCD934X_SLIM_TX_AIF_PATH(4), 5706 WCD934X_SLIM_TX_AIF_PATH(5), 5707 WCD934X_SLIM_TX_AIF_PATH(6), 5708 WCD934X_SLIM_TX_AIF_PATH(7), 5709 WCD934X_SLIM_TX_AIF_PATH(8), 5710 5711 WCD934X_ADC_MUX(0), 5712 WCD934X_ADC_MUX(1), 5713 WCD934X_ADC_MUX(2), 5714 WCD934X_ADC_MUX(3), 5715 WCD934X_ADC_MUX(4), 5716 WCD934X_ADC_MUX(5), 5717 WCD934X_ADC_MUX(6), 5718 WCD934X_ADC_MUX(7), 5719 WCD934X_ADC_MUX(8), 5720 5721 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"}, 5722 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"}, 5723 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"}, 5724 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"}, 5725 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"}, 5726 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"}, 5727 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"}, 5728 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"}, 5729 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"}, 5730 5731 {"AMIC4_5 SEL", "AMIC4", "AMIC4"}, 5732 {"AMIC4_5 SEL", "AMIC5", "AMIC5"}, 5733 5734 { "DMIC0", NULL, "DMIC0 Pin" }, 5735 { "DMIC1", NULL, "DMIC1 Pin" }, 5736 { "DMIC2", NULL, "DMIC2 Pin" }, 5737 { "DMIC3", NULL, "DMIC3 Pin" }, 5738 { "DMIC4", NULL, "DMIC4 Pin" }, 5739 { "DMIC5", NULL, "DMIC5 Pin" }, 5740 5741 {"ADC1", NULL, "AMIC1"}, 5742 {"ADC2", NULL, "AMIC2"}, 5743 {"ADC3", NULL, "AMIC3"}, 5744 {"ADC4", NULL, "AMIC4_5 SEL"}, 5745 5746 WCD934X_IIR_INP_MUX(0), 5747 WCD934X_IIR_INP_MUX(1), 5748 5749 {"SRC0", NULL, "IIR0"}, 5750 {"SRC1", NULL, "IIR1"}, 5751 }; 5752 5753 static int wcd934x_codec_set_jack(struct snd_soc_component *comp, 5754 struct snd_soc_jack *jack, void *data) 5755 { 5756 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 5757 int ret = 0; 5758 5759 if (!wcd->mbhc) 5760 return -ENOTSUPP; 5761 5762 if (jack && !wcd->mbhc_started) { 5763 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack); 5764 wcd->mbhc_started = true; 5765 } else if (wcd->mbhc_started) { 5766 wcd_mbhc_stop(wcd->mbhc); 5767 wcd->mbhc_started = false; 5768 } 5769 5770 return ret; 5771 } 5772 5773 static const struct snd_soc_component_driver wcd934x_component_drv = { 5774 .probe = wcd934x_comp_probe, 5775 .remove = wcd934x_comp_remove, 5776 .set_sysclk = wcd934x_comp_set_sysclk, 5777 .controls = wcd934x_snd_controls, 5778 .num_controls = ARRAY_SIZE(wcd934x_snd_controls), 5779 .dapm_widgets = wcd934x_dapm_widgets, 5780 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets), 5781 .dapm_routes = wcd934x_audio_map, 5782 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map), 5783 .set_jack = wcd934x_codec_set_jack, 5784 .endianness = 1, 5785 }; 5786 5787 static void wcd934x_put_device_action(void *data) 5788 { 5789 struct device *dev = data; 5790 5791 put_device(dev); 5792 } 5793 5794 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd) 5795 { 5796 struct device *dev = &wcd->sdev->dev; 5797 struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg; 5798 struct device_node *ifc_dev_np; 5799 5800 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5801 if (!ifc_dev_np) 5802 return dev_err_probe(dev, -EINVAL, "No Interface device found\n"); 5803 5804 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np); 5805 of_node_put(ifc_dev_np); 5806 if (!wcd->sidev) 5807 return dev_err_probe(dev, -EINVAL, "Unable to get SLIM Interface device\n"); 5808 5809 slim_get_logical_addr(wcd->sidev); 5810 wcd->if_regmap = devm_regmap_init_slimbus(wcd->sidev, 5811 &wcd934x_ifc_regmap_config); 5812 if (IS_ERR(wcd->if_regmap)) { 5813 put_device(&wcd->sidev->dev); 5814 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap), 5815 "Failed to allocate ifc register map\n"); 5816 } 5817 5818 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate", 5819 &wcd->dmic_sample_rate); 5820 5821 cfg->mbhc_micbias = MIC_BIAS_2; 5822 cfg->anc_micbias = MIC_BIAS_2; 5823 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 5824 cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS; 5825 cfg->micb_mv = wcd->common.micb_mv[1]; 5826 cfg->linein_th = 5000; 5827 cfg->hs_thr = 1700; 5828 cfg->hph_thr = 50; 5829 5830 wcd_dt_parse_mbhc_data(dev, cfg); 5831 5832 return 0; 5833 } 5834 5835 static int wcd934x_codec_probe(struct platform_device *pdev) 5836 { 5837 struct device *dev = &pdev->dev; 5838 struct wcd934x_ddata *data = dev_get_drvdata(dev->parent); 5839 struct wcd934x_codec *wcd; 5840 int ret, irq; 5841 5842 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5843 if (!wcd) 5844 return -ENOMEM; 5845 5846 wcd->dev = dev; 5847 wcd->regmap = data->regmap; 5848 wcd->extclk = data->extclk; 5849 wcd->sdev = to_slim_device(data->dev); 5850 mutex_init(&wcd->sysclk_mutex); 5851 mutex_init(&wcd->micb_lock); 5852 wcd->common.dev = dev->parent; 5853 wcd->common.max_bias = 4; 5854 5855 ret = wcd934x_codec_parse_data(wcd); 5856 if (ret) 5857 return ret; 5858 5859 ret = devm_add_action_or_reset(dev, wcd934x_put_device_action, &wcd->sidev->dev); 5860 if (ret) 5861 return ret; 5862 5863 /* set default rate 9P6MHz */ 5864 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 5865 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 5866 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 5867 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs)); 5868 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs)); 5869 5870 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS); 5871 if (irq < 0) 5872 return dev_err_probe(wcd->dev, irq, "Failed to get SLIM IRQ\n"); 5873 5874 ret = devm_request_threaded_irq(dev, irq, NULL, 5875 wcd934x_slim_irq_handler, 5876 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5877 "slim", wcd); 5878 if (ret) 5879 return dev_err_probe(dev, ret, "Failed to request slimbus irq\n"); 5880 5881 wcd934x_register_mclk_output(wcd); 5882 platform_set_drvdata(pdev, wcd); 5883 5884 return devm_snd_soc_register_component(dev, &wcd934x_component_drv, 5885 wcd934x_slim_dais, 5886 ARRAY_SIZE(wcd934x_slim_dais)); 5887 } 5888 5889 static const struct platform_device_id wcd934x_driver_id[] = { 5890 { .name = "wcd934x-codec" }, 5891 { } 5892 }; 5893 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id); 5894 5895 static struct platform_driver wcd934x_codec_driver = { 5896 .probe = &wcd934x_codec_probe, 5897 .id_table = wcd934x_driver_id, 5898 .driver = { 5899 .name = "wcd934x-codec", 5900 } 5901 }; 5902 5903 module_platform_driver(wcd934x_codec_driver); 5904 MODULE_DESCRIPTION("WCD934x codec driver"); 5905 MODULE_LICENSE("GPL v2"); 5906