1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _UAPI_XE_DRM_H_ 7 #define _UAPI_XE_DRM_H_ 8 9 #include "drm.h" 10 11 #if defined(__cplusplus) 12 extern "C" { 13 #endif 14 15 /* 16 * Please note that modifications to all structs defined here are 17 * subject to backwards-compatibility constraints. 18 * Sections in this file are organized as follows: 19 * 1. IOCTL definition 20 * 2. Extension definition and helper structs 21 * 3. IOCTL's Query structs in the order of the Query's entries. 22 * 4. The rest of IOCTL structs in the order of IOCTL declaration. 23 */ 24 25 /** 26 * DOC: Xe Device Block Diagram 27 * 28 * The diagram below represents a high-level simplification of a discrete 29 * GPU supported by the Xe driver. It shows some device components which 30 * are necessary to understand this API, as well as how their relations 31 * to each other. This diagram does not represent real hardware:: 32 * 33 * ┌──────────────────────────────────────────────────────────────────┐ 34 * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ 35 * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ 36 * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ 37 * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ 38 * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ 39 * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ 40 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 41 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ 42 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 43 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 44 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ 45 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 46 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 47 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ 48 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 49 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 50 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ 51 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 52 * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 53 * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ 54 * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 55 * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ 56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ 57 * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ 58 * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ 59 * └─────────────────────────────Device0───────┬──────────────────────┘ 60 * │ 61 * ───────────────────────┴────────── PCI bus 62 */ 63 64 /** 65 * DOC: Xe uAPI Overview 66 * 67 * This section aims to describe the Xe's IOCTL entries, its structs, and other 68 * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related 69 * entries and usage. 70 * 71 * List of supported IOCTLs: 72 * - &DRM_IOCTL_XE_DEVICE_QUERY 73 * - &DRM_IOCTL_XE_GEM_CREATE 74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET 75 * - &DRM_IOCTL_XE_VM_CREATE 76 * - &DRM_IOCTL_XE_VM_DESTROY 77 * - &DRM_IOCTL_XE_VM_BIND 78 * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 79 * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 80 * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 81 * - &DRM_IOCTL_XE_EXEC 82 * - &DRM_IOCTL_XE_WAIT_USER_FENCE 83 * - &DRM_IOCTL_XE_OBSERVATION 84 */ 85 86 /* 87 * xe specific ioctls. 88 * 89 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 90 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 91 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 92 */ 93 #define DRM_XE_DEVICE_QUERY 0x00 94 #define DRM_XE_GEM_CREATE 0x01 95 #define DRM_XE_GEM_MMAP_OFFSET 0x02 96 #define DRM_XE_VM_CREATE 0x03 97 #define DRM_XE_VM_DESTROY 0x04 98 #define DRM_XE_VM_BIND 0x05 99 #define DRM_XE_EXEC_QUEUE_CREATE 0x06 100 #define DRM_XE_EXEC_QUEUE_DESTROY 0x07 101 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 102 #define DRM_XE_EXEC 0x09 103 #define DRM_XE_WAIT_USER_FENCE 0x0a 104 #define DRM_XE_OBSERVATION 0x0b 105 106 /* Must be kept compact -- no holes */ 107 108 #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) 109 #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) 110 #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) 111 #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) 112 #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) 113 #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) 114 #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) 115 #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) 116 #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) 117 #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) 118 #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) 119 #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param) 120 121 /** 122 * DOC: Xe IOCTL Extensions 123 * 124 * Before detailing the IOCTLs and its structs, it is important to highlight 125 * that every IOCTL in Xe is extensible. 126 * 127 * Many interfaces need to grow over time. In most cases we can simply 128 * extend the struct and have userspace pass in more data. Another option, 129 * as demonstrated by Vulkan's approach to providing extensions for forward 130 * and backward compatibility, is to use a list of optional structs to 131 * provide those extra details. 132 * 133 * The key advantage to using an extension chain is that it allows us to 134 * redefine the interface more easily than an ever growing struct of 135 * increasing complexity, and for large parts of that interface to be 136 * entirely optional. The downside is more pointer chasing; chasing across 137 * the __user boundary with pointers encapsulated inside u64. 138 * 139 * Example chaining: 140 * 141 * .. code-block:: C 142 * 143 * struct drm_xe_user_extension ext3 { 144 * .next_extension = 0, // end 145 * .name = ..., 146 * }; 147 * struct drm_xe_user_extension ext2 { 148 * .next_extension = (uintptr_t)&ext3, 149 * .name = ..., 150 * }; 151 * struct drm_xe_user_extension ext1 { 152 * .next_extension = (uintptr_t)&ext2, 153 * .name = ..., 154 * }; 155 * 156 * Typically the struct drm_xe_user_extension would be embedded in some uAPI 157 * struct, and in this case we would feed it the head of the chain(i.e ext1), 158 * which would then apply all of the above extensions. 159 */ 160 161 /** 162 * struct drm_xe_user_extension - Base class for defining a chain of extensions 163 */ 164 struct drm_xe_user_extension { 165 /** 166 * @next_extension: 167 * 168 * Pointer to the next struct drm_xe_user_extension, or zero if the end. 169 */ 170 __u64 next_extension; 171 172 /** 173 * @name: Name of the extension. 174 * 175 * Note that the name here is just some integer. 176 * 177 * Also note that the name space for this is not global for the whole 178 * driver, but rather its scope/meaning is limited to the specific piece 179 * of uAPI which has embedded the struct drm_xe_user_extension. 180 */ 181 __u32 name; 182 183 /** 184 * @pad: MBZ 185 * 186 * All undefined bits must be zero. 187 */ 188 __u32 pad; 189 }; 190 191 /** 192 * struct drm_xe_ext_set_property - Generic set property extension 193 * 194 * A generic struct that allows any of the Xe's IOCTL to be extended 195 * with a set_property operation. 196 */ 197 struct drm_xe_ext_set_property { 198 /** @base: base user extension */ 199 struct drm_xe_user_extension base; 200 201 /** @property: property to set */ 202 __u32 property; 203 204 /** @pad: MBZ */ 205 __u32 pad; 206 207 /** @value: property value */ 208 __u64 value; 209 210 /** @reserved: Reserved */ 211 __u64 reserved[2]; 212 }; 213 214 /** 215 * struct drm_xe_engine_class_instance - instance of an engine class 216 * 217 * It is returned as part of the @drm_xe_engine, but it also is used as 218 * the input of engine selection for both @drm_xe_exec_queue_create and 219 * @drm_xe_query_engine_cycles 220 * 221 * The @engine_class can be: 222 * - %DRM_XE_ENGINE_CLASS_RENDER 223 * - %DRM_XE_ENGINE_CLASS_COPY 224 * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE 225 * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 226 * - %DRM_XE_ENGINE_CLASS_COMPUTE 227 * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual 228 * hardware engine class). Used for creating ordered queues of VM 229 * bind operations. 230 */ 231 struct drm_xe_engine_class_instance { 232 #define DRM_XE_ENGINE_CLASS_RENDER 0 233 #define DRM_XE_ENGINE_CLASS_COPY 1 234 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 235 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 236 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 237 #define DRM_XE_ENGINE_CLASS_VM_BIND 5 238 /** @engine_class: engine class id */ 239 __u16 engine_class; 240 /** @engine_instance: engine instance id */ 241 __u16 engine_instance; 242 /** @gt_id: Unique ID of this GT within the PCI Device */ 243 __u16 gt_id; 244 /** @pad: MBZ */ 245 __u16 pad; 246 }; 247 248 /** 249 * struct drm_xe_engine - describe hardware engine 250 */ 251 struct drm_xe_engine { 252 /** @instance: The @drm_xe_engine_class_instance */ 253 struct drm_xe_engine_class_instance instance; 254 255 /** @reserved: Reserved */ 256 __u64 reserved[3]; 257 }; 258 259 /** 260 * struct drm_xe_query_engines - describe engines 261 * 262 * If a query is made with a struct @drm_xe_device_query where .query 263 * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of 264 * struct @drm_xe_query_engines in .data. 265 */ 266 struct drm_xe_query_engines { 267 /** @num_engines: number of engines returned in @engines */ 268 __u32 num_engines; 269 /** @pad: MBZ */ 270 __u32 pad; 271 /** @engines: The returned engines for this device */ 272 struct drm_xe_engine engines[]; 273 }; 274 275 /** 276 * enum drm_xe_memory_class - Supported memory classes. 277 */ 278 enum drm_xe_memory_class { 279 /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ 280 DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, 281 /** 282 * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this 283 * represents the memory that is local to the device, which we 284 * call VRAM. Not valid on integrated platforms. 285 */ 286 DRM_XE_MEM_REGION_CLASS_VRAM 287 }; 288 289 /** 290 * struct drm_xe_mem_region - Describes some region as known to 291 * the driver. 292 */ 293 struct drm_xe_mem_region { 294 /** 295 * @mem_class: The memory class describing this region. 296 * 297 * See enum drm_xe_memory_class for supported values. 298 */ 299 __u16 mem_class; 300 /** 301 * @instance: The unique ID for this region, which serves as the 302 * index in the placement bitmask used as argument for 303 * &DRM_IOCTL_XE_GEM_CREATE 304 */ 305 __u16 instance; 306 /** 307 * @min_page_size: Min page-size in bytes for this region. 308 * 309 * When the kernel allocates memory for this region, the 310 * underlying pages will be at least @min_page_size in size. 311 * Buffer objects with an allowable placement in this region must be 312 * created with a size aligned to this value. 313 * GPU virtual address mappings of (parts of) buffer objects that 314 * may be placed in this region must also have their GPU virtual 315 * address and range aligned to this value. 316 * Affected IOCTLS will return %-EINVAL if alignment restrictions are 317 * not met. 318 */ 319 __u32 min_page_size; 320 /** 321 * @total_size: The usable size in bytes for this region. 322 */ 323 __u64 total_size; 324 /** 325 * @used: Estimate of the memory used in bytes for this region. 326 * 327 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 328 * accounting. Without this the value here will always equal 329 * zero. 330 */ 331 __u64 used; 332 /** 333 * @cpu_visible_size: How much of this region can be CPU 334 * accessed, in bytes. 335 * 336 * This will always be <= @total_size, and the remainder (if 337 * any) will not be CPU accessible. If the CPU accessible part 338 * is smaller than @total_size then this is referred to as a 339 * small BAR system. 340 * 341 * On systems without small BAR (full BAR), the probed_size will 342 * always equal the @total_size, since all of it will be CPU 343 * accessible. 344 * 345 * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM 346 * regions (for other types the value here will always equal 347 * zero). 348 */ 349 __u64 cpu_visible_size; 350 /** 351 * @cpu_visible_used: Estimate of CPU visible memory used, in 352 * bytes. 353 * 354 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 355 * accounting. Without this the value here will always equal 356 * zero. Note this is only currently tracked for 357 * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value 358 * here will always be zero). 359 */ 360 __u64 cpu_visible_used; 361 /** @reserved: Reserved */ 362 __u64 reserved[6]; 363 }; 364 365 /** 366 * struct drm_xe_query_mem_regions - describe memory regions 367 * 368 * If a query is made with a struct drm_xe_device_query where .query 369 * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses 370 * struct drm_xe_query_mem_regions in .data. 371 */ 372 struct drm_xe_query_mem_regions { 373 /** @num_mem_regions: number of memory regions returned in @mem_regions */ 374 __u32 num_mem_regions; 375 /** @pad: MBZ */ 376 __u32 pad; 377 /** @mem_regions: The returned memory regions for this device */ 378 struct drm_xe_mem_region mem_regions[]; 379 }; 380 381 /** 382 * struct drm_xe_query_config - describe the device configuration 383 * 384 * If a query is made with a struct drm_xe_device_query where .query 385 * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses 386 * struct drm_xe_query_config in .data. 387 * 388 * The index in @info can be: 389 * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits) 390 * and the device revision (next 8 bits) 391 * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device 392 * configuration, see list below 393 * 394 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device 395 * has usable VRAM 396 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device 397 * has low latency hint support 398 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the 399 * device has CPU address mirroring support 400 * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment 401 * required by this device, typically SZ_4K or SZ_64K 402 * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address 403 * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest 404 * available exec queue priority 405 */ 406 struct drm_xe_query_config { 407 /** @num_params: number of parameters returned in info */ 408 __u32 num_params; 409 410 /** @pad: MBZ */ 411 __u32 pad; 412 413 #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 414 #define DRM_XE_QUERY_CONFIG_FLAGS 1 415 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) 416 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1) 417 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2) 418 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 419 #define DRM_XE_QUERY_CONFIG_VA_BITS 3 420 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 421 /** @info: array of elements containing the config info */ 422 __u64 info[]; 423 }; 424 425 /** 426 * struct drm_xe_gt - describe an individual GT. 427 * 428 * To be used with drm_xe_query_gt_list, which will return a list with all the 429 * existing GT individual descriptions. 430 * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for 431 * implementing graphics and/or media operations. 432 * 433 * The index in @type can be: 434 * - %DRM_XE_QUERY_GT_TYPE_MAIN 435 * - %DRM_XE_QUERY_GT_TYPE_MEDIA 436 */ 437 struct drm_xe_gt { 438 #define DRM_XE_QUERY_GT_TYPE_MAIN 0 439 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 440 /** @type: GT type: Main or Media */ 441 __u16 type; 442 /** @tile_id: Tile ID where this GT lives (Information only) */ 443 __u16 tile_id; 444 /** @gt_id: Unique ID of this GT within the PCI Device */ 445 __u16 gt_id; 446 /** @pad: MBZ */ 447 __u16 pad[3]; 448 /** @reference_clock: A clock frequency for timestamp */ 449 __u32 reference_clock; 450 /** 451 * @near_mem_regions: Bit mask of instances from 452 * drm_xe_query_mem_regions that are nearest to the current engines 453 * of this GT. 454 * Each index in this mask refers directly to the struct 455 * drm_xe_query_mem_regions' instance, no assumptions should 456 * be made about order. The type of each region is described 457 * by struct drm_xe_query_mem_regions' mem_class. 458 */ 459 __u64 near_mem_regions; 460 /** 461 * @far_mem_regions: Bit mask of instances from 462 * drm_xe_query_mem_regions that are far from the engines of this GT. 463 * In general, they have extra indirections when compared to the 464 * @near_mem_regions. For a discrete device this could mean system 465 * memory and memory living in a different tile. 466 * Each index in this mask refers directly to the struct 467 * drm_xe_query_mem_regions' instance, no assumptions should 468 * be made about order. The type of each region is described 469 * by struct drm_xe_query_mem_regions' mem_class. 470 */ 471 __u64 far_mem_regions; 472 /** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */ 473 __u16 ip_ver_major; 474 /** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */ 475 __u16 ip_ver_minor; 476 /** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */ 477 __u16 ip_ver_rev; 478 /** @pad2: MBZ */ 479 __u16 pad2; 480 /** @reserved: Reserved */ 481 __u64 reserved[7]; 482 }; 483 484 /** 485 * struct drm_xe_query_gt_list - A list with GT description items. 486 * 487 * If a query is made with a struct drm_xe_device_query where .query 488 * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct 489 * drm_xe_query_gt_list in .data. 490 */ 491 struct drm_xe_query_gt_list { 492 /** @num_gt: number of GT items returned in gt_list */ 493 __u32 num_gt; 494 /** @pad: MBZ */ 495 __u32 pad; 496 /** @gt_list: The GT list returned for this device */ 497 struct drm_xe_gt gt_list[]; 498 }; 499 500 /** 501 * struct drm_xe_query_topology_mask - describe the topology mask of a GT 502 * 503 * This is the hardware topology which reflects the internal physical 504 * structure of the GPU. 505 * 506 * If a query is made with a struct drm_xe_device_query where .query 507 * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses 508 * struct drm_xe_query_topology_mask in .data. 509 * 510 * The @type can be: 511 * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices 512 * (DSS) available for geometry operations. For example a query response 513 * containing the following in mask: 514 * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` 515 * means 32 DSS are available for geometry. 516 * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices 517 * (DSS) available for compute operations. For example a query response 518 * containing the following in mask: 519 * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` 520 * means 32 DSS are available for compute. 521 * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type 522 * may be omitted if the driver is unable to query the mask from the 523 * hardware. 524 * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) 525 * available per Dual Sub Slices (DSS). For example a query response 526 * containing the following in mask: 527 * ``EU_PER_DSS ff ff 00 00 00 00 00 00`` 528 * means each DSS has 16 SIMD8 EUs. This type may be omitted if device 529 * doesn't have SIMD8 EUs. 530 * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution 531 * Units (EU) available per Dual Sub Slices (DSS). For example a query 532 * response containing the following in mask: 533 * ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` 534 * means each DSS has 16 SIMD16 EUs. This type may be omitted if device 535 * doesn't have SIMD16 EUs. 536 */ 537 struct drm_xe_query_topology_mask { 538 /** @gt_id: GT ID the mask is associated with */ 539 __u16 gt_id; 540 541 #define DRM_XE_TOPO_DSS_GEOMETRY 1 542 #define DRM_XE_TOPO_DSS_COMPUTE 2 543 #define DRM_XE_TOPO_L3_BANK 3 544 #define DRM_XE_TOPO_EU_PER_DSS 4 545 #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5 546 /** @type: type of mask */ 547 __u16 type; 548 549 /** @num_bytes: number of bytes in requested mask */ 550 __u32 num_bytes; 551 552 /** @mask: little-endian mask of @num_bytes */ 553 __u8 mask[]; 554 }; 555 556 /** 557 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps 558 * 559 * If a query is made with a struct drm_xe_device_query where .query is equal to 560 * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles 561 * in .data. struct drm_xe_query_engine_cycles is allocated by the user and 562 * .data points to this allocated structure. 563 * 564 * The query returns the engine cycles, which along with GT's @reference_clock, 565 * can be used to calculate the engine timestamp. In addition the 566 * query returns a set of cpu timestamps that indicate when the command 567 * streamer cycle count was captured. 568 */ 569 struct drm_xe_query_engine_cycles { 570 /** 571 * @eci: This is input by the user and is the engine for which command 572 * streamer cycles is queried. 573 */ 574 struct drm_xe_engine_class_instance eci; 575 576 /** 577 * @clockid: This is input by the user and is the reference clock id for 578 * CPU timestamp. For definition, see clock_gettime(2) and 579 * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, 580 * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. 581 */ 582 __s32 clockid; 583 584 /** @width: Width of the engine cycle counter in bits. */ 585 __u32 width; 586 587 /** 588 * @engine_cycles: Engine cycles as read from its register 589 * at 0x358 offset. 590 */ 591 __u64 engine_cycles; 592 593 /** 594 * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before 595 * reading the engine_cycles register using the reference clockid set by the 596 * user. 597 */ 598 __u64 cpu_timestamp; 599 600 /** 601 * @cpu_delta: Time delta in ns captured around reading the lower dword 602 * of the engine_cycles register. 603 */ 604 __u64 cpu_delta; 605 }; 606 607 /** 608 * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version 609 * 610 * Given a uc_type this will return the branch, major, minor and patch version 611 * of the micro-controller firmware. 612 */ 613 struct drm_xe_query_uc_fw_version { 614 /** @uc_type: The micro-controller type to query firmware version */ 615 #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 616 #define XE_QUERY_UC_TYPE_HUC 1 617 __u16 uc_type; 618 619 /** @pad: MBZ */ 620 __u16 pad; 621 622 /** @branch_ver: branch uc fw version */ 623 __u32 branch_ver; 624 /** @major_ver: major uc fw version */ 625 __u32 major_ver; 626 /** @minor_ver: minor uc fw version */ 627 __u32 minor_ver; 628 /** @patch_ver: patch uc fw version */ 629 __u32 patch_ver; 630 631 /** @pad2: MBZ */ 632 __u32 pad2; 633 634 /** @reserved: Reserved */ 635 __u64 reserved; 636 }; 637 638 /** 639 * struct drm_xe_query_pxp_status - query if PXP is ready 640 * 641 * If PXP is enabled and no fatal error has occurred, the status will be set to 642 * one of the following values: 643 * 0: PXP init still in progress 644 * 1: PXP init complete 645 * 646 * If PXP is not enabled or something has gone wrong, the query will be failed 647 * with one of the following error codes: 648 * -ENODEV: PXP not supported or disabled; 649 * -EIO: fatal error occurred during init, so PXP will never be enabled; 650 * -EINVAL: incorrect value provided as part of the query; 651 * -EFAULT: error copying the memory between kernel and userspace. 652 * 653 * The status can only be 0 in the first few seconds after driver load. If 654 * everything works as expected, the status will transition to init complete in 655 * less than 1 second, while in case of errors the driver might take longer to 656 * start returning an error code, but it should still take less than 10 seconds. 657 * 658 * The supported session type bitmask is based on the values in 659 * enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore 660 * is not reported in the bitmask. 661 * 662 */ 663 struct drm_xe_query_pxp_status { 664 /** @status: current PXP status */ 665 __u32 status; 666 667 /** @supported_session_types: bitmask of supported PXP session types */ 668 __u32 supported_session_types; 669 }; 670 671 /** 672 * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main 673 * structure to query device information 674 * 675 * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_* 676 * and sets the value in the query member. This determines the type of 677 * the structure provided by the driver in data, among struct drm_xe_query_*. 678 * 679 * The @query can be: 680 * - %DRM_XE_DEVICE_QUERY_ENGINES 681 * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS 682 * - %DRM_XE_DEVICE_QUERY_CONFIG 683 * - %DRM_XE_DEVICE_QUERY_GT_LIST 684 * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware 685 * configuration of the device such as information on slices, memory, 686 * caches, and so on. It is provided as a table of key / value 687 * attributes. 688 * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 689 * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 690 * - %DRM_XE_DEVICE_QUERY_PXP_STATUS 691 * 692 * If size is set to 0, the driver fills it with the required size for 693 * the requested type of data to query. If size is equal to the required 694 * size, the queried information is copied into data. If size is set to 695 * a value different from 0 and different from the required size, the 696 * IOCTL call returns -EINVAL. 697 * 698 * For example the following code snippet allows retrieving and printing 699 * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES: 700 * 701 * .. code-block:: C 702 * 703 * struct drm_xe_query_engines *engines; 704 * struct drm_xe_device_query query = { 705 * .extensions = 0, 706 * .query = DRM_XE_DEVICE_QUERY_ENGINES, 707 * .size = 0, 708 * .data = 0, 709 * }; 710 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 711 * engines = malloc(query.size); 712 * query.data = (uintptr_t)engines; 713 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 714 * for (int i = 0; i < engines->num_engines; i++) { 715 * printf("Engine %d: %s\n", i, 716 * engines->engines[i].instance.engine_class == 717 * DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": 718 * engines->engines[i].instance.engine_class == 719 * DRM_XE_ENGINE_CLASS_COPY ? "COPY": 720 * engines->engines[i].instance.engine_class == 721 * DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": 722 * engines->engines[i].instance.engine_class == 723 * DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": 724 * engines->engines[i].instance.engine_class == 725 * DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": 726 * "UNKNOWN"); 727 * } 728 * free(engines); 729 */ 730 struct drm_xe_device_query { 731 /** @extensions: Pointer to the first extension struct, if any */ 732 __u64 extensions; 733 734 #define DRM_XE_DEVICE_QUERY_ENGINES 0 735 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1 736 #define DRM_XE_DEVICE_QUERY_CONFIG 2 737 #define DRM_XE_DEVICE_QUERY_GT_LIST 3 738 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 739 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 740 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 741 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 742 #define DRM_XE_DEVICE_QUERY_OA_UNITS 8 743 #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9 744 #define DRM_XE_DEVICE_QUERY_EU_STALL 10 745 /** @query: The type of data to query */ 746 __u32 query; 747 748 /** @size: Size of the queried data */ 749 __u32 size; 750 751 /** @data: Queried data is placed here */ 752 __u64 data; 753 754 /** @reserved: Reserved */ 755 __u64 reserved[2]; 756 }; 757 758 /** 759 * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for 760 * gem creation 761 * 762 * The @flags can be: 763 * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING 764 * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT 765 * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a 766 * possible placement, ensure that the corresponding VRAM allocation 767 * will always use the CPU accessible part of VRAM. This is important 768 * for small-bar systems (on full-bar systems this gets turned into a 769 * noop). 770 * Note1: System memory can be used as an extra placement if the kernel 771 * should spill the allocation to system memory, if space can't be made 772 * available in the CPU accessible part of VRAM (giving the same 773 * behaviour as the i915 interface, see 774 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). 775 * Note2: For clear-color CCS surfaces the kernel needs to read the 776 * clear-color value stored in the buffer, and on discrete platforms we 777 * need to use VRAM for display surfaces, therefore the kernel requires 778 * setting this flag for such objects, otherwise an error is thrown on 779 * small-bar systems. 780 * 781 * @cpu_caching supports the following values: 782 * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back 783 * caching. On iGPU this can't be used for scanout surfaces. Currently 784 * not allowed for objects placed in VRAM. 785 * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This 786 * is uncached. Scanout surfaces should likely use this. All objects 787 * that can be placed in VRAM must use this. 788 * 789 * This ioctl supports setting the following properties via the 790 * %DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY extension, which uses the 791 * generic @drm_xe_ext_set_property struct: 792 * 793 * - %DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE - set the type of PXP session 794 * this object will be used with. Valid values are listed in enum 795 * drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so 796 * there is no need to explicitly set that. Objects used with session of type 797 * %DRM_XE_PXP_TYPE_HWDRM will be marked as invalid if a PXP invalidation 798 * event occurs after their creation. Attempting to flip an invalid object 799 * will cause a black frame to be displayed instead. Submissions with invalid 800 * objects mapped in the VM will be rejected. 801 */ 802 struct drm_xe_gem_create { 803 #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0 804 #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0 805 /** @extensions: Pointer to the first extension struct, if any */ 806 __u64 extensions; 807 808 /** 809 * @size: Size of the object to be created, must match region 810 * (system or vram) minimum alignment (&min_page_size). 811 */ 812 __u64 size; 813 814 /** 815 * @placement: A mask of memory instances of where BO can be placed. 816 * Each index in this mask refers directly to the struct 817 * drm_xe_query_mem_regions' instance, no assumptions should 818 * be made about order. The type of each region is described 819 * by struct drm_xe_query_mem_regions' mem_class. 820 */ 821 __u32 placement; 822 823 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0) 824 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1) 825 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2) 826 /** 827 * @flags: Flags, currently a mask of memory instances of where BO can 828 * be placed 829 */ 830 __u32 flags; 831 832 /** 833 * @vm_id: Attached VM, if any 834 * 835 * If a VM is specified, this BO must: 836 * 837 * 1. Only ever be bound to that VM. 838 * 2. Cannot be exported as a PRIME fd. 839 */ 840 __u32 vm_id; 841 842 /** 843 * @handle: Returned handle for the object. 844 * 845 * Object handles are nonzero. 846 */ 847 __u32 handle; 848 849 #define DRM_XE_GEM_CPU_CACHING_WB 1 850 #define DRM_XE_GEM_CPU_CACHING_WC 2 851 /** 852 * @cpu_caching: The CPU caching mode to select for this object. If 853 * mmaping the object the mode selected here will also be used. The 854 * exception is when mapping system memory (including data evicted 855 * to system) on discrete GPUs. The caching mode selected will 856 * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency 857 * between GPU- and CPU is guaranteed. The caching mode of 858 * existing CPU-mappings will be updated transparently to 859 * user-space clients. 860 */ 861 __u16 cpu_caching; 862 /** @pad: MBZ */ 863 __u16 pad[3]; 864 865 /** @reserved: Reserved */ 866 __u64 reserved[2]; 867 }; 868 869 /** 870 * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET 871 * 872 * The @flags can be: 873 * - %DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER - For user to query special offset 874 * for use in mmap ioctl. Writing to the returned mmap address will generate a 875 * PCI memory barrier with low overhead (avoiding IOCTL call as well as writing 876 * to VRAM which would also add overhead), acting like an MI_MEM_FENCE 877 * instruction. 878 * 879 * Note: The mmap size can be at most 4K, due to HW limitations. As a result 880 * this interface is only supported on CPU architectures that support 4K page 881 * size. The mmap_offset ioctl will detect this and gracefully return an 882 * error, where userspace is expected to have a different fallback method for 883 * triggering a barrier. 884 * 885 * Roughly the usage would be as follows: 886 * 887 * .. code-block:: C 888 * 889 * struct drm_xe_gem_mmap_offset mmo = { 890 * .handle = 0, // must be set to 0 891 * .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER, 892 * }; 893 * 894 * err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); 895 * map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); 896 * map[i] = 0xdeadbeaf; // issue barrier 897 */ 898 struct drm_xe_gem_mmap_offset { 899 /** @extensions: Pointer to the first extension struct, if any */ 900 __u64 extensions; 901 902 /** @handle: Handle for the object being mapped. */ 903 __u32 handle; 904 905 #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0) 906 /** @flags: Flags */ 907 __u32 flags; 908 909 /** @offset: The fake offset to use for subsequent mmap call */ 910 __u64 offset; 911 912 /** @reserved: Reserved */ 913 __u64 reserved[2]; 914 }; 915 916 /** 917 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE 918 * 919 * The @flags can be: 920 * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE 921 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts 922 * exec submissions to its exec_queues that don't have an upper time 923 * limit on the job execution time. But exec submissions to these 924 * don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, 925 * DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, 926 * used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. 927 * LR VMs can be created in recoverable page-fault mode using 928 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. 929 * If that flag is omitted, the UMD can not rely on the slightly 930 * different per-VM overcommit semantics that are enabled by 931 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may 932 * still enable recoverable pagefaults if supported by the device. 933 * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also 934 * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on 935 * demand when accessed, and also allows per-VM overcommit of memory. 936 * The xe driver internally uses recoverable pagefaults to implement 937 * this. 938 */ 939 struct drm_xe_vm_create { 940 /** @extensions: Pointer to the first extension struct, if any */ 941 __u64 extensions; 942 943 #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0) 944 #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1) 945 #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2) 946 /** @flags: Flags */ 947 __u32 flags; 948 949 /** @vm_id: Returned VM ID */ 950 __u32 vm_id; 951 952 /** @reserved: Reserved */ 953 __u64 reserved[2]; 954 }; 955 956 /** 957 * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY 958 */ 959 struct drm_xe_vm_destroy { 960 /** @vm_id: VM ID */ 961 __u32 vm_id; 962 963 /** @pad: MBZ */ 964 __u32 pad; 965 966 /** @reserved: Reserved */ 967 __u64 reserved[2]; 968 }; 969 970 /** 971 * struct drm_xe_vm_bind_op - run bind operations 972 * 973 * The @op can be: 974 * - %DRM_XE_VM_BIND_OP_MAP 975 * - %DRM_XE_VM_BIND_OP_UNMAP 976 * - %DRM_XE_VM_BIND_OP_MAP_USERPTR 977 * - %DRM_XE_VM_BIND_OP_UNMAP_ALL 978 * - %DRM_XE_VM_BIND_OP_PREFETCH 979 * 980 * and the @flags can be: 981 * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only 982 * to ensure write protection 983 * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the 984 * MAP operation immediately rather than deferring the MAP to the page 985 * fault handler. This is implied on a non-faulting VM as there is no 986 * fault handler to defer to. 987 * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page 988 * tables are setup with a special bit which indicates writes are 989 * dropped and all reads return zero. In the future, the NULL flags 990 * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO 991 * handle MBZ, and the BO offset MBZ. This flag is intended to 992 * implement VK sparse bindings. 993 * - %DRM_XE_VM_BIND_FLAG_CHECK_PXP - If the object is encrypted via PXP, 994 * reject the binding if the encryption key is no longer valid. This 995 * flag has no effect on BOs that are not marked as using PXP. 996 * - %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR - When the CPU address mirror flag is 997 * set, no mappings are created rather the range is reserved for CPU address 998 * mirroring which will be populated on GPU page faults or prefetches. Only 999 * valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address 1000 * mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO 1001 * handle MBZ, and the BO offset MBZ. 1002 */ 1003 struct drm_xe_vm_bind_op { 1004 /** @extensions: Pointer to the first extension struct, if any */ 1005 __u64 extensions; 1006 1007 /** 1008 * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP 1009 */ 1010 __u32 obj; 1011 1012 /** 1013 * @pat_index: The platform defined @pat_index to use for this mapping. 1014 * The index basically maps to some predefined memory attributes, 1015 * including things like caching, coherency, compression etc. The exact 1016 * meaning of the pat_index is platform specific and defined in the 1017 * Bspec and PRMs. When the KMD sets up the binding the index here is 1018 * encoded into the ppGTT PTE. 1019 * 1020 * For coherency the @pat_index needs to be at least 1way coherent when 1021 * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD 1022 * will extract the coherency mode from the @pat_index and reject if 1023 * there is a mismatch (see note below for pre-MTL platforms). 1024 * 1025 * Note: On pre-MTL platforms there is only a caching mode and no 1026 * explicit coherency mode, but on such hardware there is always a 1027 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with 1028 * CPU caches even with the caching mode set as uncached. It's only the 1029 * display engine that is incoherent (on dgpu it must be in VRAM which 1030 * is always mapped as WC on the CPU). However to keep the uapi somewhat 1031 * consistent with newer platforms the KMD groups the different cache 1032 * levels into the following coherency buckets on all pre-MTL platforms: 1033 * 1034 * ppGTT UC -> COH_NONE 1035 * ppGTT WC -> COH_NONE 1036 * ppGTT WT -> COH_NONE 1037 * ppGTT WB -> COH_AT_LEAST_1WAY 1038 * 1039 * In practice UC/WC/WT should only ever used for scanout surfaces on 1040 * such platforms (or perhaps in general for dma-buf if shared with 1041 * another device) since it is only the display engine that is actually 1042 * incoherent. Everything else should typically use WB given that we 1043 * have a shared-LLC. On MTL+ this completely changes and the HW 1044 * defines the coherency mode as part of the @pat_index, where 1045 * incoherent GT access is possible. 1046 * 1047 * Note: For userptr and externally imported dma-buf the kernel expects 1048 * either 1WAY or 2WAY for the @pat_index. 1049 * 1050 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions 1051 * on the @pat_index. For such mappings there is no actual memory being 1052 * mapped (the address in the PTE is invalid), so the various PAT memory 1053 * attributes likely do not apply. Simply leaving as zero is one 1054 * option (still a valid pat_index). Same applies to 1055 * DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping 1056 * there is no actual memory being mapped. 1057 */ 1058 __u16 pat_index; 1059 1060 /** @pad: MBZ */ 1061 __u16 pad; 1062 1063 union { 1064 /** 1065 * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE, 1066 * ignored for unbind 1067 */ 1068 __u64 obj_offset; 1069 1070 /** @userptr: user pointer to bind on */ 1071 __u64 userptr; 1072 1073 /** 1074 * @cpu_addr_mirror_offset: Offset from GPU @addr to create 1075 * CPU address mirror mappings. MBZ with current level of 1076 * support (e.g. 1 to 1 mapping between GPU and CPU mappings 1077 * only supported). 1078 */ 1079 __s64 cpu_addr_mirror_offset; 1080 }; 1081 1082 /** 1083 * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL 1084 */ 1085 __u64 range; 1086 1087 /** @addr: Address to operate on, MBZ for UNMAP_ALL */ 1088 __u64 addr; 1089 1090 #define DRM_XE_VM_BIND_OP_MAP 0x0 1091 #define DRM_XE_VM_BIND_OP_UNMAP 0x1 1092 #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2 1093 #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3 1094 #define DRM_XE_VM_BIND_OP_PREFETCH 0x4 1095 /** @op: Bind operation to perform */ 1096 __u32 op; 1097 1098 #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0) 1099 #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1) 1100 #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2) 1101 #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3) 1102 #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4) 1103 #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5) 1104 /** @flags: Bind flags */ 1105 __u32 flags; 1106 1107 /** 1108 * @prefetch_mem_region_instance: Memory region to prefetch VMA to. 1109 * It is a region instance, not a mask. 1110 * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation. 1111 */ 1112 __u32 prefetch_mem_region_instance; 1113 1114 /** @pad2: MBZ */ 1115 __u32 pad2; 1116 1117 /** @reserved: Reserved */ 1118 __u64 reserved[3]; 1119 }; 1120 1121 /** 1122 * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND 1123 * 1124 * Below is an example of a minimal use of @drm_xe_vm_bind to 1125 * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to 1126 * illustrate `userptr`. It can be synchronized by using the example 1127 * provided for @drm_xe_sync. 1128 * 1129 * .. code-block:: C 1130 * 1131 * data = aligned_alloc(ALIGNMENT, BO_SIZE); 1132 * struct drm_xe_vm_bind bind = { 1133 * .vm_id = vm, 1134 * .num_binds = 1, 1135 * .bind.obj = 0, 1136 * .bind.obj_offset = to_user_pointer(data), 1137 * .bind.range = BO_SIZE, 1138 * .bind.addr = BIND_ADDRESS, 1139 * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, 1140 * .bind.flags = 0, 1141 * .num_syncs = 1, 1142 * .syncs = &sync, 1143 * .exec_queue_id = 0, 1144 * }; 1145 * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind); 1146 * 1147 */ 1148 struct drm_xe_vm_bind { 1149 /** @extensions: Pointer to the first extension struct, if any */ 1150 __u64 extensions; 1151 1152 /** @vm_id: The ID of the VM to bind to */ 1153 __u32 vm_id; 1154 1155 /** 1156 * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND 1157 * and exec queue must have same vm_id. If zero, the default VM bind engine 1158 * is used. 1159 */ 1160 __u32 exec_queue_id; 1161 1162 /** @pad: MBZ */ 1163 __u32 pad; 1164 1165 /** @num_binds: number of binds in this IOCTL */ 1166 __u32 num_binds; 1167 1168 union { 1169 /** @bind: used if num_binds == 1 */ 1170 struct drm_xe_vm_bind_op bind; 1171 1172 /** 1173 * @vector_of_binds: userptr to array of struct 1174 * drm_xe_vm_bind_op if num_binds > 1 1175 */ 1176 __u64 vector_of_binds; 1177 }; 1178 1179 /** @pad2: MBZ */ 1180 __u32 pad2; 1181 1182 /** @num_syncs: amount of syncs to wait on */ 1183 __u32 num_syncs; 1184 1185 /** @syncs: pointer to struct drm_xe_sync array */ 1186 __u64 syncs; 1187 1188 /** @reserved: Reserved */ 1189 __u64 reserved[2]; 1190 }; 1191 1192 /** 1193 * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 1194 * 1195 * This ioctl supports setting the following properties via the 1196 * %DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY extension, which uses the 1197 * generic @drm_xe_ext_set_property struct: 1198 * 1199 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY - set the queue priority. 1200 * CAP_SYS_NICE is required to set a value above normal. 1201 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE - set the queue timeslice 1202 * duration in microseconds. 1203 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE - set the type of PXP session 1204 * this queue will be used with. Valid values are listed in enum 1205 * drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so 1206 * there is no need to explicitly set that. When a queue of type 1207 * %DRM_XE_PXP_TYPE_HWDRM is created, the PXP default HWDRM session 1208 * (%XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if isn't already running. 1209 * Given that going into a power-saving state kills PXP HWDRM sessions, 1210 * runtime PM will be blocked while queues of this type are alive. 1211 * All PXP queues will be killed if a PXP invalidation event occurs. 1212 * 1213 * The example below shows how to use @drm_xe_exec_queue_create to create 1214 * a simple exec_queue (no parallel submission) of class 1215 * &DRM_XE_ENGINE_CLASS_RENDER. 1216 * 1217 * .. code-block:: C 1218 * 1219 * struct drm_xe_engine_class_instance instance = { 1220 * .engine_class = DRM_XE_ENGINE_CLASS_RENDER, 1221 * }; 1222 * struct drm_xe_exec_queue_create exec_queue_create = { 1223 * .extensions = 0, 1224 * .vm_id = vm, 1225 * .num_bb_per_exec = 1, 1226 * .num_eng_per_bb = 1, 1227 * .instances = to_user_pointer(&instance), 1228 * }; 1229 * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); 1230 * 1231 * Allow users to provide a hint to kernel for cases demanding low latency 1232 * profile. Please note it will have impact on power consumption. User can 1233 * indicate low latency hint with flag while creating exec queue as 1234 * mentioned below, 1235 * 1236 * struct drm_xe_exec_queue_create exec_queue_create = { 1237 * .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, 1238 * .extensions = 0, 1239 * .vm_id = vm, 1240 * .num_bb_per_exec = 1, 1241 * .num_eng_per_bb = 1, 1242 * .instances = to_user_pointer(&instance), 1243 * }; 1244 * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); 1245 * 1246 */ 1247 struct drm_xe_exec_queue_create { 1248 #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 1249 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 1250 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 1251 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2 1252 /** @extensions: Pointer to the first extension struct, if any */ 1253 __u64 extensions; 1254 1255 /** @width: submission width (number BB per exec) for this exec queue */ 1256 __u16 width; 1257 1258 /** @num_placements: number of valid placements for this exec queue */ 1259 __u16 num_placements; 1260 1261 /** @vm_id: VM to use for this exec queue */ 1262 __u32 vm_id; 1263 1264 #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0) 1265 /** @flags: flags to use for this exec queue */ 1266 __u32 flags; 1267 1268 /** @exec_queue_id: Returned exec queue ID */ 1269 __u32 exec_queue_id; 1270 1271 /** 1272 * @instances: user pointer to a 2-d array of struct 1273 * drm_xe_engine_class_instance 1274 * 1275 * length = width (i) * num_placements (j) 1276 * index = j + i * width 1277 */ 1278 __u64 instances; 1279 1280 /** @reserved: Reserved */ 1281 __u64 reserved[2]; 1282 }; 1283 1284 /** 1285 * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 1286 */ 1287 struct drm_xe_exec_queue_destroy { 1288 /** @exec_queue_id: Exec queue ID */ 1289 __u32 exec_queue_id; 1290 1291 /** @pad: MBZ */ 1292 __u32 pad; 1293 1294 /** @reserved: Reserved */ 1295 __u64 reserved[2]; 1296 }; 1297 1298 /** 1299 * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 1300 * 1301 * The @property can be: 1302 * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 1303 */ 1304 struct drm_xe_exec_queue_get_property { 1305 /** @extensions: Pointer to the first extension struct, if any */ 1306 __u64 extensions; 1307 1308 /** @exec_queue_id: Exec queue ID */ 1309 __u32 exec_queue_id; 1310 1311 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 1312 /** @property: property to get */ 1313 __u32 property; 1314 1315 /** @value: property value */ 1316 __u64 value; 1317 1318 /** @reserved: Reserved */ 1319 __u64 reserved[2]; 1320 }; 1321 1322 /** 1323 * struct drm_xe_sync - sync object 1324 * 1325 * The @type can be: 1326 * - %DRM_XE_SYNC_TYPE_SYNCOBJ 1327 * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 1328 * - %DRM_XE_SYNC_TYPE_USER_FENCE 1329 * 1330 * and the @flags can be: 1331 * - %DRM_XE_SYNC_FLAG_SIGNAL 1332 * 1333 * A minimal use of @drm_xe_sync looks like this: 1334 * 1335 * .. code-block:: C 1336 * 1337 * struct drm_xe_sync sync = { 1338 * .flags = DRM_XE_SYNC_FLAG_SIGNAL, 1339 * .type = DRM_XE_SYNC_TYPE_SYNCOBJ, 1340 * }; 1341 * struct drm_syncobj_create syncobj_create = { 0 }; 1342 * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); 1343 * sync.handle = syncobj_create.handle; 1344 * ... 1345 * use of &sync in drm_xe_exec or drm_xe_vm_bind 1346 * ... 1347 * struct drm_syncobj_wait wait = { 1348 * .handles = &sync.handle, 1349 * .timeout_nsec = INT64_MAX, 1350 * .count_handles = 1, 1351 * .flags = 0, 1352 * .first_signaled = 0, 1353 * .pad = 0, 1354 * }; 1355 * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait); 1356 */ 1357 struct drm_xe_sync { 1358 /** @extensions: Pointer to the first extension struct, if any */ 1359 __u64 extensions; 1360 1361 #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0 1362 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 1363 #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2 1364 /** @type: Type of the this sync object */ 1365 __u32 type; 1366 1367 #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0) 1368 /** @flags: Sync Flags */ 1369 __u32 flags; 1370 1371 union { 1372 /** @handle: Handle for the object */ 1373 __u32 handle; 1374 1375 /** 1376 * @addr: Address of user fence. When sync is passed in via exec 1377 * IOCTL this is a GPU address in the VM. When sync passed in via 1378 * VM bind IOCTL this is a user pointer. In either case, it is 1379 * the users responsibility that this address is present and 1380 * mapped when the user fence is signalled. Must be qword 1381 * aligned. 1382 */ 1383 __u64 addr; 1384 }; 1385 1386 /** 1387 * @timeline_value: Input for the timeline sync object. Needs to be 1388 * different than 0 when used with %DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ. 1389 */ 1390 __u64 timeline_value; 1391 1392 /** @reserved: Reserved */ 1393 __u64 reserved[2]; 1394 }; 1395 1396 /** 1397 * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC 1398 * 1399 * This is an example to use @drm_xe_exec for execution of the object 1400 * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue 1401 * (see example in @drm_xe_exec_queue_create). It can be synchronized 1402 * by using the example provided for @drm_xe_sync. 1403 * 1404 * .. code-block:: C 1405 * 1406 * struct drm_xe_exec exec = { 1407 * .exec_queue_id = exec_queue, 1408 * .syncs = &sync, 1409 * .num_syncs = 1, 1410 * .address = BIND_ADDRESS, 1411 * .num_batch_buffer = 1, 1412 * }; 1413 * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec); 1414 * 1415 */ 1416 struct drm_xe_exec { 1417 /** @extensions: Pointer to the first extension struct, if any */ 1418 __u64 extensions; 1419 1420 /** @exec_queue_id: Exec queue ID for the batch buffer */ 1421 __u32 exec_queue_id; 1422 1423 /** @num_syncs: Amount of struct drm_xe_sync in array. */ 1424 __u32 num_syncs; 1425 1426 /** @syncs: Pointer to struct drm_xe_sync array. */ 1427 __u64 syncs; 1428 1429 /** 1430 * @address: address of batch buffer if num_batch_buffer == 1 or an 1431 * array of batch buffer addresses 1432 */ 1433 __u64 address; 1434 1435 /** 1436 * @num_batch_buffer: number of batch buffer in this exec, must match 1437 * the width of the engine 1438 */ 1439 __u16 num_batch_buffer; 1440 1441 /** @pad: MBZ */ 1442 __u16 pad[3]; 1443 1444 /** @reserved: Reserved */ 1445 __u64 reserved[2]; 1446 }; 1447 1448 /** 1449 * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE 1450 * 1451 * Wait on user fence, XE will wake-up on every HW engine interrupt in the 1452 * instances list and check if user fence is complete:: 1453 * 1454 * (*addr & MASK) OP (VALUE & MASK) 1455 * 1456 * Returns to user on user fence completion or timeout. 1457 * 1458 * The @op can be: 1459 * - %DRM_XE_UFENCE_WAIT_OP_EQ 1460 * - %DRM_XE_UFENCE_WAIT_OP_NEQ 1461 * - %DRM_XE_UFENCE_WAIT_OP_GT 1462 * - %DRM_XE_UFENCE_WAIT_OP_GTE 1463 * - %DRM_XE_UFENCE_WAIT_OP_LT 1464 * - %DRM_XE_UFENCE_WAIT_OP_LTE 1465 * 1466 * and the @flags can be: 1467 * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME 1468 * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP 1469 * 1470 * The @mask values can be for example: 1471 * - 0xffu for u8 1472 * - 0xffffu for u16 1473 * - 0xffffffffu for u32 1474 * - 0xffffffffffffffffu for u64 1475 */ 1476 struct drm_xe_wait_user_fence { 1477 /** @extensions: Pointer to the first extension struct, if any */ 1478 __u64 extensions; 1479 1480 /** 1481 * @addr: user pointer address to wait on, must qword aligned 1482 */ 1483 __u64 addr; 1484 1485 #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0 1486 #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1 1487 #define DRM_XE_UFENCE_WAIT_OP_GT 0x2 1488 #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3 1489 #define DRM_XE_UFENCE_WAIT_OP_LT 0x4 1490 #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5 1491 /** @op: wait operation (type of comparison) */ 1492 __u16 op; 1493 1494 #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) 1495 /** @flags: wait flags */ 1496 __u16 flags; 1497 1498 /** @pad: MBZ */ 1499 __u32 pad; 1500 1501 /** @value: compare value */ 1502 __u64 value; 1503 1504 /** @mask: comparison mask */ 1505 __u64 mask; 1506 1507 /** 1508 * @timeout: how long to wait before bailing, value in nanoseconds. 1509 * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) 1510 * it contains timeout expressed in nanoseconds to wait (fence will 1511 * expire at now() + timeout). 1512 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait 1513 * will end at timeout (uses system MONOTONIC_CLOCK). 1514 * Passing negative timeout leads to neverending wait. 1515 * 1516 * On relative timeout this value is updated with timeout left 1517 * (for restarting the call in case of signal delivery). 1518 * On absolute timeout this value stays intact (restarted call still 1519 * expire at the same point of time). 1520 */ 1521 __s64 timeout; 1522 1523 /** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */ 1524 __u32 exec_queue_id; 1525 1526 /** @pad2: MBZ */ 1527 __u32 pad2; 1528 1529 /** @reserved: Reserved */ 1530 __u64 reserved[2]; 1531 }; 1532 1533 /** 1534 * enum drm_xe_observation_type - Observation stream types 1535 */ 1536 enum drm_xe_observation_type { 1537 /** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */ 1538 DRM_XE_OBSERVATION_TYPE_OA, 1539 /** @DRM_XE_OBSERVATION_TYPE_EU_STALL: EU stall sampling observation stream type */ 1540 DRM_XE_OBSERVATION_TYPE_EU_STALL, 1541 }; 1542 1543 /** 1544 * enum drm_xe_observation_op - Observation stream ops 1545 */ 1546 enum drm_xe_observation_op { 1547 /** @DRM_XE_OBSERVATION_OP_STREAM_OPEN: Open an observation stream */ 1548 DRM_XE_OBSERVATION_OP_STREAM_OPEN, 1549 1550 /** @DRM_XE_OBSERVATION_OP_ADD_CONFIG: Add observation stream config */ 1551 DRM_XE_OBSERVATION_OP_ADD_CONFIG, 1552 1553 /** @DRM_XE_OBSERVATION_OP_REMOVE_CONFIG: Remove observation stream config */ 1554 DRM_XE_OBSERVATION_OP_REMOVE_CONFIG, 1555 }; 1556 1557 /** 1558 * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION 1559 * 1560 * The observation layer enables multiplexing observation streams of 1561 * multiple types. The actual params for a particular stream operation are 1562 * supplied via the @param pointer (use __copy_from_user to get these 1563 * params). 1564 */ 1565 struct drm_xe_observation_param { 1566 /** @extensions: Pointer to the first extension struct, if any */ 1567 __u64 extensions; 1568 /** @observation_type: observation stream type, of enum @drm_xe_observation_type */ 1569 __u64 observation_type; 1570 /** @observation_op: observation stream op, of enum @drm_xe_observation_op */ 1571 __u64 observation_op; 1572 /** @param: Pointer to actual stream params */ 1573 __u64 param; 1574 }; 1575 1576 /** 1577 * enum drm_xe_observation_ioctls - Observation stream fd ioctl's 1578 * 1579 * Information exchanged between userspace and kernel for observation fd 1580 * ioctl's is stream type specific 1581 */ 1582 enum drm_xe_observation_ioctls { 1583 /** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */ 1584 DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0), 1585 1586 /** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */ 1587 DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1), 1588 1589 /** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */ 1590 DRM_XE_OBSERVATION_IOCTL_CONFIG = _IO('i', 0x2), 1591 1592 /** @DRM_XE_OBSERVATION_IOCTL_STATUS: Return observation stream status */ 1593 DRM_XE_OBSERVATION_IOCTL_STATUS = _IO('i', 0x3), 1594 1595 /** @DRM_XE_OBSERVATION_IOCTL_INFO: Return observation stream info */ 1596 DRM_XE_OBSERVATION_IOCTL_INFO = _IO('i', 0x4), 1597 }; 1598 1599 /** 1600 * enum drm_xe_oa_unit_type - OA unit types 1601 */ 1602 enum drm_xe_oa_unit_type { 1603 /** 1604 * @DRM_XE_OA_UNIT_TYPE_OAG: OAG OA unit. OAR/OAC are considered 1605 * sub-types of OAG. For OAR/OAC, use OAG. 1606 */ 1607 DRM_XE_OA_UNIT_TYPE_OAG, 1608 1609 /** @DRM_XE_OA_UNIT_TYPE_OAM: OAM OA unit */ 1610 DRM_XE_OA_UNIT_TYPE_OAM, 1611 }; 1612 1613 /** 1614 * struct drm_xe_oa_unit - describe OA unit 1615 */ 1616 struct drm_xe_oa_unit { 1617 /** @extensions: Pointer to the first extension struct, if any */ 1618 __u64 extensions; 1619 1620 /** @oa_unit_id: OA unit ID */ 1621 __u32 oa_unit_id; 1622 1623 /** @oa_unit_type: OA unit type of @drm_xe_oa_unit_type */ 1624 __u32 oa_unit_type; 1625 1626 /** @capabilities: OA capabilities bit-mask */ 1627 __u64 capabilities; 1628 #define DRM_XE_OA_CAPS_BASE (1 << 0) 1629 #define DRM_XE_OA_CAPS_SYNCS (1 << 1) 1630 #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2) 1631 #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3) 1632 1633 /** @oa_timestamp_freq: OA timestamp freq */ 1634 __u64 oa_timestamp_freq; 1635 1636 /** @reserved: MBZ */ 1637 __u64 reserved[4]; 1638 1639 /** @num_engines: number of engines in @eci array */ 1640 __u64 num_engines; 1641 1642 /** @eci: engines attached to this OA unit */ 1643 struct drm_xe_engine_class_instance eci[]; 1644 }; 1645 1646 /** 1647 * struct drm_xe_query_oa_units - describe OA units 1648 * 1649 * If a query is made with a struct drm_xe_device_query where .query 1650 * is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct 1651 * drm_xe_query_oa_units in .data. 1652 * 1653 * OA unit properties for all OA units can be accessed using a code block 1654 * such as the one below: 1655 * 1656 * .. code-block:: C 1657 * 1658 * struct drm_xe_query_oa_units *qoa; 1659 * struct drm_xe_oa_unit *oau; 1660 * u8 *poau; 1661 * 1662 * // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: 1663 * poau = (u8 *)&qoa->oa_units[0]; 1664 * for (int i = 0; i < qoa->num_oa_units; i++) { 1665 * oau = (struct drm_xe_oa_unit *)poau; 1666 * // Access 'struct drm_xe_oa_unit' fields here 1667 * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); 1668 * } 1669 */ 1670 struct drm_xe_query_oa_units { 1671 /** @extensions: Pointer to the first extension struct, if any */ 1672 __u64 extensions; 1673 /** @num_oa_units: number of OA units returned in oau[] */ 1674 __u32 num_oa_units; 1675 /** @pad: MBZ */ 1676 __u32 pad; 1677 /** 1678 * @oa_units: struct @drm_xe_oa_unit array returned for this device. 1679 * Written below as a u64 array to avoid problems with nested flexible 1680 * arrays with some compilers 1681 */ 1682 __u64 oa_units[]; 1683 }; 1684 1685 /** 1686 * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec 1687 * 52198/60942 1688 */ 1689 enum drm_xe_oa_format_type { 1690 /** @DRM_XE_OA_FMT_TYPE_OAG: OAG report format */ 1691 DRM_XE_OA_FMT_TYPE_OAG, 1692 /** @DRM_XE_OA_FMT_TYPE_OAR: OAR report format */ 1693 DRM_XE_OA_FMT_TYPE_OAR, 1694 /** @DRM_XE_OA_FMT_TYPE_OAM: OAM report format */ 1695 DRM_XE_OA_FMT_TYPE_OAM, 1696 /** @DRM_XE_OA_FMT_TYPE_OAC: OAC report format */ 1697 DRM_XE_OA_FMT_TYPE_OAC, 1698 /** @DRM_XE_OA_FMT_TYPE_OAM_MPEC: OAM SAMEDIA or OAM MPEC report format */ 1699 DRM_XE_OA_FMT_TYPE_OAM_MPEC, 1700 /** @DRM_XE_OA_FMT_TYPE_PEC: PEC report format */ 1701 DRM_XE_OA_FMT_TYPE_PEC, 1702 }; 1703 1704 /** 1705 * enum drm_xe_oa_property_id - OA stream property id's 1706 * 1707 * Stream params are specified as a chain of @drm_xe_ext_set_property 1708 * struct's, with @property values from enum @drm_xe_oa_property_id and 1709 * @drm_xe_user_extension base.name set to @DRM_XE_OA_EXTENSION_SET_PROPERTY. 1710 * @param field in struct @drm_xe_observation_param points to the first 1711 * @drm_xe_ext_set_property struct. 1712 * 1713 * Exactly the same mechanism is also used for stream reconfiguration using the 1714 * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a 1715 * subset of properties below can be specified for stream reconfiguration. 1716 */ 1717 enum drm_xe_oa_property_id { 1718 #define DRM_XE_OA_EXTENSION_SET_PROPERTY 0 1719 /** 1720 * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open 1721 * the OA stream, see @oa_unit_id in 'struct 1722 * drm_xe_query_oa_units'. Defaults to 0 if not provided. 1723 */ 1724 DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1, 1725 1726 /** 1727 * @DRM_XE_OA_PROPERTY_SAMPLE_OA: A value of 1 requests inclusion of raw 1728 * OA unit reports or stream samples in a global buffer attached to an 1729 * OA unit. 1730 */ 1731 DRM_XE_OA_PROPERTY_SAMPLE_OA, 1732 1733 /** 1734 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA 1735 * reports, previously added via @DRM_XE_OBSERVATION_OP_ADD_CONFIG. 1736 */ 1737 DRM_XE_OA_PROPERTY_OA_METRIC_SET, 1738 1739 /** @DRM_XE_OA_PROPERTY_OA_FORMAT: OA counter report format */ 1740 DRM_XE_OA_PROPERTY_OA_FORMAT, 1741 /* 1742 * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942, 1743 * in terms of the following quantities: a. enum @drm_xe_oa_format_type 1744 * b. Counter select c. Counter size and d. BC report. Also refer to the 1745 * oa_formats array in drivers/gpu/drm/xe/xe_oa.c. 1746 */ 1747 #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xffu << 0) 1748 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xffu << 8) 1749 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xffu << 16) 1750 #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xffu << 24) 1751 1752 /** 1753 * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit 1754 * sampling with sampling frequency proportional to 2^(period_exponent + 1) 1755 */ 1756 DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, 1757 1758 /** 1759 * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA 1760 * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE). 1761 */ 1762 DRM_XE_OA_PROPERTY_OA_DISABLED, 1763 1764 /** 1765 * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific 1766 * @exec_queue_id. OA queries can be executed on this exec queue. 1767 */ 1768 DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID, 1769 1770 /** 1771 * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to 1772 * pass along with @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0. 1773 */ 1774 DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 1775 1776 /** 1777 * @DRM_XE_OA_PROPERTY_NO_PREEMPT: Allow preemption and timeslicing 1778 * to be disabled for the stream exec queue. 1779 */ 1780 DRM_XE_OA_PROPERTY_NO_PREEMPT, 1781 1782 /** 1783 * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array 1784 * specified in @DRM_XE_OA_PROPERTY_SYNCS 1785 */ 1786 DRM_XE_OA_PROPERTY_NUM_SYNCS, 1787 1788 /** 1789 * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array 1790 * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA 1791 * configuration will wait till input fences signal. Output fences 1792 * will signal after the new OA configuration takes effect. For 1793 * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar 1794 * to the VM bind case. 1795 */ 1796 DRM_XE_OA_PROPERTY_SYNCS, 1797 1798 /** 1799 * @DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE: Size of OA buffer to be 1800 * allocated by the driver in bytes. Supported sizes are powers of 1801 * 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA 1802 * buffer is allocated by default. 1803 */ 1804 DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, 1805 1806 /** 1807 * @DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS: Number of reports to wait 1808 * for before unblocking poll or read 1809 */ 1810 DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS, 1811 }; 1812 1813 /** 1814 * struct drm_xe_oa_config - OA metric configuration 1815 * 1816 * Multiple OA configs can be added using @DRM_XE_OBSERVATION_OP_ADD_CONFIG. A 1817 * particular config can be specified when opening an OA stream using 1818 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET property. 1819 */ 1820 struct drm_xe_oa_config { 1821 /** @extensions: Pointer to the first extension struct, if any */ 1822 __u64 extensions; 1823 1824 /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */ 1825 char uuid[36]; 1826 1827 /** @n_regs: Number of regs in @regs_ptr */ 1828 __u32 n_regs; 1829 1830 /** 1831 * @regs_ptr: Pointer to (register address, value) pairs for OA config 1832 * registers. Expected length of buffer is: (2 * sizeof(u32) * @n_regs). 1833 */ 1834 __u64 regs_ptr; 1835 }; 1836 1837 /** 1838 * struct drm_xe_oa_stream_status - OA stream status returned from 1839 * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can 1840 * call the ioctl to query stream status in response to EIO errno from 1841 * observation fd read(). 1842 */ 1843 struct drm_xe_oa_stream_status { 1844 /** @extensions: Pointer to the first extension struct, if any */ 1845 __u64 extensions; 1846 1847 /** @oa_status: OA stream status (see Bspec 46717/61226) */ 1848 __u64 oa_status; 1849 #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3) 1850 #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2) 1851 #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1) 1852 #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0) 1853 1854 /** @reserved: reserved for future use */ 1855 __u64 reserved[3]; 1856 }; 1857 1858 /** 1859 * struct drm_xe_oa_stream_info - OA stream info returned from 1860 * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl 1861 */ 1862 struct drm_xe_oa_stream_info { 1863 /** @extensions: Pointer to the first extension struct, if any */ 1864 __u64 extensions; 1865 1866 /** @oa_buf_size: OA buffer size */ 1867 __u64 oa_buf_size; 1868 1869 /** @reserved: reserved for future use */ 1870 __u64 reserved[3]; 1871 }; 1872 1873 /** 1874 * enum drm_xe_pxp_session_type - Supported PXP session types. 1875 * 1876 * We currently only support HWDRM sessions, which are used for protected 1877 * content that ends up being displayed, but the HW supports multiple types, so 1878 * we might extend support in the future. 1879 */ 1880 enum drm_xe_pxp_session_type { 1881 /** @DRM_XE_PXP_TYPE_NONE: PXP not used */ 1882 DRM_XE_PXP_TYPE_NONE = 0, 1883 /** 1884 * @DRM_XE_PXP_TYPE_HWDRM: HWDRM sessions are used for content that ends 1885 * up on the display. 1886 */ 1887 DRM_XE_PXP_TYPE_HWDRM = 1, 1888 }; 1889 1890 /* ID of the protected content session managed by Xe when PXP is active */ 1891 #define DRM_XE_PXP_HWDRM_DEFAULT_SESSION 0xf 1892 1893 /** 1894 * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids. 1895 * 1896 * These properties are passed to the driver at open as a chain of 1897 * @drm_xe_ext_set_property structures with @property set to these 1898 * properties' enums and @value set to the corresponding values of these 1899 * properties. @drm_xe_user_extension base.name should be set to 1900 * @DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY. 1901 * 1902 * With the file descriptor obtained from open, user space must enable 1903 * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before 1904 * calling read(). EIO errno from read() indicates HW dropped data 1905 * due to full buffer. 1906 */ 1907 enum drm_xe_eu_stall_property_id { 1908 #define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY 0 1909 /** 1910 * @DRM_XE_EU_STALL_PROP_GT_ID: @gt_id of the GT on which 1911 * EU stall data will be captured. 1912 */ 1913 DRM_XE_EU_STALL_PROP_GT_ID = 1, 1914 1915 /** 1916 * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate in 1917 * GPU cycles from @sampling_rates in struct @drm_xe_query_eu_stall 1918 */ 1919 DRM_XE_EU_STALL_PROP_SAMPLE_RATE, 1920 1921 /** 1922 * @DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS: Minimum number of 1923 * EU stall data reports to be present in the kernel buffer 1924 * before unblocking a blocked poll or read. 1925 */ 1926 DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS, 1927 }; 1928 1929 /** 1930 * struct drm_xe_query_eu_stall - Information about EU stall sampling. 1931 * 1932 * If a query is made with a struct @drm_xe_device_query where .query 1933 * is equal to @DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses 1934 * struct @drm_xe_query_eu_stall in .data. 1935 */ 1936 struct drm_xe_query_eu_stall { 1937 /** @extensions: Pointer to the first extension struct, if any */ 1938 __u64 extensions; 1939 1940 /** @capabilities: EU stall capabilities bit-mask */ 1941 __u64 capabilities; 1942 #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0) 1943 1944 /** @record_size: size of each EU stall data record */ 1945 __u64 record_size; 1946 1947 /** @per_xecore_buf_size: internal per XeCore buffer size */ 1948 __u64 per_xecore_buf_size; 1949 1950 /** @reserved: Reserved */ 1951 __u64 reserved[5]; 1952 1953 /** @num_sampling_rates: Number of sampling rates in @sampling_rates array */ 1954 __u64 num_sampling_rates; 1955 1956 /** 1957 * @sampling_rates: Flexible array of sampling rates 1958 * sorted in the fastest to slowest order. 1959 * Sampling rates are specified in GPU clock cycles. 1960 */ 1961 __u64 sampling_rates[]; 1962 }; 1963 1964 #if defined(__cplusplus) 1965 } 1966 #endif 1967 1968 #endif /* _UAPI_XE_DRM_H_ */ 1969