1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /** 34 * DOC: overview 35 * 36 * In the DRM subsystem, framebuffer pixel formats are described using the 37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 38 * fourcc code, a Format Modifier may optionally be provided, in order to 39 * further describe the buffer's format - for example tiling or compression. 40 * 41 * Format Modifiers 42 * ---------------- 43 * 44 * Format modifiers are used in conjunction with a fourcc code, forming a 45 * unique fourcc:modifier pair. This format:modifier pair must fully define the 46 * format and data layout of the buffer, and should be the only way to describe 47 * that particular buffer. 48 * 49 * Having multiple fourcc:modifier pairs which describe the same layout should 50 * be avoided, as such aliases run the risk of different drivers exposing 51 * different names for the same data format, forcing userspace to understand 52 * that they are aliases. 53 * 54 * Format modifiers may change any property of the buffer, including the number 55 * of planes and/or the required allocation size. Format modifiers are 56 * vendor-namespaced, and as such the relationship between a fourcc code and a 57 * modifier is specific to the modifier being used. For example, some modifiers 58 * may preserve meaning - such as number of planes - from the fourcc code, 59 * whereas others may not. 60 * 61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 62 * match only a single modifier. A modifier must not be a subset of layouts of 63 * another modifier. For instance, it's incorrect to encode pitch alignment in 64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 65 * aligned modifier. That said, modifiers can have implicit minimal 66 * requirements. 67 * 68 * For modifiers where the combination of fourcc code and modifier can alias, 69 * a canonical pair needs to be defined and used by all drivers. Preferred 70 * combinations are also encouraged where all combinations might lead to 71 * confusion and unnecessarily reduced interoperability. An example for the 72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 73 * 74 * There are two kinds of modifier users: 75 * 76 * - Kernel and user-space drivers: for drivers it's important that modifiers 77 * don't alias, otherwise two drivers might support the same format but use 78 * different aliases, preventing them from sharing buffers in an efficient 79 * format. 80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 81 * see modifiers as opaque tokens they can check for equality and intersect. 82 * These users mustn't need to know to reason about the modifier value 83 * (i.e. they are not expected to extract information out of the modifier). 84 * 85 * Vendors should document their modifier usage in as much detail as 86 * possible, to ensure maximum compatibility across devices, drivers and 87 * applications. 88 * 89 * The authoritative list of format modifier codes is found in 90 * `include/uapi/drm/drm_fourcc.h` 91 * 92 * Open Source User Waiver 93 * ----------------------- 94 * 95 * Because this is the authoritative source for pixel formats and modifiers 96 * referenced by GL, Vulkan extensions and other standards and hence used both 97 * by open source and closed source driver stacks, the usual requirement for an 98 * upstream in-kernel or open source userspace user does not apply. 99 * 100 * To ensure, as much as feasible, compatibility across stacks and avoid 101 * confusion with incompatible enumerations stakeholders for all relevant driver 102 * stacks should approve additions. 103 */ 104 105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 106 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 107 108 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 109 110 /* Reserve 0 for the invalid format specifier */ 111 #define DRM_FORMAT_INVALID 0 112 113 /* color index */ 114 #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */ 115 #define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */ 116 #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ 117 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 118 119 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */ 120 #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */ 121 122 /* 2 bpp Darkness (inverse relationship between channel value and brightness) */ 123 #define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */ 124 125 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */ 126 #define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */ 127 128 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */ 129 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */ 130 131 /* 1 bpp Red (direct relationship between channel value and brightness) */ 132 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */ 133 134 /* 2 bpp Red (direct relationship between channel value and brightness) */ 135 #define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */ 136 137 /* 4 bpp Red (direct relationship between channel value and brightness) */ 138 #define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */ 139 140 /* 8 bpp Red (direct relationship between channel value and brightness) */ 141 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 142 143 /* 10 bpp Red (direct relationship between channel value and brightness) */ 144 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ 145 146 /* 12 bpp Red (direct relationship between channel value and brightness) */ 147 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ 148 149 /* 16 bpp Red (direct relationship between channel value and brightness) */ 150 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 151 152 /* 16 bpp RG */ 153 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 154 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 155 156 /* 32 bpp RG */ 157 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 158 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 159 160 /* 8 bpp RGB */ 161 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 162 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 163 164 /* 16 bpp RGB */ 165 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 166 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 167 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 168 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 169 170 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 171 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 172 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 173 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 174 175 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 176 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 177 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 178 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 179 180 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 181 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 182 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 183 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 184 185 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 186 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 187 188 /* 24 bpp RGB */ 189 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 190 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 191 192 /* 32 bpp RGB */ 193 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 194 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 195 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 196 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 197 198 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 199 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 200 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 201 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 202 203 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 204 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 205 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 206 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 207 208 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 209 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 210 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 211 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 212 213 /* 48 bpp RGB */ 214 #define DRM_FORMAT_RGB161616 fourcc_code('R', 'G', '4', '8') /* [47:0] R:G:B 16:16:16 little endian */ 215 #define DRM_FORMAT_BGR161616 fourcc_code('B', 'G', '4', '8') /* [47:0] B:G:R 16:16:16 little endian */ 216 217 /* 64 bpp RGB */ 218 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 219 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 220 221 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 222 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 223 224 /* 225 * Half-Floating point - 16b/component 226 * IEEE 754-2008 binary16 half-precision float 227 * [15:0] sign:exponent:mantissa 1:5:10 228 */ 229 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 230 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 231 232 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 233 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 234 235 #define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ 236 #define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ 237 #define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */ 238 239 /* 240 * Floating point - 32b/component 241 * IEEE 754-2008 binary32 float 242 * [31:0] sign:exponent:mantissa 1:8:23 243 */ 244 #define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ 245 #define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */ 246 #define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */ 247 #define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */ 248 249 /* 250 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 251 * of unused padding per component: 252 */ 253 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 254 255 /* packed YCbCr */ 256 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 257 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 258 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 259 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 260 261 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 262 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */ 263 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 264 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */ 265 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 266 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 267 268 /* 269 * packed Y2xx indicate for each component, xx valid data occupy msb 270 * 16-xx padding occupy lsb 271 */ 272 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 273 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 274 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 275 276 /* 277 * packed Y4xx indicate for each component, xx valid data occupy msb 278 * 16-xx padding occupy lsb except Y410 279 */ 280 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 281 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 282 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 283 284 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 285 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 286 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 287 288 /* 289 * packed YCbCr420 2x2 tiled formats 290 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 291 */ 292 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 293 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 294 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 295 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 296 297 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 298 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 299 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 300 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 301 302 /* 303 * 1-plane YUV 4:2:0 304 * In these formats, the component ordering is specified (Y, followed by U 305 * then V), but the exact Linear layout is undefined. 306 * These formats can only be used with a non-Linear modifier. 307 */ 308 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 309 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 310 311 /* 312 * 2 plane RGB + A 313 * index 0 = RGB plane, same format as the corresponding non _A8 format has 314 * index 1 = A plane, [7:0] A 315 */ 316 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 317 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 318 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 319 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 320 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 321 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 322 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 323 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 324 325 /* 326 * 2 plane YCbCr 327 * index 0 = Y plane, [7:0] Y 328 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 329 * or 330 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 331 */ 332 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 333 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 334 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 335 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 336 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 337 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 338 /* 339 * 2 plane YCbCr 340 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 341 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 342 */ 343 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 344 #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */ 345 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */ 346 347 /* 348 * 2 plane YCbCr MSB aligned 349 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 350 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 351 */ 352 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 353 354 /* 355 * 2 plane YCbCr MSB aligned 356 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 357 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 358 */ 359 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 360 361 /* 362 * 2 plane YCbCr MSB aligned 363 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 364 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 365 */ 366 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 367 368 /* 369 * 2 plane YCbCr MSB aligned 370 * index 0 = Y plane, [15:0] Y little endian 371 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 372 */ 373 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 374 375 /* 2 plane YCbCr420. 376 * 3 10 bit components and 2 padding bits packed into 4 bytes. 377 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian 378 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian 379 */ 380 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ 381 382 /* 3 plane non-subsampled (444) YCbCr 383 * 16 bits per component, but only 10 bits are used and 6 bits are padded 384 * index 0: Y plane, [15:0] Y:x [10:6] little endian 385 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 386 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 387 */ 388 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 389 390 /* 3 plane non-subsampled (444) YCrCb 391 * 16 bits per component, but only 10 bits are used and 6 bits are padded 392 * index 0: Y plane, [15:0] Y:x [10:6] little endian 393 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 394 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 395 */ 396 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 397 398 /* 399 * 3 plane YCbCr LSB aligned 400 * In order to use these formats in a similar fashion to MSB aligned ones 401 * implementation can multiply the values by 2^6=64. For that reason the padding 402 * must only contain zeros. 403 * index 0 = Y plane, [15:0] z:Y [6:10] little endian 404 * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian 405 * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian 406 */ 407 #define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ 408 #define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ 409 #define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */ 410 411 /* 412 * 3 plane YCbCr LSB aligned 413 * In order to use these formats in a similar fashion to MSB aligned ones 414 * implementation can multiply the values by 2^4=16. For that reason the padding 415 * must only contain zeros. 416 * index 0 = Y plane, [15:0] z:Y [4:12] little endian 417 * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian 418 * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian 419 */ 420 #define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ 421 #define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ 422 #define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */ 423 424 /* 425 * 3 plane YCbCr 426 * index 0 = Y plane, [15:0] Y little endian 427 * index 1 = Cr plane, [15:0] Cr little endian 428 * index 2 = Cb plane, [15:0] Cb little endian 429 */ 430 #define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ 431 #define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ 432 #define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */ 433 434 /* 435 * 3 plane YCbCr 436 * index 0: Y plane, [7:0] Y 437 * index 1: Cb plane, [7:0] Cb 438 * index 2: Cr plane, [7:0] Cr 439 * or 440 * index 1: Cr plane, [7:0] Cr 441 * index 2: Cb plane, [7:0] Cb 442 */ 443 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 444 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 445 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 446 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 447 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 448 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 449 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 450 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 451 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 452 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 453 454 455 /* 456 * Format Modifiers: 457 * 458 * Format modifiers describe, typically, a re-ordering or modification 459 * of the data in a plane of an FB. This can be used to express tiled/ 460 * swizzled formats, or compression, or a combination of the two. 461 * 462 * The upper 8 bits of the format modifier are a vendor-id as assigned 463 * below. The lower 56 bits are assigned as vendor sees fit. 464 */ 465 466 /* Vendor Ids: */ 467 #define DRM_FORMAT_MOD_VENDOR_NONE 0 468 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 469 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 470 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 471 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 472 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 473 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 474 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 475 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 476 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 477 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 478 #define DRM_FORMAT_MOD_VENDOR_MTK 0x0b 479 #define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c 480 481 /* add more to the end as needed */ 482 483 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 484 485 #define fourcc_mod_get_vendor(modifier) \ 486 (((modifier) >> 56) & 0xff) 487 488 #define fourcc_mod_is_vendor(modifier, vendor) \ 489 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) 490 491 #define fourcc_mod_code(vendor, val) \ 492 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 493 494 /* 495 * Format Modifier tokens: 496 * 497 * When adding a new token please document the layout with a code comment, 498 * similar to the fourcc codes above. drm_fourcc.h is considered the 499 * authoritative source for all of these. 500 * 501 * Generic modifier names: 502 * 503 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 504 * for layouts which are common across multiple vendors. To preserve 505 * compatibility, in cases where a vendor-specific definition already exists and 506 * a generic name for it is desired, the common name is a purely symbolic alias 507 * and must use the same numerical value as the original definition. 508 * 509 * Note that generic names should only be used for modifiers which describe 510 * generic layouts (such as pixel re-ordering), which may have 511 * independently-developed support across multiple vendors. 512 * 513 * In future cases where a generic layout is identified before merging with a 514 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 515 * 'NONE' could be considered. This should only be for obvious, exceptional 516 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 517 * apply to a single vendor. 518 * 519 * Generic names should not be used for cases where multiple hardware vendors 520 * have implementations of the same standardised compression scheme (such as 521 * AFBC). In those cases, all implementations should use the same format 522 * modifier(s), reflecting the vendor of the standard. 523 */ 524 525 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 526 527 /* 528 * Invalid Modifier 529 * 530 * This modifier can be used as a sentinel to terminate the format modifiers 531 * list, or to initialize a variable with an invalid modifier. It might also be 532 * used to report an error back to userspace for certain APIs. 533 */ 534 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 535 536 /* 537 * Linear Layout 538 * 539 * Just plain linear layout. Note that this is different from no specifying any 540 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 541 * which tells the driver to also take driver-internal information into account 542 * and so might actually result in a tiled framebuffer. 543 */ 544 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 545 546 /* 547 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 548 * 549 * The "none" format modifier doesn't actually mean that the modifier is 550 * implicit, instead it means that the layout is linear. Whether modifiers are 551 * used is out-of-band information carried in an API-specific way (e.g. in a 552 * flag for drm_mode_fb_cmd2). 553 */ 554 #define DRM_FORMAT_MOD_NONE 0 555 556 /* Intel framebuffer modifiers */ 557 558 /* 559 * Intel X-tiling layout 560 * 561 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 562 * in row-major layout. Within the tile bytes are laid out row-major, with 563 * a platform-dependent stride. On top of that the memory can apply 564 * platform-depending swizzling of some higher address bits into bit6. 565 * 566 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 567 * On earlier platforms the is highly platforms specific and not useful for 568 * cross-driver sharing. It exists since on a given platform it does uniquely 569 * identify the layout in a simple way for i915-specific userspace, which 570 * facilitated conversion of userspace to modifiers. Additionally the exact 571 * format on some really old platforms is not known. 572 */ 573 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 574 575 /* 576 * Intel Y-tiling layout 577 * 578 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 579 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 580 * chunks column-major, with a platform-dependent height. On top of that the 581 * memory can apply platform-depending swizzling of some higher address bits 582 * into bit6. 583 * 584 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 585 * On earlier platforms the is highly platforms specific and not useful for 586 * cross-driver sharing. It exists since on a given platform it does uniquely 587 * identify the layout in a simple way for i915-specific userspace, which 588 * facilitated conversion of userspace to modifiers. Additionally the exact 589 * format on some really old platforms is not known. 590 */ 591 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 592 593 /* 594 * Intel Yf-tiling layout 595 * 596 * This is a tiled layout using 4Kb tiles in row-major layout. 597 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 598 * are arranged in four groups (two wide, two high) with column-major layout. 599 * Each group therefore consists out of four 256 byte units, which are also laid 600 * out as 2x2 column-major. 601 * 256 byte units are made out of four 64 byte blocks of pixels, producing 602 * either a square block or a 2:1 unit. 603 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 604 * in pixel depends on the pixel depth. 605 */ 606 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 607 608 /* 609 * Intel color control surface (CCS) for render compression 610 * 611 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 612 * The main surface will be plane index 0 and must be Y/Yf-tiled, 613 * the CCS will be plane index 1. 614 * 615 * Each CCS tile matches a 1024x512 pixel area of the main surface. 616 * To match certain aspects of the 3D hardware the CCS is 617 * considered to be made up of normal 128Bx32 Y tiles, Thus 618 * the CCS pitch must be specified in multiples of 128 bytes. 619 * 620 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 621 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 622 * But that fact is not relevant unless the memory is accessed 623 * directly. 624 */ 625 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 626 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 627 628 /* 629 * Intel color control surfaces (CCS) for Gen-12 render compression. 630 * 631 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 632 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 633 * main surface. In other words, 4 bits in CCS map to a main surface cache 634 * line pair. The main surface pitch is required to be a multiple of four 635 * Y-tile widths. 636 */ 637 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 638 639 /* 640 * Intel color control surfaces (CCS) for Gen-12 media compression 641 * 642 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 643 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 644 * main surface. In other words, 4 bits in CCS map to a main surface cache 645 * line pair. The main surface pitch is required to be a multiple of four 646 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 647 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 648 * planes 2 and 3 for the respective CCS. 649 */ 650 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 651 652 /* 653 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 654 * compression. 655 * 656 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 657 * and at index 1. The clear color is stored at index 2, and the pitch should 658 * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits 659 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 660 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 661 * the converted clear color of size 64 bits. The first 32 bits store the Lower 662 * Converted Clear Color value and the next 32 bits store the Higher Converted 663 * Clear Color value when applicable. The Converted Clear Color values are 664 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 665 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 666 * corresponds to an area of 4x1 tiles in the main surface. The main surface 667 * pitch is required to be a multiple of 4 tile widths. 668 */ 669 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 670 671 /* 672 * Intel Tile 4 layout 673 * 674 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same 675 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It 676 * only differs from Tile Y at the 256B granularity in between. At this 677 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape 678 * of 64B x 8 rows. 679 */ 680 #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) 681 682 /* 683 * Intel color control surfaces (CCS) for DG2 render compression. 684 * 685 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 686 * outside of the GEM object in a reserved memory area dedicated for the 687 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 688 * main surface pitch is required to be a multiple of four Tile 4 widths. 689 */ 690 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) 691 692 /* 693 * Intel color control surfaces (CCS) for DG2 media compression. 694 * 695 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 696 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 697 * 0 and 1, respectively. The CCS for all planes are stored outside of the 698 * GEM object in a reserved memory area dedicated for the storage of the 699 * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface 700 * pitch is required to be a multiple of four Tile 4 widths. 701 */ 702 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) 703 704 /* 705 * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. 706 * 707 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 708 * outside of the GEM object in a reserved memory area dedicated for the 709 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 710 * main surface pitch is required to be a multiple of four Tile 4 widths. The 711 * clear color is stored at plane index 1 and the pitch should be 64 bytes 712 * aligned. The format of the 256 bits of clear color data matches the one used 713 * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description 714 * for details. 715 */ 716 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) 717 718 /* 719 * Intel Color Control Surfaces (CCS) for display ver. 14 render compression. 720 * 721 * The main surface is tile4 and at plane index 0, the CCS is linear and 722 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 723 * main surface. In other words, 4 bits in CCS map to a main surface cache 724 * line pair. The main surface pitch is required to be a multiple of four 725 * tile4 widths. 726 */ 727 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13) 728 729 /* 730 * Intel Color Control Surfaces (CCS) for display ver. 14 media compression 731 * 732 * The main surface is tile4 and at plane index 0, the CCS is linear and 733 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 734 * main surface. In other words, 4 bits in CCS map to a main surface cache 735 * line pair. The main surface pitch is required to be a multiple of four 736 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the 737 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 738 * planes 2 and 3 for the respective CCS. 739 */ 740 #define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14) 741 742 /* 743 * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render 744 * compression. 745 * 746 * The main surface is tile4 and is at plane index 0 whereas CCS is linear 747 * and at index 1. The clear color is stored at index 2, and the pitch should 748 * be ignored. The clear color structure is 256 bits. The first 128 bits 749 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 750 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 751 * the converted clear color of size 64 bits. The first 32 bits store the Lower 752 * Converted Clear Color value and the next 32 bits store the Higher Converted 753 * Clear Color value when applicable. The Converted Clear Color values are 754 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 755 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 756 * corresponds to an area of 4x1 tiles in the main surface. The main surface 757 * pitch is required to be a multiple of 4 tile widths. 758 */ 759 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) 760 761 /* 762 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 763 * on integrated graphics 764 * 765 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 766 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 767 * 0 and 1, respectively. The CCS for all planes are stored outside of the 768 * GEM object in a reserved memory area dedicated for the storage of the 769 * CCS data for all compressible GEM objects. 770 */ 771 #define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) 772 773 /* 774 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 775 * on discrete graphics 776 * 777 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 778 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 779 * 0 and 1, respectively. The CCS for all planes are stored outside of the 780 * GEM object in a reserved memory area dedicated for the storage of the 781 * CCS data for all compressible GEM objects. The GEM object must be stored in 782 * contiguous memory with a size aligned to 64KB 783 */ 784 #define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) 785 786 /* 787 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 788 * 789 * Macroblocks are laid in a Z-shape, and each pixel data is following the 790 * standard NV12 style. 791 * As for NV12, an image is the result of two frame buffers: one for Y, 792 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 793 * Alignment requirements are (for each buffer): 794 * - multiple of 128 pixels for the width 795 * - multiple of 32 pixels for the height 796 * 797 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 798 */ 799 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 800 801 /* 802 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 803 * 804 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 805 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 806 * they correspond to their 16x16 luma block. 807 */ 808 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 809 810 /* 811 * Qualcomm Compressed Format 812 * 813 * Refers to a compressed variant of the base format that is compressed. 814 * Implementation may be platform and base-format specific. 815 * 816 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 817 * Pixel data pitch/stride is aligned with macrotile width. 818 * Pixel data height is aligned with macrotile height. 819 * Entire pixel data buffer is aligned with 4k(bytes). 820 */ 821 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 822 823 /* 824 * Qualcomm Tiled Format 825 * 826 * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed. 827 * Implementation may be platform and base-format specific. 828 * 829 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 830 * Pixel data pitch/stride is aligned with macrotile width. 831 * Pixel data height is aligned with macrotile height. 832 * Entire pixel data buffer is aligned with 4k(bytes). 833 */ 834 #define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3) 835 836 /* 837 * Qualcomm Alternate Tiled Format 838 * 839 * Alternate tiled format typically only used within GMEM. 840 * Implementation may be platform and base-format specific. 841 */ 842 #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2) 843 844 845 /* Vivante framebuffer modifiers */ 846 847 /* 848 * Vivante 4x4 tiling layout 849 * 850 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 851 * layout. 852 */ 853 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 854 855 /* 856 * Vivante 64x64 super-tiling layout 857 * 858 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 859 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 860 * major layout. 861 * 862 * For more information: see 863 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 864 */ 865 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 866 867 /* 868 * Vivante 4x4 tiling layout for dual-pipe 869 * 870 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 871 * different base address. Offsets from the base addresses are therefore halved 872 * compared to the non-split tiled layout. 873 */ 874 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 875 876 /* 877 * Vivante 64x64 super-tiling layout for dual-pipe 878 * 879 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 880 * starts at a different base address. Offsets from the base addresses are 881 * therefore halved compared to the non-split super-tiled layout. 882 */ 883 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 884 885 /* 886 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of 887 * the color buffer tiling modifiers defined above. When TS is present it's a 888 * separate buffer containing the clear/compression status of each tile. The 889 * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer 890 * tile size in bytes covered by one entry in the status buffer and s is the 891 * number of status bits per entry. 892 * We reserve the top 8 bits of the Vivante modifier space for tile status 893 * clear/compression modifiers, as future cores might add some more TS layout 894 * variations. 895 */ 896 #define VIVANTE_MOD_TS_64_4 (1ULL << 48) 897 #define VIVANTE_MOD_TS_64_2 (2ULL << 48) 898 #define VIVANTE_MOD_TS_128_4 (3ULL << 48) 899 #define VIVANTE_MOD_TS_256_4 (4ULL << 48) 900 #define VIVANTE_MOD_TS_MASK (0xfULL << 48) 901 902 /* 903 * Vivante compression modifiers. Those depend on a TS modifier being present 904 * as the TS bits get reinterpreted as compression tags instead of simple 905 * clear markers when compression is enabled. 906 */ 907 #define VIVANTE_MOD_COMP_DEC400 (1ULL << 52) 908 #define VIVANTE_MOD_COMP_MASK (0xfULL << 52) 909 910 /* Masking out the extension bits will yield the base modifier. */ 911 #define VIVANTE_MOD_EXT_MASK (VIVANTE_MOD_TS_MASK | \ 912 VIVANTE_MOD_COMP_MASK) 913 914 /* NVIDIA frame buffer modifiers */ 915 916 /* 917 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 918 * 919 * Pixels are arranged in simple tiles of 16 x 16 bytes. 920 */ 921 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 922 923 /* 924 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 925 * and Tegra GPUs starting with Tegra K1. 926 * 927 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 928 * based on the architecture generation. GOBs themselves are then arranged in 929 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 930 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 931 * a block depth or height of "4"). 932 * 933 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 934 * in full detail. 935 * 936 * Macro 937 * Bits Param Description 938 * ---- ----- ----------------------------------------------------------------- 939 * 940 * 3:0 h log2(height) of each block, in GOBs. Placed here for 941 * compatibility with the existing 942 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 943 * 944 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 945 * compatibility with the existing 946 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 947 * 948 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 949 * size). Must be zero. 950 * 951 * Note there is no log2(width) parameter. Some portions of the 952 * hardware support a block width of two gobs, but it is impractical 953 * to use due to lack of support elsewhere, and has no known 954 * benefits. 955 * 956 * 11:9 - Reserved (To support 2D-array textures with variable array stride 957 * in blocks, specified via log2(tile width in blocks)). Must be 958 * zero. 959 * 960 * 19:12 k Page Kind. This value directly maps to a field in the page 961 * tables of all GPUs >= NV50. It affects the exact layout of bits 962 * in memory and can be derived from the tuple 963 * 964 * (format, GPU model, compression type, samples per pixel) 965 * 966 * Where compression type is defined below. If GPU model were 967 * implied by the format modifier, format, or memory buffer, page 968 * kind would not need to be included in the modifier itself, but 969 * since the modifier should define the layout of the associated 970 * memory buffer independent from any device or other context, it 971 * must be included here. 972 * 973 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 974 * starting with Fermi GPUs. Additionally, the mapping between page 975 * kind and bit layout has changed at various points. 976 * 977 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 978 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 979 * 2 = Gob Height 8, Turing+ Page Kind mapping 980 * 3 = Reserved for future use. 981 * 982 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 983 * bit remapping step that occurs at an even lower level than the 984 * page kind and block linear swizzles. This causes the layout of 985 * surfaces mapped in those SOC's GPUs to be incompatible with the 986 * equivalent mapping on other GPUs in the same system. 987 * 988 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 989 * 1 = Desktop GPU and Tegra Xavier+ Layout 990 * 991 * 25:23 c Lossless Framebuffer Compression type. 992 * 993 * 0 = none 994 * 1 = ROP/3D, layout 1, exact compression format implied by Page 995 * Kind field 996 * 2 = ROP/3D, layout 2, exact compression format implied by Page 997 * Kind field 998 * 3 = CDE horizontal 999 * 4 = CDE vertical 1000 * 5 = Reserved for future use 1001 * 6 = Reserved for future use 1002 * 7 = Reserved for future use 1003 * 1004 * 55:25 - Reserved for future use. Must be zero. 1005 */ 1006 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 1007 fourcc_mod_code(NVIDIA, (0x10 | \ 1008 ((h) & 0xf) | \ 1009 (((k) & 0xff) << 12) | \ 1010 (((g) & 0x3) << 20) | \ 1011 (((s) & 0x1) << 22) | \ 1012 (((c) & 0x7) << 23))) 1013 1014 /* To grandfather in prior block linear format modifiers to the above layout, 1015 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 1016 * with block-linear layouts, is remapped within drivers to the value 0xfe, 1017 * which corresponds to the "generic" kind used for simple single-sample 1018 * uncompressed color formats on Fermi - Volta GPUs. 1019 */ 1020 static inline __u64 1021 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 1022 { 1023 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 1024 return modifier; 1025 else 1026 return modifier | (0xfe << 12); 1027 } 1028 1029 /* 1030 * 16Bx2 Block Linear layout, used by Tegra K1 and later 1031 * 1032 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 1033 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 1034 * 1035 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 1036 * 1037 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 1038 * Valid values are: 1039 * 1040 * 0 == ONE_GOB 1041 * 1 == TWO_GOBS 1042 * 2 == FOUR_GOBS 1043 * 3 == EIGHT_GOBS 1044 * 4 == SIXTEEN_GOBS 1045 * 5 == THIRTYTWO_GOBS 1046 * 1047 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 1048 * in full detail. 1049 */ 1050 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 1051 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 1052 1053 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 1054 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 1055 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 1056 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 1057 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 1058 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 1059 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 1060 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 1061 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 1062 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 1063 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 1064 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 1065 1066 /* 1067 * Some Broadcom modifiers take parameters, for example the number of 1068 * vertical lines in the image. Reserve the lower 32 bits for modifier 1069 * type, and the next 24 bits for parameters. Top 8 bits are the 1070 * vendor code. 1071 */ 1072 #define __fourcc_mod_broadcom_param_shift 8 1073 #define __fourcc_mod_broadcom_param_bits 48 1074 #define fourcc_mod_broadcom_code(val, params) \ 1075 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) 1076 #define fourcc_mod_broadcom_param(m) \ 1077 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 1078 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 1079 #define fourcc_mod_broadcom_mod(m) \ 1080 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 1081 __fourcc_mod_broadcom_param_shift)) 1082 1083 /* 1084 * Broadcom VC4 "T" format 1085 * 1086 * This is the primary layout that the V3D GPU can texture from (it 1087 * can't do linear). The T format has: 1088 * 1089 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 1090 * pixels at 32 bit depth. 1091 * 1092 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 1093 * 16x16 pixels). 1094 * 1095 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 1096 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 1097 * they're (TR, BR, BL, TL), where bottom left is start of memory. 1098 * 1099 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 1100 * tiles) or right-to-left (odd rows of 4k tiles). 1101 */ 1102 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 1103 1104 /* 1105 * Broadcom SAND format 1106 * 1107 * This is the native format that the H.264 codec block uses. For VC4 1108 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 1109 * 1110 * The image can be considered to be split into columns, and the 1111 * columns are placed consecutively into memory. The width of those 1112 * columns can be either 32, 64, 128, or 256 pixels, but in practice 1113 * only 128 pixel columns are used. 1114 * 1115 * The pitch between the start of each column is set to optimally 1116 * switch between SDRAM banks. This is passed as the number of lines 1117 * of column width in the modifier (we can't use the stride value due 1118 * to various core checks that look at it , so you should set the 1119 * stride to width*cpp). 1120 * 1121 * Note that the column height for this format modifier is the same 1122 * for all of the planes, assuming that each column contains both Y 1123 * and UV. Some SAND-using hardware stores UV in a separate tiled 1124 * image from Y to reduce the column height, which is not supported 1125 * with these modifiers. 1126 * 1127 * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also 1128 * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes 1129 * wide, but as this is a 10 bpp format that translates to 96 pixels. 1130 */ 1131 1132 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 1133 fourcc_mod_broadcom_code(2, v) 1134 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 1135 fourcc_mod_broadcom_code(3, v) 1136 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 1137 fourcc_mod_broadcom_code(4, v) 1138 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 1139 fourcc_mod_broadcom_code(5, v) 1140 1141 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 1142 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 1143 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 1144 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 1145 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 1146 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 1147 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 1148 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 1149 1150 /* Broadcom UIF format 1151 * 1152 * This is the common format for the current Broadcom multimedia 1153 * blocks, including V3D 3.x and newer, newer video codecs, and 1154 * displays. 1155 * 1156 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 1157 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 1158 * stored in columns, with padding between the columns to ensure that 1159 * moving from one column to the next doesn't hit the same SDRAM page 1160 * bank. 1161 * 1162 * To calculate the padding, it is assumed that each hardware block 1163 * and the software driving it knows the platform's SDRAM page size, 1164 * number of banks, and XOR address, and that it's identical between 1165 * all blocks using the format. This tiling modifier will use XOR as 1166 * necessary to reduce the padding. If a hardware block can't do XOR, 1167 * the assumption is that a no-XOR tiling modifier will be created. 1168 */ 1169 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 1170 1171 /* 1172 * Arm Framebuffer Compression (AFBC) modifiers 1173 * 1174 * AFBC is a proprietary lossless image compression protocol and format. 1175 * It provides fine-grained random access and minimizes the amount of data 1176 * transferred between IP blocks. 1177 * 1178 * AFBC has several features which may be supported and/or used, which are 1179 * represented using bits in the modifier. Not all combinations are valid, 1180 * and different devices or use-cases may support different combinations. 1181 * 1182 * Further information on the use of AFBC modifiers can be found in 1183 * Documentation/gpu/afbc.rst 1184 */ 1185 1186 /* 1187 * The top 4 bits (out of the 56 bits allotted for specifying vendor specific 1188 * modifiers) denote the category for modifiers. Currently we have three 1189 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of 1190 * sixteen different categories. 1191 */ 1192 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 1193 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 1194 1195 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 1196 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 1197 1198 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 1199 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 1200 1201 /* 1202 * AFBC superblock size 1203 * 1204 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 1205 * size (in pixels) must be aligned to a multiple of the superblock size. 1206 * Four lowest significant bits(LSBs) are reserved for block size. 1207 * 1208 * Where one superblock size is specified, it applies to all planes of the 1209 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 1210 * the first applies to the Luma plane and the second applies to the Chroma 1211 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 1212 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 1213 */ 1214 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 1215 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 1216 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 1217 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 1218 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 1219 1220 /* 1221 * AFBC lossless colorspace transform 1222 * 1223 * Indicates that the buffer makes use of the AFBC lossless colorspace 1224 * transform. 1225 */ 1226 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 1227 1228 /* 1229 * AFBC block-split 1230 * 1231 * Indicates that the payload of each superblock is split. The second 1232 * half of the payload is positioned at a predefined offset from the start 1233 * of the superblock payload. 1234 */ 1235 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 1236 1237 /* 1238 * AFBC sparse layout 1239 * 1240 * This flag indicates that the payload of each superblock must be stored at a 1241 * predefined position relative to the other superblocks in the same AFBC 1242 * buffer. This order is the same order used by the header buffer. In this mode 1243 * each superblock is given the same amount of space as an uncompressed 1244 * superblock of the particular format would require, rounding up to the next 1245 * multiple of 128 bytes in size. 1246 */ 1247 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 1248 1249 /* 1250 * AFBC copy-block restrict 1251 * 1252 * Buffers with this flag must obey the copy-block restriction. The restriction 1253 * is such that there are no copy-blocks referring across the border of 8x8 1254 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 1255 */ 1256 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 1257 1258 /* 1259 * AFBC tiled layout 1260 * 1261 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 1262 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 1263 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 1264 * larger bpp formats. The order between the tiles is scan line. 1265 * When the tiled layout is used, the buffer size (in pixels) must be aligned 1266 * to the tile size. 1267 */ 1268 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 1269 1270 /* 1271 * AFBC solid color blocks 1272 * 1273 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 1274 * can be reduced if a whole superblock is a single color. 1275 */ 1276 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 1277 1278 /* 1279 * AFBC double-buffer 1280 * 1281 * Indicates that the buffer is allocated in a layout safe for front-buffer 1282 * rendering. 1283 */ 1284 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 1285 1286 /* 1287 * AFBC buffer content hints 1288 * 1289 * Indicates that the buffer includes per-superblock content hints. 1290 */ 1291 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1292 1293 /* AFBC uncompressed storage mode 1294 * 1295 * Indicates that the buffer is using AFBC uncompressed storage mode. 1296 * In this mode all superblock payloads in the buffer use the uncompressed 1297 * storage mode, which is usually only used for data which cannot be compressed. 1298 * The buffer layout is the same as for AFBC buffers without USM set, this only 1299 * affects the storage mode of the individual superblocks. Note that even a 1300 * buffer without USM set may use uncompressed storage mode for some or all 1301 * superblocks, USM just guarantees it for all. 1302 */ 1303 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1304 1305 /* 1306 * Arm Fixed-Rate Compression (AFRC) modifiers 1307 * 1308 * AFRC is a proprietary fixed rate image compression protocol and format, 1309 * designed to provide guaranteed bandwidth and memory footprint 1310 * reductions in graphics and media use-cases. 1311 * 1312 * AFRC buffers consist of one or more planes, with the same components 1313 * and meaning as an uncompressed buffer using the same pixel format. 1314 * 1315 * Within each plane, the pixel/luma/chroma values are grouped into 1316 * "coding unit" blocks which are individually compressed to a 1317 * fixed size (in bytes). All coding units within a given plane of a buffer 1318 * store the same number of values, and have the same compressed size. 1319 * 1320 * The coding unit size is configurable, allowing different rates of compression. 1321 * 1322 * The start of each AFRC buffer plane must be aligned to an alignment granule which 1323 * depends on the coding unit size. 1324 * 1325 * Coding Unit Size Plane Alignment 1326 * ---------------- --------------- 1327 * 16 bytes 1024 bytes 1328 * 24 bytes 512 bytes 1329 * 32 bytes 2048 bytes 1330 * 1331 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned 1332 * to a multiple of the paging tile dimensions. 1333 * The dimensions of each paging tile depend on whether the buffer is optimised for 1334 * scanline (SCAN layout) or rotated (ROT layout) access. 1335 * 1336 * Layout Paging Tile Width Paging Tile Height 1337 * ------ ----------------- ------------------ 1338 * SCAN 16 coding units 4 coding units 1339 * ROT 8 coding units 8 coding units 1340 * 1341 * The dimensions of each coding unit depend on the number of components 1342 * in the compressed plane and whether the buffer is optimised for 1343 * scanline (SCAN layout) or rotated (ROT layout) access. 1344 * 1345 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height 1346 * ----------------------------- --------- ----------------- ------------------ 1347 * 1 SCAN 16 samples 4 samples 1348 * Example: 16x4 luma samples in a 'Y' plane 1349 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1350 * ----------------------------- --------- ----------------- ------------------ 1351 * 1 ROT 8 samples 8 samples 1352 * Example: 8x8 luma samples in a 'Y' plane 1353 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1354 * ----------------------------- --------- ----------------- ------------------ 1355 * 2 DONT CARE 8 samples 4 samples 1356 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer 1357 * ----------------------------- --------- ----------------- ------------------ 1358 * 3 DONT CARE 4 samples 4 samples 1359 * Example: 4x4 pixels in an RGB buffer without alpha 1360 * ----------------------------- --------- ----------------- ------------------ 1361 * 4 DONT CARE 4 samples 4 samples 1362 * Example: 4x4 pixels in an RGB buffer with alpha 1363 */ 1364 1365 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 1366 1367 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ 1368 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) 1369 1370 /* 1371 * AFRC coding unit size modifier. 1372 * 1373 * Indicates the number of bytes used to store each compressed coding unit for 1374 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance 1375 * is the same for both Cb and Cr, which may be stored in separate planes. 1376 * 1377 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store 1378 * each compressed coding unit in the first plane of the buffer. For RGBA buffers 1379 * this is the only plane, while for semi-planar and fully-planar YUV buffers, 1380 * this corresponds to the luma plane. 1381 * 1382 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store 1383 * each compressed coding unit in the second and third planes in the buffer. 1384 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). 1385 * 1386 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified 1387 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. 1388 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and 1389 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. 1390 */ 1391 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf 1392 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) 1393 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) 1394 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) 1395 1396 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) 1397 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) 1398 1399 /* 1400 * AFRC scanline memory layout. 1401 * 1402 * Indicates if the buffer uses the scanline-optimised layout 1403 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. 1404 * The memory layout is the same for all planes. 1405 */ 1406 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) 1407 1408 /* 1409 * Arm 16x16 Block U-Interleaved modifier 1410 * 1411 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1412 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1413 * in the block are reordered. 1414 */ 1415 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1416 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1417 1418 /* 1419 * Allwinner tiled modifier 1420 * 1421 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1422 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1423 * planes. 1424 * 1425 * With this tiling, the luminance samples are disposed in tiles representing 1426 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1427 * The pixel order in each tile is linear and the tiles are disposed linearly, 1428 * both in row-major order. 1429 */ 1430 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1431 1432 /* 1433 * Amlogic Video Framebuffer Compression modifiers 1434 * 1435 * Amlogic uses a proprietary lossless image compression protocol and format 1436 * for their hardware video codec accelerators, either video decoders or 1437 * video input encoders. 1438 * 1439 * It considerably reduces memory bandwidth while writing and reading 1440 * frames in memory. 1441 * 1442 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1443 * per component YCbCr 420, single plane : 1444 * - DRM_FORMAT_YUV420_8BIT 1445 * - DRM_FORMAT_YUV420_10BIT 1446 * 1447 * The first 8 bits of the mode defines the layout, then the following 8 bits 1448 * defines the options changing the layout. 1449 * 1450 * Not all combinations are valid, and different SoCs may support different 1451 * combinations of layout and options. 1452 */ 1453 #define __fourcc_mod_amlogic_layout_mask 0xff 1454 #define __fourcc_mod_amlogic_options_shift 8 1455 #define __fourcc_mod_amlogic_options_mask 0xff 1456 1457 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1458 fourcc_mod_code(AMLOGIC, \ 1459 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1460 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1461 << __fourcc_mod_amlogic_options_shift)) 1462 1463 /* Amlogic FBC Layouts */ 1464 1465 /* 1466 * Amlogic FBC Basic Layout 1467 * 1468 * The basic layout is composed of: 1469 * - a body content organized in 64x32 superblocks with 4096 bytes per 1470 * superblock in default mode. 1471 * - a 32 bytes per 128x64 header block 1472 * 1473 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1474 */ 1475 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1476 1477 /* 1478 * Amlogic FBC Scatter Memory layout 1479 * 1480 * Indicates the header contains IOMMU references to the compressed 1481 * frames content to optimize memory access and layout. 1482 * 1483 * In this mode, only the header memory address is needed, thus the 1484 * content memory organization is tied to the current producer 1485 * execution and cannot be saved/dumped neither transferrable between 1486 * Amlogic SoCs supporting this modifier. 1487 * 1488 * Due to the nature of the layout, these buffers are not expected to 1489 * be accessible by the user-space clients, but only accessible by the 1490 * hardware producers and consumers. 1491 * 1492 * The user-space clients should expect a failure while trying to mmap 1493 * the DMA-BUF handle returned by the producer. 1494 */ 1495 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1496 1497 /* Amlogic FBC Layout Options Bit Mask */ 1498 1499 /* 1500 * Amlogic FBC Memory Saving mode 1501 * 1502 * Indicates the storage is packed when pixel size is multiple of word 1503 * boundaries, i.e. 8bit should be stored in this mode to save allocation 1504 * memory. 1505 * 1506 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1507 * the basic layout and 3200 bytes per 64x32 superblock combined with 1508 * the scatter layout. 1509 */ 1510 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1511 1512 /* MediaTek modifiers 1513 * Bits Parameter Notes 1514 * ----- ------------------------ --------------------------------------------- 1515 * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* 1516 * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* 1517 * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* 1518 * 1519 */ 1520 1521 #define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) 1522 1523 /* 1524 * MediaTek Tiled Modifier 1525 * The lowest 8 bits of the modifier is used to specify the tiling 1526 * layout. Only the 16L_32S tiling is used for now, but we define an 1527 * "untiled" version and leave room for future expansion. 1528 */ 1529 #define MTK_FMT_MOD_TILE_MASK 0xf 1530 #define MTK_FMT_MOD_TILE_NONE 0x0 1531 #define MTK_FMT_MOD_TILE_16L32S 0x1 1532 1533 /* 1534 * Bits 8-15 specify compression options 1535 */ 1536 #define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8) 1537 #define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8) 1538 #define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) 1539 1540 /* 1541 * Bits 16-23 specify how the bits of 10 bit formats are 1542 * stored out in memory 1543 */ 1544 #define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16) 1545 #define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16) 1546 #define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) 1547 #define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) 1548 1549 /* alias for the most common tiling format */ 1550 #define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) 1551 1552 /* 1553 * Apple GPU-tiled layouts. 1554 * 1555 * Apple GPUs support nonlinear tilings with optional lossless compression. 1556 * 1557 * GPU-tiled images are divided into 16KiB tiles: 1558 * 1559 * Bytes per pixel Tile size 1560 * --------------- --------- 1561 * 1 128x128 1562 * 2 128x64 1563 * 4 64x64 1564 * 8 64x32 1565 * 16 32x32 1566 * 1567 * Tiles are raster-order. Pixels within a tile are interleaved (Morton order). 1568 * 1569 * Compressed images pad the body to 128-bytes and are immediately followed by a 1570 * metadata section. The metadata section rounds the image dimensions to 1571 * powers-of-two and contains 8 bytes for each 16x16 compression subtile. 1572 * Subtiles are interleaved (Morton order). 1573 * 1574 * All images are 128-byte aligned. 1575 * 1576 * These layouts fundamentally do not have meaningful strides. No matter how we 1577 * specify strides for these layouts, userspace unaware of Apple image layouts 1578 * will be unable to use correctly the specified stride for any purpose. 1579 * Userspace aware of the image layouts do not use strides. The most "correct" 1580 * convention would be setting the image stride to 0. Unfortunately, some 1581 * software assumes the stride is at least (width * bytes per pixel). We 1582 * therefore require that stride equals (width * bytes per pixel). Since the 1583 * stride is arbitrary here, we pick the simplest convention. 1584 * 1585 * Although containing two sections, compressed image layouts are treated in 1586 * software as a single plane. This is modelled after AFBC, a similar 1587 * scheme. Attempting to separate the sections to be "explicit" in DRM would 1588 * only generate more confusion, as software does not treat the image this way. 1589 * 1590 * For detailed information on the hardware image layouts, see 1591 * https://docs.mesa3d.org/drivers/asahi.html#image-layouts 1592 */ 1593 #define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1) 1594 #define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2) 1595 1596 /* 1597 * AMD modifiers 1598 * 1599 * Memory layout: 1600 * 1601 * without DCC: 1602 * - main surface 1603 * 1604 * with DCC & without DCC_RETILE: 1605 * - main surface in plane 0 1606 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1607 * 1608 * with DCC & DCC_RETILE: 1609 * - main surface in plane 0 1610 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1611 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1612 * 1613 * For multi-plane formats the above surfaces get merged into one plane for 1614 * each format plane, based on the required alignment only. 1615 * 1616 * Bits Parameter Notes 1617 * ----- ------------------------ --------------------------------------------- 1618 * 1619 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1620 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1621 * 13 DCC 1622 * 14 DCC_RETILE 1623 * 15 DCC_PIPE_ALIGN 1624 * 16 DCC_INDEPENDENT_64B 1625 * 17 DCC_INDEPENDENT_128B 1626 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1627 * 20 DCC_CONSTANT_ENCODE 1628 * 23:21 PIPE_XOR_BITS Only for some chips 1629 * 26:24 BANK_XOR_BITS Only for some chips 1630 * 29:27 PACKERS Only for some chips 1631 * 32:30 RB Only for some chips 1632 * 35:33 PIPE Only for some chips 1633 * 55:36 - Reserved for future use, must be zero 1634 */ 1635 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1636 1637 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1638 1639 /* Reserve 0 for GFX8 and older */ 1640 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1641 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1642 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1643 #define AMD_FMT_MOD_TILE_VER_GFX11 4 1644 #define AMD_FMT_MOD_TILE_VER_GFX12 5 1645 1646 /* 1647 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1648 * version. 1649 */ 1650 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1651 1652 /* 1653 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1654 * GFX9 as canonical version. 1655 * 1656 * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. 1657 */ 1658 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1659 #define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 1660 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1661 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1662 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1663 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 1664 1665 /* Gfx12 swizzle modes: 1666 * 0 - LINEAR 1667 * 1 - 256B_2D - 2D block dimensions 1668 * 2 - 4KB_2D 1669 * 3 - 64KB_2D 1670 * 4 - 256KB_2D 1671 * 5 - 4KB_3D - 3D block dimensions 1672 * 6 - 64KB_3D 1673 * 7 - 256KB_3D 1674 */ 1675 #define AMD_FMT_MOD_TILE_GFX12_256B_2D 1 1676 #define AMD_FMT_MOD_TILE_GFX12_4K_2D 2 1677 #define AMD_FMT_MOD_TILE_GFX12_64K_2D 3 1678 #define AMD_FMT_MOD_TILE_GFX12_256K_2D 4 1679 1680 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1681 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1682 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1683 1684 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1685 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1686 #define AMD_FMT_MOD_TILE_SHIFT 8 1687 #define AMD_FMT_MOD_TILE_MASK 0x1F 1688 1689 /* Whether DCC compression is enabled. */ 1690 #define AMD_FMT_MOD_DCC_SHIFT 13 1691 #define AMD_FMT_MOD_DCC_MASK 0x1 1692 1693 /* 1694 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1695 * one which is not-aligned. 1696 */ 1697 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1698 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1699 1700 /* Only set if DCC_RETILE = false */ 1701 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1702 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1703 1704 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1705 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1706 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1707 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1708 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1709 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1710 1711 /* 1712 * DCC supports embedding some clear colors directly in the DCC surface. 1713 * However, on older GPUs the rendering HW ignores the embedded clear color 1714 * and prefers the driver provided color. This necessitates doing a fastclear 1715 * eliminate operation before a process transfers control. 1716 * 1717 * If this bit is set that means the fastclear eliminate is not needed for these 1718 * embeddable colors. 1719 */ 1720 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1721 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1722 1723 /* 1724 * The below fields are for accounting for per GPU differences. These are only 1725 * relevant for GFX9 and later and if the tile field is *_X/_T. 1726 * 1727 * PIPE_XOR_BITS = always needed 1728 * BANK_XOR_BITS = only for TILE_VER_GFX9 1729 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1730 * RB = only for TILE_VER_GFX9 & DCC 1731 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1732 */ 1733 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1734 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1735 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1736 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1737 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1738 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1739 #define AMD_FMT_MOD_RB_SHIFT 30 1740 #define AMD_FMT_MOD_RB_MASK 0x7 1741 #define AMD_FMT_MOD_PIPE_SHIFT 33 1742 #define AMD_FMT_MOD_PIPE_MASK 0x7 1743 1744 #define AMD_FMT_MOD_SET(field, value) \ 1745 ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT) 1746 #define AMD_FMT_MOD_GET(field, value) \ 1747 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1748 #define AMD_FMT_MOD_CLEAR(field) \ 1749 (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1750 1751 #if defined(__cplusplus) 1752 } 1753 #endif 1754 1755 #endif /* DRM_FOURCC_H */ 1756