1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /** 34 * DOC: overview 35 * 36 * In the DRM subsystem, framebuffer pixel formats are described using the 37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 38 * fourcc code, a Format Modifier may optionally be provided, in order to 39 * further describe the buffer's format - for example tiling or compression. 40 * 41 * Format Modifiers 42 * ---------------- 43 * 44 * Format modifiers are used in conjunction with a fourcc code, forming a 45 * unique fourcc:modifier pair. This format:modifier pair must fully define the 46 * format and data layout of the buffer, and should be the only way to describe 47 * that particular buffer. 48 * 49 * Having multiple fourcc:modifier pairs which describe the same layout should 50 * be avoided, as such aliases run the risk of different drivers exposing 51 * different names for the same data format, forcing userspace to understand 52 * that they are aliases. 53 * 54 * Format modifiers may change any property of the buffer, including the number 55 * of planes and/or the required allocation size. Format modifiers are 56 * vendor-namespaced, and as such the relationship between a fourcc code and a 57 * modifier is specific to the modifier being used. For example, some modifiers 58 * may preserve meaning - such as number of planes - from the fourcc code, 59 * whereas others may not. 60 * 61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 62 * match only a single modifier. A modifier must not be a subset of layouts of 63 * another modifier. For instance, it's incorrect to encode pitch alignment in 64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 65 * aligned modifier. That said, modifiers can have implicit minimal 66 * requirements. 67 * 68 * For modifiers where the combination of fourcc code and modifier can alias, 69 * a canonical pair needs to be defined and used by all drivers. Preferred 70 * combinations are also encouraged where all combinations might lead to 71 * confusion and unnecessarily reduced interoperability. An example for the 72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 73 * 74 * There are two kinds of modifier users: 75 * 76 * - Kernel and user-space drivers: for drivers it's important that modifiers 77 * don't alias, otherwise two drivers might support the same format but use 78 * different aliases, preventing them from sharing buffers in an efficient 79 * format. 80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 81 * see modifiers as opaque tokens they can check for equality and intersect. 82 * These users mustn't need to know to reason about the modifier value 83 * (i.e. they are not expected to extract information out of the modifier). 84 * 85 * Vendors should document their modifier usage in as much detail as 86 * possible, to ensure maximum compatibility across devices, drivers and 87 * applications. 88 * 89 * The authoritative list of format modifier codes is found in 90 * `include/uapi/drm/drm_fourcc.h` 91 * 92 * Open Source User Waiver 93 * ----------------------- 94 * 95 * Because this is the authoritative source for pixel formats and modifiers 96 * referenced by GL, Vulkan extensions and other standards and hence used both 97 * by open source and closed source driver stacks, the usual requirement for an 98 * upstream in-kernel or open source userspace user does not apply. 99 * 100 * To ensure, as much as feasible, compatibility across stacks and avoid 101 * confusion with incompatible enumerations stakeholders for all relevant driver 102 * stacks should approve additions. 103 */ 104 105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 106 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 107 108 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 109 110 /* Reserve 0 for the invalid format specifier */ 111 #define DRM_FORMAT_INVALID 0 112 113 /* color index */ 114 #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */ 115 #define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */ 116 #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ 117 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 118 119 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */ 120 #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */ 121 122 /* 2 bpp Darkness (inverse relationship between channel value and brightness) */ 123 #define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */ 124 125 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */ 126 #define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */ 127 128 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */ 129 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */ 130 131 /* 1 bpp Red (direct relationship between channel value and brightness) */ 132 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */ 133 134 /* 2 bpp Red (direct relationship between channel value and brightness) */ 135 #define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */ 136 137 /* 4 bpp Red (direct relationship between channel value and brightness) */ 138 #define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */ 139 140 /* 8 bpp Red (direct relationship between channel value and brightness) */ 141 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 142 143 /* 10 bpp Red (direct relationship between channel value and brightness) */ 144 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ 145 146 /* 12 bpp Red (direct relationship between channel value and brightness) */ 147 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ 148 149 /* 16 bpp Red (direct relationship between channel value and brightness) */ 150 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 151 152 /* 16 bpp RG */ 153 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 154 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 155 156 /* 32 bpp RG */ 157 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 158 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 159 160 /* 8 bpp RGB */ 161 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 162 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 163 164 /* 16 bpp RGB */ 165 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 166 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 167 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 168 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 169 170 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 171 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 172 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 173 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 174 175 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 176 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 177 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 178 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 179 180 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 181 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 182 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 183 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 184 185 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 186 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 187 188 /* 24 bpp RGB */ 189 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 190 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 191 192 /* 32 bpp RGB */ 193 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 194 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 195 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 196 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 197 198 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 199 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 200 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 201 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 202 203 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 204 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 205 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 206 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 207 208 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 209 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 210 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 211 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 212 213 /* 64 bpp RGB */ 214 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 215 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 216 217 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 218 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 219 220 /* 221 * Floating point 64bpp RGB 222 * IEEE 754-2008 binary16 half-precision float 223 * [15:0] sign:exponent:mantissa 1:5:10 224 */ 225 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 226 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 227 228 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 229 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 230 231 /* 232 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 233 * of unused padding per component: 234 */ 235 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 236 237 /* packed YCbCr */ 238 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 239 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 240 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 241 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 242 243 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 244 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */ 245 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 246 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */ 247 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 248 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 249 250 /* 251 * packed Y2xx indicate for each component, xx valid data occupy msb 252 * 16-xx padding occupy lsb 253 */ 254 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 255 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 256 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 257 258 /* 259 * packed Y4xx indicate for each component, xx valid data occupy msb 260 * 16-xx padding occupy lsb except Y410 261 */ 262 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 263 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 264 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 265 266 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 267 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 268 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 269 270 /* 271 * packed YCbCr420 2x2 tiled formats 272 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 273 */ 274 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 275 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 276 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 277 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 278 279 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 280 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 281 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 282 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 283 284 /* 285 * 1-plane YUV 4:2:0 286 * In these formats, the component ordering is specified (Y, followed by U 287 * then V), but the exact Linear layout is undefined. 288 * These formats can only be used with a non-Linear modifier. 289 */ 290 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 291 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 292 293 /* 294 * 2 plane RGB + A 295 * index 0 = RGB plane, same format as the corresponding non _A8 format has 296 * index 1 = A plane, [7:0] A 297 */ 298 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 299 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 300 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 301 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 302 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 303 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 304 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 305 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 306 307 /* 308 * 2 plane YCbCr 309 * index 0 = Y plane, [7:0] Y 310 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 311 * or 312 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 313 */ 314 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 315 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 316 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 317 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 318 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 319 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 320 /* 321 * 2 plane YCbCr 322 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 323 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 324 */ 325 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 326 #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */ 327 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */ 328 329 /* 330 * 2 plane YCbCr MSB aligned 331 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 332 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 333 */ 334 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 335 336 /* 337 * 2 plane YCbCr MSB aligned 338 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 339 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 340 */ 341 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 342 343 /* 344 * 2 plane YCbCr MSB aligned 345 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 346 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 347 */ 348 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 349 350 /* 351 * 2 plane YCbCr MSB aligned 352 * index 0 = Y plane, [15:0] Y little endian 353 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 354 */ 355 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 356 357 /* 2 plane YCbCr420. 358 * 3 10 bit components and 2 padding bits packed into 4 bytes. 359 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian 360 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian 361 */ 362 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ 363 364 /* 3 plane non-subsampled (444) YCbCr 365 * 16 bits per component, but only 10 bits are used and 6 bits are padded 366 * index 0: Y plane, [15:0] Y:x [10:6] little endian 367 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 368 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 369 */ 370 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 371 372 /* 3 plane non-subsampled (444) YCrCb 373 * 16 bits per component, but only 10 bits are used and 6 bits are padded 374 * index 0: Y plane, [15:0] Y:x [10:6] little endian 375 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 376 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 377 */ 378 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 379 380 /* 381 * 3 plane YCbCr 382 * index 0: Y plane, [7:0] Y 383 * index 1: Cb plane, [7:0] Cb 384 * index 2: Cr plane, [7:0] Cr 385 * or 386 * index 1: Cr plane, [7:0] Cr 387 * index 2: Cb plane, [7:0] Cb 388 */ 389 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 390 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 391 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 392 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 393 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 394 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 395 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 396 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 397 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 398 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 399 400 401 /* 402 * Format Modifiers: 403 * 404 * Format modifiers describe, typically, a re-ordering or modification 405 * of the data in a plane of an FB. This can be used to express tiled/ 406 * swizzled formats, or compression, or a combination of the two. 407 * 408 * The upper 8 bits of the format modifier are a vendor-id as assigned 409 * below. The lower 56 bits are assigned as vendor sees fit. 410 */ 411 412 /* Vendor Ids: */ 413 #define DRM_FORMAT_MOD_VENDOR_NONE 0 414 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 415 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 416 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 417 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 418 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 419 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 420 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 421 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 422 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 423 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 424 #define DRM_FORMAT_MOD_VENDOR_MTK 0x0b 425 426 /* add more to the end as needed */ 427 428 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 429 430 #define fourcc_mod_get_vendor(modifier) \ 431 (((modifier) >> 56) & 0xff) 432 433 #define fourcc_mod_is_vendor(modifier, vendor) \ 434 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) 435 436 #define fourcc_mod_code(vendor, val) \ 437 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 438 439 /* 440 * Format Modifier tokens: 441 * 442 * When adding a new token please document the layout with a code comment, 443 * similar to the fourcc codes above. drm_fourcc.h is considered the 444 * authoritative source for all of these. 445 * 446 * Generic modifier names: 447 * 448 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 449 * for layouts which are common across multiple vendors. To preserve 450 * compatibility, in cases where a vendor-specific definition already exists and 451 * a generic name for it is desired, the common name is a purely symbolic alias 452 * and must use the same numerical value as the original definition. 453 * 454 * Note that generic names should only be used for modifiers which describe 455 * generic layouts (such as pixel re-ordering), which may have 456 * independently-developed support across multiple vendors. 457 * 458 * In future cases where a generic layout is identified before merging with a 459 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 460 * 'NONE' could be considered. This should only be for obvious, exceptional 461 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 462 * apply to a single vendor. 463 * 464 * Generic names should not be used for cases where multiple hardware vendors 465 * have implementations of the same standardised compression scheme (such as 466 * AFBC). In those cases, all implementations should use the same format 467 * modifier(s), reflecting the vendor of the standard. 468 */ 469 470 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 471 472 /* 473 * Invalid Modifier 474 * 475 * This modifier can be used as a sentinel to terminate the format modifiers 476 * list, or to initialize a variable with an invalid modifier. It might also be 477 * used to report an error back to userspace for certain APIs. 478 */ 479 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 480 481 /* 482 * Linear Layout 483 * 484 * Just plain linear layout. Note that this is different from no specifying any 485 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 486 * which tells the driver to also take driver-internal information into account 487 * and so might actually result in a tiled framebuffer. 488 */ 489 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 490 491 /* 492 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 493 * 494 * The "none" format modifier doesn't actually mean that the modifier is 495 * implicit, instead it means that the layout is linear. Whether modifiers are 496 * used is out-of-band information carried in an API-specific way (e.g. in a 497 * flag for drm_mode_fb_cmd2). 498 */ 499 #define DRM_FORMAT_MOD_NONE 0 500 501 /* Intel framebuffer modifiers */ 502 503 /* 504 * Intel X-tiling layout 505 * 506 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 507 * in row-major layout. Within the tile bytes are laid out row-major, with 508 * a platform-dependent stride. On top of that the memory can apply 509 * platform-depending swizzling of some higher address bits into bit6. 510 * 511 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 512 * On earlier platforms the is highly platforms specific and not useful for 513 * cross-driver sharing. It exists since on a given platform it does uniquely 514 * identify the layout in a simple way for i915-specific userspace, which 515 * facilitated conversion of userspace to modifiers. Additionally the exact 516 * format on some really old platforms is not known. 517 */ 518 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 519 520 /* 521 * Intel Y-tiling layout 522 * 523 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 524 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 525 * chunks column-major, with a platform-dependent height. On top of that the 526 * memory can apply platform-depending swizzling of some higher address bits 527 * into bit6. 528 * 529 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 530 * On earlier platforms the is highly platforms specific and not useful for 531 * cross-driver sharing. It exists since on a given platform it does uniquely 532 * identify the layout in a simple way for i915-specific userspace, which 533 * facilitated conversion of userspace to modifiers. Additionally the exact 534 * format on some really old platforms is not known. 535 */ 536 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 537 538 /* 539 * Intel Yf-tiling layout 540 * 541 * This is a tiled layout using 4Kb tiles in row-major layout. 542 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 543 * are arranged in four groups (two wide, two high) with column-major layout. 544 * Each group therefore consists out of four 256 byte units, which are also laid 545 * out as 2x2 column-major. 546 * 256 byte units are made out of four 64 byte blocks of pixels, producing 547 * either a square block or a 2:1 unit. 548 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 549 * in pixel depends on the pixel depth. 550 */ 551 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 552 553 /* 554 * Intel color control surface (CCS) for render compression 555 * 556 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 557 * The main surface will be plane index 0 and must be Y/Yf-tiled, 558 * the CCS will be plane index 1. 559 * 560 * Each CCS tile matches a 1024x512 pixel area of the main surface. 561 * To match certain aspects of the 3D hardware the CCS is 562 * considered to be made up of normal 128Bx32 Y tiles, Thus 563 * the CCS pitch must be specified in multiples of 128 bytes. 564 * 565 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 566 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 567 * But that fact is not relevant unless the memory is accessed 568 * directly. 569 */ 570 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 571 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 572 573 /* 574 * Intel color control surfaces (CCS) for Gen-12 render compression. 575 * 576 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 577 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 578 * main surface. In other words, 4 bits in CCS map to a main surface cache 579 * line pair. The main surface pitch is required to be a multiple of four 580 * Y-tile widths. 581 */ 582 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 583 584 /* 585 * Intel color control surfaces (CCS) for Gen-12 media compression 586 * 587 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 588 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 589 * main surface. In other words, 4 bits in CCS map to a main surface cache 590 * line pair. The main surface pitch is required to be a multiple of four 591 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 592 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 593 * planes 2 and 3 for the respective CCS. 594 */ 595 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 596 597 /* 598 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 599 * compression. 600 * 601 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 602 * and at index 1. The clear color is stored at index 2, and the pitch should 603 * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits 604 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 605 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 606 * the converted clear color of size 64 bits. The first 32 bits store the Lower 607 * Converted Clear Color value and the next 32 bits store the Higher Converted 608 * Clear Color value when applicable. The Converted Clear Color values are 609 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 610 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 611 * corresponds to an area of 4x1 tiles in the main surface. The main surface 612 * pitch is required to be a multiple of 4 tile widths. 613 */ 614 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 615 616 /* 617 * Intel Tile 4 layout 618 * 619 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same 620 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It 621 * only differs from Tile Y at the 256B granularity in between. At this 622 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape 623 * of 64B x 8 rows. 624 */ 625 #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) 626 627 /* 628 * Intel color control surfaces (CCS) for DG2 render compression. 629 * 630 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 631 * outside of the GEM object in a reserved memory area dedicated for the 632 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 633 * main surface pitch is required to be a multiple of four Tile 4 widths. 634 */ 635 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) 636 637 /* 638 * Intel color control surfaces (CCS) for DG2 media compression. 639 * 640 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 641 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 642 * 0 and 1, respectively. The CCS for all planes are stored outside of the 643 * GEM object in a reserved memory area dedicated for the storage of the 644 * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface 645 * pitch is required to be a multiple of four Tile 4 widths. 646 */ 647 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) 648 649 /* 650 * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. 651 * 652 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 653 * outside of the GEM object in a reserved memory area dedicated for the 654 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 655 * main surface pitch is required to be a multiple of four Tile 4 widths. The 656 * clear color is stored at plane index 1 and the pitch should be 64 bytes 657 * aligned. The format of the 256 bits of clear color data matches the one used 658 * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description 659 * for details. 660 */ 661 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) 662 663 /* 664 * Intel Color Control Surfaces (CCS) for display ver. 14 render compression. 665 * 666 * The main surface is tile4 and at plane index 0, the CCS is linear and 667 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 668 * main surface. In other words, 4 bits in CCS map to a main surface cache 669 * line pair. The main surface pitch is required to be a multiple of four 670 * tile4 widths. 671 */ 672 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13) 673 674 /* 675 * Intel Color Control Surfaces (CCS) for display ver. 14 media compression 676 * 677 * The main surface is tile4 and at plane index 0, the CCS is linear and 678 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 679 * main surface. In other words, 4 bits in CCS map to a main surface cache 680 * line pair. The main surface pitch is required to be a multiple of four 681 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the 682 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 683 * planes 2 and 3 for the respective CCS. 684 */ 685 #define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14) 686 687 /* 688 * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render 689 * compression. 690 * 691 * The main surface is tile4 and is at plane index 0 whereas CCS is linear 692 * and at index 1. The clear color is stored at index 2, and the pitch should 693 * be ignored. The clear color structure is 256 bits. The first 128 bits 694 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 695 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 696 * the converted clear color of size 64 bits. The first 32 bits store the Lower 697 * Converted Clear Color value and the next 32 bits store the Higher Converted 698 * Clear Color value when applicable. The Converted Clear Color values are 699 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 700 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 701 * corresponds to an area of 4x1 tiles in the main surface. The main surface 702 * pitch is required to be a multiple of 4 tile widths. 703 */ 704 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) 705 706 /* 707 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 708 * on integrated graphics 709 * 710 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 711 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 712 * 0 and 1, respectively. The CCS for all planes are stored outside of the 713 * GEM object in a reserved memory area dedicated for the storage of the 714 * CCS data for all compressible GEM objects. 715 */ 716 #define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) 717 718 /* 719 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 720 * on discrete graphics 721 * 722 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 723 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 724 * 0 and 1, respectively. The CCS for all planes are stored outside of the 725 * GEM object in a reserved memory area dedicated for the storage of the 726 * CCS data for all compressible GEM objects. The GEM object must be stored in 727 * contiguous memory with a size aligned to 64KB 728 */ 729 #define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) 730 731 /* 732 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 733 * 734 * Macroblocks are laid in a Z-shape, and each pixel data is following the 735 * standard NV12 style. 736 * As for NV12, an image is the result of two frame buffers: one for Y, 737 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 738 * Alignment requirements are (for each buffer): 739 * - multiple of 128 pixels for the width 740 * - multiple of 32 pixels for the height 741 * 742 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 743 */ 744 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 745 746 /* 747 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 748 * 749 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 750 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 751 * they correspond to their 16x16 luma block. 752 */ 753 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 754 755 /* 756 * Qualcomm Compressed Format 757 * 758 * Refers to a compressed variant of the base format that is compressed. 759 * Implementation may be platform and base-format specific. 760 * 761 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 762 * Pixel data pitch/stride is aligned with macrotile width. 763 * Pixel data height is aligned with macrotile height. 764 * Entire pixel data buffer is aligned with 4k(bytes). 765 */ 766 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 767 768 /* 769 * Qualcomm Tiled Format 770 * 771 * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed. 772 * Implementation may be platform and base-format specific. 773 * 774 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 775 * Pixel data pitch/stride is aligned with macrotile width. 776 * Pixel data height is aligned with macrotile height. 777 * Entire pixel data buffer is aligned with 4k(bytes). 778 */ 779 #define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3) 780 781 /* 782 * Qualcomm Alternate Tiled Format 783 * 784 * Alternate tiled format typically only used within GMEM. 785 * Implementation may be platform and base-format specific. 786 */ 787 #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2) 788 789 790 /* Vivante framebuffer modifiers */ 791 792 /* 793 * Vivante 4x4 tiling layout 794 * 795 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 796 * layout. 797 */ 798 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 799 800 /* 801 * Vivante 64x64 super-tiling layout 802 * 803 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 804 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 805 * major layout. 806 * 807 * For more information: see 808 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 809 */ 810 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 811 812 /* 813 * Vivante 4x4 tiling layout for dual-pipe 814 * 815 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 816 * different base address. Offsets from the base addresses are therefore halved 817 * compared to the non-split tiled layout. 818 */ 819 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 820 821 /* 822 * Vivante 64x64 super-tiling layout for dual-pipe 823 * 824 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 825 * starts at a different base address. Offsets from the base addresses are 826 * therefore halved compared to the non-split super-tiled layout. 827 */ 828 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 829 830 /* 831 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of 832 * the color buffer tiling modifiers defined above. When TS is present it's a 833 * separate buffer containing the clear/compression status of each tile. The 834 * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer 835 * tile size in bytes covered by one entry in the status buffer and s is the 836 * number of status bits per entry. 837 * We reserve the top 8 bits of the Vivante modifier space for tile status 838 * clear/compression modifiers, as future cores might add some more TS layout 839 * variations. 840 */ 841 #define VIVANTE_MOD_TS_64_4 (1ULL << 48) 842 #define VIVANTE_MOD_TS_64_2 (2ULL << 48) 843 #define VIVANTE_MOD_TS_128_4 (3ULL << 48) 844 #define VIVANTE_MOD_TS_256_4 (4ULL << 48) 845 #define VIVANTE_MOD_TS_MASK (0xfULL << 48) 846 847 /* 848 * Vivante compression modifiers. Those depend on a TS modifier being present 849 * as the TS bits get reinterpreted as compression tags instead of simple 850 * clear markers when compression is enabled. 851 */ 852 #define VIVANTE_MOD_COMP_DEC400 (1ULL << 52) 853 #define VIVANTE_MOD_COMP_MASK (0xfULL << 52) 854 855 /* Masking out the extension bits will yield the base modifier. */ 856 #define VIVANTE_MOD_EXT_MASK (VIVANTE_MOD_TS_MASK | \ 857 VIVANTE_MOD_COMP_MASK) 858 859 /* NVIDIA frame buffer modifiers */ 860 861 /* 862 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 863 * 864 * Pixels are arranged in simple tiles of 16 x 16 bytes. 865 */ 866 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 867 868 /* 869 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 870 * and Tegra GPUs starting with Tegra K1. 871 * 872 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 873 * based on the architecture generation. GOBs themselves are then arranged in 874 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 875 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 876 * a block depth or height of "4"). 877 * 878 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 879 * in full detail. 880 * 881 * Macro 882 * Bits Param Description 883 * ---- ----- ----------------------------------------------------------------- 884 * 885 * 3:0 h log2(height) of each block, in GOBs. Placed here for 886 * compatibility with the existing 887 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 888 * 889 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 890 * compatibility with the existing 891 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 892 * 893 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 894 * size). Must be zero. 895 * 896 * Note there is no log2(width) parameter. Some portions of the 897 * hardware support a block width of two gobs, but it is impractical 898 * to use due to lack of support elsewhere, and has no known 899 * benefits. 900 * 901 * 11:9 - Reserved (To support 2D-array textures with variable array stride 902 * in blocks, specified via log2(tile width in blocks)). Must be 903 * zero. 904 * 905 * 19:12 k Page Kind. This value directly maps to a field in the page 906 * tables of all GPUs >= NV50. It affects the exact layout of bits 907 * in memory and can be derived from the tuple 908 * 909 * (format, GPU model, compression type, samples per pixel) 910 * 911 * Where compression type is defined below. If GPU model were 912 * implied by the format modifier, format, or memory buffer, page 913 * kind would not need to be included in the modifier itself, but 914 * since the modifier should define the layout of the associated 915 * memory buffer independent from any device or other context, it 916 * must be included here. 917 * 918 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 919 * starting with Fermi GPUs. Additionally, the mapping between page 920 * kind and bit layout has changed at various points. 921 * 922 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 923 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 924 * 2 = Gob Height 8, Turing+ Page Kind mapping 925 * 3 = Reserved for future use. 926 * 927 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 928 * bit remapping step that occurs at an even lower level than the 929 * page kind and block linear swizzles. This causes the layout of 930 * surfaces mapped in those SOC's GPUs to be incompatible with the 931 * equivalent mapping on other GPUs in the same system. 932 * 933 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 934 * 1 = Desktop GPU and Tegra Xavier+ Layout 935 * 936 * 25:23 c Lossless Framebuffer Compression type. 937 * 938 * 0 = none 939 * 1 = ROP/3D, layout 1, exact compression format implied by Page 940 * Kind field 941 * 2 = ROP/3D, layout 2, exact compression format implied by Page 942 * Kind field 943 * 3 = CDE horizontal 944 * 4 = CDE vertical 945 * 5 = Reserved for future use 946 * 6 = Reserved for future use 947 * 7 = Reserved for future use 948 * 949 * 55:25 - Reserved for future use. Must be zero. 950 */ 951 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 952 fourcc_mod_code(NVIDIA, (0x10 | \ 953 ((h) & 0xf) | \ 954 (((k) & 0xff) << 12) | \ 955 (((g) & 0x3) << 20) | \ 956 (((s) & 0x1) << 22) | \ 957 (((c) & 0x7) << 23))) 958 959 /* To grandfather in prior block linear format modifiers to the above layout, 960 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 961 * with block-linear layouts, is remapped within drivers to the value 0xfe, 962 * which corresponds to the "generic" kind used for simple single-sample 963 * uncompressed color formats on Fermi - Volta GPUs. 964 */ 965 static inline __u64 966 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 967 { 968 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 969 return modifier; 970 else 971 return modifier | (0xfe << 12); 972 } 973 974 /* 975 * 16Bx2 Block Linear layout, used by Tegra K1 and later 976 * 977 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 978 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 979 * 980 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 981 * 982 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 983 * Valid values are: 984 * 985 * 0 == ONE_GOB 986 * 1 == TWO_GOBS 987 * 2 == FOUR_GOBS 988 * 3 == EIGHT_GOBS 989 * 4 == SIXTEEN_GOBS 990 * 5 == THIRTYTWO_GOBS 991 * 992 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 993 * in full detail. 994 */ 995 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 996 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 997 998 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 999 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 1000 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 1001 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 1002 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 1003 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 1004 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 1005 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 1006 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 1007 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 1008 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 1009 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 1010 1011 /* 1012 * Some Broadcom modifiers take parameters, for example the number of 1013 * vertical lines in the image. Reserve the lower 32 bits for modifier 1014 * type, and the next 24 bits for parameters. Top 8 bits are the 1015 * vendor code. 1016 */ 1017 #define __fourcc_mod_broadcom_param_shift 8 1018 #define __fourcc_mod_broadcom_param_bits 48 1019 #define fourcc_mod_broadcom_code(val, params) \ 1020 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) 1021 #define fourcc_mod_broadcom_param(m) \ 1022 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 1023 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 1024 #define fourcc_mod_broadcom_mod(m) \ 1025 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 1026 __fourcc_mod_broadcom_param_shift)) 1027 1028 /* 1029 * Broadcom VC4 "T" format 1030 * 1031 * This is the primary layout that the V3D GPU can texture from (it 1032 * can't do linear). The T format has: 1033 * 1034 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 1035 * pixels at 32 bit depth. 1036 * 1037 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 1038 * 16x16 pixels). 1039 * 1040 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 1041 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 1042 * they're (TR, BR, BL, TL), where bottom left is start of memory. 1043 * 1044 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 1045 * tiles) or right-to-left (odd rows of 4k tiles). 1046 */ 1047 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 1048 1049 /* 1050 * Broadcom SAND format 1051 * 1052 * This is the native format that the H.264 codec block uses. For VC4 1053 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 1054 * 1055 * The image can be considered to be split into columns, and the 1056 * columns are placed consecutively into memory. The width of those 1057 * columns can be either 32, 64, 128, or 256 pixels, but in practice 1058 * only 128 pixel columns are used. 1059 * 1060 * The pitch between the start of each column is set to optimally 1061 * switch between SDRAM banks. This is passed as the number of lines 1062 * of column width in the modifier (we can't use the stride value due 1063 * to various core checks that look at it , so you should set the 1064 * stride to width*cpp). 1065 * 1066 * Note that the column height for this format modifier is the same 1067 * for all of the planes, assuming that each column contains both Y 1068 * and UV. Some SAND-using hardware stores UV in a separate tiled 1069 * image from Y to reduce the column height, which is not supported 1070 * with these modifiers. 1071 * 1072 * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also 1073 * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes 1074 * wide, but as this is a 10 bpp format that translates to 96 pixels. 1075 */ 1076 1077 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 1078 fourcc_mod_broadcom_code(2, v) 1079 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 1080 fourcc_mod_broadcom_code(3, v) 1081 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 1082 fourcc_mod_broadcom_code(4, v) 1083 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 1084 fourcc_mod_broadcom_code(5, v) 1085 1086 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 1087 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 1088 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 1089 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 1090 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 1091 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 1092 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 1093 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 1094 1095 /* Broadcom UIF format 1096 * 1097 * This is the common format for the current Broadcom multimedia 1098 * blocks, including V3D 3.x and newer, newer video codecs, and 1099 * displays. 1100 * 1101 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 1102 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 1103 * stored in columns, with padding between the columns to ensure that 1104 * moving from one column to the next doesn't hit the same SDRAM page 1105 * bank. 1106 * 1107 * To calculate the padding, it is assumed that each hardware block 1108 * and the software driving it knows the platform's SDRAM page size, 1109 * number of banks, and XOR address, and that it's identical between 1110 * all blocks using the format. This tiling modifier will use XOR as 1111 * necessary to reduce the padding. If a hardware block can't do XOR, 1112 * the assumption is that a no-XOR tiling modifier will be created. 1113 */ 1114 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 1115 1116 /* 1117 * Arm Framebuffer Compression (AFBC) modifiers 1118 * 1119 * AFBC is a proprietary lossless image compression protocol and format. 1120 * It provides fine-grained random access and minimizes the amount of data 1121 * transferred between IP blocks. 1122 * 1123 * AFBC has several features which may be supported and/or used, which are 1124 * represented using bits in the modifier. Not all combinations are valid, 1125 * and different devices or use-cases may support different combinations. 1126 * 1127 * Further information on the use of AFBC modifiers can be found in 1128 * Documentation/gpu/afbc.rst 1129 */ 1130 1131 /* 1132 * The top 4 bits (out of the 56 bits allotted for specifying vendor specific 1133 * modifiers) denote the category for modifiers. Currently we have three 1134 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of 1135 * sixteen different categories. 1136 */ 1137 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 1138 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 1139 1140 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 1141 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 1142 1143 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 1144 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 1145 1146 /* 1147 * AFBC superblock size 1148 * 1149 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 1150 * size (in pixels) must be aligned to a multiple of the superblock size. 1151 * Four lowest significant bits(LSBs) are reserved for block size. 1152 * 1153 * Where one superblock size is specified, it applies to all planes of the 1154 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 1155 * the first applies to the Luma plane and the second applies to the Chroma 1156 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 1157 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 1158 */ 1159 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 1160 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 1161 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 1162 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 1163 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 1164 1165 /* 1166 * AFBC lossless colorspace transform 1167 * 1168 * Indicates that the buffer makes use of the AFBC lossless colorspace 1169 * transform. 1170 */ 1171 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 1172 1173 /* 1174 * AFBC block-split 1175 * 1176 * Indicates that the payload of each superblock is split. The second 1177 * half of the payload is positioned at a predefined offset from the start 1178 * of the superblock payload. 1179 */ 1180 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 1181 1182 /* 1183 * AFBC sparse layout 1184 * 1185 * This flag indicates that the payload of each superblock must be stored at a 1186 * predefined position relative to the other superblocks in the same AFBC 1187 * buffer. This order is the same order used by the header buffer. In this mode 1188 * each superblock is given the same amount of space as an uncompressed 1189 * superblock of the particular format would require, rounding up to the next 1190 * multiple of 128 bytes in size. 1191 */ 1192 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 1193 1194 /* 1195 * AFBC copy-block restrict 1196 * 1197 * Buffers with this flag must obey the copy-block restriction. The restriction 1198 * is such that there are no copy-blocks referring across the border of 8x8 1199 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 1200 */ 1201 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 1202 1203 /* 1204 * AFBC tiled layout 1205 * 1206 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 1207 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 1208 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 1209 * larger bpp formats. The order between the tiles is scan line. 1210 * When the tiled layout is used, the buffer size (in pixels) must be aligned 1211 * to the tile size. 1212 */ 1213 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 1214 1215 /* 1216 * AFBC solid color blocks 1217 * 1218 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 1219 * can be reduced if a whole superblock is a single color. 1220 */ 1221 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 1222 1223 /* 1224 * AFBC double-buffer 1225 * 1226 * Indicates that the buffer is allocated in a layout safe for front-buffer 1227 * rendering. 1228 */ 1229 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 1230 1231 /* 1232 * AFBC buffer content hints 1233 * 1234 * Indicates that the buffer includes per-superblock content hints. 1235 */ 1236 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1237 1238 /* AFBC uncompressed storage mode 1239 * 1240 * Indicates that the buffer is using AFBC uncompressed storage mode. 1241 * In this mode all superblock payloads in the buffer use the uncompressed 1242 * storage mode, which is usually only used for data which cannot be compressed. 1243 * The buffer layout is the same as for AFBC buffers without USM set, this only 1244 * affects the storage mode of the individual superblocks. Note that even a 1245 * buffer without USM set may use uncompressed storage mode for some or all 1246 * superblocks, USM just guarantees it for all. 1247 */ 1248 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1249 1250 /* 1251 * Arm Fixed-Rate Compression (AFRC) modifiers 1252 * 1253 * AFRC is a proprietary fixed rate image compression protocol and format, 1254 * designed to provide guaranteed bandwidth and memory footprint 1255 * reductions in graphics and media use-cases. 1256 * 1257 * AFRC buffers consist of one or more planes, with the same components 1258 * and meaning as an uncompressed buffer using the same pixel format. 1259 * 1260 * Within each plane, the pixel/luma/chroma values are grouped into 1261 * "coding unit" blocks which are individually compressed to a 1262 * fixed size (in bytes). All coding units within a given plane of a buffer 1263 * store the same number of values, and have the same compressed size. 1264 * 1265 * The coding unit size is configurable, allowing different rates of compression. 1266 * 1267 * The start of each AFRC buffer plane must be aligned to an alignment granule which 1268 * depends on the coding unit size. 1269 * 1270 * Coding Unit Size Plane Alignment 1271 * ---------------- --------------- 1272 * 16 bytes 1024 bytes 1273 * 24 bytes 512 bytes 1274 * 32 bytes 2048 bytes 1275 * 1276 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned 1277 * to a multiple of the paging tile dimensions. 1278 * The dimensions of each paging tile depend on whether the buffer is optimised for 1279 * scanline (SCAN layout) or rotated (ROT layout) access. 1280 * 1281 * Layout Paging Tile Width Paging Tile Height 1282 * ------ ----------------- ------------------ 1283 * SCAN 16 coding units 4 coding units 1284 * ROT 8 coding units 8 coding units 1285 * 1286 * The dimensions of each coding unit depend on the number of components 1287 * in the compressed plane and whether the buffer is optimised for 1288 * scanline (SCAN layout) or rotated (ROT layout) access. 1289 * 1290 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height 1291 * ----------------------------- --------- ----------------- ------------------ 1292 * 1 SCAN 16 samples 4 samples 1293 * Example: 16x4 luma samples in a 'Y' plane 1294 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1295 * ----------------------------- --------- ----------------- ------------------ 1296 * 1 ROT 8 samples 8 samples 1297 * Example: 8x8 luma samples in a 'Y' plane 1298 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1299 * ----------------------------- --------- ----------------- ------------------ 1300 * 2 DONT CARE 8 samples 4 samples 1301 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer 1302 * ----------------------------- --------- ----------------- ------------------ 1303 * 3 DONT CARE 4 samples 4 samples 1304 * Example: 4x4 pixels in an RGB buffer without alpha 1305 * ----------------------------- --------- ----------------- ------------------ 1306 * 4 DONT CARE 4 samples 4 samples 1307 * Example: 4x4 pixels in an RGB buffer with alpha 1308 */ 1309 1310 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 1311 1312 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ 1313 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) 1314 1315 /* 1316 * AFRC coding unit size modifier. 1317 * 1318 * Indicates the number of bytes used to store each compressed coding unit for 1319 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance 1320 * is the same for both Cb and Cr, which may be stored in separate planes. 1321 * 1322 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store 1323 * each compressed coding unit in the first plane of the buffer. For RGBA buffers 1324 * this is the only plane, while for semi-planar and fully-planar YUV buffers, 1325 * this corresponds to the luma plane. 1326 * 1327 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store 1328 * each compressed coding unit in the second and third planes in the buffer. 1329 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). 1330 * 1331 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified 1332 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. 1333 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and 1334 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. 1335 */ 1336 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf 1337 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) 1338 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) 1339 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) 1340 1341 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) 1342 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) 1343 1344 /* 1345 * AFRC scanline memory layout. 1346 * 1347 * Indicates if the buffer uses the scanline-optimised layout 1348 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. 1349 * The memory layout is the same for all planes. 1350 */ 1351 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) 1352 1353 /* 1354 * Arm 16x16 Block U-Interleaved modifier 1355 * 1356 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1357 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1358 * in the block are reordered. 1359 */ 1360 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1361 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1362 1363 /* 1364 * Allwinner tiled modifier 1365 * 1366 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1367 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1368 * planes. 1369 * 1370 * With this tiling, the luminance samples are disposed in tiles representing 1371 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1372 * The pixel order in each tile is linear and the tiles are disposed linearly, 1373 * both in row-major order. 1374 */ 1375 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1376 1377 /* 1378 * Amlogic Video Framebuffer Compression modifiers 1379 * 1380 * Amlogic uses a proprietary lossless image compression protocol and format 1381 * for their hardware video codec accelerators, either video decoders or 1382 * video input encoders. 1383 * 1384 * It considerably reduces memory bandwidth while writing and reading 1385 * frames in memory. 1386 * 1387 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1388 * per component YCbCr 420, single plane : 1389 * - DRM_FORMAT_YUV420_8BIT 1390 * - DRM_FORMAT_YUV420_10BIT 1391 * 1392 * The first 8 bits of the mode defines the layout, then the following 8 bits 1393 * defines the options changing the layout. 1394 * 1395 * Not all combinations are valid, and different SoCs may support different 1396 * combinations of layout and options. 1397 */ 1398 #define __fourcc_mod_amlogic_layout_mask 0xff 1399 #define __fourcc_mod_amlogic_options_shift 8 1400 #define __fourcc_mod_amlogic_options_mask 0xff 1401 1402 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1403 fourcc_mod_code(AMLOGIC, \ 1404 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1405 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1406 << __fourcc_mod_amlogic_options_shift)) 1407 1408 /* Amlogic FBC Layouts */ 1409 1410 /* 1411 * Amlogic FBC Basic Layout 1412 * 1413 * The basic layout is composed of: 1414 * - a body content organized in 64x32 superblocks with 4096 bytes per 1415 * superblock in default mode. 1416 * - a 32 bytes per 128x64 header block 1417 * 1418 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1419 */ 1420 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1421 1422 /* 1423 * Amlogic FBC Scatter Memory layout 1424 * 1425 * Indicates the header contains IOMMU references to the compressed 1426 * frames content to optimize memory access and layout. 1427 * 1428 * In this mode, only the header memory address is needed, thus the 1429 * content memory organization is tied to the current producer 1430 * execution and cannot be saved/dumped neither transferrable between 1431 * Amlogic SoCs supporting this modifier. 1432 * 1433 * Due to the nature of the layout, these buffers are not expected to 1434 * be accessible by the user-space clients, but only accessible by the 1435 * hardware producers and consumers. 1436 * 1437 * The user-space clients should expect a failure while trying to mmap 1438 * the DMA-BUF handle returned by the producer. 1439 */ 1440 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1441 1442 /* Amlogic FBC Layout Options Bit Mask */ 1443 1444 /* 1445 * Amlogic FBC Memory Saving mode 1446 * 1447 * Indicates the storage is packed when pixel size is multiple of word 1448 * boundaries, i.e. 8bit should be stored in this mode to save allocation 1449 * memory. 1450 * 1451 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1452 * the basic layout and 3200 bytes per 64x32 superblock combined with 1453 * the scatter layout. 1454 */ 1455 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1456 1457 /* MediaTek modifiers 1458 * Bits Parameter Notes 1459 * ----- ------------------------ --------------------------------------------- 1460 * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* 1461 * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* 1462 * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* 1463 * 1464 */ 1465 1466 #define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) 1467 1468 /* 1469 * MediaTek Tiled Modifier 1470 * The lowest 8 bits of the modifier is used to specify the tiling 1471 * layout. Only the 16L_32S tiling is used for now, but we define an 1472 * "untiled" version and leave room for future expansion. 1473 */ 1474 #define MTK_FMT_MOD_TILE_MASK 0xf 1475 #define MTK_FMT_MOD_TILE_NONE 0x0 1476 #define MTK_FMT_MOD_TILE_16L32S 0x1 1477 1478 /* 1479 * Bits 8-15 specify compression options 1480 */ 1481 #define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8) 1482 #define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8) 1483 #define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) 1484 1485 /* 1486 * Bits 16-23 specify how the bits of 10 bit formats are 1487 * stored out in memory 1488 */ 1489 #define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16) 1490 #define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16) 1491 #define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) 1492 #define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) 1493 1494 /* alias for the most common tiling format */ 1495 #define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) 1496 1497 /* 1498 * AMD modifiers 1499 * 1500 * Memory layout: 1501 * 1502 * without DCC: 1503 * - main surface 1504 * 1505 * with DCC & without DCC_RETILE: 1506 * - main surface in plane 0 1507 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1508 * 1509 * with DCC & DCC_RETILE: 1510 * - main surface in plane 0 1511 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1512 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1513 * 1514 * For multi-plane formats the above surfaces get merged into one plane for 1515 * each format plane, based on the required alignment only. 1516 * 1517 * Bits Parameter Notes 1518 * ----- ------------------------ --------------------------------------------- 1519 * 1520 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1521 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1522 * 13 DCC 1523 * 14 DCC_RETILE 1524 * 15 DCC_PIPE_ALIGN 1525 * 16 DCC_INDEPENDENT_64B 1526 * 17 DCC_INDEPENDENT_128B 1527 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1528 * 20 DCC_CONSTANT_ENCODE 1529 * 23:21 PIPE_XOR_BITS Only for some chips 1530 * 26:24 BANK_XOR_BITS Only for some chips 1531 * 29:27 PACKERS Only for some chips 1532 * 32:30 RB Only for some chips 1533 * 35:33 PIPE Only for some chips 1534 * 55:36 - Reserved for future use, must be zero 1535 */ 1536 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1537 1538 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1539 1540 /* Reserve 0 for GFX8 and older */ 1541 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1542 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1543 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1544 #define AMD_FMT_MOD_TILE_VER_GFX11 4 1545 #define AMD_FMT_MOD_TILE_VER_GFX12 5 1546 1547 /* 1548 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1549 * version. 1550 */ 1551 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1552 1553 /* 1554 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1555 * GFX9 as canonical version. 1556 * 1557 * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. 1558 */ 1559 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1560 #define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 1561 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1562 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1563 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1564 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 1565 1566 /* Gfx12 swizzle modes: 1567 * 0 - LINEAR 1568 * 1 - 256B_2D - 2D block dimensions 1569 * 2 - 4KB_2D 1570 * 3 - 64KB_2D 1571 * 4 - 256KB_2D 1572 * 5 - 4KB_3D - 3D block dimensions 1573 * 6 - 64KB_3D 1574 * 7 - 256KB_3D 1575 */ 1576 #define AMD_FMT_MOD_TILE_GFX12_256B_2D 1 1577 #define AMD_FMT_MOD_TILE_GFX12_4K_2D 2 1578 #define AMD_FMT_MOD_TILE_GFX12_64K_2D 3 1579 #define AMD_FMT_MOD_TILE_GFX12_256K_2D 4 1580 1581 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1582 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1583 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1584 1585 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1586 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1587 #define AMD_FMT_MOD_TILE_SHIFT 8 1588 #define AMD_FMT_MOD_TILE_MASK 0x1F 1589 1590 /* Whether DCC compression is enabled. */ 1591 #define AMD_FMT_MOD_DCC_SHIFT 13 1592 #define AMD_FMT_MOD_DCC_MASK 0x1 1593 1594 /* 1595 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1596 * one which is not-aligned. 1597 */ 1598 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1599 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1600 1601 /* Only set if DCC_RETILE = false */ 1602 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1603 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1604 1605 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1606 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1607 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1608 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1609 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1610 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1611 1612 /* 1613 * DCC supports embedding some clear colors directly in the DCC surface. 1614 * However, on older GPUs the rendering HW ignores the embedded clear color 1615 * and prefers the driver provided color. This necessitates doing a fastclear 1616 * eliminate operation before a process transfers control. 1617 * 1618 * If this bit is set that means the fastclear eliminate is not needed for these 1619 * embeddable colors. 1620 */ 1621 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1622 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1623 1624 /* 1625 * The below fields are for accounting for per GPU differences. These are only 1626 * relevant for GFX9 and later and if the tile field is *_X/_T. 1627 * 1628 * PIPE_XOR_BITS = always needed 1629 * BANK_XOR_BITS = only for TILE_VER_GFX9 1630 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1631 * RB = only for TILE_VER_GFX9 & DCC 1632 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1633 */ 1634 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1635 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1636 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1637 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1638 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1639 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1640 #define AMD_FMT_MOD_RB_SHIFT 30 1641 #define AMD_FMT_MOD_RB_MASK 0x7 1642 #define AMD_FMT_MOD_PIPE_SHIFT 33 1643 #define AMD_FMT_MOD_PIPE_MASK 0x7 1644 1645 #define AMD_FMT_MOD_SET(field, value) \ 1646 ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT) 1647 #define AMD_FMT_MOD_GET(field, value) \ 1648 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1649 #define AMD_FMT_MOD_CLEAR(field) \ 1650 (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1651 1652 #if defined(__cplusplus) 1653 } 1654 #endif 1655 1656 #endif /* DRM_FOURCC_H */ 1657