1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 #include "dc_ddc_types.h" 31 32 enum dc_lane_count { 33 LANE_COUNT_UNKNOWN = 0, 34 LANE_COUNT_ONE = 1, 35 LANE_COUNT_TWO = 2, 36 LANE_COUNT_FOUR = 4, 37 LANE_COUNT_EIGHT = 8, 38 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 39 }; 40 41 /* This is actually a reference clock (27MHz) multiplier 42 * 162MBps bandwidth for 1.62GHz like rate, 43 * 270MBps for 2.70GHz, 44 * 324MBps for 3.24Ghz, 45 * 540MBps for 5.40GHz 46 * 810MBps for 8.10GHz 47 */ 48 enum dc_link_rate { 49 LINK_RATE_UNKNOWN = 0, 50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane 55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane 57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane 58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane 59 /* Starting from DP2.0 link rate enum directly represents actual 60 * link rate value in unit of 10 mbps 61 */ 62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane 63 LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane 64 LINK_RATE_UHBR20 = 2000, // UHBR20 - 20.0 Gbps/Lane 65 }; 66 67 enum dc_link_spread { 68 LINK_SPREAD_DISABLED = 0x00, 69 /* 0.5 % downspread 30 kHz */ 70 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 71 /* 0.5 % downspread 33 kHz */ 72 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 73 }; 74 75 enum dc_voltage_swing { 76 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 77 VOLTAGE_SWING_LEVEL1, 78 VOLTAGE_SWING_LEVEL2, 79 VOLTAGE_SWING_LEVEL3, 80 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 81 }; 82 83 enum dc_pre_emphasis { 84 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 85 PRE_EMPHASIS_LEVEL1, 86 PRE_EMPHASIS_LEVEL2, 87 PRE_EMPHASIS_LEVEL3, 88 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 89 }; 90 /* Post Cursor 2 is optional for transmitter 91 * and it applies only to the main link operating at HBR2 92 */ 93 enum dc_post_cursor2 { 94 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 95 POST_CURSOR2_LEVEL1, 96 POST_CURSOR2_LEVEL2, 97 POST_CURSOR2_LEVEL3, 98 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 99 }; 100 101 enum dc_dp_ffe_preset_level { 102 DP_FFE_PRESET_LEVEL0 = 0, 103 DP_FFE_PRESET_LEVEL1, 104 DP_FFE_PRESET_LEVEL2, 105 DP_FFE_PRESET_LEVEL3, 106 DP_FFE_PRESET_LEVEL4, 107 DP_FFE_PRESET_LEVEL5, 108 DP_FFE_PRESET_LEVEL6, 109 DP_FFE_PRESET_LEVEL7, 110 DP_FFE_PRESET_LEVEL8, 111 DP_FFE_PRESET_LEVEL9, 112 DP_FFE_PRESET_LEVEL10, 113 DP_FFE_PRESET_LEVEL11, 114 DP_FFE_PRESET_LEVEL12, 115 DP_FFE_PRESET_LEVEL13, 116 DP_FFE_PRESET_LEVEL14, 117 DP_FFE_PRESET_LEVEL15, 118 DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15, 119 }; 120 121 enum dc_dp_training_pattern { 122 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 123 DP_TRAINING_PATTERN_SEQUENCE_2, 124 DP_TRAINING_PATTERN_SEQUENCE_3, 125 DP_TRAINING_PATTERN_SEQUENCE_4, 126 DP_TRAINING_PATTERN_VIDEOIDLE, 127 DP_128b_132b_TPS1, 128 DP_128b_132b_TPS2, 129 DP_128b_132b_TPS2_CDS, 130 }; 131 132 enum dp_link_encoding { 133 DP_UNKNOWN_ENCODING = 0, 134 DP_8b_10b_ENCODING = 1, 135 DP_128b_132b_ENCODING = 2, 136 }; 137 138 enum dp_test_link_rate { 139 DP_TEST_LINK_RATE_RBR = 0x06, 140 DP_TEST_LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 141 DP_TEST_LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 142 DP_TEST_LINK_RATE_HBR = 0x0A, 143 DP_TEST_LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane 144 DP_TEST_LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 145 DP_TEST_LINK_RATE_HBR2 = 0x14, 146 DP_TEST_LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane 147 DP_TEST_LINK_RATE_HBR3 = 0x1E, 148 DP_TEST_LINK_RATE_UHBR10 = 0x01, 149 DP_TEST_LINK_RATE_UHBR20 = 0x02, 150 DP_TEST_LINK_RATE_UHBR13_5_LEGACY = 0x03, /* For backward compatibility*/ 151 DP_TEST_LINK_RATE_UHBR13_5 = 0x04, 152 }; 153 154 struct dc_link_settings { 155 enum dc_lane_count lane_count; 156 enum dc_link_rate link_rate; 157 enum dc_link_spread link_spread; 158 bool use_link_rate_set; 159 uint8_t link_rate_set; 160 }; 161 162 struct dc_tunnel_settings { 163 bool should_enable_dp_tunneling; 164 bool should_use_dp_bw_allocation; 165 uint8_t cm_id; 166 uint8_t group_id; 167 uint32_t bw_granularity; 168 uint32_t estimated_bw; 169 uint32_t allocated_bw; 170 }; 171 172 union dc_dp_ffe_preset { 173 struct { 174 uint8_t level : 4; 175 uint8_t reserved : 1; 176 uint8_t no_preshoot : 1; 177 uint8_t no_deemphasis : 1; 178 uint8_t method2 : 1; 179 } settings; 180 uint8_t raw; 181 }; 182 183 struct dc_lane_settings { 184 enum dc_voltage_swing VOLTAGE_SWING; 185 enum dc_pre_emphasis PRE_EMPHASIS; 186 enum dc_post_cursor2 POST_CURSOR2; 187 union dc_dp_ffe_preset FFE_PRESET; 188 }; 189 190 struct dc_link_training_overrides { 191 enum dc_voltage_swing *voltage_swing; 192 enum dc_pre_emphasis *pre_emphasis; 193 enum dc_post_cursor2 *post_cursor2; 194 union dc_dp_ffe_preset *ffe_preset; 195 196 uint16_t *cr_pattern_time; 197 uint16_t *eq_pattern_time; 198 enum dc_dp_training_pattern *pattern_for_cr; 199 enum dc_dp_training_pattern *pattern_for_eq; 200 201 enum dc_link_spread *downspread; 202 bool *alternate_scrambler_reset; 203 bool *enhanced_framing; 204 bool *mst_enable; 205 bool *fec_enable; 206 }; 207 208 union payload_table_update_status { 209 struct { 210 uint8_t VC_PAYLOAD_TABLE_UPDATED:1; 211 uint8_t ACT_HANDLED:1; 212 } bits; 213 uint8_t raw; 214 }; 215 216 union dpcd_rev { 217 struct { 218 uint8_t MINOR:4; 219 uint8_t MAJOR:4; 220 } bits; 221 uint8_t raw; 222 }; 223 224 union max_lane_count { 225 struct { 226 uint8_t MAX_LANE_COUNT:5; 227 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 228 uint8_t TPS3_SUPPORTED:1; 229 uint8_t ENHANCED_FRAME_CAP:1; 230 } bits; 231 uint8_t raw; 232 }; 233 234 union max_down_spread { 235 struct { 236 uint8_t MAX_DOWN_SPREAD:1; 237 uint8_t RESERVED:5; 238 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 239 uint8_t TPS4_SUPPORTED:1; 240 } bits; 241 uint8_t raw; 242 }; 243 244 union mstm_cap { 245 struct { 246 uint8_t MST_CAP:1; 247 uint8_t RESERVED:7; 248 } bits; 249 uint8_t raw; 250 }; 251 252 union lane_count_set { 253 struct { 254 uint8_t LANE_COUNT_SET:5; 255 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 256 uint8_t RESERVED:1; 257 uint8_t ENHANCED_FRAMING:1; 258 } bits; 259 uint8_t raw; 260 }; 261 262 union lane_status { 263 struct { 264 uint8_t CR_DONE_0:1; 265 uint8_t CHANNEL_EQ_DONE_0:1; 266 uint8_t SYMBOL_LOCKED_0:1; 267 uint8_t RESERVED0:1; 268 uint8_t CR_DONE_1:1; 269 uint8_t CHANNEL_EQ_DONE_1:1; 270 uint8_t SYMBOL_LOCKED_1:1; 271 uint8_t RESERVED_1:1; 272 } bits; 273 uint8_t raw; 274 }; 275 276 union device_service_irq { 277 struct { 278 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 279 uint8_t AUTOMATED_TEST:1; 280 uint8_t CP_IRQ:1; 281 uint8_t MCCS_IRQ:1; 282 uint8_t DOWN_REP_MSG_RDY:1; 283 uint8_t UP_REQ_MSG_RDY:1; 284 uint8_t SINK_SPECIFIC:1; 285 uint8_t reserved:1; 286 } bits; 287 uint8_t raw; 288 }; 289 290 union sink_count { 291 struct { 292 uint8_t SINK_COUNT:6; 293 uint8_t CPREADY:1; 294 uint8_t RESERVED:1; 295 } bits; 296 uint8_t raw; 297 }; 298 299 union lane_align_status_updated { 300 struct { 301 uint8_t INTERLANE_ALIGN_DONE:1; 302 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 303 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1; 304 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1; 305 uint8_t LT_FAILED_128b_132b:1; 306 uint8_t RESERVED:1; 307 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 308 uint8_t LINK_STATUS_UPDATED:1; 309 } bits; 310 uint8_t raw; 311 }; 312 313 union link_service_irq_vector_esi0 { 314 struct { 315 uint8_t DP_LINK_RX_CAP_CHANGED:1; 316 uint8_t DP_LINK_STATUS_CHANGED:1; 317 uint8_t DP_LINK_STREAM_STATUS_CHANGED:1; 318 uint8_t DP_LINK_HDMI_LINK_STATUS_CHANGED:1; 319 uint8_t DP_LINK_CONNECTED_OFF_ENTRY_REQUESTED:1; 320 uint8_t DP_LINK_TUNNELING_IRQ:1; 321 uint8_t reserved:2; 322 } bits; 323 uint8_t raw; 324 }; 325 326 union lane_adjust { 327 struct { 328 uint8_t VOLTAGE_SWING_LANE:2; 329 uint8_t PRE_EMPHASIS_LANE:2; 330 uint8_t RESERVED:4; 331 } bits; 332 struct { 333 uint8_t PRESET_VALUE :4; 334 uint8_t RESERVED :4; 335 } tx_ffe; 336 uint8_t raw; 337 }; 338 339 union dpcd_training_pattern { 340 struct { 341 uint8_t TRAINING_PATTERN_SET:4; 342 uint8_t RECOVERED_CLOCK_OUT_EN:1; 343 uint8_t SCRAMBLING_DISABLE:1; 344 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 345 } v1_4; 346 struct { 347 uint8_t TRAINING_PATTERN_SET:2; 348 uint8_t LINK_QUAL_PATTERN_SET:2; 349 uint8_t RESERVED:4; 350 } v1_3; 351 uint8_t raw; 352 }; 353 354 /* Training Lane is used to configure downstream DP device's voltage swing 355 and pre-emphasis levels*/ 356 /* The DPCD addresses are from 0x103 to 0x106*/ 357 union dpcd_training_lane { 358 struct { 359 uint8_t VOLTAGE_SWING_SET:2; 360 uint8_t MAX_SWING_REACHED:1; 361 uint8_t PRE_EMPHASIS_SET:2; 362 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 363 uint8_t RESERVED:2; 364 } bits; 365 struct { 366 uint8_t PRESET_VALUE :4; 367 uint8_t RESERVED :4; 368 } tx_ffe; 369 uint8_t raw; 370 }; 371 372 /* TMDS-converter related */ 373 union dwnstream_port_caps_byte0 { 374 struct { 375 uint8_t DWN_STRM_PORTX_TYPE:3; 376 uint8_t DWN_STRM_PORTX_HPD:1; 377 uint8_t RESERVERD:4; 378 } bits; 379 uint8_t raw; 380 }; 381 382 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 383 enum dpcd_downstream_port_detailed_type { 384 DOWN_STREAM_DETAILED_DP = 0, 385 DOWN_STREAM_DETAILED_VGA, 386 DOWN_STREAM_DETAILED_DVI, 387 DOWN_STREAM_DETAILED_HDMI, 388 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 389 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 390 }; 391 392 union dwnstream_port_caps_byte2 { 393 struct { 394 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 395 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3; 396 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1; 397 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1; 398 uint8_t RESERVED:1; 399 } bits; 400 uint8_t raw; 401 }; 402 403 union dp_downstream_port_present { 404 uint8_t byte; 405 struct { 406 uint8_t PORT_PRESENT:1; 407 uint8_t PORT_TYPE:2; 408 uint8_t FMT_CONVERSION:1; 409 uint8_t DETAILED_CAPS:1; 410 uint8_t RESERVED:3; 411 } fields; 412 }; 413 414 union dwnstream_port_caps_byte3_dvi { 415 struct { 416 uint8_t RESERVED1:1; 417 uint8_t DUAL_LINK:1; 418 uint8_t HIGH_COLOR_DEPTH:1; 419 uint8_t RESERVED2:5; 420 } bits; 421 uint8_t raw; 422 }; 423 424 union dwnstream_port_caps_byte3_hdmi { 425 struct { 426 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 427 uint8_t YCrCr422_PASS_THROUGH:1; 428 uint8_t YCrCr420_PASS_THROUGH:1; 429 uint8_t YCrCr422_CONVERSION:1; 430 uint8_t YCrCr420_CONVERSION:1; 431 uint8_t RESERVED:3; 432 } bits; 433 uint8_t raw; 434 }; 435 436 union hdmi_encoded_link_bw { 437 struct { 438 uint8_t FRL_MODE:1; // Bit 0 439 uint8_t BW_9Gbps:1; 440 uint8_t BW_18Gbps:1; 441 uint8_t BW_24Gbps:1; 442 uint8_t BW_32Gbps:1; 443 uint8_t BW_40Gbps:1; 444 uint8_t BW_48Gbps:1; 445 uint8_t FRL_LINK_TRAINING_FINISHED:1; // Bit 7 446 } bits; 447 uint8_t raw; 448 }; 449 450 union hdmi_tx_link_status { 451 struct { 452 uint8_t HDMI_TX_LINK_ACTIVE_STATUS:1; 453 uint8_t HDMI_TX_READY_STATUS:1; 454 uint8_t RESERVED:6; 455 } bits; 456 uint8_t raw; 457 }; 458 459 union autonomous_mode_and_frl_link_status { 460 struct { 461 uint8_t FRL_LT_IN_PROGRESS_STATUS:1; 462 uint8_t FRL_LT_LINK_CONFIG_IN_PROGRESS:3; 463 uint8_t RESERVED:1; 464 uint8_t FALLBACK_POLICY:1; 465 uint8_t FALLBACK_POLICY_VALID:1; 466 uint8_t REGULATED_AUTONOMOUS_MODE_SUPPORTED:1; 467 } bits; 468 uint8_t raw; 469 }; 470 471 /*4-byte structure for detailed capabilities of a down-stream port 472 (DP-to-TMDS converter).*/ 473 union dwnstream_portxcaps { 474 struct { 475 union dwnstream_port_caps_byte0 byte0; 476 unsigned char max_TMDS_clock; //byte1 477 union dwnstream_port_caps_byte2 byte2; 478 479 union { 480 union dwnstream_port_caps_byte3_dvi byteDVI; 481 union dwnstream_port_caps_byte3_hdmi byteHDMI; 482 } byte3; 483 } bytes; 484 485 unsigned char raw[4]; 486 }; 487 488 union downstream_port { 489 struct { 490 unsigned char present:1; 491 unsigned char type:2; 492 unsigned char format_conv:1; 493 unsigned char detailed_caps:1; 494 unsigned char reserved:3; 495 } bits; 496 unsigned char raw; 497 }; 498 499 500 union sink_status { 501 struct { 502 uint8_t RX_PORT0_STATUS:1; 503 uint8_t RX_PORT1_STATUS:1; 504 uint8_t RESERVED:6; 505 } bits; 506 uint8_t raw; 507 }; 508 509 /* 7-byte structure corresponding to 6 registers (200h-205h) 510 * and LINK_SERVICE_IRQ_ESI0 (2005h) for tunneling IRQ 511 * read during handling of HPD-IRQ 512 */ 513 union hpd_irq_data { 514 struct { 515 union sink_count sink_cnt;/* 200h */ 516 union device_service_irq device_service_irq;/* 201h */ 517 union lane_status lane01_status;/* 202h */ 518 union lane_status lane23_status;/* 203h */ 519 union lane_align_status_updated lane_status_updated;/* 204h */ 520 union sink_status sink_status;/* 205h */ 521 union link_service_irq_vector_esi0 link_service_irq_esi0;/* 2005h */ 522 } bytes; 523 uint8_t raw[7]; 524 }; 525 526 union down_stream_port_count { 527 struct { 528 uint8_t DOWN_STR_PORT_COUNT:4; 529 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 530 /*Bit 6 = MSA_TIMING_PAR_IGNORED 531 0 = Sink device requires the MSA timing parameters 532 1 = Sink device is capable of rendering incoming video 533 stream without MSA timing parameters*/ 534 uint8_t IGNORE_MSA_TIMING_PARAM:1; 535 /*Bit 7 = OUI Support 536 0 = OUI not supported 537 1 = OUI supported 538 (OUI and Device Identification mandatory for DP 1.2)*/ 539 uint8_t OUI_SUPPORT:1; 540 } bits; 541 uint8_t raw; 542 }; 543 544 union down_spread_ctrl { 545 struct { 546 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 547 /* Bits 4 = SPREAD_AMP. Spreading amplitude 548 0 = Main link signal is not downspread 549 1 = Main link signal is downspread <= 0.5% 550 with frequency in the range of 30kHz ~ 33kHz*/ 551 uint8_t SPREAD_AMP:1; 552 uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/ 553 /* Bit 6 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE. 554 0 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is not enabled by the Source device (default) 555 1 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is enabled by Source device */ 556 uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1; 557 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 558 0 = Source device will send valid data for the MSA Timing Params 559 1 = Source device may send invalid data for these MSA Timing Params*/ 560 uint8_t IGNORE_MSA_TIMING_PARAM:1; 561 } bits; 562 uint8_t raw; 563 }; 564 565 union dpcd_edp_config { 566 struct { 567 uint8_t PANEL_MODE_EDP:1; 568 uint8_t FRAMING_CHANGE_ENABLE:1; 569 uint8_t RESERVED:5; 570 uint8_t PANEL_SELF_TEST_ENABLE:1; 571 } bits; 572 uint8_t raw; 573 }; 574 575 struct dp_device_vendor_id { 576 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 577 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 578 }; 579 580 struct dp_sink_hw_fw_revision { 581 uint8_t ieee_hw_rev; 582 uint8_t ieee_fw_rev[2]; 583 }; 584 585 struct dpcd_vendor_signature { 586 bool is_valid; 587 588 union dpcd_ieee_vendor_signature { 589 struct { 590 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 591 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 592 uint8_t ieee_hw_rev; 593 uint8_t ieee_fw_rev[2]; 594 }; 595 uint8_t raw[12]; 596 } data; 597 }; 598 599 struct dpcd_amd_signature { 600 uint8_t AMD_IEEE_TxSignature_byte1; 601 uint8_t AMD_IEEE_TxSignature_byte2; 602 uint8_t AMD_IEEE_TxSignature_byte3; 603 }; 604 605 struct dpcd_amd_device_id { 606 uint8_t device_id_byte1; 607 uint8_t device_id_byte2; 608 uint8_t zero[4]; 609 uint8_t dce_version; 610 uint8_t dal_version_byte1; 611 uint8_t dal_version_byte2; 612 }; 613 614 struct target_luminance_value { 615 uint8_t byte0; 616 uint8_t byte1; 617 uint8_t byte2; 618 }; 619 620 struct dpcd_source_backlight_set { 621 struct { 622 uint8_t byte0; 623 uint8_t byte1; 624 uint8_t byte2; 625 uint8_t byte3; 626 } backlight_level_millinits; 627 628 struct { 629 uint8_t byte0; 630 uint8_t byte1; 631 } backlight_transition_time_ms; 632 }; 633 634 union dpcd_source_backlight_get { 635 struct { 636 uint32_t backlight_millinits_peak; /* 326h */ 637 uint32_t backlight_millinits_avg; /* 32Ah */ 638 } bytes; 639 uint8_t raw[8]; 640 }; 641 642 /*DPCD register of DP receiver capability field bits-*/ 643 union edp_configuration_cap { 644 struct { 645 uint8_t ALT_SCRAMBLER_RESET:1; 646 uint8_t FRAMING_CHANGE:1; 647 uint8_t RESERVED:1; 648 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 649 uint8_t RESERVED2:4; 650 } bits; 651 uint8_t raw; 652 }; 653 654 union dprx_feature { 655 struct { 656 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 657 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 658 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 659 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 660 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 661 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 662 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 663 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 664 } bits; 665 uint8_t raw; 666 }; 667 668 union training_aux_rd_interval { 669 struct { 670 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 671 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 672 } bits; 673 uint8_t raw; 674 }; 675 676 /* Automated test structures */ 677 union test_request { 678 struct { 679 uint8_t LINK_TRAINING :1; 680 uint8_t LINK_TEST_PATTRN :1; 681 uint8_t EDID_READ :1; 682 uint8_t PHY_TEST_PATTERN :1; 683 uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2; 684 uint8_t AUDIO_TEST_PATTERN :1; 685 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 686 } bits; 687 uint8_t raw; 688 }; 689 690 union test_response { 691 struct { 692 uint8_t ACK :1; 693 uint8_t NO_ACK :1; 694 uint8_t EDID_CHECKSUM_WRITE:1; 695 uint8_t RESERVED :5; 696 } bits; 697 uint8_t raw; 698 }; 699 700 union phy_test_pattern { 701 struct { 702 /* This field is 7 bits for DP2.0 */ 703 uint8_t PATTERN :7; 704 uint8_t RESERVED :1; 705 } bits; 706 uint8_t raw; 707 }; 708 709 /* States of Compliance Test Specification (CTS DP1.2). */ 710 union compliance_test_state { 711 struct { 712 unsigned char STEREO_3D_RUNNING : 1; 713 unsigned char RESERVED : 7; 714 } bits; 715 unsigned char raw; 716 }; 717 718 union link_test_pattern { 719 struct { 720 /* dpcd_link_test_patterns */ 721 unsigned char PATTERN :2; 722 unsigned char RESERVED:6; 723 } bits; 724 unsigned char raw; 725 }; 726 727 union test_misc { 728 struct dpcd_test_misc_bits { 729 unsigned char SYNC_CLOCK :1; 730 /* dpcd_test_color_format */ 731 unsigned char CLR_FORMAT :2; 732 /* dpcd_test_dyn_range */ 733 unsigned char DYN_RANGE :1; 734 unsigned char YCBCR_COEFS :1; 735 /* dpcd_test_bit_depth */ 736 unsigned char BPC :3; 737 } bits; 738 unsigned char raw; 739 }; 740 741 union audio_test_mode { 742 struct { 743 unsigned char sampling_rate :4; 744 unsigned char channel_count :4; 745 } bits; 746 unsigned char raw; 747 }; 748 749 union audio_test_pattern_period { 750 struct { 751 unsigned char pattern_period :4; 752 unsigned char reserved :4; 753 } bits; 754 unsigned char raw; 755 }; 756 757 struct audio_test_pattern_type { 758 unsigned char value; 759 }; 760 761 struct dp_audio_test_data_flags { 762 uint8_t test_requested :1; 763 uint8_t disable_video :1; 764 }; 765 766 struct dp_audio_test_data { 767 768 struct dp_audio_test_data_flags flags; 769 uint8_t sampling_rate; 770 uint8_t channel_count; 771 uint8_t pattern_type; 772 uint8_t pattern_period[8]; 773 }; 774 775 /* FEC capability DPCD register field bits-*/ 776 union dpcd_fec_capability { 777 struct { 778 uint8_t FEC_CAPABLE:1; 779 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 780 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 781 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 782 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1; 783 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1; 784 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1; 785 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1; 786 } bits; 787 uint8_t raw; 788 }; 789 790 /* DSC capability DPCD register field bits-*/ 791 struct dpcd_dsc_support { 792 uint8_t DSC_SUPPORT :1; 793 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 794 uint8_t RESERVED :6; 795 }; 796 797 struct dpcd_dsc_algorithm_revision { 798 uint8_t DSC_VERSION_MAJOR :4; 799 uint8_t DSC_VERSION_MINOR :4; 800 }; 801 802 struct dpcd_dsc_rc_buffer_block_size { 803 uint8_t RC_BLOCK_BUFFER_SIZE :2; 804 uint8_t RESERVED :6; 805 }; 806 807 struct dpcd_dsc_slice_capability1 { 808 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 809 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 810 uint8_t RESERVED :1; 811 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 812 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 813 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 814 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 815 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 816 }; 817 818 struct dpcd_dsc_line_buffer_bit_depth { 819 uint8_t LINE_BUFFER_BIT_DEPTH :4; 820 uint8_t RESERVED :4; 821 }; 822 823 struct dpcd_dsc_block_prediction_support { 824 uint8_t BLOCK_PREDICTION_SUPPORT:1; 825 uint8_t RESERVED :7; 826 }; 827 828 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 829 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 830 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 831 uint8_t RESERVED :2; 832 }; 833 834 struct dpcd_dsc_decoder_color_format_capabilities { 835 uint8_t RGB_SUPPORT :1; 836 uint8_t Y_CB_CR_444_SUPPORT :1; 837 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 838 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 839 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 840 uint8_t RESERVED :3; 841 }; 842 843 struct dpcd_dsc_decoder_color_depth_capabilities { 844 uint8_t RESERVED0 :1; 845 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 846 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 847 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 848 uint8_t RESERVED1 :4; 849 }; 850 851 struct dpcd_peak_dsc_throughput_dsc_sink { 852 uint8_t THROUGHPUT_MODE_0:4; 853 uint8_t THROUGHPUT_MODE_1:4; 854 }; 855 856 struct dpcd_dsc_slice_capabilities_2 { 857 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 858 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 859 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 860 uint8_t RESERVED :5; 861 }; 862 863 struct dpcd_bits_per_pixel_increment{ 864 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 865 uint8_t RESERVED :5; 866 }; 867 union dpcd_dsc_basic_capabilities { 868 struct { 869 struct dpcd_dsc_support dsc_support; 870 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 871 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 872 uint8_t dsc_rc_buffer_size; 873 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 874 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 875 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 876 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 877 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 878 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 879 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 880 uint8_t dsc_maximum_slice_width; 881 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 882 uint8_t reserved; 883 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 884 } fields; 885 uint8_t raw[16]; 886 }; 887 888 union dpcd_dsc_branch_decoder_capabilities { 889 struct { 890 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 891 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 892 uint8_t BRANCH_MAX_LINE_WIDTH; 893 } fields; 894 uint8_t raw[3]; 895 }; 896 897 struct dpcd_dsc_capabilities { 898 union dpcd_dsc_basic_capabilities dsc_basic_caps; 899 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 900 }; 901 902 /* These parameters are from PSR capabilities reported by Sink DPCD */ 903 struct psr_caps { 904 unsigned char psr_version; 905 unsigned int psr_rfb_setup_time; 906 bool psr_exit_link_training_required; 907 unsigned char edp_revision; 908 unsigned char support_ver; 909 bool su_granularity_required; 910 bool y_coordinate_required; 911 uint8_t su_y_granularity; 912 bool alpm_cap; 913 bool standby_support; 914 uint8_t rate_control_caps; 915 unsigned int psr_power_opt_flag; 916 }; 917 918 union dpcd_dprx_feature_enumeration_list_cont_1 { 919 struct { 920 uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1; 921 uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1; 922 uint8_t RESERVED0: 2; 923 uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1; 924 uint8_t RESERVED1: 3; 925 } bits; 926 uint8_t raw; 927 }; 928 929 struct adaptive_sync_caps { 930 union dpcd_dprx_feature_enumeration_list_cont_1 dp_adap_sync_caps; 931 }; 932 933 /* Length of router topology ID read from DPCD in bytes. */ 934 #define DPCD_USB4_TOPOLOGY_ID_LEN 5 935 936 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */ 937 union dp_tun_cap_support { 938 struct { 939 uint8_t dp_tunneling :1; 940 uint8_t rsvd :5; 941 uint8_t panel_replay_tun_opt :1; 942 uint8_t dpia_bw_alloc :1; 943 } bits; 944 uint8_t raw; 945 }; 946 947 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ 948 union dpia_info { 949 struct { 950 uint8_t dpia_num :5; 951 uint8_t rsvd :3; 952 } bits; 953 uint8_t raw; 954 }; 955 956 /* DPCD[0xE0020] USB4_DRIVER_BW_CAPABILITY register. */ 957 union usb4_driver_bw_cap { 958 struct { 959 uint8_t rsvd :7; 960 uint8_t driver_bw_alloc_support :1; 961 } bits; 962 uint8_t raw; 963 }; 964 965 /* DPCD[0xE0021] DP_IN_ADAPTER_TUNNEL_INFORMATION register. */ 966 union dpia_tunnel_info { 967 struct { 968 uint8_t group_id :3; 969 uint8_t rsvd :5; 970 } bits; 971 uint8_t raw; 972 }; 973 974 /* DP Tunneling over USB4 */ 975 struct dpcd_usb4_dp_tunneling_info { 976 union dp_tun_cap_support dp_tun_cap; 977 union dpia_info dpia_info; 978 union usb4_driver_bw_cap driver_bw_cap; 979 union dpia_tunnel_info dpia_tunnel_info; 980 uint8_t usb4_driver_id; 981 uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN]; 982 }; 983 984 union dp_main_line_channel_coding_cap { 985 struct { 986 uint8_t DP_8b_10b_SUPPORTED :1; 987 uint8_t DP_128b_132b_SUPPORTED :1; 988 uint8_t RESERVED :6; 989 } bits; 990 uint8_t raw; 991 }; 992 993 union dp_main_link_channel_coding_lttpr_cap { 994 struct { 995 uint8_t DP_128b_132b_SUPPORTED :1; 996 uint8_t RESERVED :7; 997 } bits; 998 uint8_t raw; 999 }; 1000 1001 union dp_128b_132b_supported_link_rates { 1002 struct { 1003 uint8_t UHBR10 :1; 1004 uint8_t UHBR20 :1; 1005 uint8_t UHBR13_5:1; 1006 uint8_t RESERVED:5; 1007 } bits; 1008 uint8_t raw; 1009 }; 1010 1011 union dp_128b_132b_supported_lttpr_link_rates { 1012 struct { 1013 uint8_t UHBR10 :1; 1014 uint8_t UHBR20 :1; 1015 uint8_t UHBR13_5:1; 1016 uint8_t RESERVED:5; 1017 } bits; 1018 uint8_t raw; 1019 }; 1020 1021 union dp_alpm_lttpr_cap { 1022 struct { 1023 uint8_t AUX_LESS_ALPM_SUPPORTED :1; 1024 uint8_t RESERVED :7; 1025 } bits; 1026 uint8_t raw; 1027 }; 1028 1029 union dp_sink_video_fallback_formats { 1030 struct { 1031 uint8_t dp_1024x768_60Hz_24bpp_support :1; 1032 uint8_t dp_1280x720_60Hz_24bpp_support :1; 1033 uint8_t dp_1920x1080_60Hz_24bpp_support :1; 1034 uint8_t RESERVED :5; 1035 } bits; 1036 uint8_t raw; 1037 }; 1038 1039 union dp_receive_port0_cap { 1040 struct { 1041 uint8_t RESERVED :1; 1042 uint8_t LOCAL_EDID_PRESENT :1; 1043 uint8_t ASSOCIATED_TO_PRECEDING_PORT:1; 1044 uint8_t HBLANK_EXPANSION_CAPABLE :1; 1045 uint8_t BUFFER_SIZE_UNIT :1; 1046 uint8_t BUFFER_SIZE_PER_PORT :1; 1047 uint8_t HBLANK_REDUCTION_CAPABLE :1; 1048 uint8_t RESERVED2:1; 1049 uint8_t BUFFER_SIZE:8; 1050 } bits; 1051 uint8_t raw[2]; 1052 }; 1053 1054 union dpcd_max_uncompressed_pixel_rate_cap { 1055 struct { 1056 uint16_t max_uncompressed_pixel_rate_cap :15; 1057 uint16_t valid :1; 1058 } bits; 1059 uint8_t raw[2]; 1060 }; 1061 1062 union dp_fec_capability1 { 1063 struct { 1064 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1; 1065 uint8_t RESERVED :7; 1066 } bits; 1067 uint8_t raw; 1068 }; 1069 1070 union dp_cable_id { 1071 struct { 1072 uint8_t UHBR10_20_CAPABILITY :2; 1073 uint8_t UHBR13_5_CAPABILITY :1; 1074 uint8_t CABLE_TYPE :3; 1075 uint8_t RESERVED :2; 1076 } bits; 1077 uint8_t raw; 1078 }; 1079 1080 struct dp_color_depth_caps { 1081 uint8_t support_6bpc :1; 1082 uint8_t support_8bpc :1; 1083 uint8_t support_10bpc :1; 1084 uint8_t support_12bpc :1; 1085 uint8_t support_16bpc :1; 1086 uint8_t RESERVED :3; 1087 }; 1088 1089 struct dp_encoding_format_caps { 1090 uint8_t support_rgb :1; 1091 uint8_t support_ycbcr444:1; 1092 uint8_t support_ycbcr422:1; 1093 uint8_t support_ycbcr420:1; 1094 uint8_t RESERVED :4; 1095 }; 1096 1097 union dp_dfp_cap_ext { 1098 struct { 1099 uint8_t supported; 1100 uint8_t max_pixel_rate_in_mps[2]; 1101 uint8_t max_video_h_active_width[2]; 1102 uint8_t max_video_v_active_height[2]; 1103 struct dp_encoding_format_caps encoding_format_caps; 1104 struct dp_color_depth_caps rgb_color_depth_caps; 1105 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1106 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1107 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1108 } fields; 1109 uint8_t raw[12]; 1110 }; 1111 1112 union dp_128b_132b_training_aux_rd_interval { 1113 struct { 1114 uint8_t VALUE :7; 1115 uint8_t UNIT :1; 1116 } bits; 1117 uint8_t raw; 1118 }; 1119 1120 union edp_alpm_caps { 1121 struct { 1122 uint8_t AUX_WAKE_ALPM_CAP :1; 1123 uint8_t PM_STATE_2A_SUPPORT :1; 1124 uint8_t AUX_LESS_ALPM_CAP :1; 1125 uint8_t RESERVED :5; 1126 } bits; 1127 uint8_t raw; 1128 }; 1129 1130 union edp_psr_dpcd_caps { 1131 struct { 1132 uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1; 1133 uint8_t PSR_SETUP_TIME :3; 1134 uint8_t Y_COORDINATE_REQUIRED :1; 1135 uint8_t SU_GRANULARITY_REQUIRED :1; 1136 uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1; 1137 uint8_t RESERVED :1; 1138 } bits; 1139 uint8_t raw; 1140 }; 1141 1142 struct edp_psr_info { 1143 uint8_t psr_version; 1144 union edp_psr_dpcd_caps psr_dpcd_caps; 1145 uint8_t psr2_su_y_granularity_cap; 1146 uint8_t force_psrsu_cap; 1147 }; 1148 1149 struct replay_info { 1150 uint8_t pixel_deviation_per_line; 1151 uint8_t max_deviation_line; 1152 }; 1153 1154 struct dprx_states { 1155 bool cable_id_written; 1156 }; 1157 1158 enum dpcd_downstream_port_max_bpc { 1159 DOWN_STREAM_MAX_8BPC = 0, 1160 DOWN_STREAM_MAX_10BPC, 1161 DOWN_STREAM_MAX_12BPC, 1162 DOWN_STREAM_MAX_16BPC 1163 }; 1164 1165 enum link_training_offset { 1166 DPRX = 0, 1167 LTTPR_PHY_REPEATER1 = 1, 1168 LTTPR_PHY_REPEATER2 = 2, 1169 LTTPR_PHY_REPEATER3 = 3, 1170 LTTPR_PHY_REPEATER4 = 4, 1171 LTTPR_PHY_REPEATER5 = 5, 1172 LTTPR_PHY_REPEATER6 = 6, 1173 LTTPR_PHY_REPEATER7 = 7, 1174 LTTPR_PHY_REPEATER8 = 8 1175 }; 1176 1177 #define MAX_REPEATER_CNT 8 1178 1179 struct dc_lttpr_caps { 1180 union dpcd_rev revision; 1181 uint8_t mode; 1182 uint8_t max_lane_count; 1183 uint8_t max_link_rate; 1184 uint8_t phy_repeater_cnt; 1185 uint8_t max_ext_timeout; 1186 union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; 1187 union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; 1188 union dp_alpm_lttpr_cap alpm; 1189 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 1190 uint8_t lttpr_ieee_oui[3]; // Always read from closest LTTPR to host 1191 uint8_t lttpr_device_id[6]; // Always read from closest LTTPR to host 1192 }; 1193 1194 struct dc_dongle_dfp_cap_ext { 1195 bool supported; 1196 uint16_t max_pixel_rate_in_mps; 1197 uint16_t max_video_h_active_width; 1198 uint16_t max_video_v_active_height; 1199 struct dp_encoding_format_caps encoding_format_caps; 1200 struct dp_color_depth_caps rgb_color_depth_caps; 1201 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1202 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1203 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1204 }; 1205 1206 struct dc_dongle_caps { 1207 /* dongle type (DP converter, CV smart dongle) */ 1208 enum display_dongle_type dongle_type; 1209 bool extendedCapValid; 1210 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1211 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1212 bool is_dp_hdmi_s3d_converter; 1213 bool is_dp_hdmi_ycbcr422_pass_through; 1214 bool is_dp_hdmi_ycbcr420_pass_through; 1215 bool is_dp_hdmi_ycbcr422_converter; 1216 bool is_dp_hdmi_ycbcr420_converter; 1217 uint32_t dp_hdmi_max_bpc; 1218 uint32_t dp_hdmi_max_pixel_clk_in_khz; 1219 uint32_t dp_hdmi_frl_max_link_bw_in_kbps; 1220 uint32_t dp_hdmi_regulated_autonomous_mode_support; 1221 struct dc_dongle_dfp_cap_ext dfp_cap_ext; 1222 }; 1223 1224 struct dpcd_caps { 1225 union dpcd_rev dpcd_rev; 1226 union max_lane_count max_ln_count; 1227 union max_down_spread max_down_spread; 1228 union dprx_feature dprx_feature; 1229 1230 /* valid only for eDP v1.4 or higher*/ 1231 uint8_t edp_supported_link_rates_count; 1232 enum dc_link_rate edp_supported_link_rates[8]; 1233 1234 /* dongle type (DP converter, CV smart dongle) */ 1235 enum display_dongle_type dongle_type; 1236 bool is_dongle_type_one; 1237 /* branch device or sink device */ 1238 bool is_branch_dev; 1239 /* Dongle's downstream count. */ 1240 union sink_count sink_count; 1241 bool is_mst_capable; 1242 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1243 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1244 struct dc_dongle_caps dongle_caps; 1245 1246 uint32_t sink_dev_id; 1247 int8_t sink_dev_id_str[6]; 1248 int8_t sink_hw_revision; 1249 int8_t sink_fw_revision[2]; 1250 1251 uint32_t branch_dev_id; 1252 int8_t branch_dev_name[6]; 1253 int8_t branch_hw_revision; 1254 int8_t branch_fw_revision[2]; 1255 int8_t branch_vendor_specific_data[4]; 1256 1257 bool allow_invalid_MSA_timing_param; 1258 bool panel_mode_edp; 1259 bool dpcd_display_control_capable; 1260 bool ext_receiver_cap_field_present; 1261 bool set_power_state_capable_edp; 1262 bool dynamic_backlight_capable_edp; 1263 union dpcd_fec_capability fec_cap; 1264 struct dpcd_dsc_capabilities dsc_caps; 1265 struct dc_lttpr_caps lttpr_caps; 1266 struct adaptive_sync_caps adaptive_sync_caps; 1267 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1268 union dpcd_max_uncompressed_pixel_rate_cap max_uncompressed_pixel_rate_cap; 1269 1270 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1271 union dp_main_line_channel_coding_cap channel_coding_cap; 1272 union dp_sink_video_fallback_formats fallback_formats; 1273 union dp_fec_capability1 fec_cap1; 1274 bool panel_luminance_control; 1275 union dp_cable_id cable_id; 1276 uint8_t edp_rev; 1277 union edp_alpm_caps alpm_caps; 1278 struct edp_psr_info psr_info; 1279 1280 struct replay_info pr_info; 1281 uint16_t edp_oled_emission_rate; 1282 union dp_receive_port0_cap receive_port0_cap; 1283 /* Indicates the number of SST links supported by MSO (Multi-Stream Output) */ 1284 uint8_t mso_cap_sst_links_supported; 1285 }; 1286 1287 union dpcd_sink_ext_caps { 1288 struct { 1289 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1290 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1291 */ 1292 uint8_t sdr_aux_backlight_control : 1; 1293 uint8_t hdr_aux_backlight_control : 1; 1294 uint8_t reserved_1 : 2; 1295 uint8_t oled : 1; 1296 uint8_t reserved_2 : 1; 1297 uint8_t miniled : 1; 1298 uint8_t emission_output : 1; 1299 } bits; 1300 uint8_t raw; 1301 }; 1302 1303 enum dc_link_fec_state { 1304 dc_link_fec_not_ready, 1305 dc_link_fec_ready, 1306 dc_link_fec_enabled 1307 }; 1308 1309 union dpcd_psr_configuration { 1310 struct { 1311 unsigned char ENABLE : 1; 1312 unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1; 1313 unsigned char CRC_VERIFICATION : 1; 1314 unsigned char FRAME_CAPTURE_INDICATION : 1; 1315 /* For eDP 1.4, PSR v2*/ 1316 unsigned char LINE_CAPTURE_INDICATION : 1; 1317 /* For eDP 1.4, PSR v2*/ 1318 unsigned char IRQ_HPD_WITH_CRC_ERROR : 1; 1319 unsigned char ENABLE_PSR2 : 1; 1320 unsigned char EARLY_TRANSPORT_ENABLE : 1; 1321 } bits; 1322 unsigned char raw; 1323 }; 1324 1325 union replay_enable_and_configuration { 1326 struct { 1327 unsigned char FREESYNC_PANEL_REPLAY_MODE :1; 1328 unsigned char TIMING_DESYNC_ERROR_VERIFICATION :1; 1329 unsigned char STATE_TRANSITION_ERROR_DETECTION :1; 1330 unsigned char RESERVED :5; 1331 } bits; 1332 unsigned char raw; 1333 }; 1334 1335 union dpcd_replay_configuration { 1336 struct { 1337 unsigned char STATE_TRANSITION_ERROR_STATUS : 1; 1338 unsigned char DESYNC_ERROR_STATUS : 1; 1339 unsigned char SINK_DEVICE_REPLAY_STATUS : 3; 1340 unsigned char SINK_FRAME_LOCKED : 2; 1341 unsigned char RESERVED : 1; 1342 } bits; 1343 unsigned char raw; 1344 }; 1345 1346 union dpcd_alpm_configuration { 1347 struct { 1348 unsigned char ENABLE : 1; 1349 unsigned char IRQ_HPD_ENABLE : 1; 1350 unsigned char RESERVED : 6; 1351 } bits; 1352 unsigned char raw; 1353 }; 1354 1355 union dpcd_sink_active_vtotal_control_mode { 1356 struct { 1357 unsigned char ENABLE : 1; 1358 unsigned char RESERVED : 7; 1359 } bits; 1360 unsigned char raw; 1361 }; 1362 1363 union psr_error_status { 1364 struct { 1365 unsigned char LINK_CRC_ERROR :1; 1366 unsigned char RFB_STORAGE_ERROR :1; 1367 unsigned char VSC_SDP_ERROR :1; 1368 unsigned char RESERVED :5; 1369 } bits; 1370 unsigned char raw; 1371 }; 1372 1373 union psr_sink_psr_status { 1374 struct { 1375 unsigned char SINK_SELF_REFRESH_STATUS :3; 1376 unsigned char RESERVED :5; 1377 } bits; 1378 unsigned char raw; 1379 }; 1380 1381 struct edp_trace_power_timestamps { 1382 uint64_t poweroff; 1383 uint64_t poweron; 1384 }; 1385 1386 struct dp_trace_lt_counts { 1387 unsigned int total; 1388 unsigned int fail; 1389 }; 1390 1391 enum link_training_result { 1392 LINK_TRAINING_SUCCESS, 1393 LINK_TRAINING_CR_FAIL_LANE0, 1394 LINK_TRAINING_CR_FAIL_LANE1, 1395 LINK_TRAINING_CR_FAIL_LANE23, 1396 /* CR DONE bit is cleared during EQ step */ 1397 LINK_TRAINING_EQ_FAIL_CR, 1398 /* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */ 1399 LINK_TRAINING_EQ_FAIL_CR_PARTIAL, 1400 /* other failure during EQ step */ 1401 LINK_TRAINING_EQ_FAIL_EQ, 1402 LINK_TRAINING_LQA_FAIL, 1403 /* one of the CR,EQ or symbol lock is dropped */ 1404 LINK_TRAINING_LINK_LOSS, 1405 /* Abort link training (because sink unplugged) */ 1406 LINK_TRAINING_ABORT, 1407 DP_128b_132b_LT_FAILED, 1408 DP_128b_132b_MAX_LOOP_COUNT_REACHED, 1409 DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT, 1410 DP_128b_132b_CDS_DONE_TIMEOUT, 1411 }; 1412 1413 struct dp_trace_lt { 1414 struct dp_trace_lt_counts counts; 1415 struct dp_trace_timestamps { 1416 unsigned long long start; 1417 unsigned long long end; 1418 } timestamps; 1419 enum link_training_result result; 1420 bool is_logged; 1421 }; 1422 1423 struct dp_trace { 1424 struct dp_trace_lt detect_lt_trace; 1425 struct dp_trace_lt commit_lt_trace; 1426 unsigned int link_loss_count; 1427 bool is_initialized; 1428 struct edp_trace_power_timestamps edp_trace_power_timestamps; 1429 }; 1430 1431 /* TODO - This is a temporary location for any new DPCD definitions. 1432 * We should move these to drm_dp header. 1433 */ 1434 #ifndef DP_LINK_SQUARE_PATTERN 1435 #define DP_LINK_SQUARE_PATTERN 0x10F 1436 #endif 1437 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 1438 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 0x2217 1439 #endif 1440 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 1441 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 0x110 1442 #endif 1443 #ifndef DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP 1444 #define DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP 0x221c 1445 #endif 1446 #ifndef DP_LTTPR_ALPM_CAPABILITIES 1447 #define DP_LTTPR_ALPM_CAPABILITIES 0xF0009 1448 #endif 1449 #ifndef DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS 1450 #define DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS 0x303C 1451 #endif 1452 #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 1453 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 1454 #endif 1455 #ifndef DP_TUNNELING_IRQ 1456 #define DP_TUNNELING_IRQ (1 << 5) 1457 #endif 1458 #ifndef DP_BRANCH_VENDOR_SPECIFIC_START 1459 #define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C 1460 #endif 1461 #ifndef DP_LTTPR_IEEE_OUI 1462 #define DP_LTTPR_IEEE_OUI 0xF003D 1463 #endif 1464 #ifndef DP_LTTPR_DEVICE_ID 1465 #define DP_LTTPR_DEVICE_ID 0xF0040 1466 #endif 1467 /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/ 1468 #ifndef DP_TUNNELING_CAPABILITIES 1469 #define DP_TUNNELING_CAPABILITIES 0xE000D /* 1.4a */ 1470 #endif 1471 #ifndef USB4_DRIVER_ID 1472 #define USB4_DRIVER_ID 0xE000F /* 1.4a */ 1473 #endif 1474 #ifndef USB4_DRIVER_BW_CAPABILITY 1475 #define USB4_DRIVER_BW_CAPABILITY 0xE0020 /* 1.4a */ 1476 #endif 1477 #ifndef DP_IN_ADAPTER_TUNNEL_INFO 1478 #define DP_IN_ADAPTER_TUNNEL_INFO 0xE0021 /* 1.4a */ 1479 #endif 1480 #ifndef DP_BW_GRANULALITY 1481 #define DP_BW_GRANULALITY 0xE0022 /* 1.4a */ 1482 #endif 1483 #ifndef ESTIMATED_BW 1484 #define ESTIMATED_BW 0xE0023 /* 1.4a */ 1485 #endif 1486 #ifndef ALLOCATED_BW 1487 #define ALLOCATED_BW 0xE0024 /* 1.4a */ 1488 #endif 1489 #ifndef DP_TUNNELING_STATUS 1490 #define DP_TUNNELING_STATUS 0xE0025 /* 1.4a */ 1491 #endif 1492 #ifndef DP_TUNNELING_MAX_LINK_RATE 1493 #define DP_TUNNELING_MAX_LINK_RATE 0xE0028 /* 1.4a */ 1494 #endif 1495 #ifndef DP_TUNNELING_MAX_LANE_COUNT 1496 #define DP_TUNNELING_MAX_LANE_COUNT 0xE0029 /* 1.4a */ 1497 #endif 1498 #ifndef DPTX_BW_ALLOCATION_MODE_CONTROL 1499 #define DPTX_BW_ALLOCATION_MODE_CONTROL 0xE0030 /* 1.4a */ 1500 #endif 1501 #ifndef REQUESTED_BW 1502 #define REQUESTED_BW 0xE0031 /* 1.4a */ 1503 #endif 1504 # ifndef DP_TUNNELING_BW_ALLOC_BITS_MASK 1505 # define DP_TUNNELING_BW_ALLOC_BITS_MASK (0x0F << 0) 1506 # endif 1507 # ifndef DP_TUNNELING_BW_REQUEST_FAILED 1508 # define DP_TUNNELING_BW_REQUEST_FAILED (1 << 0) 1509 # endif 1510 # ifndef DP_TUNNELING_BW_REQUEST_SUCCEEDED 1511 # define DP_TUNNELING_BW_REQUEST_SUCCEEDED (1 << 1) 1512 # endif 1513 # ifndef DP_TUNNELING_ESTIMATED_BW_CHANGED 1514 # define DP_TUNNELING_ESTIMATED_BW_CHANGED (1 << 2) 1515 # endif 1516 # ifndef DP_TUNNELING_BW_ALLOC_CAP_CHANGED 1517 # define DP_TUNNELING_BW_ALLOC_CAP_CHANGED (1 << 3) 1518 # endif 1519 # ifndef DPTX_BW_ALLOC_UNMASK_IRQ 1520 # define DPTX_BW_ALLOC_UNMASK_IRQ (1 << 6) 1521 # endif 1522 # ifndef DPTX_BW_ALLOC_MODE_ENABLE 1523 # define DPTX_BW_ALLOC_MODE_ENABLE (1 << 7) 1524 # endif 1525 1526 #endif /* DC_DP_TYPES_H */ 1527