1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 /* 24 * link_encoder.h 25 * 26 * Created on: Oct 6, 2015 27 * Author: yonsun 28 */ 29 30 #ifndef LINK_ENCODER_H_ 31 #define LINK_ENCODER_H_ 32 33 #include "grph_object_defs.h" 34 #include "signal_types.h" 35 #include "dc_types.h" 36 37 struct dc_context; 38 struct encoder_set_dp_phy_pattern_param; 39 struct link_mst_stream_allocation_table; 40 struct dc_link_settings; 41 struct link_training_settings; 42 struct pipe_ctx; 43 44 struct encoder_init_data { 45 enum channel_id channel; 46 struct graphics_object_id connector; 47 enum hpd_source_id hpd_source; 48 /* TODO: in DAL2, here was pointer to EventManagerInterface */ 49 struct graphics_object_id encoder; 50 enum engine_id analog_engine; 51 struct dc_context *ctx; 52 enum transmitter transmitter; 53 }; 54 55 struct encoder_feature_support { 56 union { 57 struct { 58 uint32_t IS_HBR2_CAPABLE:1; 59 uint32_t IS_HBR3_CAPABLE:1; 60 uint32_t IS_TPS3_CAPABLE:1; 61 uint32_t IS_TPS4_CAPABLE:1; 62 uint32_t HDMI_6GB_EN:1; 63 uint32_t IS_DP2_CAPABLE:1; 64 uint32_t IS_UHBR10_CAPABLE:1; 65 uint32_t IS_UHBR13_5_CAPABLE:1; 66 uint32_t IS_UHBR20_CAPABLE:1; 67 uint32_t DP_IS_USB_C:1; 68 } bits; 69 uint32_t raw; 70 } flags; 71 72 enum dc_color_depth max_hdmi_deep_color; 73 unsigned int max_hdmi_pixel_clock; 74 bool hdmi_ycbcr420_supported; 75 bool dp_ycbcr420_supported; 76 bool fec_supported; 77 }; 78 79 struct link_encoder { 80 const struct link_encoder_funcs *funcs; 81 int32_t aux_channel_offset; 82 struct dc_context *ctx; 83 struct graphics_object_id id; 84 struct graphics_object_id connector; 85 uint32_t output_signals; 86 enum engine_id preferred_engine; 87 enum engine_id analog_engine; 88 struct encoder_feature_support features; 89 enum transmitter transmitter; 90 enum hpd_source_id hpd_source; 91 bool usbc_combo_phy; 92 }; 93 94 struct link_enc_state { 95 96 uint32_t dphy_fec_en; 97 uint32_t dphy_fec_ready_shadow; 98 uint32_t dphy_fec_active_status; 99 uint32_t dp_link_training_complete; 100 101 }; 102 103 enum encoder_type_select { 104 ENCODER_TYPE_DIG = 0, 105 ENCODER_TYPE_HDMI_FRL = 1, 106 ENCODER_TYPE_DP_128B132B = 2 107 }; 108 109 struct link_encoder_funcs { 110 void (*read_state)( 111 struct link_encoder *enc, struct link_enc_state *s); 112 bool (*validate_output_with_stream)( 113 struct link_encoder *enc, const struct dc_stream_state *stream); 114 void (*hw_init)(struct link_encoder *enc); 115 void (*setup)(struct link_encoder *enc, 116 enum signal_type signal); 117 void (*enable_tmds_output)(struct link_encoder *enc, 118 enum clock_source_id clock_source, 119 enum dc_color_depth color_depth, 120 enum signal_type signal, 121 uint32_t pixel_clock); 122 void (*enable_dp_output)(struct link_encoder *enc, 123 const struct dc_link_settings *link_settings, 124 enum clock_source_id clock_source); 125 void (*enable_dp_mst_output)(struct link_encoder *enc, 126 const struct dc_link_settings *link_settings, 127 enum clock_source_id clock_source); 128 void (*enable_lvds_output)(struct link_encoder *enc, 129 enum clock_source_id clock_source, 130 uint32_t pixel_clock); 131 void (*disable_output)(struct link_encoder *link_enc, 132 enum signal_type signal); 133 void (*dp_set_lane_settings)(struct link_encoder *enc, 134 const struct dc_link_settings *link_settings, 135 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); 136 void (*dp_set_phy_pattern)(struct link_encoder *enc, 137 const struct encoder_set_dp_phy_pattern_param *para); 138 void (*update_mst_stream_allocation_table)( 139 struct link_encoder *enc, 140 const struct link_mst_stream_allocation_table *table); 141 void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc, 142 bool exit_link_training_required); 143 void (*psr_program_secondary_packet)(struct link_encoder *enc, 144 unsigned int sdp_transmit_line_num_deadline); 145 void (*connect_dig_be_to_fe)(struct link_encoder *enc, 146 enum engine_id engine, 147 bool connect); 148 void (*enable_hpd)(struct link_encoder *enc); 149 void (*disable_hpd)(struct link_encoder *enc); 150 bool (*is_dig_enabled)(struct link_encoder *enc); 151 unsigned int (*get_dig_frontend)(struct link_encoder *enc); 152 void (*destroy)(struct link_encoder **enc); 153 154 void (*fec_set_enable)(struct link_encoder *enc, 155 bool enable); 156 157 void (*fec_set_ready)(struct link_encoder *enc, 158 bool ready); 159 160 bool (*fec_is_active)(struct link_encoder *enc); 161 bool (*is_in_alt_mode) (struct link_encoder *enc); 162 163 void (*get_max_link_cap)(struct link_encoder *enc, 164 struct dc_link_settings *link_settings); 165 166 enum signal_type (*get_dig_mode)( 167 struct link_encoder *enc); 168 169 void (*set_dio_phy_mux)( 170 struct link_encoder *enc, 171 enum encoder_type_select sel, 172 uint32_t hpo_inst); 173 void (*enable_dpia_output)(struct link_encoder *enc, 174 const struct dc_link_settings *link_settings, 175 uint8_t dpia_id, 176 uint8_t digmode, 177 uint8_t fec_rdy); 178 void (*disable_dpia_output)(struct link_encoder *link_enc, 179 uint8_t dpia_id, 180 uint8_t digmode); 181 }; 182 183 /* 184 * Used to track assignments of links (display endpoints) to link encoders. 185 * 186 * Entry in link_enc_assignments table in struct resource_context. 187 * Entries only marked valid once encoder assigned to a link and invalidated once unassigned. 188 * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint. 189 */ 190 struct link_enc_assignment { 191 bool valid; 192 struct display_endpoint_id ep_id; 193 enum engine_id eng_id; 194 struct dc_stream_state *stream; 195 }; 196 197 enum link_enc_cfg_mode { 198 LINK_ENC_CFG_STEADY, /* Normal operation - use current_state. */ 199 LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */ 200 }; 201 202 enum dp2_link_mode { 203 DP2_LINK_TRAINING_TPS1, 204 DP2_LINK_TRAINING_TPS2, 205 DP2_LINK_ACTIVE, 206 DP2_TEST_PATTERN 207 }; 208 209 enum dp2_phy_tp_select { 210 DP_DPHY_TP_SELECT_TPS1, 211 DP_DPHY_TP_SELECT_TPS2, 212 DP_DPHY_TP_SELECT_PRBS, 213 DP_DPHY_TP_SELECT_CUSTOM, 214 DP_DPHY_TP_SELECT_SQUARE 215 }; 216 217 enum dp2_phy_tp_prbs { 218 DP_DPHY_TP_PRBS7, 219 DP_DPHY_TP_PRBS9, 220 DP_DPHY_TP_PRBS11, 221 DP_DPHY_TP_PRBS15, 222 DP_DPHY_TP_PRBS23, 223 DP_DPHY_TP_PRBS31 224 }; 225 226 struct hpo_dp_link_enc_state { 227 uint32_t link_enc_enabled; 228 uint32_t link_mode; 229 uint32_t lane_count; 230 uint32_t slot_count[4]; 231 uint32_t stream_src[4]; 232 uint32_t vc_rate_x[4]; 233 uint32_t vc_rate_y[4]; 234 }; 235 236 struct hpo_dp_link_encoder { 237 const struct hpo_dp_link_encoder_funcs *funcs; 238 struct dc_context *ctx; 239 int inst; 240 enum engine_id preferred_engine; 241 enum transmitter transmitter; 242 enum hpd_source_id hpd_source; 243 }; 244 245 struct hpo_dp_link_encoder_funcs { 246 247 void (*enable_link_phy)(struct hpo_dp_link_encoder *enc, 248 const struct dc_link_settings *link_settings, 249 enum transmitter transmitter, 250 enum hpd_source_id hpd_source); 251 252 void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc, 253 enum signal_type signal); 254 255 void (*link_enable)( 256 struct hpo_dp_link_encoder *enc, 257 enum dc_lane_count num_lanes); 258 259 void (*link_disable)( 260 struct hpo_dp_link_encoder *enc); 261 262 void (*set_link_test_pattern)( 263 struct hpo_dp_link_encoder *enc, 264 struct encoder_set_dp_phy_pattern_param *tp_params); 265 266 void (*update_stream_allocation_table)( 267 struct hpo_dp_link_encoder *enc, 268 const struct link_mst_stream_allocation_table *table); 269 270 void (*set_throttled_vcp_size)( 271 struct hpo_dp_link_encoder *enc, 272 uint32_t stream_encoder_inst, 273 struct fixed31_32 avg_time_slots_per_mtp); 274 275 bool (*is_in_alt_mode) ( 276 struct hpo_dp_link_encoder *enc); 277 278 void (*read_state)( 279 struct hpo_dp_link_encoder *enc, 280 struct hpo_dp_link_enc_state *state); 281 282 void (*set_ffe)( 283 struct hpo_dp_link_encoder *enc, 284 const struct dc_link_settings *link_settings, 285 uint8_t ffe_preset); 286 }; 287 288 #endif /* LINK_ENCODER_H_ */ 289