1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 * Author: Rob Clark <robdclark@gmail.com>
8 */
9
10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
11 #include <linux/debugfs.h>
12 #include <linux/kthread.h>
13 #include <linux/seq_file.h>
14
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_file.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_framebuffer.h>
20
21 #include "msm_drv.h"
22 #include "dpu_kms.h"
23 #include "dpu_hwio.h"
24 #include "dpu_hw_catalog.h"
25 #include "dpu_hw_intf.h"
26 #include "dpu_hw_ctl.h"
27 #include "dpu_hw_cwb.h"
28 #include "dpu_hw_dspp.h"
29 #include "dpu_hw_dsc.h"
30 #include "dpu_hw_merge3d.h"
31 #include "dpu_hw_cdm.h"
32 #include "dpu_formats.h"
33 #include "dpu_encoder_phys.h"
34 #include "dpu_crtc.h"
35 #include "dpu_trace.h"
36 #include "dpu_core_irq.h"
37 #include "disp/msm_disp_snapshot.h"
38
39 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
40 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
41
42 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
43 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
44
45 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\
46 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
47
48 /*
49 * Two to anticipate panels that can do cmd/vid dynamic switching
50 * plan is to create all possible physical encoder types, and switch between
51 * them at runtime
52 */
53 #define NUM_PHYS_ENCODER_TYPES 2
54
55 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
56 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
57
58 #define MAX_CHANNELS_PER_ENC 2
59
60 #define IDLE_SHORT_TIMEOUT 1
61
62 /* timeout in frames waiting for frame done */
63 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
64
65 /**
66 * enum dpu_enc_rc_events - events for resource control state machine
67 * @DPU_ENC_RC_EVENT_KICKOFF:
68 * This event happens at NORMAL priority.
69 * Event that signals the start of the transfer. When this event is
70 * received, enable MDP/DSI core clocks. Regardless of the previous
71 * state, the resource should be in ON state at the end of this event.
72 * @DPU_ENC_RC_EVENT_FRAME_DONE:
73 * This event happens at INTERRUPT level.
74 * Event signals the end of the data transfer after the PP FRAME_DONE
75 * event. At the end of this event, a delayed work is scheduled to go to
76 * IDLE_PC state after IDLE_TIMEOUT time.
77 * @DPU_ENC_RC_EVENT_PRE_STOP:
78 * This event happens at NORMAL priority.
79 * This event, when received during the ON state, leave the RC STATE
80 * in the PRE_OFF state. It should be followed by the STOP event as
81 * part of encoder disable.
82 * If received during IDLE or OFF states, it will do nothing.
83 * @DPU_ENC_RC_EVENT_STOP:
84 * This event happens at NORMAL priority.
85 * When this event is received, disable all the MDP/DSI core clocks, and
86 * disable IRQs. It should be called from the PRE_OFF or IDLE states.
87 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
88 * PRE_OFF is expected when PRE_STOP was executed during the ON state.
89 * Resource state should be in OFF at the end of the event.
90 * @DPU_ENC_RC_EVENT_ENTER_IDLE:
91 * This event happens at NORMAL priority from a work item.
92 * Event signals that there were no frame updates for IDLE_TIMEOUT time.
93 * This would disable MDP/DSI core clocks and change the resource state
94 * to IDLE.
95 */
96 enum dpu_enc_rc_events {
97 DPU_ENC_RC_EVENT_KICKOFF = 1,
98 DPU_ENC_RC_EVENT_FRAME_DONE,
99 DPU_ENC_RC_EVENT_PRE_STOP,
100 DPU_ENC_RC_EVENT_STOP,
101 DPU_ENC_RC_EVENT_ENTER_IDLE
102 };
103
104 /*
105 * enum dpu_enc_rc_states - states that the resource control maintains
106 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
107 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
108 * @DPU_ENC_RC_STATE_ON: Resource is in ON state
109 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
110 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
111 */
112 enum dpu_enc_rc_states {
113 DPU_ENC_RC_STATE_OFF,
114 DPU_ENC_RC_STATE_PRE_OFF,
115 DPU_ENC_RC_STATE_ON,
116 DPU_ENC_RC_STATE_IDLE
117 };
118
119 /**
120 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
121 * encoders. Virtual encoder manages one "logical" display. Physical
122 * encoders manage one intf block, tied to a specific panel/sub-panel.
123 * Virtual encoder defers as much as possible to the physical encoders.
124 * Virtual encoder registers itself with the DRM Framework as the encoder.
125 * @base: drm_encoder base class for registration with DRM
126 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
127 * @enabled: True if the encoder is active, protected by enc_lock
128 * @commit_done_timedout: True if there has been a timeout on commit after
129 * enabling the encoder.
130 * @num_phys_encs: Actual number of physical encoders contained.
131 * @phys_encs: Container of physical encoders managed.
132 * @cur_master: Pointer to the current master in this mode. Optimization
133 * Only valid after enable. Cleared as disable.
134 * @cur_slave: As above but for the slave encoder.
135 * @hw_pp: Handle to the pingpong blocks used for the display. No.
136 * pingpong blocks can be different than num_phys_encs.
137 * @hw_cwb: Handle to the CWB muxes used for concurrent writeback
138 * display. Number of CWB muxes can be different than
139 * num_phys_encs.
140 * @hw_dsc: Handle to the DSC blocks used for the display.
141 * @dsc_mask: Bitmask of used DSC blocks.
142 * @cwb_mask: Bitmask of used CWB muxes
143 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
144 * for partial update right-only cases, such as pingpong
145 * split where virtual pingpong does not generate IRQs
146 * @crtc: Pointer to the currently assigned crtc. Normally you
147 * would use crtc->state->encoder_mask to determine the
148 * link between encoder/crtc. However in this case we need
149 * to track crtc in the disable() hook which is called
150 * _after_ encoder_mask is cleared.
151 * @connector: If a mode is set, cached pointer to the active connector
152 * @enc_lock: Lock around physical encoder
153 * create/destroy/enable/disable
154 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
155 * busy processing current command.
156 * Bit0 = phys_encs[0] etc.
157 * @frame_done_timeout_ms: frame done timeout in ms
158 * @frame_done_timeout_cnt: atomic counter tracking the number of frame
159 * done timeouts
160 * @frame_done_timer: watchdog timer for frame done event
161 * @disp_info: local copy of msm_display_info struct
162 * @idle_pc_supported: indicate if idle power collaps is supported
163 * @rc_lock: resource control mutex lock to protect
164 * virt encoder over various state changes
165 * @rc_state: resource controller state
166 * @delayed_off_work: delayed worker to schedule disabling of
167 * clks and resources after IDLE_TIMEOUT time.
168 * @topology: topology of the display
169 * @idle_timeout: idle timeout duration in milliseconds
170 * @wide_bus_en: wide bus is enabled on this interface
171 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
172 */
173 struct dpu_encoder_virt {
174 struct drm_encoder base;
175 spinlock_t enc_spinlock;
176
177 bool enabled;
178 bool commit_done_timedout;
179
180 unsigned int num_phys_encs;
181 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
182 struct dpu_encoder_phys *cur_master;
183 struct dpu_encoder_phys *cur_slave;
184 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
185 struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC];
186 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
187
188 unsigned int dsc_mask;
189 unsigned int cwb_mask;
190
191 bool intfs_swapped;
192
193 struct drm_crtc *crtc;
194 struct drm_connector *connector;
195
196 struct mutex enc_lock;
197 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
198
199 atomic_t frame_done_timeout_ms;
200 atomic_t frame_done_timeout_cnt;
201 struct timer_list frame_done_timer;
202
203 struct msm_display_info disp_info;
204
205 bool idle_pc_supported;
206 struct mutex rc_lock;
207 enum dpu_enc_rc_states rc_state;
208 struct delayed_work delayed_off_work;
209 struct msm_display_topology topology;
210
211 u32 idle_timeout;
212
213 bool wide_bus_en;
214
215 /* DSC configuration */
216 struct drm_dsc_config *dsc;
217 };
218
219 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
220
221 static u32 dither_matrix[DITHER_MATRIX_SZ] = {
222 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
223 };
224
225 /**
226 * dpu_encoder_get_drm_fmt - return DRM fourcc format
227 * @phys_enc: Pointer to physical encoder structure
228 */
dpu_encoder_get_drm_fmt(struct dpu_encoder_phys * phys_enc)229 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc)
230 {
231 struct drm_encoder *drm_enc;
232 struct dpu_encoder_virt *dpu_enc;
233 struct drm_display_info *info;
234 struct drm_display_mode *mode;
235
236 drm_enc = phys_enc->parent;
237 dpu_enc = to_dpu_encoder_virt(drm_enc);
238 info = &dpu_enc->connector->display_info;
239 mode = &phys_enc->cached_mode;
240
241 if (drm_mode_is_420_only(info, mode))
242 return DRM_FORMAT_YUV420;
243
244 return DRM_FORMAT_RGB888;
245 }
246
247 /**
248 * dpu_encoder_needs_periph_flush - return true if physical encoder requires
249 * peripheral flush
250 * @phys_enc: Pointer to physical encoder structure
251 */
dpu_encoder_needs_periph_flush(struct dpu_encoder_phys * phys_enc)252 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc)
253 {
254 struct drm_encoder *drm_enc;
255 struct dpu_encoder_virt *dpu_enc;
256 struct msm_display_info *disp_info;
257 struct msm_drm_private *priv;
258 struct drm_display_mode *mode;
259
260 drm_enc = phys_enc->parent;
261 dpu_enc = to_dpu_encoder_virt(drm_enc);
262 disp_info = &dpu_enc->disp_info;
263 priv = drm_enc->dev->dev_private;
264 mode = &phys_enc->cached_mode;
265
266 return phys_enc->hw_intf->cap->type == INTF_DP &&
267 msm_dp_needs_periph_flush(priv->kms->dp[disp_info->h_tile_instance[0]], mode);
268 }
269
270 /**
271 * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled
272 * @drm_enc: Pointer to previously created drm encoder structure
273 */
dpu_encoder_is_widebus_enabled(const struct drm_encoder * drm_enc)274 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
275 {
276 const struct dpu_encoder_virt *dpu_enc;
277 struct msm_drm_private *priv = drm_enc->dev->dev_private;
278 const struct msm_display_info *disp_info;
279 int index;
280
281 dpu_enc = to_dpu_encoder_virt(drm_enc);
282 disp_info = &dpu_enc->disp_info;
283 index = disp_info->h_tile_instance[0];
284
285 if (disp_info->intf_type == INTF_DP)
286 return msm_dp_wide_bus_available(priv->kms->dp[index]);
287 else if (disp_info->intf_type == INTF_DSI)
288 return msm_dsi_wide_bus_enabled(priv->kms->dsi[index]);
289
290 return false;
291 }
292
293 /**
294 * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
295 * for the encoder.
296 * @drm_enc: Pointer to previously created drm encoder structure
297 */
dpu_encoder_is_dsc_enabled(const struct drm_encoder * drm_enc)298 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc)
299 {
300 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
301
302 return dpu_enc->dsc ? true : false;
303 }
304
305 /**
306 * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
307 * in virtual encoder that can collect CRC values
308 * @drm_enc: Pointer to previously created drm encoder structure
309 * Returns: Number of physical encoders for given drm encoder
310 */
dpu_encoder_get_crc_values_cnt(const struct drm_encoder * drm_enc)311 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
312 {
313 struct dpu_encoder_virt *dpu_enc;
314 int i, num_intf = 0;
315
316 dpu_enc = to_dpu_encoder_virt(drm_enc);
317
318 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
319 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
320
321 if (phys->hw_intf && phys->hw_intf->ops.setup_misr
322 && phys->hw_intf->ops.collect_misr)
323 num_intf++;
324 }
325
326 return num_intf;
327 }
328
329 /**
330 * dpu_encoder_setup_misr - enable misr calculations
331 * @drm_enc: Pointer to previously created drm encoder structure
332 */
dpu_encoder_setup_misr(const struct drm_encoder * drm_enc)333 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
334 {
335 struct dpu_encoder_virt *dpu_enc;
336
337 int i;
338
339 dpu_enc = to_dpu_encoder_virt(drm_enc);
340
341 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
342 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
343
344 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
345 continue;
346
347 phys->hw_intf->ops.setup_misr(phys->hw_intf);
348 }
349 }
350
351 /**
352 * dpu_encoder_get_crc - get the crc value from interface blocks
353 * @drm_enc: Pointer to previously created drm encoder structure
354 * @crcs: array to fill with CRC data
355 * @pos: offset into the @crcs array
356 * Returns: 0 on success, error otherwise
357 */
dpu_encoder_get_crc(const struct drm_encoder * drm_enc,u32 * crcs,int pos)358 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos)
359 {
360 struct dpu_encoder_virt *dpu_enc;
361
362 int i, rc = 0, entries_added = 0;
363
364 if (!drm_enc->crtc) {
365 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index);
366 return -EINVAL;
367 }
368
369 dpu_enc = to_dpu_encoder_virt(drm_enc);
370
371 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
372 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
373
374 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr)
375 continue;
376
377 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]);
378 if (rc)
379 return rc;
380 entries_added++;
381 }
382
383 return entries_added;
384 }
385
_dpu_encoder_setup_dither(struct dpu_hw_pingpong * hw_pp,unsigned bpc)386 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
387 {
388 struct dpu_hw_dither_cfg dither_cfg = { 0 };
389
390 if (!hw_pp->ops.setup_dither)
391 return;
392
393 switch (bpc) {
394 case 6:
395 dither_cfg.c0_bitdepth = 6;
396 dither_cfg.c1_bitdepth = 6;
397 dither_cfg.c2_bitdepth = 6;
398 dither_cfg.c3_bitdepth = 6;
399 dither_cfg.temporal_en = 0;
400 break;
401 default:
402 hw_pp->ops.setup_dither(hw_pp, NULL);
403 return;
404 }
405
406 memcpy(&dither_cfg.matrix, dither_matrix,
407 sizeof(u32) * DITHER_MATRIX_SZ);
408
409 hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
410 }
411
dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)412 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)
413 {
414 switch (intf_mode) {
415 case INTF_MODE_VIDEO:
416 return "INTF_MODE_VIDEO";
417 case INTF_MODE_CMD:
418 return "INTF_MODE_CMD";
419 case INTF_MODE_WB_BLOCK:
420 return "INTF_MODE_WB_BLOCK";
421 case INTF_MODE_WB_LINE:
422 return "INTF_MODE_WB_LINE";
423 default:
424 return "INTF_MODE_UNKNOWN";
425 }
426 }
427
428 /**
429 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
430 * timed out, including reporting frame error event to crtc and debug dump
431 * @phys_enc: Pointer to physical encoder structure
432 * @intr_idx: Failing interrupt index
433 */
dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys * phys_enc,enum dpu_intr_idx intr_idx)434 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
435 enum dpu_intr_idx intr_idx)
436 {
437 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n",
438 DRMID(phys_enc->parent),
439 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
440 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1,
441 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1,
442 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
443
444 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
445 DPU_ENCODER_FRAME_EVENT_ERROR);
446 }
447
448 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
449 u32 irq_idx, struct dpu_encoder_wait_info *info);
450
451 /**
452 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
453 * note: will call dpu_encoder_helper_wait_for_irq on timeout
454 * @phys_enc: Pointer to physical encoder structure
455 * @irq_idx: IRQ index
456 * @func: IRQ callback to be called in case of timeout
457 * @wait_info: wait info struct
458 * @return: 0 or -ERROR
459 */
dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys * phys_enc,unsigned int irq_idx,void (* func)(void * arg),struct dpu_encoder_wait_info * wait_info)460 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
461 unsigned int irq_idx,
462 void (*func)(void *arg),
463 struct dpu_encoder_wait_info *wait_info)
464 {
465 u32 irq_status;
466 int ret;
467
468 if (!wait_info) {
469 DPU_ERROR("invalid params\n");
470 return -EINVAL;
471 }
472 /* note: do master / slave checking outside */
473
474 /* return EWOULDBLOCK since we know the wait isn't necessary */
475 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
476 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n",
477 DRMID(phys_enc->parent), func,
478 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
479 return -EWOULDBLOCK;
480 }
481
482 if (irq_idx == 0) {
483 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
484 DRMID(phys_enc->parent), func);
485 return 0;
486 }
487
488 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n",
489 DRMID(phys_enc->parent), func,
490 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0,
491 atomic_read(wait_info->atomic_cnt));
492
493 ret = dpu_encoder_helper_wait_event_timeout(
494 DRMID(phys_enc->parent),
495 irq_idx,
496 wait_info);
497
498 if (ret <= 0) {
499 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx);
500 if (irq_status) {
501 unsigned long flags;
502
503 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
504 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
505 DRMID(phys_enc->parent), func,
506 phys_enc->hw_pp->idx - PINGPONG_0,
507 atomic_read(wait_info->atomic_cnt));
508 local_irq_save(flags);
509 func(phys_enc);
510 local_irq_restore(flags);
511 ret = 0;
512 } else {
513 ret = -ETIMEDOUT;
514 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
515 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
516 DRMID(phys_enc->parent), func,
517 phys_enc->hw_pp->idx - PINGPONG_0,
518 atomic_read(wait_info->atomic_cnt));
519 }
520 } else {
521 ret = 0;
522 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
523 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
524 phys_enc->hw_pp->idx - PINGPONG_0,
525 atomic_read(wait_info->atomic_cnt));
526 }
527
528 return ret;
529 }
530
531 /**
532 * dpu_encoder_get_vsync_count - get vsync count for the encoder.
533 * @drm_enc: Pointer to previously created drm encoder structure
534 */
dpu_encoder_get_vsync_count(struct drm_encoder * drm_enc)535 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc)
536 {
537 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
538 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL;
539 return phys ? atomic_read(&phys->vsync_cnt) : 0;
540 }
541
542 /**
543 * dpu_encoder_get_linecount - get interface line count for the encoder.
544 * @drm_enc: Pointer to previously created drm encoder structure
545 */
dpu_encoder_get_linecount(struct drm_encoder * drm_enc)546 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
547 {
548 struct dpu_encoder_virt *dpu_enc;
549 struct dpu_encoder_phys *phys;
550 int linecount = 0;
551
552 dpu_enc = to_dpu_encoder_virt(drm_enc);
553 phys = dpu_enc ? dpu_enc->cur_master : NULL;
554
555 if (phys && phys->ops.get_line_count)
556 linecount = phys->ops.get_line_count(phys);
557
558 return linecount;
559 }
560
561 /**
562 * dpu_encoder_helper_split_config - split display configuration helper function
563 * This helper function may be used by physical encoders to configure
564 * the split display related registers.
565 * @phys_enc: Pointer to physical encoder structure
566 * @interface: enum dpu_intf setting
567 */
dpu_encoder_helper_split_config(struct dpu_encoder_phys * phys_enc,enum dpu_intf interface)568 void dpu_encoder_helper_split_config(
569 struct dpu_encoder_phys *phys_enc,
570 enum dpu_intf interface)
571 {
572 struct dpu_encoder_virt *dpu_enc;
573 struct split_pipe_cfg cfg = { 0 };
574 struct dpu_hw_mdp *hw_mdptop;
575 struct msm_display_info *disp_info;
576
577 if (!phys_enc->hw_mdptop || !phys_enc->parent) {
578 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
579 return;
580 }
581
582 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
583 hw_mdptop = phys_enc->hw_mdptop;
584 disp_info = &dpu_enc->disp_info;
585
586 if (disp_info->intf_type != INTF_DSI)
587 return;
588
589 /**
590 * disable split modes since encoder will be operating in as the only
591 * encoder, either for the entire use case in the case of, for example,
592 * single DSI, or for this frame in the case of left/right only partial
593 * update.
594 */
595 if (phys_enc->split_role == ENC_ROLE_SOLO) {
596 if (hw_mdptop->ops.setup_split_pipe)
597 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
598 return;
599 }
600
601 cfg.en = true;
602 cfg.mode = phys_enc->intf_mode;
603 cfg.intf = interface;
604
605 if (cfg.en && phys_enc->ops.needs_single_flush &&
606 phys_enc->ops.needs_single_flush(phys_enc))
607 cfg.split_flush_en = true;
608
609 if (phys_enc->split_role == ENC_ROLE_MASTER) {
610 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
611
612 if (hw_mdptop->ops.setup_split_pipe)
613 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
614 }
615 }
616
617 /**
618 * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology.
619 * @drm_enc: Pointer to previously created drm encoder structure
620 */
dpu_encoder_use_dsc_merge(struct drm_encoder * drm_enc)621 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
622 {
623 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
624 int i, intf_count = 0, num_dsc = 0;
625
626 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
627 if (dpu_enc->phys_encs[i])
628 intf_count++;
629
630 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
631 if (dpu_enc->hw_dsc[i])
632 num_dsc++;
633
634 return (num_dsc > 0) && (num_dsc > intf_count);
635 }
636
637 /**
638 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
639 * This helper function is used by physical encoder to get DSC config
640 * used for this encoder.
641 * @drm_enc: Pointer to encoder structure
642 */
dpu_encoder_get_dsc_config(struct drm_encoder * drm_enc)643 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
644 {
645 struct msm_drm_private *priv = drm_enc->dev->dev_private;
646 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
647 int index = dpu_enc->disp_info.h_tile_instance[0];
648
649 if (dpu_enc->disp_info.intf_type == INTF_DSI)
650 return msm_dsi_get_dsc_config(priv->kms->dsi[index]);
651
652 return NULL;
653 }
654
dpu_encoder_update_topology(struct drm_encoder * drm_enc,struct msm_display_topology * topology,struct drm_atomic_state * state,const struct drm_display_mode * adj_mode)655 void dpu_encoder_update_topology(struct drm_encoder *drm_enc,
656 struct msm_display_topology *topology,
657 struct drm_atomic_state *state,
658 const struct drm_display_mode *adj_mode)
659 {
660 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
661 struct msm_drm_private *priv = dpu_enc->base.dev->dev_private;
662 struct msm_display_info *disp_info = &dpu_enc->disp_info;
663 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
664 struct drm_connector *connector;
665 struct drm_connector_state *conn_state;
666 struct drm_framebuffer *fb;
667 struct drm_dsc_config *dsc;
668
669 int i;
670
671 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
672 if (dpu_enc->phys_encs[i])
673 topology->num_intf++;
674
675 dsc = dpu_encoder_get_dsc_config(drm_enc);
676
677 /* We only support 2 DSC mode (with 2 LM and 1 INTF) */
678 if (dsc) {
679 /*
680 * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces
681 * when Display Stream Compression (DSC) is enabled,
682 * and when enough DSC blocks are available.
683 * This is power-optimal and can drive up to (including) 4k
684 * screens.
685 */
686 WARN(topology->num_intf > 2,
687 "DSC topology cannot support more than 2 interfaces\n");
688 if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2)
689 topology->num_dsc = 2;
690 else
691 topology->num_dsc = 1;
692 }
693
694 connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
695 if (!connector)
696 return;
697 conn_state = drm_atomic_get_new_connector_state(state, connector);
698 if (!conn_state)
699 return;
700
701 /*
702 * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it.
703 * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check()
704 * earlier.
705 */
706 if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) {
707 fb = conn_state->writeback_job->fb;
708
709 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb)))
710 topology->num_cdm++;
711 } else if (disp_info->intf_type == INTF_DP) {
712 if (msm_dp_is_yuv_420_enabled(priv->kms->dp[disp_info->h_tile_instance[0]],
713 adj_mode))
714 topology->num_cdm++;
715 }
716 }
717
dpu_encoder_needs_modeset(struct drm_encoder * drm_enc,struct drm_atomic_state * state)718 bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_state *state)
719 {
720 struct drm_connector *connector;
721 struct drm_connector_state *conn_state;
722 struct drm_framebuffer *fb;
723 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
724
725 if (!drm_enc || !state)
726 return false;
727
728 connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
729 if (!connector)
730 return false;
731
732 conn_state = drm_atomic_get_new_connector_state(state, connector);
733
734 /**
735 * These checks are duplicated from dpu_encoder_update_topology() since
736 * CRTC and encoder don't hold topology information
737 */
738 if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) {
739 fb = conn_state->writeback_job->fb;
740 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) {
741 if (!dpu_enc->cur_master->hw_cdm)
742 return true;
743 } else {
744 if (dpu_enc->cur_master->hw_cdm)
745 return true;
746 }
747 }
748
749 return false;
750 }
751
_dpu_encoder_update_vsync_source(struct dpu_encoder_virt * dpu_enc,struct msm_display_info * disp_info)752 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
753 struct msm_display_info *disp_info)
754 {
755 struct dpu_vsync_source_cfg vsync_cfg = { 0 };
756 struct msm_drm_private *priv;
757 struct dpu_kms *dpu_kms;
758 struct dpu_hw_mdp *hw_mdptop;
759 struct drm_encoder *drm_enc;
760 struct dpu_encoder_phys *phys_enc;
761 int i;
762
763 if (!dpu_enc || !disp_info) {
764 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
765 dpu_enc != NULL, disp_info != NULL);
766 return;
767 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
768 DPU_ERROR("invalid num phys enc %d/%d\n",
769 dpu_enc->num_phys_encs,
770 (int) ARRAY_SIZE(dpu_enc->hw_pp));
771 return;
772 }
773
774 drm_enc = &dpu_enc->base;
775 /* this pointers are checked in virt_enable_helper */
776 priv = drm_enc->dev->dev_private;
777
778 dpu_kms = to_dpu_kms(priv->kms);
779 hw_mdptop = dpu_kms->hw_mdp;
780 if (!hw_mdptop) {
781 DPU_ERROR("invalid mdptop\n");
782 return;
783 }
784
785 if (hw_mdptop->ops.setup_vsync_source) {
786 for (i = 0; i < dpu_enc->num_phys_encs; i++)
787 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
788
789 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
790 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode);
791
792 vsync_cfg.vsync_source = disp_info->vsync_source;
793
794 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
795
796 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
797 phys_enc = dpu_enc->phys_encs[i];
798
799 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel)
800 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf,
801 vsync_cfg.vsync_source);
802 }
803 }
804 }
805
_dpu_encoder_irq_enable(struct drm_encoder * drm_enc)806 static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc)
807 {
808 struct dpu_encoder_virt *dpu_enc;
809 int i;
810
811 if (!drm_enc) {
812 DPU_ERROR("invalid encoder\n");
813 return;
814 }
815
816 dpu_enc = to_dpu_encoder_virt(drm_enc);
817
818 DPU_DEBUG_ENC(dpu_enc, "\n");
819 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
820 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
821
822 phys->ops.irq_enable(phys);
823 }
824 }
825
_dpu_encoder_irq_disable(struct drm_encoder * drm_enc)826 static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc)
827 {
828 struct dpu_encoder_virt *dpu_enc;
829 int i;
830
831 if (!drm_enc) {
832 DPU_ERROR("invalid encoder\n");
833 return;
834 }
835
836 dpu_enc = to_dpu_encoder_virt(drm_enc);
837
838 DPU_DEBUG_ENC(dpu_enc, "\n");
839 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
840 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
841
842 phys->ops.irq_disable(phys);
843 }
844 }
845
_dpu_encoder_resource_enable(struct drm_encoder * drm_enc)846 static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc)
847 {
848 struct msm_drm_private *priv;
849 struct dpu_kms *dpu_kms;
850 struct dpu_encoder_virt *dpu_enc;
851
852 dpu_enc = to_dpu_encoder_virt(drm_enc);
853 priv = drm_enc->dev->dev_private;
854 dpu_kms = to_dpu_kms(priv->kms);
855
856 trace_dpu_enc_rc_enable(DRMID(drm_enc));
857
858 if (!dpu_enc->cur_master) {
859 DPU_ERROR("encoder master not set\n");
860 return;
861 }
862
863 /* enable DPU core clks */
864 pm_runtime_get_sync(&dpu_kms->pdev->dev);
865
866 /* enable all the irq */
867 _dpu_encoder_irq_enable(drm_enc);
868 }
869
_dpu_encoder_resource_disable(struct drm_encoder * drm_enc)870 static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc)
871 {
872 struct msm_drm_private *priv;
873 struct dpu_kms *dpu_kms;
874 struct dpu_encoder_virt *dpu_enc;
875
876 dpu_enc = to_dpu_encoder_virt(drm_enc);
877 priv = drm_enc->dev->dev_private;
878 dpu_kms = to_dpu_kms(priv->kms);
879
880 trace_dpu_enc_rc_disable(DRMID(drm_enc));
881
882 if (!dpu_enc->cur_master) {
883 DPU_ERROR("encoder master not set\n");
884 return;
885 }
886
887 /* disable all the irq */
888 _dpu_encoder_irq_disable(drm_enc);
889
890 /* disable DPU core clks */
891 pm_runtime_put_sync(&dpu_kms->pdev->dev);
892 }
893
dpu_encoder_resource_control(struct drm_encoder * drm_enc,u32 sw_event)894 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
895 u32 sw_event)
896 {
897 struct dpu_encoder_virt *dpu_enc;
898 struct msm_drm_private *priv;
899 bool is_vid_mode = false;
900
901 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
902 DPU_ERROR("invalid parameters\n");
903 return -EINVAL;
904 }
905 dpu_enc = to_dpu_encoder_virt(drm_enc);
906 priv = drm_enc->dev->dev_private;
907 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
908
909 /*
910 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
911 * events and return early for other events (ie wb display).
912 */
913 if (!dpu_enc->idle_pc_supported &&
914 (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
915 sw_event != DPU_ENC_RC_EVENT_STOP &&
916 sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
917 return 0;
918
919 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
920 dpu_enc->rc_state, "begin");
921
922 switch (sw_event) {
923 case DPU_ENC_RC_EVENT_KICKOFF:
924 /* cancel delayed off work, if any */
925 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
926 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
927 sw_event);
928
929 mutex_lock(&dpu_enc->rc_lock);
930
931 /* return if the resource control is already in ON state */
932 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
933 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
934 DRMID(drm_enc), sw_event);
935 mutex_unlock(&dpu_enc->rc_lock);
936 return 0;
937 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
938 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
939 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
940 DRMID(drm_enc), sw_event,
941 dpu_enc->rc_state);
942 mutex_unlock(&dpu_enc->rc_lock);
943 return -EINVAL;
944 }
945
946 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
947 _dpu_encoder_irq_enable(drm_enc);
948 else
949 _dpu_encoder_resource_enable(drm_enc);
950
951 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
952
953 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
954 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
955 "kickoff");
956
957 mutex_unlock(&dpu_enc->rc_lock);
958 break;
959
960 case DPU_ENC_RC_EVENT_FRAME_DONE:
961 /*
962 * mutex lock is not used as this event happens at interrupt
963 * context. And locking is not required as, the other events
964 * like KICKOFF and STOP does a wait-for-idle before executing
965 * the resource_control
966 */
967 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
968 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
969 DRMID(drm_enc), sw_event,
970 dpu_enc->rc_state);
971 return -EINVAL;
972 }
973
974 /*
975 * schedule off work item only when there are no
976 * frames pending
977 */
978 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
979 DRM_DEBUG_KMS("id:%d skip schedule work\n",
980 DRMID(drm_enc));
981 return 0;
982 }
983
984 queue_delayed_work(priv->kms->wq, &dpu_enc->delayed_off_work,
985 msecs_to_jiffies(dpu_enc->idle_timeout));
986
987 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
988 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
989 "frame done");
990 break;
991
992 case DPU_ENC_RC_EVENT_PRE_STOP:
993 /* cancel delayed off work, if any */
994 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
995 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
996 sw_event);
997
998 mutex_lock(&dpu_enc->rc_lock);
999
1000 if (is_vid_mode &&
1001 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
1002 _dpu_encoder_irq_enable(drm_enc);
1003 }
1004 /* skip if is already OFF or IDLE, resources are off already */
1005 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
1006 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
1007 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
1008 DRMID(drm_enc), sw_event,
1009 dpu_enc->rc_state);
1010 mutex_unlock(&dpu_enc->rc_lock);
1011 return 0;
1012 }
1013
1014 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
1015
1016 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1017 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1018 "pre stop");
1019
1020 mutex_unlock(&dpu_enc->rc_lock);
1021 break;
1022
1023 case DPU_ENC_RC_EVENT_STOP:
1024 mutex_lock(&dpu_enc->rc_lock);
1025
1026 /* return if the resource control is already in OFF state */
1027 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
1028 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
1029 DRMID(drm_enc), sw_event);
1030 mutex_unlock(&dpu_enc->rc_lock);
1031 return 0;
1032 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
1033 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
1034 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1035 mutex_unlock(&dpu_enc->rc_lock);
1036 return -EINVAL;
1037 }
1038
1039 /**
1040 * expect to arrive here only if in either idle state or pre-off
1041 * and in IDLE state the resources are already disabled
1042 */
1043 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
1044 _dpu_encoder_resource_disable(drm_enc);
1045
1046 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
1047
1048 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1049 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1050 "stop");
1051
1052 mutex_unlock(&dpu_enc->rc_lock);
1053 break;
1054
1055 case DPU_ENC_RC_EVENT_ENTER_IDLE:
1056 mutex_lock(&dpu_enc->rc_lock);
1057
1058 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
1059 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
1060 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1061 mutex_unlock(&dpu_enc->rc_lock);
1062 return 0;
1063 }
1064
1065 /*
1066 * if we are in ON but a frame was just kicked off,
1067 * ignore the IDLE event, it's probably a stale timer event
1068 */
1069 if (dpu_enc->frame_busy_mask[0]) {
1070 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
1071 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1072 mutex_unlock(&dpu_enc->rc_lock);
1073 return 0;
1074 }
1075
1076 if (is_vid_mode)
1077 _dpu_encoder_irq_disable(drm_enc);
1078 else
1079 _dpu_encoder_resource_disable(drm_enc);
1080
1081 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
1082
1083 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1084 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1085 "idle");
1086
1087 mutex_unlock(&dpu_enc->rc_lock);
1088 break;
1089
1090 default:
1091 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
1092 sw_event);
1093 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1094 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1095 "error");
1096 break;
1097 }
1098
1099 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1100 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1101 "end");
1102 return 0;
1103 }
1104
1105 /**
1106 * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder.
1107 * @drm_enc: Pointer to previously created drm encoder structure
1108 * @job: Pointer to the current drm writeback job
1109 */
dpu_encoder_prepare_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1110 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
1111 struct drm_writeback_job *job)
1112 {
1113 struct dpu_encoder_virt *dpu_enc;
1114 int i;
1115
1116 dpu_enc = to_dpu_encoder_virt(drm_enc);
1117
1118 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1119 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1120
1121 if (phys->ops.prepare_wb_job)
1122 phys->ops.prepare_wb_job(phys, job);
1123
1124 }
1125 }
1126
1127 /**
1128 * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder.
1129 * @drm_enc: Pointer to previously created drm encoder structure
1130 * @job: Pointer to the current drm writeback job
1131 */
dpu_encoder_cleanup_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1132 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
1133 struct drm_writeback_job *job)
1134 {
1135 struct dpu_encoder_virt *dpu_enc;
1136 int i;
1137
1138 dpu_enc = to_dpu_encoder_virt(drm_enc);
1139
1140 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1141 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1142
1143 if (phys->ops.cleanup_wb_job)
1144 phys->ops.cleanup_wb_job(phys, job);
1145
1146 }
1147 }
1148
dpu_encoder_virt_atomic_mode_set(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1149 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
1150 struct drm_crtc_state *crtc_state,
1151 struct drm_connector_state *conn_state)
1152 {
1153 struct dpu_encoder_virt *dpu_enc;
1154 struct msm_drm_private *priv;
1155 struct dpu_kms *dpu_kms;
1156 struct dpu_global_state *global_state;
1157 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
1158 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
1159 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
1160 struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC];
1161 int num_ctl, num_pp, num_dsc;
1162 int num_cwb = 0;
1163 bool is_cwb_encoder;
1164 unsigned int dsc_mask = 0;
1165 unsigned int cwb_mask = 0;
1166 int i;
1167
1168 if (!drm_enc) {
1169 DPU_ERROR("invalid encoder\n");
1170 return;
1171 }
1172
1173 dpu_enc = to_dpu_encoder_virt(drm_enc);
1174 DPU_DEBUG_ENC(dpu_enc, "\n");
1175
1176 priv = drm_enc->dev->dev_private;
1177 dpu_kms = to_dpu_kms(priv->kms);
1178 is_cwb_encoder = drm_crtc_in_clone_mode(crtc_state) &&
1179 dpu_enc->disp_info.intf_type == INTF_WB;
1180
1181 global_state = dpu_kms_get_existing_global_state(dpu_kms);
1182 if (IS_ERR_OR_NULL(global_state)) {
1183 DPU_ERROR("Failed to get global state");
1184 return;
1185 }
1186
1187 trace_dpu_enc_mode_set(DRMID(drm_enc));
1188
1189 /* Query resource that have been reserved in atomic check step. */
1190 if (is_cwb_encoder) {
1191 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1192 drm_enc->crtc,
1193 DPU_HW_BLK_DCWB_PINGPONG,
1194 hw_pp, ARRAY_SIZE(hw_pp));
1195 num_cwb = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1196 drm_enc->crtc,
1197 DPU_HW_BLK_CWB,
1198 hw_cwb, ARRAY_SIZE(hw_cwb));
1199 } else {
1200 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1201 drm_enc->crtc,
1202 DPU_HW_BLK_PINGPONG, hw_pp,
1203 ARRAY_SIZE(hw_pp));
1204 }
1205
1206 for (i = 0; i < num_cwb; i++) {
1207 dpu_enc->hw_cwb[i] = to_dpu_hw_cwb(hw_cwb[i]);
1208 cwb_mask |= BIT(dpu_enc->hw_cwb[i]->idx - CWB_0);
1209 }
1210
1211 dpu_enc->cwb_mask = cwb_mask;
1212
1213 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1214 drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1215
1216 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1217 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1218 : NULL;
1219
1220 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1221 drm_enc->crtc, DPU_HW_BLK_DSC,
1222 hw_dsc, ARRAY_SIZE(hw_dsc));
1223 for (i = 0; i < num_dsc; i++) {
1224 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
1225 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
1226 }
1227
1228 dpu_enc->dsc_mask = dsc_mask;
1229
1230 if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) ||
1231 dpu_enc->disp_info.intf_type == INTF_DP) {
1232 struct dpu_hw_blk *hw_cdm = NULL;
1233
1234 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1235 drm_enc->crtc, DPU_HW_BLK_CDM,
1236 &hw_cdm, 1);
1237 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL;
1238 }
1239
1240 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1241 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1242
1243 phys->hw_pp = dpu_enc->hw_pp[i];
1244 if (!phys->hw_pp) {
1245 DPU_ERROR_ENC(dpu_enc,
1246 "no pp block assigned at idx: %d\n", i);
1247 return;
1248 }
1249
1250 /* Use first (and only) CTL if active CTLs are supported */
1251 if (num_ctl == 1)
1252 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]);
1253 else
1254 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
1255 if (!phys->hw_ctl) {
1256 DPU_ERROR_ENC(dpu_enc,
1257 "no ctl block assigned at idx: %d\n", i);
1258 return;
1259 }
1260
1261 phys->cached_mode = crtc_state->adjusted_mode;
1262 if (phys->ops.atomic_mode_set)
1263 phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
1264 }
1265 }
1266
_dpu_encoder_virt_enable_helper(struct drm_encoder * drm_enc)1267 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1268 {
1269 struct dpu_encoder_virt *dpu_enc = NULL;
1270 int i;
1271
1272 if (!drm_enc || !drm_enc->dev) {
1273 DPU_ERROR("invalid parameters\n");
1274 return;
1275 }
1276
1277 dpu_enc = to_dpu_encoder_virt(drm_enc);
1278 if (!dpu_enc || !dpu_enc->cur_master) {
1279 DPU_ERROR("invalid dpu encoder/master\n");
1280 return;
1281 }
1282
1283
1284 if (dpu_enc->disp_info.intf_type == INTF_DP &&
1285 dpu_enc->cur_master->hw_mdptop &&
1286 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1287 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1288 dpu_enc->cur_master->hw_mdptop);
1289
1290 if (dpu_enc->disp_info.is_cmd_mode)
1291 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1292
1293 if (dpu_enc->disp_info.intf_type == INTF_DSI &&
1294 !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1295 unsigned bpc = dpu_enc->connector->display_info.bpc;
1296 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1297 if (!dpu_enc->hw_pp[i])
1298 continue;
1299 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1300 }
1301 }
1302 }
1303
1304 /**
1305 * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs
1306 * @drm_enc: encoder pointer
1307 */
dpu_encoder_virt_runtime_resume(struct drm_encoder * drm_enc)1308 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1309 {
1310 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1311
1312 mutex_lock(&dpu_enc->enc_lock);
1313
1314 if (!dpu_enc->enabled)
1315 goto out;
1316
1317 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1318 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1319 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1320 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1321
1322 _dpu_encoder_virt_enable_helper(drm_enc);
1323
1324 out:
1325 mutex_unlock(&dpu_enc->enc_lock);
1326 }
1327
dpu_encoder_virt_atomic_enable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1328 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
1329 struct drm_atomic_state *state)
1330 {
1331 struct dpu_encoder_virt *dpu_enc = NULL;
1332 int ret = 0;
1333 struct drm_display_mode *cur_mode = NULL;
1334
1335 dpu_enc = to_dpu_encoder_virt(drm_enc);
1336 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
1337
1338 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
1339
1340 mutex_lock(&dpu_enc->enc_lock);
1341
1342 dpu_enc->commit_done_timedout = false;
1343
1344 dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
1345
1346 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1347
1348 dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc);
1349
1350 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1351 cur_mode->vdisplay);
1352
1353 /* always enable slave encoder before master */
1354 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1355 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1356
1357 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1358 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1359
1360 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1361 if (ret) {
1362 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1363 ret);
1364 goto out;
1365 }
1366
1367 _dpu_encoder_virt_enable_helper(drm_enc);
1368
1369 dpu_enc->enabled = true;
1370
1371 out:
1372 mutex_unlock(&dpu_enc->enc_lock);
1373 }
1374
dpu_encoder_virt_atomic_disable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1375 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
1376 struct drm_atomic_state *state)
1377 {
1378 struct dpu_encoder_virt *dpu_enc = NULL;
1379 struct drm_crtc *crtc;
1380 struct drm_crtc_state *old_state = NULL;
1381 int i = 0;
1382
1383 dpu_enc = to_dpu_encoder_virt(drm_enc);
1384 DPU_DEBUG_ENC(dpu_enc, "\n");
1385
1386 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
1387 if (crtc)
1388 old_state = drm_atomic_get_old_crtc_state(state, crtc);
1389
1390 /*
1391 * The encoder is already disabled if self refresh mode was set earlier,
1392 * in the old_state for the corresponding crtc.
1393 */
1394 if (old_state && old_state->self_refresh_active)
1395 return;
1396
1397 mutex_lock(&dpu_enc->enc_lock);
1398 dpu_enc->enabled = false;
1399
1400 trace_dpu_enc_disable(DRMID(drm_enc));
1401
1402 /* wait for idle */
1403 dpu_encoder_wait_for_tx_complete(drm_enc);
1404
1405 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1406
1407 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1408 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1409
1410 if (phys->ops.disable)
1411 phys->ops.disable(phys);
1412 }
1413
1414
1415 /* after phys waits for frame-done, should be no more frames pending */
1416 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1417 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1418 timer_delete_sync(&dpu_enc->frame_done_timer);
1419 }
1420
1421 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1422
1423 dpu_enc->connector = NULL;
1424
1425 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1426
1427 mutex_unlock(&dpu_enc->enc_lock);
1428 }
1429
dpu_encoder_get_intf(const struct dpu_mdss_cfg * catalog,struct dpu_rm * dpu_rm,enum dpu_intf_type type,u32 controller_id)1430 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
1431 struct dpu_rm *dpu_rm,
1432 enum dpu_intf_type type, u32 controller_id)
1433 {
1434 int i = 0;
1435
1436 if (type == INTF_WB)
1437 return NULL;
1438
1439 for (i = 0; i < catalog->intf_count; i++) {
1440 if (catalog->intf[i].type == type
1441 && catalog->intf[i].controller_id == controller_id) {
1442 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id);
1443 }
1444 }
1445
1446 return NULL;
1447 }
1448
1449 /**
1450 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception
1451 * @drm_enc: Pointer to drm encoder structure
1452 * @phy_enc: Pointer to physical encoder
1453 * Note: This is called from IRQ handler context.
1454 */
dpu_encoder_vblank_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1455 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1456 struct dpu_encoder_phys *phy_enc)
1457 {
1458 struct dpu_encoder_virt *dpu_enc = NULL;
1459 unsigned long lock_flags;
1460
1461 if (!drm_enc || !phy_enc)
1462 return;
1463
1464 DPU_ATRACE_BEGIN("encoder_vblank_callback");
1465 dpu_enc = to_dpu_encoder_virt(drm_enc);
1466
1467 atomic_inc(&phy_enc->vsync_cnt);
1468
1469 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1470 if (dpu_enc->crtc)
1471 dpu_crtc_vblank_callback(dpu_enc->crtc);
1472 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1473
1474 DPU_ATRACE_END("encoder_vblank_callback");
1475 }
1476
1477 /**
1478 * dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception
1479 * @drm_enc: Pointer to drm encoder structure
1480 * @phy_enc: Pointer to physical encoder
1481 * Note: This is called from IRQ handler context.
1482 */
dpu_encoder_underrun_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1483 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1484 struct dpu_encoder_phys *phy_enc)
1485 {
1486 if (!phy_enc)
1487 return;
1488
1489 DPU_ATRACE_BEGIN("encoder_underrun_callback");
1490 atomic_inc(&phy_enc->underrun_cnt);
1491
1492 /* trigger dump only on the first underrun */
1493 if (atomic_read(&phy_enc->underrun_cnt) == 1)
1494 msm_disp_snapshot_state(drm_enc->dev);
1495
1496 trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1497 atomic_read(&phy_enc->underrun_cnt));
1498 DPU_ATRACE_END("encoder_underrun_callback");
1499 }
1500
1501 /**
1502 * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to
1503 * @drm_enc: encoder pointer
1504 * @crtc: crtc pointer
1505 */
dpu_encoder_assign_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc)1506 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1507 {
1508 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1509 unsigned long lock_flags;
1510
1511 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1512 /* crtc should always be cleared before re-assigning */
1513 WARN_ON(crtc && dpu_enc->crtc);
1514 dpu_enc->crtc = crtc;
1515 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1516 }
1517
1518 /**
1519 * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if
1520 * the encoder is assigned to the given crtc
1521 * @drm_enc: encoder pointer
1522 * @crtc: crtc pointer
1523 * @enable: true if vblank should be enabled
1524 */
dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc,bool enable)1525 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1526 struct drm_crtc *crtc, bool enable)
1527 {
1528 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1529 unsigned long lock_flags;
1530 int i;
1531
1532 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1533
1534 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1535 if (dpu_enc->crtc != crtc) {
1536 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1537 return;
1538 }
1539 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1540
1541 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1542 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1543
1544 if (phys->ops.control_vblank_irq)
1545 phys->ops.control_vblank_irq(phys, enable);
1546 }
1547 }
1548
1549 /**
1550 * dpu_encoder_frame_done_callback - Notify virtual encoder that this phys
1551 * encoder completes last request frame
1552 * @drm_enc: Pointer to drm encoder structure
1553 * @ready_phys: Pointer to physical encoder
1554 * @event: Event to process
1555 */
dpu_encoder_frame_done_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * ready_phys,u32 event)1556 void dpu_encoder_frame_done_callback(
1557 struct drm_encoder *drm_enc,
1558 struct dpu_encoder_phys *ready_phys, u32 event)
1559 {
1560 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1561 unsigned int i;
1562
1563 if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1564 | DPU_ENCODER_FRAME_EVENT_ERROR
1565 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1566
1567 if (!dpu_enc->frame_busy_mask[0]) {
1568 /**
1569 * suppress frame_done without waiter,
1570 * likely autorefresh
1571 */
1572 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,
1573 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
1574 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1,
1575 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1);
1576 return;
1577 }
1578
1579 /* One of the physical encoders has become idle */
1580 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1581 if (dpu_enc->phys_encs[i] == ready_phys) {
1582 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1583 dpu_enc->frame_busy_mask[0]);
1584 clear_bit(i, dpu_enc->frame_busy_mask);
1585 }
1586 }
1587
1588 if (!dpu_enc->frame_busy_mask[0]) {
1589 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1590 timer_delete(&dpu_enc->frame_done_timer);
1591
1592 dpu_encoder_resource_control(drm_enc,
1593 DPU_ENC_RC_EVENT_FRAME_DONE);
1594
1595 if (dpu_enc->crtc)
1596 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
1597 }
1598 } else {
1599 if (dpu_enc->crtc)
1600 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
1601 }
1602 }
1603
dpu_encoder_off_work(struct work_struct * work)1604 static void dpu_encoder_off_work(struct work_struct *work)
1605 {
1606 struct dpu_encoder_virt *dpu_enc = container_of(work,
1607 struct dpu_encoder_virt, delayed_off_work.work);
1608
1609 dpu_encoder_resource_control(&dpu_enc->base,
1610 DPU_ENC_RC_EVENT_ENTER_IDLE);
1611
1612 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1613 DPU_ENCODER_FRAME_EVENT_IDLE);
1614 }
1615
1616 /**
1617 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1618 * @drm_enc: Pointer to drm encoder structure
1619 * @phys: Pointer to physical encoder structure
1620 * @extra_flush_bits: Additional bit mask to include in flush trigger
1621 */
_dpu_encoder_trigger_flush(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phys,uint32_t extra_flush_bits)1622 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1623 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1624 {
1625 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1626 struct dpu_hw_ctl *ctl;
1627 int pending_kickoff_cnt;
1628 u32 ret = UINT_MAX;
1629
1630 if (!phys->hw_pp) {
1631 DPU_ERROR("invalid pingpong hw\n");
1632 return;
1633 }
1634
1635 ctl = phys->hw_ctl;
1636 if (!ctl->ops.trigger_flush) {
1637 DPU_ERROR("missing trigger cb\n");
1638 return;
1639 }
1640
1641 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1642
1643 /* Return early if encoder is writeback and in clone mode */
1644 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL &&
1645 dpu_enc->cwb_mask) {
1646 DPU_DEBUG("encoder %d skip flush for concurrent writeback encoder\n",
1647 DRMID(drm_enc));
1648 return;
1649 }
1650
1651
1652 if (extra_flush_bits && ctl->ops.update_pending_flush)
1653 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1654
1655 ctl->ops.trigger_flush(ctl);
1656
1657 if (ctl->ops.get_pending_flush)
1658 ret = ctl->ops.get_pending_flush(ctl);
1659
1660 trace_dpu_enc_trigger_flush(DRMID(drm_enc),
1661 dpu_encoder_helper_get_intf_type(phys->intf_mode),
1662 phys->hw_intf ? phys->hw_intf->idx : -1,
1663 phys->hw_wb ? phys->hw_wb->idx : -1,
1664 pending_kickoff_cnt, ctl->idx,
1665 extra_flush_bits, ret);
1666 }
1667
1668 /**
1669 * _dpu_encoder_trigger_start - trigger start for a physical encoder
1670 * @phys: Pointer to physical encoder structure
1671 */
_dpu_encoder_trigger_start(struct dpu_encoder_phys * phys)1672 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1673 {
1674 struct dpu_encoder_virt *dpu_enc;
1675
1676 if (!phys) {
1677 DPU_ERROR("invalid argument(s)\n");
1678 return;
1679 }
1680
1681 if (!phys->hw_pp) {
1682 DPU_ERROR("invalid pingpong hw\n");
1683 return;
1684 }
1685
1686 dpu_enc = to_dpu_encoder_virt(phys->parent);
1687
1688 if (phys->parent->encoder_type == DRM_MODE_ENCODER_VIRTUAL &&
1689 dpu_enc->cwb_mask) {
1690 DPU_DEBUG("encoder %d CWB enabled, skipping\n", DRMID(phys->parent));
1691 return;
1692 }
1693
1694 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1695 phys->ops.trigger_start(phys);
1696 }
1697
1698 /**
1699 * dpu_encoder_helper_trigger_start - control start helper function
1700 * This helper function may be optionally specified by physical
1701 * encoders if they require ctl_start triggering.
1702 * @phys_enc: Pointer to physical encoder structure
1703 */
dpu_encoder_helper_trigger_start(struct dpu_encoder_phys * phys_enc)1704 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1705 {
1706 struct dpu_hw_ctl *ctl;
1707
1708 ctl = phys_enc->hw_ctl;
1709 if (ctl->ops.trigger_start) {
1710 ctl->ops.trigger_start(ctl);
1711 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1712 }
1713 }
1714
dpu_encoder_helper_wait_event_timeout(int32_t drm_id,unsigned int irq_idx,struct dpu_encoder_wait_info * info)1715 static int dpu_encoder_helper_wait_event_timeout(
1716 int32_t drm_id,
1717 unsigned int irq_idx,
1718 struct dpu_encoder_wait_info *info)
1719 {
1720 int rc = 0;
1721 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1722 s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1723 s64 time;
1724
1725 do {
1726 rc = wait_event_timeout(*(info->wq),
1727 atomic_read(info->atomic_cnt) == 0, jiffies);
1728 time = ktime_to_ms(ktime_get());
1729
1730 trace_dpu_enc_wait_event_timeout(drm_id,
1731 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
1732 rc, time,
1733 expected_time,
1734 atomic_read(info->atomic_cnt));
1735 /* If we timed out, counter is valid and time is less, wait again */
1736 } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1737 (time < expected_time));
1738
1739 return rc;
1740 }
1741
dpu_encoder_helper_hw_reset(struct dpu_encoder_phys * phys_enc)1742 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1743 {
1744 struct dpu_encoder_virt *dpu_enc;
1745 struct dpu_hw_ctl *ctl;
1746 int rc;
1747 struct drm_encoder *drm_enc;
1748
1749 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1750 ctl = phys_enc->hw_ctl;
1751 drm_enc = phys_enc->parent;
1752
1753 if (!ctl->ops.reset)
1754 return;
1755
1756 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1757 ctl->idx);
1758
1759 rc = ctl->ops.reset(ctl);
1760 if (rc) {
1761 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1762 msm_disp_snapshot_state(drm_enc->dev);
1763 }
1764
1765 phys_enc->enable_state = DPU_ENC_ENABLED;
1766 }
1767
1768 /**
1769 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1770 * Iterate through the physical encoders and perform consolidated flush
1771 * and/or control start triggering as needed. This is done in the virtual
1772 * encoder rather than the individual physical ones in order to handle
1773 * use cases that require visibility into multiple physical encoders at
1774 * a time.
1775 * @dpu_enc: Pointer to virtual encoder structure
1776 */
_dpu_encoder_kickoff_phys(struct dpu_encoder_virt * dpu_enc)1777 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1778 {
1779 struct dpu_hw_ctl *ctl;
1780 uint32_t i, pending_flush;
1781 unsigned long lock_flags;
1782
1783 pending_flush = 0x0;
1784
1785 /* update pending counts and trigger kickoff ctl flush atomically */
1786 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1787
1788 /* don't perform flush/start operations for slave encoders */
1789 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1790 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1791
1792 if (phys->enable_state == DPU_ENC_DISABLED)
1793 continue;
1794
1795 ctl = phys->hw_ctl;
1796
1797 /*
1798 * This is cleared in frame_done worker, which isn't invoked
1799 * for async commits. So don't set this for async, since it'll
1800 * roll over to the next commit.
1801 */
1802 if (phys->split_role != ENC_ROLE_SLAVE)
1803 set_bit(i, dpu_enc->frame_busy_mask);
1804
1805 if (!phys->ops.needs_single_flush ||
1806 !phys->ops.needs_single_flush(phys))
1807 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1808 else if (ctl->ops.get_pending_flush)
1809 pending_flush |= ctl->ops.get_pending_flush(ctl);
1810 }
1811
1812 /* for split flush, combine pending flush masks and send to master */
1813 if (pending_flush && dpu_enc->cur_master) {
1814 _dpu_encoder_trigger_flush(
1815 &dpu_enc->base,
1816 dpu_enc->cur_master,
1817 pending_flush);
1818 }
1819
1820 _dpu_encoder_trigger_start(dpu_enc->cur_master);
1821
1822 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1823 }
1824
1825 /**
1826 * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous
1827 * kickoff and trigger the ctl prepare progress for command mode display.
1828 * @drm_enc: encoder pointer
1829 */
dpu_encoder_trigger_kickoff_pending(struct drm_encoder * drm_enc)1830 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1831 {
1832 struct dpu_encoder_virt *dpu_enc;
1833 struct dpu_encoder_phys *phys;
1834 unsigned int i;
1835 struct dpu_hw_ctl *ctl;
1836 struct msm_display_info *disp_info;
1837
1838 if (!drm_enc) {
1839 DPU_ERROR("invalid encoder\n");
1840 return;
1841 }
1842 dpu_enc = to_dpu_encoder_virt(drm_enc);
1843 disp_info = &dpu_enc->disp_info;
1844
1845 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1846 phys = dpu_enc->phys_encs[i];
1847
1848 ctl = phys->hw_ctl;
1849 ctl->ops.clear_pending_flush(ctl);
1850
1851 /* update only for command mode primary ctl */
1852 if ((phys == dpu_enc->cur_master) &&
1853 disp_info->is_cmd_mode
1854 && ctl->ops.trigger_pending)
1855 ctl->ops.trigger_pending(ctl);
1856 }
1857 }
1858
_dpu_encoder_calculate_linetime(struct dpu_encoder_virt * dpu_enc,struct drm_display_mode * mode)1859 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1860 struct drm_display_mode *mode)
1861 {
1862 u64 pclk_rate;
1863 u32 pclk_period;
1864 u32 line_time;
1865
1866 /*
1867 * For linetime calculation, only operate on master encoder.
1868 */
1869 if (!dpu_enc->cur_master)
1870 return 0;
1871
1872 if (!dpu_enc->cur_master->ops.get_line_count) {
1873 DPU_ERROR("get_line_count function not defined\n");
1874 return 0;
1875 }
1876
1877 pclk_rate = mode->clock; /* pixel clock in kHz */
1878 if (pclk_rate == 0) {
1879 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1880 return 0;
1881 }
1882
1883 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1884 if (pclk_period == 0) {
1885 DPU_ERROR("pclk period is 0\n");
1886 return 0;
1887 }
1888
1889 /*
1890 * Line time calculation based on Pixel clock and HTOTAL.
1891 * Final unit is in ns.
1892 */
1893 line_time = (pclk_period * mode->htotal) / 1000;
1894 if (line_time == 0) {
1895 DPU_ERROR("line time calculation is 0\n");
1896 return 0;
1897 }
1898
1899 DPU_DEBUG_ENC(dpu_enc,
1900 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1901 pclk_rate, pclk_period, line_time);
1902
1903 return line_time;
1904 }
1905
1906 /**
1907 * dpu_encoder_vsync_time - get the time of the next vsync
1908 * @drm_enc: encoder pointer
1909 * @wakeup_time: pointer to ktime_t to write the vsync time to
1910 */
dpu_encoder_vsync_time(struct drm_encoder * drm_enc,ktime_t * wakeup_time)1911 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1912 {
1913 struct drm_display_mode *mode;
1914 struct dpu_encoder_virt *dpu_enc;
1915 u32 cur_line;
1916 u32 line_time;
1917 u32 vtotal, time_to_vsync;
1918 ktime_t cur_time;
1919
1920 dpu_enc = to_dpu_encoder_virt(drm_enc);
1921
1922 if (!drm_enc->crtc || !drm_enc->crtc->state) {
1923 DPU_ERROR("crtc/crtc state object is NULL\n");
1924 return -EINVAL;
1925 }
1926 mode = &drm_enc->crtc->state->adjusted_mode;
1927
1928 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1929 if (!line_time)
1930 return -EINVAL;
1931
1932 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1933
1934 vtotal = mode->vtotal;
1935 if (cur_line >= vtotal)
1936 time_to_vsync = line_time * vtotal;
1937 else
1938 time_to_vsync = line_time * (vtotal - cur_line);
1939
1940 if (time_to_vsync == 0) {
1941 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1942 vtotal);
1943 return -EINVAL;
1944 }
1945
1946 cur_time = ktime_get();
1947 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1948
1949 DPU_DEBUG_ENC(dpu_enc,
1950 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1951 cur_line, vtotal, time_to_vsync,
1952 ktime_to_ms(cur_time),
1953 ktime_to_ms(*wakeup_time));
1954 return 0;
1955 }
1956
1957 static u32
dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config * dsc,u32 enc_ip_width)1958 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
1959 u32 enc_ip_width)
1960 {
1961 int ssm_delay, total_pixels, soft_slice_per_enc;
1962
1963 soft_slice_per_enc = enc_ip_width / dsc->slice_width;
1964
1965 /*
1966 * minimum number of initial line pixels is a sum of:
1967 * 1. sub-stream multiplexer delay (83 groups for 8bpc,
1968 * 91 for 10 bpc) * 3
1969 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
1970 * 3. the initial xmit delay
1971 * 4. total pipeline delay through the "lock step" of encoder (47)
1972 * 5. 6 additional pixels as the output of the rate buffer is
1973 * 48 bits wide
1974 */
1975 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
1976 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
1977 if (soft_slice_per_enc > 1)
1978 total_pixels += (ssm_delay * 3);
1979 return DIV_ROUND_UP(total_pixels, dsc->slice_width);
1980 }
1981
dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp,struct drm_dsc_config * dsc,u32 common_mode,u32 initial_lines)1982 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
1983 struct dpu_hw_dsc *hw_dsc,
1984 struct dpu_hw_pingpong *hw_pp,
1985 struct drm_dsc_config *dsc,
1986 u32 common_mode,
1987 u32 initial_lines)
1988 {
1989 if (hw_dsc->ops.dsc_config)
1990 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines);
1991
1992 if (hw_dsc->ops.dsc_config_thresh)
1993 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
1994
1995 if (hw_pp->ops.setup_dsc)
1996 hw_pp->ops.setup_dsc(hw_pp);
1997
1998 if (hw_dsc->ops.dsc_bind_pingpong_blk)
1999 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx);
2000
2001 if (hw_pp->ops.enable_dsc)
2002 hw_pp->ops.enable_dsc(hw_pp);
2003
2004 if (ctl->ops.update_pending_flush_dsc)
2005 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
2006 }
2007
dpu_encoder_prep_dsc(struct dpu_encoder_virt * dpu_enc,struct drm_dsc_config * dsc)2008 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
2009 struct drm_dsc_config *dsc)
2010 {
2011 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
2012 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
2013 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
2014 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
2015 int this_frame_slices;
2016 int intf_ip_w, enc_ip_w;
2017 int dsc_common_mode;
2018 int pic_width;
2019 u32 initial_lines;
2020 int num_dsc = 0;
2021 int i;
2022
2023 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2024 hw_pp[i] = dpu_enc->hw_pp[i];
2025 hw_dsc[i] = dpu_enc->hw_dsc[i];
2026
2027 if (!hw_pp[i] || !hw_dsc[i])
2028 break;
2029
2030 num_dsc++;
2031 }
2032
2033 pic_width = dsc->pic_width;
2034
2035 dsc_common_mode = 0;
2036 if (num_dsc > 1)
2037 dsc_common_mode |= DSC_MODE_SPLIT_PANEL;
2038 if (dpu_encoder_use_dsc_merge(enc_master->parent))
2039 dsc_common_mode |= DSC_MODE_MULTIPLEX;
2040 if (enc_master->intf_mode == INTF_MODE_VIDEO)
2041 dsc_common_mode |= DSC_MODE_VIDEO;
2042
2043 this_frame_slices = pic_width / dsc->slice_width;
2044 intf_ip_w = this_frame_slices * dsc->slice_width;
2045
2046 enc_ip_w = intf_ip_w / num_dsc;
2047 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
2048
2049 for (i = 0; i < num_dsc; i++)
2050 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
2051 dsc, dsc_common_mode, initial_lines);
2052 }
2053
2054 /**
2055 * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl
2056 * path (i.e. ctl flush and start) at next appropriate time.
2057 * Immediately: if no previous commit is outstanding.
2058 * Delayed: Block until next trigger can be issued.
2059 * @drm_enc: encoder pointer
2060 */
dpu_encoder_prepare_for_kickoff(struct drm_encoder * drm_enc)2061 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
2062 {
2063 struct dpu_encoder_virt *dpu_enc;
2064 struct dpu_encoder_phys *phys;
2065 bool needs_hw_reset = false;
2066 unsigned int i;
2067
2068 dpu_enc = to_dpu_encoder_virt(drm_enc);
2069
2070 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
2071
2072 /* prepare for next kickoff, may include waiting on previous kickoff */
2073 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
2074 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2075 phys = dpu_enc->phys_encs[i];
2076 if (phys->ops.prepare_for_kickoff)
2077 phys->ops.prepare_for_kickoff(phys);
2078 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
2079 needs_hw_reset = true;
2080 }
2081 DPU_ATRACE_END("enc_prepare_for_kickoff");
2082
2083 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
2084
2085 /* if any phys needs reset, reset all phys, in-order */
2086 if (needs_hw_reset) {
2087 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
2088 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2089 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
2090 }
2091 }
2092
2093 if (dpu_enc->dsc)
2094 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
2095 }
2096
2097 /**
2098 * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit.
2099 * @drm_enc: Pointer to drm encoder structure
2100 */
dpu_encoder_is_valid_for_commit(struct drm_encoder * drm_enc)2101 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc)
2102 {
2103 struct dpu_encoder_virt *dpu_enc;
2104 unsigned int i;
2105 struct dpu_encoder_phys *phys;
2106
2107 dpu_enc = to_dpu_encoder_virt(drm_enc);
2108
2109 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
2110 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2111 phys = dpu_enc->phys_encs[i];
2112 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) {
2113 DPU_DEBUG("invalid FB not kicking off\n");
2114 return false;
2115 }
2116 }
2117 }
2118
2119 return true;
2120 }
2121
2122 /**
2123 * dpu_encoder_start_frame_done_timer - Start the encoder frame done timer
2124 * @drm_enc: Pointer to drm encoder structure
2125 */
dpu_encoder_start_frame_done_timer(struct drm_encoder * drm_enc)2126 void dpu_encoder_start_frame_done_timer(struct drm_encoder *drm_enc)
2127 {
2128 struct dpu_encoder_virt *dpu_enc;
2129 unsigned long timeout_ms;
2130
2131 dpu_enc = to_dpu_encoder_virt(drm_enc);
2132 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
2133 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
2134
2135 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
2136 mod_timer(&dpu_enc->frame_done_timer,
2137 jiffies + msecs_to_jiffies(timeout_ms));
2138
2139 }
2140
2141 /**
2142 * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path
2143 * (i.e. ctl flush and start) immediately.
2144 * @drm_enc: encoder pointer
2145 */
dpu_encoder_kickoff(struct drm_encoder * drm_enc)2146 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
2147 {
2148 struct dpu_encoder_virt *dpu_enc;
2149 struct dpu_encoder_phys *phys;
2150 unsigned int i;
2151
2152 DPU_ATRACE_BEGIN("encoder_kickoff");
2153 dpu_enc = to_dpu_encoder_virt(drm_enc);
2154
2155 trace_dpu_enc_kickoff(DRMID(drm_enc));
2156
2157 /* All phys encs are ready to go, trigger the kickoff */
2158 _dpu_encoder_kickoff_phys(dpu_enc);
2159
2160 /* allow phys encs to handle any post-kickoff business */
2161 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2162 phys = dpu_enc->phys_encs[i];
2163 if (phys->ops.handle_post_kickoff)
2164 phys->ops.handle_post_kickoff(phys);
2165 }
2166
2167 DPU_ATRACE_END("encoder_kickoff");
2168 }
2169
dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys * phys_enc)2170 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
2171 {
2172 struct dpu_hw_mixer_cfg mixer;
2173 int i, num_lm;
2174 struct dpu_global_state *global_state;
2175 struct dpu_hw_blk *hw_lm[2];
2176 struct dpu_hw_mixer *hw_mixer[2];
2177 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2178
2179 memset(&mixer, 0, sizeof(mixer));
2180
2181 /* reset all mixers for this encoder */
2182 if (ctl->ops.clear_all_blendstages)
2183 ctl->ops.clear_all_blendstages(ctl);
2184
2185 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms);
2186
2187 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state,
2188 phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
2189
2190 for (i = 0; i < num_lm; i++) {
2191 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]);
2192 if (ctl->ops.update_pending_flush_mixer)
2193 ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx);
2194
2195 /* clear all blendstages */
2196 if (ctl->ops.setup_blendstage)
2197 ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL);
2198
2199 if (hw_mixer[i]->ops.clear_all_blendstages)
2200 hw_mixer[i]->ops.clear_all_blendstages(hw_mixer[i]);
2201
2202 if (ctl->ops.set_active_lms)
2203 ctl->ops.set_active_lms(ctl, NULL);
2204
2205 if (ctl->ops.set_active_fetch_pipes)
2206 ctl->ops.set_active_fetch_pipes(ctl, NULL);
2207
2208 if (ctl->ops.set_active_pipes)
2209 ctl->ops.set_active_pipes(ctl, NULL);
2210 }
2211 }
2212
dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp)2213 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl,
2214 struct dpu_hw_dsc *hw_dsc,
2215 struct dpu_hw_pingpong *hw_pp)
2216 {
2217 if (hw_dsc->ops.dsc_disable)
2218 hw_dsc->ops.dsc_disable(hw_dsc);
2219
2220 if (hw_pp->ops.disable_dsc)
2221 hw_pp->ops.disable_dsc(hw_pp);
2222
2223 if (hw_dsc->ops.dsc_bind_pingpong_blk)
2224 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE);
2225
2226 if (ctl->ops.update_pending_flush_dsc)
2227 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
2228 }
2229
dpu_encoder_unprep_dsc(struct dpu_encoder_virt * dpu_enc)2230 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc)
2231 {
2232 /* coding only for 2LM, 2enc, 1 dsc config */
2233 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
2234 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
2235 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
2236 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
2237 int i;
2238
2239 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2240 hw_pp[i] = dpu_enc->hw_pp[i];
2241 hw_dsc[i] = dpu_enc->hw_dsc[i];
2242
2243 if (hw_pp[i] && hw_dsc[i])
2244 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]);
2245 }
2246 }
2247
2248 /**
2249 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline
2250 * @phys_enc: Pointer to physical encoder structure
2251 */
dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys * phys_enc)2252 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
2253 {
2254 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2255 struct dpu_hw_intf_cfg intf_cfg = { 0 };
2256 int i;
2257 struct dpu_encoder_virt *dpu_enc;
2258
2259 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2260
2261 ctl->ops.reset(ctl);
2262
2263 dpu_encoder_helper_reset_mixers(phys_enc);
2264
2265 /*
2266 * TODO: move the once-only operation like CTL flush/trigger
2267 * into dpu_encoder_virt_disable() and all operations which need
2268 * to be done per phys encoder into the phys_disable() op.
2269 */
2270 if (phys_enc->hw_wb) {
2271 /* disable the PP block */
2272 if (phys_enc->hw_wb->ops.bind_pingpong_blk)
2273 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE);
2274
2275 /* mark WB flush as pending */
2276 if (ctl->ops.update_pending_flush_wb)
2277 ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx);
2278 } else {
2279 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2280 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk)
2281 phys_enc->hw_intf->ops.bind_pingpong_blk(
2282 dpu_enc->phys_encs[i]->hw_intf,
2283 PINGPONG_NONE);
2284
2285 /* mark INTF flush as pending */
2286 if (ctl->ops.update_pending_flush_intf)
2287 ctl->ops.update_pending_flush_intf(ctl,
2288 dpu_enc->phys_encs[i]->hw_intf->idx);
2289 }
2290 }
2291
2292 if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither)
2293 phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL);
2294
2295 if (dpu_enc->cwb_mask)
2296 dpu_encoder_helper_phys_setup_cwb(phys_enc, false);
2297
2298 /* reset the merge 3D HW block */
2299 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) {
2300 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
2301 BLEND_3D_NONE);
2302 if (ctl->ops.update_pending_flush_merge_3d)
2303 ctl->ops.update_pending_flush_merge_3d(ctl,
2304 phys_enc->hw_pp->merge_3d->idx);
2305 }
2306
2307 if (phys_enc->hw_cdm) {
2308 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp)
2309 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
2310 PINGPONG_NONE);
2311 if (ctl->ops.update_pending_flush_cdm)
2312 ctl->ops.update_pending_flush_cdm(ctl,
2313 phys_enc->hw_cdm->idx);
2314 }
2315
2316 if (dpu_enc->dsc) {
2317 dpu_encoder_unprep_dsc(dpu_enc);
2318 dpu_enc->dsc = NULL;
2319 }
2320
2321 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
2322 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
2323 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
2324 intf_cfg.cwb = dpu_enc->cwb_mask;
2325
2326 if (phys_enc->hw_intf)
2327 intf_cfg.intf = phys_enc->hw_intf->idx;
2328 if (phys_enc->hw_wb)
2329 intf_cfg.wb = phys_enc->hw_wb->idx;
2330
2331 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d)
2332 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
2333
2334 if (ctl->ops.reset_intf_cfg)
2335 ctl->ops.reset_intf_cfg(ctl, &intf_cfg);
2336
2337 ctl->ops.trigger_flush(ctl);
2338 ctl->ops.trigger_start(ctl);
2339 ctl->ops.clear_pending_flush(ctl);
2340 }
2341
dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys * phys_enc,bool enable)2342 void dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys *phys_enc,
2343 bool enable)
2344 {
2345 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2346 struct dpu_hw_cwb *hw_cwb;
2347 struct dpu_hw_ctl *hw_ctl;
2348 struct dpu_hw_cwb_setup_cfg cwb_cfg;
2349
2350 struct dpu_kms *dpu_kms;
2351 struct dpu_global_state *global_state;
2352 struct dpu_hw_blk *rt_pp_list[MAX_CHANNELS_PER_ENC];
2353 int num_pp;
2354
2355 if (!phys_enc->hw_wb)
2356 return;
2357
2358 hw_ctl = phys_enc->hw_ctl;
2359
2360 if (!phys_enc->hw_ctl) {
2361 DPU_DEBUG("[wb:%d] no ctl assigned\n",
2362 phys_enc->hw_wb->idx - WB_0);
2363 return;
2364 }
2365
2366 dpu_kms = phys_enc->dpu_kms;
2367 global_state = dpu_kms_get_existing_global_state(dpu_kms);
2368 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
2369 phys_enc->parent->crtc,
2370 DPU_HW_BLK_PINGPONG, rt_pp_list,
2371 ARRAY_SIZE(rt_pp_list));
2372
2373 if (num_pp == 0 || num_pp > MAX_CHANNELS_PER_ENC) {
2374 DPU_DEBUG_ENC(dpu_enc, "invalid num_pp %d\n", num_pp);
2375 return;
2376 }
2377
2378 /*
2379 * The CWB mux supports using LM or DSPP as tap points. For now,
2380 * always use LM tap point
2381 */
2382 cwb_cfg.input = INPUT_MODE_LM_OUT;
2383
2384 for (int i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2385 hw_cwb = dpu_enc->hw_cwb[i];
2386 if (!hw_cwb)
2387 continue;
2388
2389 if (enable) {
2390 struct dpu_hw_pingpong *hw_pp =
2391 to_dpu_hw_pingpong(rt_pp_list[i]);
2392 cwb_cfg.pp_idx = hw_pp->idx;
2393 } else {
2394 cwb_cfg.pp_idx = PINGPONG_NONE;
2395 }
2396
2397 hw_cwb->ops.config_cwb(hw_cwb, &cwb_cfg);
2398
2399 if (hw_ctl->ops.update_pending_flush_cwb)
2400 hw_ctl->ops.update_pending_flush_cwb(hw_ctl, hw_cwb->idx);
2401 }
2402 }
2403
2404 /**
2405 * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block
2406 * @phys_enc: Pointer to physical encoder
2407 * @dpu_fmt: Pinter to the format description
2408 * @output_type: HDMI/WB
2409 */
dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys * phys_enc,const struct msm_format * dpu_fmt,u32 output_type)2410 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
2411 const struct msm_format *dpu_fmt,
2412 u32 output_type)
2413 {
2414 struct dpu_hw_cdm *hw_cdm;
2415 struct dpu_hw_cdm_cfg *cdm_cfg;
2416 struct dpu_hw_pingpong *hw_pp;
2417 int ret;
2418
2419 if (!phys_enc)
2420 return;
2421
2422 cdm_cfg = &phys_enc->cdm_cfg;
2423 hw_pp = phys_enc->hw_pp;
2424 hw_cdm = phys_enc->hw_cdm;
2425
2426 if (!hw_cdm)
2427 return;
2428
2429 if (!MSM_FORMAT_IS_YUV(dpu_fmt)) {
2430 DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),
2431 &dpu_fmt->pixel_format);
2432 if (hw_cdm->ops.bind_pingpong_blk)
2433 hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
2434
2435 return;
2436 }
2437
2438 memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));
2439
2440 cdm_cfg->output_width = phys_enc->cached_mode.hdisplay;
2441 cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
2442 cdm_cfg->output_fmt = dpu_fmt;
2443 cdm_cfg->output_type = output_type;
2444 cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?
2445 CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
2446 cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
2447
2448 /* enable 10 bit logic */
2449 switch (cdm_cfg->output_fmt->chroma_sample) {
2450 case CHROMA_FULL:
2451 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2452 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2453 break;
2454 case CHROMA_H2V1:
2455 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2456 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2457 break;
2458 case CHROMA_420:
2459 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2460 cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
2461 break;
2462 case CHROMA_H1V2:
2463 default:
2464 DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
2465 DRMID(phys_enc->parent));
2466 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2467 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2468 break;
2469 }
2470
2471 DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n",
2472 DRMID(phys_enc->parent), cdm_cfg->output_width,
2473 cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,
2474 cdm_cfg->output_type, cdm_cfg->output_bit_depth,
2475 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
2476
2477 if (hw_cdm->ops.enable) {
2478 cdm_cfg->pp_id = hw_pp->idx;
2479 ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
2480 if (ret < 0) {
2481 DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",
2482 DRMID(phys_enc->parent), ret);
2483 return;
2484 }
2485 }
2486 }
2487
2488 #ifdef CONFIG_DEBUG_FS
_dpu_encoder_status_show(struct seq_file * s,void * data)2489 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
2490 {
2491 struct drm_encoder *drm_enc = s->private;
2492 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
2493 int i;
2494
2495 mutex_lock(&dpu_enc->enc_lock);
2496 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2497 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2498
2499 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d",
2500 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1,
2501 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1,
2502 atomic_read(&phys->vsync_cnt),
2503 atomic_read(&phys->underrun_cnt),
2504 atomic_read(&dpu_enc->frame_done_timeout_cnt));
2505
2506 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode));
2507 }
2508 mutex_unlock(&dpu_enc->enc_lock);
2509
2510 return 0;
2511 }
2512
2513 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
2514
dpu_encoder_debugfs_init(struct drm_encoder * drm_enc,struct dentry * root)2515 static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root)
2516 {
2517 /* don't error check these */
2518 debugfs_create_file("status", 0600,
2519 root, drm_enc, &_dpu_encoder_status_fops);
2520 }
2521 #else
2522 #define dpu_encoder_debugfs_init NULL
2523 #endif
2524
dpu_encoder_virt_add_phys_encs(struct drm_device * dev,struct msm_display_info * disp_info,struct dpu_encoder_virt * dpu_enc,struct dpu_enc_phys_init_params * params)2525 static int dpu_encoder_virt_add_phys_encs(
2526 struct drm_device *dev,
2527 struct msm_display_info *disp_info,
2528 struct dpu_encoder_virt *dpu_enc,
2529 struct dpu_enc_phys_init_params *params)
2530 {
2531 struct dpu_encoder_phys *enc = NULL;
2532
2533 DPU_DEBUG_ENC(dpu_enc, "\n");
2534
2535 /*
2536 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
2537 * in this function, check up-front.
2538 */
2539 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
2540 ARRAY_SIZE(dpu_enc->phys_encs)) {
2541 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2542 dpu_enc->num_phys_encs);
2543 return -EINVAL;
2544 }
2545
2546
2547 if (disp_info->intf_type == INTF_WB) {
2548 enc = dpu_encoder_phys_wb_init(dev, params);
2549
2550 if (IS_ERR(enc)) {
2551 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
2552 PTR_ERR(enc));
2553 return PTR_ERR(enc);
2554 }
2555
2556 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2557 ++dpu_enc->num_phys_encs;
2558 } else if (disp_info->is_cmd_mode) {
2559 enc = dpu_encoder_phys_cmd_init(dev, params);
2560
2561 if (IS_ERR(enc)) {
2562 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2563 PTR_ERR(enc));
2564 return PTR_ERR(enc);
2565 }
2566
2567 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2568 ++dpu_enc->num_phys_encs;
2569 } else {
2570 enc = dpu_encoder_phys_vid_init(dev, params);
2571
2572 if (IS_ERR(enc)) {
2573 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2574 PTR_ERR(enc));
2575 return PTR_ERR(enc);
2576 }
2577
2578 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2579 ++dpu_enc->num_phys_encs;
2580 }
2581
2582 if (params->split_role == ENC_ROLE_SLAVE)
2583 dpu_enc->cur_slave = enc;
2584 else
2585 dpu_enc->cur_master = enc;
2586
2587 return 0;
2588 }
2589
2590 /**
2591 * dpu_encoder_get_clones - Calculate the possible_clones for DPU encoder
2592 * @drm_enc: DRM encoder pointer
2593 * Returns: possible_clones mask
2594 */
dpu_encoder_get_clones(struct drm_encoder * drm_enc)2595 uint32_t dpu_encoder_get_clones(struct drm_encoder *drm_enc)
2596 {
2597 struct drm_encoder *curr;
2598 int type = drm_enc->encoder_type;
2599 uint32_t clone_mask = drm_encoder_mask(drm_enc);
2600
2601 /*
2602 * Set writeback as possible clones of real-time DSI encoders and vice
2603 * versa
2604 *
2605 * Writeback encoders can't be clones of each other and DSI
2606 * encoders can't be clones of each other.
2607 *
2608 * TODO: Add DP encoders as valid possible clones for writeback encoders
2609 * (and vice versa) once concurrent writeback has been validated for DP
2610 */
2611 drm_for_each_encoder(curr, drm_enc->dev) {
2612 if ((type == DRM_MODE_ENCODER_VIRTUAL &&
2613 curr->encoder_type == DRM_MODE_ENCODER_DSI) ||
2614 (type == DRM_MODE_ENCODER_DSI &&
2615 curr->encoder_type == DRM_MODE_ENCODER_VIRTUAL))
2616 clone_mask |= drm_encoder_mask(curr);
2617 }
2618
2619 return clone_mask;
2620 }
2621
dpu_encoder_setup_display(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct msm_display_info * disp_info)2622 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2623 struct dpu_kms *dpu_kms,
2624 struct msm_display_info *disp_info)
2625 {
2626 int ret = 0;
2627 int i = 0;
2628 struct dpu_enc_phys_init_params phys_params;
2629
2630 if (!dpu_enc) {
2631 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2632 return -EINVAL;
2633 }
2634
2635 dpu_enc->cur_master = NULL;
2636
2637 memset(&phys_params, 0, sizeof(phys_params));
2638 phys_params.dpu_kms = dpu_kms;
2639 phys_params.parent = &dpu_enc->base;
2640 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2641
2642 WARN_ON(disp_info->num_of_h_tiles < 1);
2643
2644 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2645
2646 if (disp_info->intf_type != INTF_WB)
2647 dpu_enc->idle_pc_supported =
2648 dpu_kms->catalog->caps->has_idle_pc;
2649
2650 mutex_lock(&dpu_enc->enc_lock);
2651 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2652 /*
2653 * Left-most tile is at index 0, content is controller id
2654 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2655 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2656 */
2657 u32 controller_id = disp_info->h_tile_instance[i];
2658
2659 if (disp_info->num_of_h_tiles > 1) {
2660 if (i == 0)
2661 phys_params.split_role = ENC_ROLE_MASTER;
2662 else
2663 phys_params.split_role = ENC_ROLE_SLAVE;
2664 } else {
2665 phys_params.split_role = ENC_ROLE_SOLO;
2666 }
2667
2668 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2669 i, controller_id, phys_params.split_role);
2670
2671 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm,
2672 disp_info->intf_type,
2673 controller_id);
2674
2675 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX)
2676 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id);
2677
2678 if (!phys_params.hw_intf && !phys_params.hw_wb) {
2679 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
2680 ret = -EINVAL;
2681 break;
2682 }
2683
2684 if (phys_params.hw_intf && phys_params.hw_wb) {
2685 DPU_ERROR_ENC(dpu_enc,
2686 "invalid phys both intf and wb block at idx: %d\n", i);
2687 ret = -EINVAL;
2688 break;
2689 }
2690
2691 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info,
2692 dpu_enc, &phys_params);
2693 if (ret) {
2694 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2695 break;
2696 }
2697 }
2698
2699 mutex_unlock(&dpu_enc->enc_lock);
2700
2701 return ret;
2702 }
2703
dpu_encoder_frame_done_timeout(struct timer_list * t)2704 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2705 {
2706 struct dpu_encoder_virt *dpu_enc = timer_container_of(dpu_enc, t,
2707 frame_done_timer);
2708 struct drm_encoder *drm_enc = &dpu_enc->base;
2709 u32 event;
2710
2711 if (!drm_enc->dev) {
2712 DPU_ERROR("invalid parameters\n");
2713 return;
2714 }
2715
2716 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc) {
2717 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2718 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2719 return;
2720 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2721 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2722 return;
2723 }
2724
2725 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n");
2726
2727 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1)
2728 msm_disp_snapshot_state(drm_enc->dev);
2729
2730 event = DPU_ENCODER_FRAME_EVENT_ERROR;
2731 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2732 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
2733 }
2734
2735 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2736 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
2737 .atomic_disable = dpu_encoder_virt_atomic_disable,
2738 .atomic_enable = dpu_encoder_virt_atomic_enable,
2739 };
2740
2741 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2742 .debugfs_init = dpu_encoder_debugfs_init,
2743 };
2744
2745 /**
2746 * dpu_encoder_init - initialize virtual encoder object
2747 * @dev: Pointer to drm device structure
2748 * @drm_enc_mode: corresponding DRM_MODE_ENCODER_* constant
2749 * @disp_info: Pointer to display information structure
2750 * Returns: Pointer to newly created drm encoder
2751 */
dpu_encoder_init(struct drm_device * dev,int drm_enc_mode,struct msm_display_info * disp_info)2752 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2753 int drm_enc_mode,
2754 struct msm_display_info *disp_info)
2755 {
2756 struct msm_drm_private *priv = dev->dev_private;
2757 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2758 struct dpu_encoder_virt *dpu_enc;
2759 int ret;
2760
2761 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base,
2762 &dpu_encoder_funcs, drm_enc_mode, NULL);
2763 if (IS_ERR(dpu_enc))
2764 return ERR_CAST(dpu_enc);
2765
2766 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2767
2768 spin_lock_init(&dpu_enc->enc_spinlock);
2769 dpu_enc->enabled = false;
2770 mutex_init(&dpu_enc->enc_lock);
2771 mutex_init(&dpu_enc->rc_lock);
2772
2773 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2774 if (ret) {
2775 DPU_ERROR("failed to setup encoder\n");
2776 return ERR_PTR(-ENOMEM);
2777 }
2778
2779 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2780 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
2781 timer_setup(&dpu_enc->frame_done_timer,
2782 dpu_encoder_frame_done_timeout, 0);
2783
2784 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2785 dpu_encoder_off_work);
2786 dpu_enc->idle_timeout = IDLE_TIMEOUT;
2787
2788 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2789
2790 DPU_DEBUG_ENC(dpu_enc, "created\n");
2791
2792 return &dpu_enc->base;
2793 }
2794
2795 /**
2796 * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state
2797 * @drm_enc: encoder pointer
2798 *
2799 * Wait for hardware to have flushed the current pending changes to hardware at
2800 * a vblank or CTL_START. Physical encoders will map this differently depending
2801 * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START.
2802 *
2803 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2804 */
dpu_encoder_wait_for_commit_done(struct drm_encoder * drm_enc)2805 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc)
2806 {
2807 struct dpu_encoder_virt *dpu_enc = NULL;
2808 int i, ret = 0;
2809
2810 if (!drm_enc) {
2811 DPU_ERROR("invalid encoder\n");
2812 return -EINVAL;
2813 }
2814 dpu_enc = to_dpu_encoder_virt(drm_enc);
2815 DPU_DEBUG_ENC(dpu_enc, "\n");
2816
2817 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2818 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2819
2820 if (phys->ops.wait_for_commit_done) {
2821 DPU_ATRACE_BEGIN("wait_for_commit_done");
2822 ret = phys->ops.wait_for_commit_done(phys);
2823 DPU_ATRACE_END("wait_for_commit_done");
2824 if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) {
2825 dpu_enc->commit_done_timedout = true;
2826 msm_disp_snapshot_state(drm_enc->dev);
2827 }
2828 if (ret)
2829 return ret;
2830 }
2831 }
2832
2833 return ret;
2834 }
2835
2836 /**
2837 * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel
2838 * @drm_enc: encoder pointer
2839 *
2840 * Wait for the hardware to transfer all the pixels to the panel. Physical
2841 * encoders will map this differently depending on the type: vid mode -> vsync_irq,
2842 * cmd mode -> pp_done.
2843 *
2844 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2845 */
dpu_encoder_wait_for_tx_complete(struct drm_encoder * drm_enc)2846 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc)
2847 {
2848 struct dpu_encoder_virt *dpu_enc = NULL;
2849 int i, ret = 0;
2850
2851 if (!drm_enc) {
2852 DPU_ERROR("invalid encoder\n");
2853 return -EINVAL;
2854 }
2855 dpu_enc = to_dpu_encoder_virt(drm_enc);
2856 DPU_DEBUG_ENC(dpu_enc, "\n");
2857
2858 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2859 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2860
2861 if (phys->ops.wait_for_tx_complete) {
2862 DPU_ATRACE_BEGIN("wait_for_tx_complete");
2863 ret = phys->ops.wait_for_tx_complete(phys);
2864 DPU_ATRACE_END("wait_for_tx_complete");
2865 if (ret)
2866 return ret;
2867 }
2868 }
2869
2870 return ret;
2871 }
2872
2873 /**
2874 * dpu_encoder_get_intf_mode - get interface mode of the given encoder
2875 * @encoder: Pointer to drm encoder object
2876 */
dpu_encoder_get_intf_mode(struct drm_encoder * encoder)2877 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2878 {
2879 struct dpu_encoder_virt *dpu_enc = NULL;
2880
2881 if (!encoder) {
2882 DPU_ERROR("invalid encoder\n");
2883 return INTF_MODE_NONE;
2884 }
2885 dpu_enc = to_dpu_encoder_virt(encoder);
2886
2887 if (dpu_enc->cur_master)
2888 return dpu_enc->cur_master->intf_mode;
2889
2890 if (dpu_enc->num_phys_encs)
2891 return dpu_enc->phys_encs[0]->intf_mode;
2892
2893 return INTF_MODE_NONE;
2894 }
2895
2896 /**
2897 * dpu_encoder_helper_get_cwb_mask - get CWB blocks mask for the DPU encoder
2898 * @phys_enc: Pointer to physical encoder structure
2899 */
dpu_encoder_helper_get_cwb_mask(struct dpu_encoder_phys * phys_enc)2900 unsigned int dpu_encoder_helper_get_cwb_mask(struct dpu_encoder_phys *phys_enc)
2901 {
2902 struct drm_encoder *encoder = phys_enc->parent;
2903 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2904
2905 return dpu_enc->cwb_mask;
2906 }
2907
2908 /**
2909 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
2910 * This helper function is used by physical encoder to get DSC blocks mask
2911 * used for this encoder.
2912 * @phys_enc: Pointer to physical encoder structure
2913 */
dpu_encoder_helper_get_dsc(struct dpu_encoder_phys * phys_enc)2914 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
2915 {
2916 struct drm_encoder *encoder = phys_enc->parent;
2917 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2918
2919 return dpu_enc->dsc_mask;
2920 }
2921
dpu_encoder_phys_init(struct dpu_encoder_phys * phys_enc,struct dpu_enc_phys_init_params * p)2922 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc,
2923 struct dpu_enc_phys_init_params *p)
2924 {
2925 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
2926 phys_enc->hw_intf = p->hw_intf;
2927 phys_enc->hw_wb = p->hw_wb;
2928 phys_enc->parent = p->parent;
2929 phys_enc->dpu_kms = p->dpu_kms;
2930 phys_enc->split_role = p->split_role;
2931 phys_enc->enc_spinlock = p->enc_spinlock;
2932 phys_enc->enable_state = DPU_ENC_DISABLED;
2933
2934 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
2935 atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
2936
2937 atomic_set(&phys_enc->vsync_cnt, 0);
2938 atomic_set(&phys_enc->underrun_cnt, 0);
2939
2940 init_waitqueue_head(&phys_enc->pending_kickoff_wq);
2941 }
2942