1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_BLK_NAME_LEN 16 23 24 #define DPU_MAX_IMG_WIDTH 0x3fff 25 #define DPU_MAX_IMG_HEIGHT 0x3fff 26 27 #define CRTC_DUAL_MIXERS 2 28 29 #define MAX_XIN_COUNT 16 30 31 /** 32 * SSPP sub-blocks/features 33 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 34 * @DPU_SSPP_SCALER_QSEED3_COMPATIBLE, QSEED3-compatible alogorithm support (includes QSEED3, QSEED3LITE and QSEED4) 35 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 36 * @DPU_SSPP_CSC, Support of Color space converion 37 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 38 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 39 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 40 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 41 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 42 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 43 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 44 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 45 * @DPU_SSPP_CDP Supports client driven prefetch 46 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 47 * @DPU_SSPP_MAX maximum value 48 */ 49 enum { 50 DPU_SSPP_SCALER_QSEED2 = 0x1, 51 DPU_SSPP_SCALER_QSEED3_COMPATIBLE, 52 DPU_SSPP_SCALER_RGB, 53 DPU_SSPP_CSC, 54 DPU_SSPP_CSC_10BIT, 55 DPU_SSPP_CURSOR, 56 DPU_SSPP_QOS, 57 DPU_SSPP_EXCL_RECT, 58 DPU_SSPP_SMART_DMA_V1, 59 DPU_SSPP_SMART_DMA_V2, 60 DPU_SSPP_TS_PREFILL, 61 DPU_SSPP_TS_PREFILL_REC1, 62 DPU_SSPP_CDP, 63 DPU_SSPP_INLINE_ROTATION, 64 DPU_SSPP_MAX 65 }; 66 67 /* 68 * MIXER sub-blocks/features 69 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 70 * @DPU_MIXER_MAX maximum value 71 */ 72 enum { 73 DPU_MIXER_SOURCESPLIT = 0x1, 74 DPU_MIXER_MAX, 75 }; 76 77 /** 78 * DSPP sub-blocks 79 * @DPU_DSPP_PCC Panel color correction block 80 * @DPU_DSPP_GC Gamma correction block 81 */ 82 enum { 83 DPU_DSPP_PCC = 0x1, 84 DPU_DSPP_GC, 85 DPU_DSPP_MAX 86 }; 87 88 /** 89 * CTL sub-blocks 90 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 91 * @DPU_CTL_MAX 92 */ 93 enum { 94 DPU_CTL_SPLIT_DISPLAY = 0x1, 95 DPU_CTL_MAX 96 }; 97 98 /** 99 * WB sub-blocks and features 100 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 101 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 102 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 103 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 104 * @DPU_WB_DITHER, Dither block 105 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 106 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 107 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 108 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 109 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 110 * the destination image 111 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 112 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 113 * @DPU_WB_CDP Writeback supports client driven prefetch 114 * @DPU_WB_CROP CWB supports cropping 115 * @DPU_WB_MAX maximum value 116 */ 117 enum { 118 DPU_WB_LINE_MODE = 0x1, 119 DPU_WB_BLOCK_MODE, 120 DPU_WB_UBWC, 121 DPU_WB_YUV_CONFIG, 122 DPU_WB_PIPE_ALPHA, 123 DPU_WB_XY_ROI_OFFSET, 124 DPU_WB_QOS, 125 DPU_WB_QOS_8LVL, 126 DPU_WB_CDP, 127 DPU_WB_CROP, 128 DPU_WB_MAX 129 }; 130 131 /** 132 * VBIF sub-blocks and features 133 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 134 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 135 * @DPU_VBIF_MAX maximum value 136 */ 137 enum { 138 DPU_VBIF_QOS_OTLIM = 0x1, 139 DPU_VBIF_QOS_REMAP, 140 DPU_VBIF_MAX 141 }; 142 143 /** 144 * DSC sub-blocks/features 145 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding 146 * @DPU_DSC_MAX 147 */ 148 enum { 149 DPU_DSC_NATIVE_42x_EN = 0x1, 150 DPU_DSC_MAX 151 }; 152 153 /** 154 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 155 * @name: string name for debug purposes 156 * @id: enum identifying this block 157 * @base: register base offset to mdss 158 * @len: length of hardware block 159 */ 160 #define DPU_HW_BLK_INFO \ 161 char name[DPU_HW_BLK_NAME_LEN]; \ 162 u32 id; \ 163 u32 base; \ 164 u32 len 165 166 /** 167 * struct dpu_scaler_blk: Scaler information 168 * @name: string name for debug purposes 169 * @base: offset of this sub-block relative to the block offset 170 * @len: register block length of this sub-block 171 * @version: qseed block revision, on QSEED3+ platforms this is the value of 172 * scaler_blk.base + QSEED3_HW_VERSION registers. 173 */ 174 struct dpu_scaler_blk { 175 char name[DPU_HW_BLK_NAME_LEN]; 176 u32 base; 177 u32 len; 178 u32 version; 179 }; 180 181 struct dpu_csc_blk { 182 char name[DPU_HW_BLK_NAME_LEN]; 183 u32 base; 184 u32 len; 185 }; 186 187 /** 188 * struct dpu_pp_blk : Pixel processing sub-blk information 189 * @name: string name for debug purposes 190 * @base: offset of this sub-block relative to the block offset 191 * @len: register block length of this sub-block 192 * @version: HW Algorithm version 193 */ 194 struct dpu_pp_blk { 195 char name[DPU_HW_BLK_NAME_LEN]; 196 u32 base; 197 u32 len; 198 u32 version; 199 }; 200 201 /** 202 * struct dpu_dsc_blk - DSC Encoder sub-blk information 203 * @name: string name for debug purposes 204 * @base: offset of this sub-block relative to the block offset 205 * @len: register block length of this sub-block 206 */ 207 struct dpu_dsc_blk { 208 char name[DPU_HW_BLK_NAME_LEN]; 209 u32 base; 210 u32 len; 211 }; 212 213 /** 214 * struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information 215 * @name: string name for debug purposes 216 * @base: offset of this sub-block relative to the block offset 217 * @len: register block length of this sub-block 218 */ 219 struct dpu_sspp_v13_rec_blk { 220 char name[DPU_HW_BLK_NAME_LEN]; 221 u32 base; 222 u32 len; 223 }; 224 225 /** 226 * enum dpu_qos_lut_usage - define QoS LUT use cases 227 */ 228 enum dpu_qos_lut_usage { 229 DPU_QOS_LUT_USAGE_LINEAR, 230 DPU_QOS_LUT_USAGE_MACROTILE, 231 DPU_QOS_LUT_USAGE_NRT, 232 DPU_QOS_LUT_USAGE_MAX, 233 }; 234 235 /** 236 * struct dpu_qos_lut_entry - define QoS LUT table entry 237 * @fl: fill level, or zero on last entry to indicate default lut 238 * @lut: lut to use if equal to or less than fill level 239 */ 240 struct dpu_qos_lut_entry { 241 u32 fl; 242 u64 lut; 243 }; 244 245 /** 246 * struct dpu_qos_lut_tbl - define QoS LUT table 247 * @nentry: number of entry in this table 248 * @entries: Pointer to table entries 249 */ 250 struct dpu_qos_lut_tbl { 251 u32 nentry; 252 const struct dpu_qos_lut_entry *entries; 253 }; 254 255 /** 256 * struct dpu_rotation_cfg - define inline rotation config 257 * @rot_maxheight: max pre rotated height allowed for rotation 258 * @rot_num_formats: number of elements in @rot_format_list 259 * @rot_format_list: list of supported rotator formats 260 */ 261 struct dpu_rotation_cfg { 262 u32 rot_maxheight; 263 size_t rot_num_formats; 264 const u32 *rot_format_list; 265 }; 266 267 /** 268 * struct dpu_caps - define DPU capabilities 269 * @max_mixer_width max layer mixer line width support. 270 * @max_mixer_blendstages max layer mixer blend stages or 271 * supported z order 272 * @has_src_split source split feature status 273 * @has_dim_layer dim layer feature status 274 * @has_idle_pc indicate if idle power collapse feature is supported 275 * @has_3d_merge indicate if 3D merge is supported 276 * @max_linewidth max linewidth for sspp 277 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 278 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 279 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 280 */ 281 struct dpu_caps { 282 u32 max_mixer_width; 283 u32 max_mixer_blendstages; 284 bool has_src_split; 285 bool has_dim_layer; 286 bool has_idle_pc; 287 bool has_3d_merge; 288 /* SSPP limits */ 289 u32 max_linewidth; 290 u32 pixel_ram_size; 291 u32 max_hdeci_exp; 292 u32 max_vdeci_exp; 293 }; 294 295 /** 296 * struct dpu_sspp_sub_blks : SSPP sub-blocks 297 * common: Pointer to common configurations shared by sub blocks 298 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 299 * @qseed_ver: qseed version 300 * @scaler_blk: 301 * @csc_blk: 302 * @format_list: Pointer to list of supported formats 303 * @num_formats: Number of supported formats 304 * @dpu_rotation_cfg: inline rotation configuration 305 */ 306 struct dpu_sspp_sub_blks { 307 u32 max_per_pipe_bw; 308 u32 qseed_ver; 309 struct dpu_scaler_blk scaler_blk; 310 struct dpu_pp_blk csc_blk; 311 struct dpu_sspp_v13_rec_blk sspp_rec0_blk; 312 struct dpu_sspp_v13_rec_blk sspp_rec1_blk; 313 314 const u32 *format_list; 315 u32 num_formats; 316 const struct dpu_rotation_cfg *rotation_cfg; 317 }; 318 319 /** 320 * struct dpu_lm_sub_blks: information of mixer block 321 * @maxwidth: Max pixel width supported by this mixer 322 * @maxblendstages: Max number of blend-stages supported 323 * @blendstage_base: Blend-stage register base offset 324 */ 325 struct dpu_lm_sub_blks { 326 u32 maxblendstages; 327 u32 blendstage_base[MAX_BLOCKS]; 328 }; 329 330 /** 331 * struct dpu_dspp_sub_blks: Information of DSPP block 332 * @pcc: pixel color correction block 333 * @gc: gamma correction block 334 */ 335 struct dpu_dspp_sub_blks { 336 struct dpu_pp_blk pcc; 337 struct dpu_pp_blk gc; 338 }; 339 340 struct dpu_pingpong_sub_blks { 341 struct dpu_pp_blk dither; 342 }; 343 344 /** 345 * struct dpu_dsc_sub_blks - DSC sub-blks 346 * @enc: DSC encoder sub-block 347 * @ctl: DSC controller sub-block 348 */ 349 struct dpu_dsc_sub_blks { 350 struct dpu_dsc_blk enc; 351 struct dpu_dsc_blk ctl; 352 }; 353 354 /** 355 * dpu_clk_ctrl_type - Defines top level clock control signals 356 */ 357 enum dpu_clk_ctrl_type { 358 DPU_CLK_CTRL_NONE, 359 DPU_CLK_CTRL_VIG0, 360 DPU_CLK_CTRL_VIG1, 361 DPU_CLK_CTRL_VIG2, 362 DPU_CLK_CTRL_VIG3, 363 DPU_CLK_CTRL_VIG4, 364 DPU_CLK_CTRL_RGB0, 365 DPU_CLK_CTRL_RGB1, 366 DPU_CLK_CTRL_RGB2, 367 DPU_CLK_CTRL_RGB3, 368 DPU_CLK_CTRL_DMA0, 369 DPU_CLK_CTRL_DMA1, 370 DPU_CLK_CTRL_DMA2, 371 DPU_CLK_CTRL_DMA3, 372 DPU_CLK_CTRL_DMA4, 373 DPU_CLK_CTRL_DMA5, 374 DPU_CLK_CTRL_CURSOR0, 375 DPU_CLK_CTRL_CURSOR1, 376 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 377 DPU_CLK_CTRL_REG_DMA, 378 DPU_CLK_CTRL_WB2, 379 DPU_CLK_CTRL_MAX, 380 }; 381 382 /* struct dpu_clk_ctrl_reg : Clock control register 383 * @reg_off: register offset 384 * @bit_off: bit offset 385 */ 386 struct dpu_clk_ctrl_reg { 387 u32 reg_off; 388 u32 bit_off; 389 }; 390 391 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 392 * @id: index identifying this block 393 * @base: register base offset to mdss 394 * @clk_ctrls clock control register definition 395 */ 396 struct dpu_mdp_cfg { 397 DPU_HW_BLK_INFO; 398 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 399 }; 400 401 /* struct dpu_ctl_cfg : MDP CTL instance info 402 * @id: index identifying this block 403 * @base: register base offset to mdss 404 * @features bit mask identifying sub-blocks/features 405 * @intr_start: interrupt index for CTL_START 406 */ 407 struct dpu_ctl_cfg { 408 DPU_HW_BLK_INFO; 409 unsigned long features; 410 unsigned int intr_start; 411 }; 412 413 /** 414 * struct dpu_sspp_cfg - information of source pipes 415 * @id: index identifying this block 416 * @base register offset of this block 417 * @features bit mask identifying sub-blocks/features 418 * @sblk: SSPP sub-blocks information 419 * @xin_id: bus client identifier 420 * @clk_ctrl clock control identifier 421 * @type sspp type identifier 422 */ 423 struct dpu_sspp_cfg { 424 DPU_HW_BLK_INFO; 425 unsigned long features; 426 const struct dpu_sspp_sub_blks *sblk; 427 u32 xin_id; 428 enum dpu_clk_ctrl_type clk_ctrl; 429 u32 type; 430 }; 431 432 /** 433 * struct dpu_lm_cfg - information of layer mixer blocks 434 * @id: index identifying this block 435 * @base register offset of this block 436 * @features bit mask identifying sub-blocks/features 437 * @sblk: LM Sub-blocks information 438 * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported 439 * @lm_pair: ID of LM that can be controlled by same CTL 440 */ 441 struct dpu_lm_cfg { 442 DPU_HW_BLK_INFO; 443 unsigned long features; 444 const struct dpu_lm_sub_blks *sblk; 445 u32 pingpong; 446 u32 dspp; 447 unsigned long lm_pair; 448 }; 449 450 /** 451 * struct dpu_dspp_cfg - information of DSPP blocks 452 * @id enum identifying this block 453 * @base register offset of this block 454 * supported by this block 455 * @sblk sub-blocks information 456 */ 457 struct dpu_dspp_cfg { 458 DPU_HW_BLK_INFO; 459 const struct dpu_dspp_sub_blks *sblk; 460 }; 461 462 /** 463 * struct dpu_pingpong_cfg - information of PING-PONG blocks 464 * @id enum identifying this block 465 * @base register offset of this block 466 * @intr_done: index for PINGPONG done interrupt 467 * @intr_rdptr: index for PINGPONG readpointer done interrupt 468 * @sblk sub-blocks information 469 */ 470 struct dpu_pingpong_cfg { 471 DPU_HW_BLK_INFO; 472 u32 merge_3d; 473 unsigned int intr_done; 474 unsigned int intr_rdptr; 475 const struct dpu_pingpong_sub_blks *sblk; 476 }; 477 478 /** 479 * struct dpu_merge_3d_cfg - information of DSPP blocks 480 * @id enum identifying this block 481 * @base register offset of this block 482 * @sblk sub-blocks information 483 */ 484 struct dpu_merge_3d_cfg { 485 DPU_HW_BLK_INFO; 486 const struct dpu_merge_3d_sub_blks *sblk; 487 }; 488 489 /** 490 * struct dpu_dsc_cfg - information of DSC blocks 491 * @id enum identifying this block 492 * @base register offset of this block 493 * @len: length of hardware block 494 * @features bit mask identifying sub-blocks/features 495 * @sblk: sub-blocks information 496 */ 497 struct dpu_dsc_cfg { 498 DPU_HW_BLK_INFO; 499 unsigned long features; 500 const struct dpu_dsc_sub_blks *sblk; 501 }; 502 503 /** 504 * struct dpu_intf_cfg - information of timing engine blocks 505 * @id enum identifying this block 506 * @base register offset of this block 507 * @type: Interface type(DSI, DP, HDMI) 508 * @controller_id: Controller Instance ID in case of multiple of intf type 509 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 510 * @intr_underrun: index for INTF underrun interrupt 511 * @intr_vsync: index for INTF VSYNC interrupt 512 * @intr_tear_rd_ptr: Index for INTF TEAR_RD_PTR interrupt 513 */ 514 struct dpu_intf_cfg { 515 DPU_HW_BLK_INFO; 516 u32 type; /* interface type*/ 517 u32 controller_id; 518 u32 prog_fetch_lines_worst_case; 519 unsigned int intr_underrun; 520 unsigned int intr_vsync; 521 unsigned int intr_tear_rd_ptr; 522 }; 523 524 /** 525 * struct dpu_wb_cfg - information of writeback blocks 526 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 527 * @vbif_idx: vbif client index 528 * @maxlinewidth: max line width supported by writeback block 529 * @xin_id: bus client identifier 530 * @intr_wb_done: interrupt index for WB_DONE 531 * @format_list: list of formats supported by this writeback block 532 * @num_formats: number of formats supported by this writeback block 533 * @clk_ctrl: clock control identifier 534 */ 535 struct dpu_wb_cfg { 536 DPU_HW_BLK_INFO; 537 unsigned long features; 538 u8 vbif_idx; 539 u32 maxlinewidth; 540 u32 xin_id; 541 unsigned int intr_wb_done; 542 const u32 *format_list; 543 u32 num_formats; 544 enum dpu_clk_ctrl_type clk_ctrl; 545 }; 546 547 /* 548 * struct dpu_cwb_cfg : MDP CWB mux instance info 549 * @id: enum identifying this block 550 * @base: register base offset to mdss 551 * @features bit mask identifying sub-blocks/features 552 */ 553 struct dpu_cwb_cfg { 554 DPU_HW_BLK_INFO; 555 }; 556 557 /** 558 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 559 * @pps pixel per seconds 560 * @ot_limit OT limit to use up to specified pixel per second 561 */ 562 struct dpu_vbif_dynamic_ot_cfg { 563 u64 pps; 564 u32 ot_limit; 565 }; 566 567 /** 568 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 569 * @count length of cfg 570 * @cfg pointer to array of configuration settings with 571 * ascending requirements 572 */ 573 struct dpu_vbif_dynamic_ot_tbl { 574 u32 count; 575 const struct dpu_vbif_dynamic_ot_cfg *cfg; 576 }; 577 578 /** 579 * struct dpu_vbif_qos_tbl - QoS priority table 580 * @npriority_lvl num of priority level 581 * @priority_lvl pointer to array of priority level in ascending order 582 */ 583 struct dpu_vbif_qos_tbl { 584 u32 npriority_lvl; 585 const u32 *priority_lvl; 586 }; 587 588 /** 589 * struct dpu_vbif_cfg - information of VBIF blocks 590 * @id enum identifying this block 591 * @base register offset of this block 592 * @features bit mask identifying sub-blocks/features 593 * @ot_rd_limit default OT read limit 594 * @ot_wr_limit default OT write limit 595 * @xin_halt_timeout maximum time (in usec) for xin to halt 596 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 597 * @dynamic_ot_rd_tbl dynamic OT read configuration table 598 * @dynamic_ot_wr_tbl dynamic OT write configuration table 599 * @qos_rt_tbl real-time QoS priority table 600 * @qos_nrt_tbl non-real-time QoS priority table 601 * @memtype_count number of defined memtypes 602 * @memtype array of xin memtype definitions 603 */ 604 struct dpu_vbif_cfg { 605 DPU_HW_BLK_INFO; 606 unsigned long features; 607 u32 default_ot_rd_limit; 608 u32 default_ot_wr_limit; 609 u32 xin_halt_timeout; 610 u32 qos_rp_remap_size; 611 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 612 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 613 struct dpu_vbif_qos_tbl qos_rt_tbl; 614 struct dpu_vbif_qos_tbl qos_nrt_tbl; 615 u32 memtype_count; 616 u32 memtype[MAX_XIN_COUNT]; 617 }; 618 619 /** 620 * struct dpu_cdm_cfg - information of chroma down blocks 621 * @name string name for debug purposes 622 * @id enum identifying this block 623 * @base register offset of this block 624 */ 625 struct dpu_cdm_cfg { 626 DPU_HW_BLK_INFO; 627 }; 628 629 /** 630 * Define CDP use cases 631 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 632 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 633 */ 634 enum { 635 DPU_PERF_CDP_USAGE_RT, 636 DPU_PERF_CDP_USAGE_NRT, 637 DPU_PERF_CDP_USAGE_MAX 638 }; 639 640 /** 641 * struct dpu_perf_cdp_cfg - define CDP use case configuration 642 * @rd_enable: true if read pipe CDP is enabled 643 * @wr_enable: true if write pipe CDP is enabled 644 */ 645 struct dpu_perf_cdp_cfg { 646 bool rd_enable; 647 bool wr_enable; 648 }; 649 650 /** 651 * struct dpu_mdss_version - DPU's major and minor versions 652 * @core_major_ver: DPU core's major version 653 * @core_minor_ver: DPU core's minor version 654 */ 655 struct dpu_mdss_version { 656 u8 core_major_ver; 657 u8 core_minor_ver; 658 }; 659 660 /** 661 * struct dpu_perf_cfg - performance control settings 662 * @max_bw_low low threshold of maximum bandwidth (kbps) 663 * @max_bw_high high threshold of maximum bandwidth (kbps) 664 * @min_core_ib minimum bandwidth for core (kbps) 665 * @min_core_ib minimum mnoc ib vote in kbps 666 * @min_llcc_ib minimum llcc ib vote in kbps 667 * @min_dram_ib minimum dram ib vote in kbps 668 * @undersized_prefill_lines undersized prefill in lines 669 * @xtra_prefill_lines extra prefill latency in lines 670 * @dest_scale_prefill_lines destination scaler latency in lines 671 * @macrotile_perfill_lines macrotile latency in lines 672 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 673 * @linear_prefill_lines linear latency in lines 674 * @downscaling_prefill_lines downscaling latency in lines 675 * @amortizable_theshold minimum y position for traffic shaping prefill 676 * @min_prefill_lines minimum pipeline latency in lines 677 * @clk_inefficiency_factor DPU src clock inefficiency factor 678 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 679 * @safe_lut_tbl: LUT tables for safe signals 680 * @danger_lut_tbl: LUT tables for danger signals 681 * @qos_lut_tbl: LUT tables for QoS signals 682 * @cdp_cfg cdp use case configurations 683 */ 684 struct dpu_perf_cfg { 685 u32 max_bw_low; 686 u32 max_bw_high; 687 u32 min_core_ib; 688 u32 min_llcc_ib; 689 u32 min_dram_ib; 690 u32 undersized_prefill_lines; 691 u32 xtra_prefill_lines; 692 u32 dest_scale_prefill_lines; 693 u32 macrotile_prefill_lines; 694 u32 yuv_nv12_prefill_lines; 695 u32 linear_prefill_lines; 696 u32 downscaling_prefill_lines; 697 u32 amortizable_threshold; 698 u32 min_prefill_lines; 699 u32 clk_inefficiency_factor; 700 u32 bw_inefficiency_factor; 701 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 702 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 703 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 704 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 705 }; 706 707 /** 708 * struct dpu_mdss_cfg - information of MDSS HW 709 * This is the main catalog data structure representing 710 * this HW version. Contains dpu's major and minor versions, 711 * number of instances, register offsets, capabilities of the 712 * all MDSS HW sub-blocks. 713 * 714 * @dma_formats Supported formats for dma pipe 715 * @cursor_formats Supported formats for cursor pipe 716 * @vig_formats Supported formats for vig pipe 717 */ 718 struct dpu_mdss_cfg { 719 const struct dpu_mdss_version *mdss_ver; 720 721 const struct dpu_caps *caps; 722 723 const struct dpu_mdp_cfg *mdp; 724 725 u32 ctl_count; 726 const struct dpu_ctl_cfg *ctl; 727 728 u32 sspp_count; 729 const struct dpu_sspp_cfg *sspp; 730 731 u32 mixer_count; 732 const struct dpu_lm_cfg *mixer; 733 734 u32 pingpong_count; 735 const struct dpu_pingpong_cfg *pingpong; 736 737 u32 merge_3d_count; 738 const struct dpu_merge_3d_cfg *merge_3d; 739 740 u32 dsc_count; 741 const struct dpu_dsc_cfg *dsc; 742 743 u32 intf_count; 744 const struct dpu_intf_cfg *intf; 745 746 u32 vbif_count; 747 const struct dpu_vbif_cfg *vbif; 748 749 u32 wb_count; 750 const struct dpu_wb_cfg *wb; 751 752 const struct dpu_cdm_cfg *cdm; 753 754 u32 ad_count; 755 756 u32 dspp_count; 757 const struct dpu_dspp_cfg *dspp; 758 759 u32 cwb_count; 760 const struct dpu_cwb_cfg *cwb; 761 762 /* Add additional block data structures here */ 763 764 const struct dpu_perf_cfg *perf; 765 const struct dpu_format_extended *dma_formats; 766 const struct dpu_format_extended *cursor_formats; 767 const struct dpu_format_extended *vig_formats; 768 }; 769 770 extern const struct dpu_mdss_cfg dpu_glymur_cfg; 771 extern const struct dpu_mdss_cfg dpu_kaanapali_cfg; 772 extern const struct dpu_mdss_cfg dpu_msm8917_cfg; 773 extern const struct dpu_mdss_cfg dpu_msm8937_cfg; 774 extern const struct dpu_mdss_cfg dpu_msm8953_cfg; 775 extern const struct dpu_mdss_cfg dpu_msm8996_cfg; 776 extern const struct dpu_mdss_cfg dpu_msm8998_cfg; 777 extern const struct dpu_mdss_cfg dpu_sar2130p_cfg; 778 extern const struct dpu_mdss_cfg dpu_sdm630_cfg; 779 extern const struct dpu_mdss_cfg dpu_sdm660_cfg; 780 extern const struct dpu_mdss_cfg dpu_sdm845_cfg; 781 extern const struct dpu_mdss_cfg dpu_sdm670_cfg; 782 extern const struct dpu_mdss_cfg dpu_sm8150_cfg; 783 extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; 784 extern const struct dpu_mdss_cfg dpu_sm7150_cfg; 785 extern const struct dpu_mdss_cfg dpu_sm8250_cfg; 786 extern const struct dpu_mdss_cfg dpu_sc7180_cfg; 787 extern const struct dpu_mdss_cfg dpu_sm6115_cfg; 788 extern const struct dpu_mdss_cfg dpu_sm6125_cfg; 789 extern const struct dpu_mdss_cfg dpu_sm6150_cfg; 790 extern const struct dpu_mdss_cfg dpu_sm6350_cfg; 791 extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; 792 extern const struct dpu_mdss_cfg dpu_sm6375_cfg; 793 extern const struct dpu_mdss_cfg dpu_sm8350_cfg; 794 extern const struct dpu_mdss_cfg dpu_sc7280_cfg; 795 extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; 796 extern const struct dpu_mdss_cfg dpu_sm8450_cfg; 797 extern const struct dpu_mdss_cfg dpu_sa8775p_cfg; 798 extern const struct dpu_mdss_cfg dpu_sm8550_cfg; 799 extern const struct dpu_mdss_cfg dpu_sm8650_cfg; 800 extern const struct dpu_mdss_cfg dpu_sm8750_cfg; 801 extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; 802 803 #endif /* _DPU_HW_CATALOG_H */ 804