1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83TD510 PHY
3 * Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/ethtool_netlink.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/phy.h>
11
12 #define DP83TD510E_PHY_ID 0x20000181
13
14 /* MDIO_MMD_VEND2 registers */
15 #define DP83TD510E_PHY_STS 0x10
16 /* Bit 7 - mii_interrupt, active high. Clears on read.
17 * Note: Clearing does not necessarily deactivate IRQ pin if interrupts pending.
18 * This differs from the DP83TD510E datasheet (2020) which states this bit
19 * clears on write 0.
20 */
21 #define DP83TD510E_STS_MII_INT BIT(7)
22 #define DP83TD510E_LINK_STATUS BIT(0)
23
24 #define DP83TD510E_GEN_CFG 0x11
25 #define DP83TD510E_GENCFG_INT_POLARITY BIT(3)
26 #define DP83TD510E_GENCFG_INT_EN BIT(1)
27 #define DP83TD510E_GENCFG_INT_OE BIT(0)
28
29 #define DP83TD510E_INTERRUPT_REG_1 0x12
30 #define DP83TD510E_INT1_LINK BIT(13)
31 #define DP83TD510E_INT1_LINK_EN BIT(5)
32
33 #define DP83TD510E_CTRL 0x1f
34 #define DP83TD510E_CTRL_HW_RESET BIT(15)
35 #define DP83TD510E_CTRL_SW_RESET BIT(14)
36
37 /*
38 * DP83TD510E_PKT_STAT_x registers correspond to similarly named registers
39 * in the datasheet (PKT_STAT_1 through PKT_STAT_6). These registers store
40 * 32-bit or 16-bit counters for TX and RX statistics and must be read in
41 * sequence to ensure the counters are cleared correctly.
42 *
43 * - DP83TD510E_PKT_STAT_1: Contains TX packet count bits [15:0].
44 * - DP83TD510E_PKT_STAT_2: Contains TX packet count bits [31:16].
45 * - DP83TD510E_PKT_STAT_3: Contains TX error packet count.
46 * - DP83TD510E_PKT_STAT_4: Contains RX packet count bits [15:0].
47 * - DP83TD510E_PKT_STAT_5: Contains RX packet count bits [31:16].
48 * - DP83TD510E_PKT_STAT_6: Contains RX error packet count.
49 *
50 * Keeping the register names as defined in the datasheet helps maintain
51 * clarity and alignment with the documentation.
52 */
53 #define DP83TD510E_PKT_STAT_1 0x12b
54 #define DP83TD510E_PKT_STAT_2 0x12c
55 #define DP83TD510E_PKT_STAT_3 0x12d
56 #define DP83TD510E_PKT_STAT_4 0x12e
57 #define DP83TD510E_PKT_STAT_5 0x12f
58 #define DP83TD510E_PKT_STAT_6 0x130
59
60 #define DP83TD510E_AN_STAT_1 0x60c
61 #define DP83TD510E_MASTER_SLAVE_RESOL_FAIL BIT(15)
62
63 #define DP83TD510E_MSE_DETECT 0xa85
64
65 #define DP83TD510_SQI_MAX 7
66
67 /* Register values are converted to SNR(dB) as suggested by
68 * "Application Report - DP83TD510E Cable Diagnostics Toolkit":
69 * SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB.
70 * SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic
71 * features for 100BASE-T1 automotive Ethernet PHYs"
72 */
73 static const u16 dp83td510_mse_sqi_map[] = {
74 0x0569, /* < 18dB */
75 0x044c, /* 18dB =< SNR < 19dB */
76 0x0369, /* 19dB =< SNR < 20dB */
77 0x02b6, /* 20dB =< SNR < 21dB */
78 0x0227, /* 21dB =< SNR < 22dB */
79 0x01b6, /* 22dB =< SNR < 23dB */
80 0x015b, /* 23dB =< SNR < 24dB */
81 0x0000 /* 24dB =< SNR */
82 };
83
84 struct dp83td510_stats {
85 u64 tx_pkt_cnt;
86 u64 tx_err_pkt_cnt;
87 u64 rx_pkt_cnt;
88 u64 rx_err_pkt_cnt;
89 };
90
91 struct dp83td510_priv {
92 bool alcd_test_active;
93 struct dp83td510_stats stats;
94 };
95
96 /* Time Domain Reflectometry (TDR) Functionality of DP83TD510 PHY
97 *
98 * I assume that this PHY is using a variation of Spread Spectrum Time Domain
99 * Reflectometry (SSTDR) rather than the commonly used TDR found in many PHYs.
100 * Here are the following observations which likely confirm this:
101 * - The DP83TD510 PHY transmits a modulated signal of configurable length
102 * (default 16000 µs) instead of a single pulse pattern, which is typical
103 * for traditional TDR.
104 * - The pulse observed on the wire, triggered by the HW RESET register, is not
105 * part of the cable testing process.
106 *
107 * I assume that SSTDR seems to be a logical choice for the 10BaseT1L
108 * environment due to improved noise resistance, making it suitable for
109 * environments with significant electrical noise, such as long 10BaseT1L cable
110 * runs.
111 *
112 * Configuration Variables:
113 * The SSTDR variation used in this PHY involves more configuration variables
114 * that can dramatically affect the functionality and precision of cable
115 * testing. Since most of these configuration options are either not well
116 * documented or documented with minimal details, the following sections
117 * describe my understanding and observations of these variables and their
118 * impact on TDR functionality.
119 *
120 * Timeline:
121 * ,<--cfg_pre_silence_time
122 * | ,<-SSTDR Modulated Transmission
123 * | | ,<--cfg_post_silence_time
124 * | | | ,<--Force Link Mode
125 * |<--'-->|<-------'------->|<--'-->|<--------'------->|
126 *
127 * - cfg_pre_silence_time: Optional silence time before TDR transmission starts.
128 * - SSTDR Modulated Transmission: Transmission duration configured by
129 * cfg_tdr_tx_duration and amplitude configured by cfg_tdr_tx_type.
130 * - cfg_post_silence_time: Silence time after TDR transmission.
131 * - Force Link Mode: If nothing is configured after cfg_post_silence_time,
132 * the PHY continues in force link mode without autonegotiation.
133 */
134
135 #define DP83TD510E_TDR_CFG 0x1e
136 #define DP83TD510E_TDR_START BIT(15)
137 #define DP83TD510E_TDR_DONE BIT(1)
138 #define DP83TD510E_TDR_FAIL BIT(0)
139
140 #define DP83TD510E_TDR_CFG1 0x300
141 /* cfg_tdr_tx_type: Transmit voltage level for TDR.
142 * 0 = 1V, 1 = 2.4V
143 * Note: Using different voltage levels may not work
144 * in all configuration variations. For example, setting
145 * 2.4V may give different cable length measurements.
146 * Other settings may be needed to make it work properly.
147 */
148 #define DP83TD510E_TDR_TX_TYPE BIT(12)
149 #define DP83TD510E_TDR_TX_TYPE_1V 0
150 #define DP83TD510E_TDR_TX_TYPE_2_4V 1
151 /* cfg_post_silence_time: Time after the TDR sequence. Since we force master mode
152 * for the TDR will proceed with forced link state after this time. For Linux
153 * it is better to set max value to avoid false link state detection.
154 */
155 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME GENMASK(3, 2)
156 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_0MS 0
157 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_10MS 1
158 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_100MS 2
159 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS 3
160 /* cfg_pre_silence_time: Time before the TDR sequence. It should be enough to
161 * settle down all pulses and reflections. Since for 10BASE-T1L we have
162 * maximum 2000m cable length, we can set it to 1ms.
163 */
164 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME GENMASK(1, 0)
165 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_0MS 0
166 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS 1
167 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_100MS 2
168 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_1000MS 3
169
170 #define DP83TD510E_TDR_CFG2 0x301
171 #define DP83TD510E_TDR_END_TAP_INDEX_1 GENMASK(14, 8)
172 #define DP83TD510E_TDR_END_TAP_INDEX_1_DEF 36
173 #define DP83TD510E_TDR_START_TAP_INDEX_1 GENMASK(6, 0)
174 #define DP83TD510E_TDR_START_TAP_INDEX_1_DEF 4
175
176 #define DP83TD510E_TDR_CFG3 0x302
177 /* cfg_tdr_tx_duration: Duration of the TDR transmission in microseconds.
178 * This value sets the duration of the modulated signal used for TDR
179 * measurements.
180 * - Default: 16000 µs
181 * - Observation: A minimum duration of 6000 µs is recommended to ensure
182 * accurate detection of cable faults. Durations shorter than 6000 µs may
183 * result in incomplete data, especially for shorter cables (e.g., 20 meters),
184 * leading to false "OK" results. Longer durations (e.g., 6000 µs or more)
185 * provide better accuracy, particularly for detecting open circuits.
186 */
187 #define DP83TD510E_TDR_TX_DURATION_US GENMASK(15, 0)
188 #define DP83TD510E_TDR_TX_DURATION_US_DEF 16000
189
190 #define DP83TD510E_TDR_FAULT_CFG1 0x303
191 #define DP83TD510E_TDR_FLT_LOC_OFFSET_1 GENMASK(14, 8)
192 #define DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF 4
193 #define DP83TD510E_TDR_FLT_INIT_1 GENMASK(7, 0)
194 #define DP83TD510E_TDR_FLT_INIT_1_DEF 62
195
196 #define DP83TD510E_TDR_FAULT_STAT 0x30c
197 #define DP83TD510E_TDR_PEAK_DETECT BIT(11)
198 #define DP83TD510E_TDR_PEAK_SIGN BIT(10)
199 #define DP83TD510E_TDR_PEAK_LOCATION GENMASK(9, 0)
200
201 /* Not documented registers and values but recommended according to
202 * "DP83TD510E Cable Diagnostics Toolkit revC"
203 */
204 #define DP83TD510E_UNKN_030E 0x30e
205 #define DP83TD510E_030E_VAL 0x2520
206
207 #define DP83TD510E_LEDS_CFG_1 0x460
208 #define DP83TD510E_LED_FN(idx, val) (((val) & 0xf) << ((idx) * 4))
209 #define DP83TD510E_LED_FN_MASK(idx) (0xf << ((idx) * 4))
210 /* link OK */
211 #define DP83TD510E_LED_MODE_LINK_OK 0x0
212 /* TX/RX activity */
213 #define DP83TD510E_LED_MODE_TX_RX_ACTIVITY 0x1
214 /* TX activity */
215 #define DP83TD510E_LED_MODE_TX_ACTIVITY 0x2
216 /* RX activity */
217 #define DP83TD510E_LED_MODE_RX_ACTIVITY 0x3
218 /* LR */
219 #define DP83TD510E_LED_MODE_LR 0x4
220 /* SR */
221 #define DP83TD510E_LED_MODE_SR 0x5
222 /* LED SPEED: High for 10Base-T */
223 #define DP83TD510E_LED_MODE_LED_SPEED 0x6
224 /* Duplex mode */
225 #define DP83TD510E_LED_MODE_DUPLEX 0x7
226 /* link + blink on activity with stretch option */
227 #define DP83TD510E_LED_MODE_LINK_BLINK 0x8
228 /* blink on activity with stretch option */
229 #define DP83TD510E_LED_MODE_BLINK_ACTIVITY 0x9
230 /* blink on tx activity with stretch option */
231 #define DP83TD510E_LED_MODE_BLINK_TX 0xa
232 /* blink on rx activity with stretch option */
233 #define DP83TD510E_LED_MODE_BLINK_RX 0xb
234 /* link_lost */
235 #define DP83TD510E_LED_MODE_LINK_LOST 0xc
236 /* PRBS error: toggles on error */
237 #define DP83TD510E_LED_MODE_PRBS_ERROR 0xd
238 /* XMII TX/RX Error with stretch option */
239 #define DP83TD510E_LED_MODE_XMII_ERR 0xe
240
241 #define DP83TD510E_LED_COUNT 4
242
243 #define DP83TD510E_LEDS_CFG_2 0x469
244 #define DP83TD510E_LED_POLARITY(idx) BIT((idx) * 4 + 2)
245 #define DP83TD510E_LED_DRV_VAL(idx) BIT((idx) * 4 + 1)
246 #define DP83TD510E_LED_DRV_EN(idx) BIT((idx) * 4)
247
248 #define DP83TD510E_ALCD_STAT 0xa9f
249 #define DP83TD510E_ALCD_COMPLETE BIT(15)
250 #define DP83TD510E_ALCD_CABLE_LENGTH GENMASK(10, 0)
251
dp83td510_led_brightness_set(struct phy_device * phydev,u8 index,enum led_brightness brightness)252 static int dp83td510_led_brightness_set(struct phy_device *phydev, u8 index,
253 enum led_brightness brightness)
254 {
255 u32 val;
256
257 if (index >= DP83TD510E_LED_COUNT)
258 return -EINVAL;
259
260 val = DP83TD510E_LED_DRV_EN(index);
261
262 if (brightness)
263 val |= DP83TD510E_LED_DRV_VAL(index);
264
265 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2,
266 DP83TD510E_LED_DRV_VAL(index) |
267 DP83TD510E_LED_DRV_EN(index), val);
268 }
269
dp83td510_led_mode(u8 index,unsigned long rules)270 static int dp83td510_led_mode(u8 index, unsigned long rules)
271 {
272 if (index >= DP83TD510E_LED_COUNT)
273 return -EINVAL;
274
275 switch (rules) {
276 case BIT(TRIGGER_NETDEV_LINK):
277 return DP83TD510E_LED_MODE_LINK_OK;
278 case BIT(TRIGGER_NETDEV_LINK_10):
279 return DP83TD510E_LED_MODE_LED_SPEED;
280 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
281 return DP83TD510E_LED_MODE_DUPLEX;
282 case BIT(TRIGGER_NETDEV_TX):
283 return DP83TD510E_LED_MODE_TX_ACTIVITY;
284 case BIT(TRIGGER_NETDEV_RX):
285 return DP83TD510E_LED_MODE_RX_ACTIVITY;
286 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
287 return DP83TD510E_LED_MODE_TX_RX_ACTIVITY;
288 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
289 BIT(TRIGGER_NETDEV_RX):
290 return DP83TD510E_LED_MODE_LINK_BLINK;
291 default:
292 return -EOPNOTSUPP;
293 }
294 }
295
dp83td510_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)296 static int dp83td510_led_hw_is_supported(struct phy_device *phydev, u8 index,
297 unsigned long rules)
298 {
299 int ret;
300
301 ret = dp83td510_led_mode(index, rules);
302 if (ret < 0)
303 return ret;
304
305 return 0;
306 }
307
dp83td510_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)308 static int dp83td510_led_hw_control_set(struct phy_device *phydev, u8 index,
309 unsigned long rules)
310 {
311 int mode, ret;
312
313 mode = dp83td510_led_mode(index, rules);
314 if (mode < 0)
315 return mode;
316
317 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_1,
318 DP83TD510E_LED_FN_MASK(index),
319 DP83TD510E_LED_FN(index, mode));
320 if (ret)
321 return ret;
322
323 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2,
324 DP83TD510E_LED_DRV_EN(index), 0);
325 }
326
dp83td510_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)327 static int dp83td510_led_hw_control_get(struct phy_device *phydev,
328 u8 index, unsigned long *rules)
329 {
330 int val;
331
332 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_1);
333 if (val < 0)
334 return val;
335
336 val &= DP83TD510E_LED_FN_MASK(index);
337 val >>= index * 4;
338
339 switch (val) {
340 case DP83TD510E_LED_MODE_LINK_OK:
341 *rules = BIT(TRIGGER_NETDEV_LINK);
342 break;
343 /* LED mode: LED SPEED (10BaseT1L indicator) */
344 case DP83TD510E_LED_MODE_LED_SPEED:
345 *rules = BIT(TRIGGER_NETDEV_LINK_10);
346 break;
347 case DP83TD510E_LED_MODE_DUPLEX:
348 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
349 break;
350 case DP83TD510E_LED_MODE_TX_ACTIVITY:
351 *rules = BIT(TRIGGER_NETDEV_TX);
352 break;
353 case DP83TD510E_LED_MODE_RX_ACTIVITY:
354 *rules = BIT(TRIGGER_NETDEV_RX);
355 break;
356 case DP83TD510E_LED_MODE_TX_RX_ACTIVITY:
357 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
358 break;
359 case DP83TD510E_LED_MODE_LINK_BLINK:
360 *rules = BIT(TRIGGER_NETDEV_LINK) |
361 BIT(TRIGGER_NETDEV_TX) |
362 BIT(TRIGGER_NETDEV_RX);
363 break;
364 default:
365 *rules = 0;
366 break;
367 }
368
369 return 0;
370 }
371
dp83td510_led_polarity_set(struct phy_device * phydev,int index,unsigned long modes)372 static int dp83td510_led_polarity_set(struct phy_device *phydev, int index,
373 unsigned long modes)
374 {
375 u16 polarity = DP83TD510E_LED_POLARITY(index);
376 u32 mode;
377
378 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
379 switch (mode) {
380 case PHY_LED_ACTIVE_LOW:
381 polarity = 0;
382 break;
383 default:
384 return -EINVAL;
385 }
386 }
387
388 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2,
389 DP83TD510E_LED_POLARITY(index), polarity);
390 }
391
392 /**
393 * dp83td510_update_stats - Update the PHY statistics for the DP83TD510 PHY.
394 * @phydev: Pointer to the phy_device structure.
395 *
396 * The function reads the PHY statistics registers and updates the statistics
397 * structure.
398 *
399 * Returns: 0 on success or a negative error code on failure.
400 */
dp83td510_update_stats(struct phy_device * phydev)401 static int dp83td510_update_stats(struct phy_device *phydev)
402 {
403 struct dp83td510_priv *priv = phydev->priv;
404 u32 count;
405 int ret;
406
407 /* The DP83TD510E_PKT_STAT registers are divided into two groups:
408 * - Group 1 (TX stats): DP83TD510E_PKT_STAT_1 to DP83TD510E_PKT_STAT_3
409 * - Group 2 (RX stats): DP83TD510E_PKT_STAT_4 to DP83TD510E_PKT_STAT_6
410 *
411 * Registers in each group are cleared only after reading them in a
412 * plain sequence (e.g., 1, 2, 3 for Group 1 or 4, 5, 6 for Group 2).
413 * Any deviation from the sequence, such as reading 1, 2, 1, 2, 3, will
414 * prevent the group from being cleared. Additionally, the counters
415 * for a group are frozen as soon as the first register in that group
416 * is accessed.
417 */
418 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_1);
419 if (ret < 0)
420 return ret;
421 /* tx_pkt_cnt_15_0 */
422 count = ret;
423
424 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_2);
425 if (ret < 0)
426 return ret;
427 /* tx_pkt_cnt_31_16 */
428 count |= ret << 16;
429 priv->stats.tx_pkt_cnt += count;
430
431 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_3);
432 if (ret < 0)
433 return ret;
434 /* tx_err_pkt_cnt */
435 priv->stats.tx_err_pkt_cnt += ret;
436
437 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_4);
438 if (ret < 0)
439 return ret;
440 /* rx_pkt_cnt_15_0 */
441 count = ret;
442
443 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_5);
444 if (ret < 0)
445 return ret;
446 /* rx_pkt_cnt_31_16 */
447 count |= ret << 16;
448 priv->stats.rx_pkt_cnt += count;
449
450 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_6);
451 if (ret < 0)
452 return ret;
453 /* rx_err_pkt_cnt */
454 priv->stats.rx_err_pkt_cnt += ret;
455
456 return 0;
457 }
458
dp83td510_get_phy_stats(struct phy_device * phydev,struct ethtool_eth_phy_stats * eth_stats,struct ethtool_phy_stats * stats)459 static void dp83td510_get_phy_stats(struct phy_device *phydev,
460 struct ethtool_eth_phy_stats *eth_stats,
461 struct ethtool_phy_stats *stats)
462 {
463 struct dp83td510_priv *priv = phydev->priv;
464
465 stats->tx_packets = priv->stats.tx_pkt_cnt;
466 stats->tx_errors = priv->stats.tx_err_pkt_cnt;
467 stats->rx_packets = priv->stats.rx_pkt_cnt;
468 stats->rx_errors = priv->stats.rx_err_pkt_cnt;
469 }
470
dp83td510_config_intr(struct phy_device * phydev)471 static int dp83td510_config_intr(struct phy_device *phydev)
472 {
473 int ret;
474
475 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
476 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
477 DP83TD510E_INTERRUPT_REG_1,
478 DP83TD510E_INT1_LINK_EN);
479 if (ret)
480 return ret;
481
482 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
483 DP83TD510E_GEN_CFG,
484 DP83TD510E_GENCFG_INT_POLARITY |
485 DP83TD510E_GENCFG_INT_EN |
486 DP83TD510E_GENCFG_INT_OE);
487 } else {
488 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
489 DP83TD510E_INTERRUPT_REG_1, 0x0);
490 if (ret)
491 return ret;
492
493 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
494 DP83TD510E_GEN_CFG,
495 DP83TD510E_GENCFG_INT_EN);
496 if (ret)
497 return ret;
498 }
499
500 return ret;
501 }
502
dp83td510_handle_interrupt(struct phy_device * phydev)503 static irqreturn_t dp83td510_handle_interrupt(struct phy_device *phydev)
504 {
505 int ret;
506
507 /* Read the current enabled interrupts */
508 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1);
509 if (ret < 0) {
510 phy_error(phydev);
511 return IRQ_NONE;
512 } else if (!(ret & DP83TD510E_INT1_LINK_EN) ||
513 !(ret & DP83TD510E_INT1_LINK)) {
514 return IRQ_NONE;
515 }
516
517 phy_trigger_machine(phydev);
518
519 return IRQ_HANDLED;
520 }
521
dp83td510_read_status(struct phy_device * phydev)522 static int dp83td510_read_status(struct phy_device *phydev)
523 {
524 u16 phy_sts;
525 int ret;
526
527 phydev->speed = SPEED_UNKNOWN;
528 phydev->duplex = DUPLEX_UNKNOWN;
529 phydev->pause = 0;
530 phydev->asym_pause = 0;
531 linkmode_zero(phydev->lp_advertising);
532
533 phy_sts = phy_read(phydev, DP83TD510E_PHY_STS);
534
535 phydev->link = !!(phy_sts & DP83TD510E_LINK_STATUS);
536 if (phydev->link) {
537 /* This PHY supports only one link mode: 10BaseT1L_Full */
538 phydev->duplex = DUPLEX_FULL;
539 phydev->speed = SPEED_10;
540
541 if (phydev->autoneg == AUTONEG_ENABLE) {
542 ret = genphy_c45_read_lpa(phydev);
543 if (ret)
544 return ret;
545
546 phy_resolve_aneg_linkmode(phydev);
547 }
548 }
549
550 if (phydev->autoneg == AUTONEG_ENABLE) {
551 ret = genphy_c45_baset1_read_status(phydev);
552 if (ret < 0)
553 return ret;
554
555 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
556 DP83TD510E_AN_STAT_1);
557 if (ret < 0)
558 return ret;
559
560 if (ret & DP83TD510E_MASTER_SLAVE_RESOL_FAIL)
561 phydev->master_slave_state = MASTER_SLAVE_STATE_ERR;
562 } else {
563 return genphy_c45_pma_baset1_read_master_slave(phydev);
564 }
565
566 return 0;
567 }
568
dp83td510_config_aneg(struct phy_device * phydev)569 static int dp83td510_config_aneg(struct phy_device *phydev)
570 {
571 bool changed = false;
572 int ret;
573
574 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
575 if (ret < 0)
576 return ret;
577
578 if (phydev->autoneg == AUTONEG_DISABLE)
579 return genphy_c45_an_disable_aneg(phydev);
580
581 ret = genphy_c45_an_config_aneg(phydev);
582 if (ret < 0)
583 return ret;
584 if (ret > 0)
585 changed = true;
586
587 return genphy_c45_check_and_restart_aneg(phydev, changed);
588 }
589
dp83td510_get_sqi(struct phy_device * phydev)590 static int dp83td510_get_sqi(struct phy_device *phydev)
591 {
592 int sqi, ret;
593 u16 mse_val;
594
595 if (!phydev->link)
596 return 0;
597
598 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT);
599 if (ret < 0)
600 return ret;
601
602 mse_val = 0xFFFF & ret;
603 for (sqi = 0; sqi < ARRAY_SIZE(dp83td510_mse_sqi_map); sqi++) {
604 if (mse_val >= dp83td510_mse_sqi_map[sqi])
605 return sqi;
606 }
607
608 return -EINVAL;
609 }
610
dp83td510_get_sqi_max(struct phy_device * phydev)611 static int dp83td510_get_sqi_max(struct phy_device *phydev)
612 {
613 return DP83TD510_SQI_MAX;
614 }
615
616 /**
617 * dp83td510_cable_test_start - Start the cable test for the DP83TD510 PHY.
618 * @phydev: Pointer to the phy_device structure.
619 *
620 * This sequence is implemented according to the "Application Note DP83TD510E
621 * Cable Diagnostics Toolkit revC".
622 *
623 * Returns: 0 on success, a negative error code on failure.
624 */
dp83td510_cable_test_start(struct phy_device * phydev)625 static int dp83td510_cable_test_start(struct phy_device *phydev)
626 {
627 struct dp83td510_priv *priv = phydev->priv;
628 int ret;
629
630 /* If link partner is active, we won't be able to use TDR, since
631 * we can't force link partner to be silent. The autonegotiation
632 * pulses will be too frequent and the TDR sequence will be
633 * too long. So, TDR will always fail. Since the link is established
634 * we already know that the cable is working, so we can get some
635 * extra information line the cable length using ALCD.
636 */
637 if (phydev->link) {
638 priv->alcd_test_active = true;
639 return 0;
640 }
641
642 priv->alcd_test_active = false;
643
644 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
645 DP83TD510E_CTRL_HW_RESET);
646 if (ret)
647 return ret;
648
649 ret = genphy_c45_an_disable_aneg(phydev);
650 if (ret)
651 return ret;
652
653 /* Force master mode */
654 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
655 MDIO_PMA_PMD_BT1_CTRL_CFG_MST);
656 if (ret)
657 return ret;
658
659 /* There is no official recommendation for this register, but it is
660 * better to use 1V for TDR since other values seems to be optimized
661 * for this amplitude. Except of amplitude, it is better to configure
662 * pre TDR silence time to 10ms to avoid false reflections (value 0
663 * seems to be too short, otherwise we need to implement own silence
664 * time). Also, post TDR silence time should be set to 1000ms to avoid
665 * false link state detection, it fits to the polling time of the
666 * PHY framework. The idea is to wait until
667 * dp83td510_cable_test_get_status() will be called and reconfigure
668 * the PHY to the default state within the post silence time window.
669 */
670 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG1,
671 DP83TD510E_TDR_TX_TYPE |
672 DP83TD510E_TDR_CFG1_POST_SILENCE_TIME |
673 DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME,
674 DP83TD510E_TDR_TX_TYPE_1V |
675 DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS |
676 DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS);
677 if (ret)
678 return ret;
679
680 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2,
681 FIELD_PREP(DP83TD510E_TDR_END_TAP_INDEX_1,
682 DP83TD510E_TDR_END_TAP_INDEX_1_DEF) |
683 FIELD_PREP(DP83TD510E_TDR_START_TAP_INDEX_1,
684 DP83TD510E_TDR_START_TAP_INDEX_1_DEF));
685 if (ret)
686 return ret;
687
688 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_FAULT_CFG1,
689 FIELD_PREP(DP83TD510E_TDR_FLT_LOC_OFFSET_1,
690 DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF) |
691 FIELD_PREP(DP83TD510E_TDR_FLT_INIT_1,
692 DP83TD510E_TDR_FLT_INIT_1_DEF));
693 if (ret)
694 return ret;
695
696 /* Undocumented register, from the "Application Note DP83TD510E Cable
697 * Diagnostics Toolkit revC".
698 */
699 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_UNKN_030E,
700 DP83TD510E_030E_VAL);
701 if (ret)
702 return ret;
703
704 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG3,
705 DP83TD510E_TDR_TX_DURATION_US_DEF);
706 if (ret)
707 return ret;
708
709 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
710 DP83TD510E_CTRL_SW_RESET);
711 if (ret)
712 return ret;
713
714 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG,
715 DP83TD510E_TDR_START);
716 }
717
718 /**
719 * dp83td510_cable_test_get_tdr_status - Get the status of the TDR test for the
720 * DP83TD510 PHY.
721 * @phydev: Pointer to the phy_device structure.
722 * @finished: Pointer to a boolean that indicates whether the test is finished.
723 *
724 * The function sets the @finished flag to true if the test is complete.
725 *
726 * Returns: 0 on success or a negative error code on failure.
727 */
dp83td510_cable_test_get_tdr_status(struct phy_device * phydev,bool * finished)728 static int dp83td510_cable_test_get_tdr_status(struct phy_device *phydev,
729 bool *finished)
730 {
731 int ret, stat;
732
733 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG);
734 if (ret < 0)
735 return ret;
736
737 if (!(ret & DP83TD510E_TDR_DONE))
738 return 0;
739
740 if (!(ret & DP83TD510E_TDR_FAIL)) {
741 int location;
742
743 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
744 DP83TD510E_TDR_FAULT_STAT);
745 if (ret < 0)
746 return ret;
747
748 if (ret & DP83TD510E_TDR_PEAK_DETECT) {
749 if (ret & DP83TD510E_TDR_PEAK_SIGN)
750 stat = ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
751 else
752 stat = ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
753
754 location = FIELD_GET(DP83TD510E_TDR_PEAK_LOCATION,
755 ret) * 100;
756 ethnl_cable_test_fault_length(phydev,
757 ETHTOOL_A_CABLE_PAIR_A,
758 location);
759 } else {
760 stat = ETHTOOL_A_CABLE_RESULT_CODE_OK;
761 }
762 } else {
763 /* Most probably we have active link partner */
764 stat = ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
765 }
766
767 *finished = true;
768
769 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, stat);
770
771 return phy_init_hw(phydev);
772 }
773
774 /**
775 * dp83td510_cable_test_get_alcd_status - Get the status of the ALCD test for the
776 * DP83TD510 PHY.
777 * @phydev: Pointer to the phy_device structure.
778 * @finished: Pointer to a boolean that indicates whether the test is finished.
779 *
780 * The function sets the @finished flag to true if the test is complete.
781 * The function reads the cable length and reports it to the user.
782 *
783 * Returns: 0 on success or a negative error code on failure.
784 */
dp83td510_cable_test_get_alcd_status(struct phy_device * phydev,bool * finished)785 static int dp83td510_cable_test_get_alcd_status(struct phy_device *phydev,
786 bool *finished)
787 {
788 unsigned int location;
789 int ret, phy_sts;
790
791 phy_sts = phy_read(phydev, DP83TD510E_PHY_STS);
792
793 if (!(phy_sts & DP83TD510E_LINK_STATUS)) {
794 /* If the link is down, we can't do any thing usable now */
795 ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
796 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC,
797 ETHTOOL_A_CABLE_INF_SRC_ALCD);
798 *finished = true;
799 return 0;
800 }
801
802 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_ALCD_STAT);
803 if (ret < 0)
804 return ret;
805
806 if (!(ret & DP83TD510E_ALCD_COMPLETE))
807 return 0;
808
809 location = FIELD_GET(DP83TD510E_ALCD_CABLE_LENGTH, ret) * 100;
810
811 ethnl_cable_test_fault_length_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
812 location,
813 ETHTOOL_A_CABLE_INF_SRC_ALCD);
814
815 ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
816 ETHTOOL_A_CABLE_RESULT_CODE_OK,
817 ETHTOOL_A_CABLE_INF_SRC_ALCD);
818 *finished = true;
819
820 return 0;
821 }
822
823 /**
824 * dp83td510_cable_test_get_status - Get the status of the cable test for the
825 * DP83TD510 PHY.
826 * @phydev: Pointer to the phy_device structure.
827 * @finished: Pointer to a boolean that indicates whether the test is finished.
828 *
829 * The function sets the @finished flag to true if the test is complete.
830 *
831 * Returns: 0 on success or a negative error code on failure.
832 */
dp83td510_cable_test_get_status(struct phy_device * phydev,bool * finished)833 static int dp83td510_cable_test_get_status(struct phy_device *phydev,
834 bool *finished)
835 {
836 struct dp83td510_priv *priv = phydev->priv;
837 *finished = false;
838
839 if (priv->alcd_test_active)
840 return dp83td510_cable_test_get_alcd_status(phydev, finished);
841
842 return dp83td510_cable_test_get_tdr_status(phydev, finished);
843 }
844
dp83td510_get_features(struct phy_device * phydev)845 static int dp83td510_get_features(struct phy_device *phydev)
846 {
847 /* This PHY can't respond on MDIO bus if no RMII clock is enabled.
848 * In case RMII mode is used (most meaningful mode for this PHY) and
849 * the PHY do not have own XTAL, and CLK providing MAC is not probed,
850 * we won't be able to read all needed ability registers.
851 * So provide it manually.
852 */
853
854 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
855 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
856 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
857 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
858 phydev->supported);
859
860 return 0;
861 }
862
dp83td510_probe(struct phy_device * phydev)863 static int dp83td510_probe(struct phy_device *phydev)
864 {
865 struct device *dev = &phydev->mdio.dev;
866 struct dp83td510_priv *priv;
867
868 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
869 if (!priv)
870 return -ENOMEM;
871
872 phydev->priv = priv;
873
874 return 0;
875 }
876
877 static struct phy_driver dp83td510_driver[] = {
878 {
879 PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID),
880 .name = "TI DP83TD510E",
881
882 .flags = PHY_POLL_CABLE_TEST,
883 .probe = dp83td510_probe,
884 .config_aneg = dp83td510_config_aneg,
885 .read_status = dp83td510_read_status,
886 .get_features = dp83td510_get_features,
887 .config_intr = dp83td510_config_intr,
888 .handle_interrupt = dp83td510_handle_interrupt,
889 .get_sqi = dp83td510_get_sqi,
890 .get_sqi_max = dp83td510_get_sqi_max,
891 .cable_test_start = dp83td510_cable_test_start,
892 .cable_test_get_status = dp83td510_cable_test_get_status,
893 .get_phy_stats = dp83td510_get_phy_stats,
894 .update_stats = dp83td510_update_stats,
895
896 .led_brightness_set = dp83td510_led_brightness_set,
897 .led_hw_is_supported = dp83td510_led_hw_is_supported,
898 .led_hw_control_set = dp83td510_led_hw_control_set,
899 .led_hw_control_get = dp83td510_led_hw_control_get,
900 .led_polarity_set = dp83td510_led_polarity_set,
901
902 .suspend = genphy_suspend,
903 .resume = genphy_resume,
904 } };
905 module_phy_driver(dp83td510_driver);
906
907 static const struct mdio_device_id __maybe_unused dp83td510_tbl[] = {
908 { PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) },
909 { }
910 };
911 MODULE_DEVICE_TABLE(mdio, dp83td510_tbl);
912
913 MODULE_DESCRIPTION("Texas Instruments DP83TD510E PHY driver");
914 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
915 MODULE_LICENSE("GPL v2");
916