1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
3 *
4 * Copyright (C) 2017 Texas Instruments Inc.
5 */
6
7 #include <linux/ethtool.h>
8 #include <linux/etherdevice.h>
9 #include <linux/kernel.h>
10 #include <linux/mii.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/phy.h>
14 #include <linux/netdevice.h>
15 #include <linux/bitfield.h>
16
17 #define DP83822_PHY_ID 0x2000a240
18 #define DP83825S_PHY_ID 0x2000a140
19 #define DP83825I_PHY_ID 0x2000a150
20 #define DP83825CM_PHY_ID 0x2000a160
21 #define DP83825CS_PHY_ID 0x2000a170
22 #define DP83826C_PHY_ID 0x2000a130
23 #define DP83826NC_PHY_ID 0x2000a110
24
25 #define MII_DP83822_CTRL_2 0x0a
26 #define MII_DP83822_PHYSTS 0x10
27 #define MII_DP83822_PHYSCR 0x11
28 #define MII_DP83822_MISR1 0x12
29 #define MII_DP83822_MISR2 0x13
30 #define MII_DP83822_FCSCR 0x14
31 #define MII_DP83822_RCSR 0x17
32 #define MII_DP83822_RESET_CTRL 0x1f
33 #define MII_DP83822_MLEDCR 0x25
34 #define MII_DP83822_LDCTRL 0x403
35 #define MII_DP83822_LEDCFG1 0x460
36 #define MII_DP83822_IOCTRL 0x461
37 #define MII_DP83822_IOCTRL1 0x462
38 #define MII_DP83822_IOCTRL2 0x463
39 #define MII_DP83822_GENCFG 0x465
40 #define MII_DP83822_SOR1 0x467
41
42 /* DP83826 specific registers */
43 #define MII_DP83826_VOD_CFG1 0x30b
44 #define MII_DP83826_VOD_CFG2 0x30c
45
46 /* GENCFG */
47 #define DP83822_SIG_DET_LOW BIT(0)
48
49 /* Control Register 2 bits */
50 #define DP83822_FX_ENABLE BIT(14)
51
52 #define DP83822_SW_RESET BIT(15)
53 #define DP83822_DIG_RESTART BIT(14)
54
55 /* PHY STS bits */
56 #define DP83822_PHYSTS_DUPLEX BIT(2)
57 #define DP83822_PHYSTS_10 BIT(1)
58 #define DP83822_PHYSTS_LINK BIT(0)
59
60 /* PHYSCR Register Fields */
61 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
62 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
63
64 /* MISR1 bits */
65 #define DP83822_RX_ERR_HF_INT_EN BIT(0)
66 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
67 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2)
68 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3)
69 #define DP83822_SPEED_CHANGED_INT_EN BIT(4)
70 #define DP83822_LINK_STAT_INT_EN BIT(5)
71 #define DP83822_ENERGY_DET_INT_EN BIT(6)
72 #define DP83822_LINK_QUAL_INT_EN BIT(7)
73
74 /* MISR2 bits */
75 #define DP83822_JABBER_DET_INT_EN BIT(0)
76 #define DP83822_WOL_PKT_INT_EN BIT(1)
77 #define DP83822_SLEEP_MODE_INT_EN BIT(2)
78 #define DP83822_MDI_XOVER_INT_EN BIT(3)
79 #define DP83822_LB_FIFO_INT_EN BIT(4)
80 #define DP83822_PAGE_RX_INT_EN BIT(5)
81 #define DP83822_ANEG_ERR_INT_EN BIT(6)
82 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
83
84 /* INT_STAT1 bits */
85 #define DP83822_WOL_INT_EN BIT(4)
86 #define DP83822_WOL_INT_STAT BIT(12)
87
88 #define MII_DP83822_RXSOP1 0x04a5
89 #define MII_DP83822_RXSOP2 0x04a6
90 #define MII_DP83822_RXSOP3 0x04a7
91
92 /* WoL Registers */
93 #define MII_DP83822_WOL_CFG 0x04a0
94 #define MII_DP83822_WOL_STAT 0x04a1
95 #define MII_DP83822_WOL_DA1 0x04a2
96 #define MII_DP83822_WOL_DA2 0x04a3
97 #define MII_DP83822_WOL_DA3 0x04a4
98
99 /* WoL bits */
100 #define DP83822_WOL_MAGIC_EN BIT(0)
101 #define DP83822_WOL_SECURE_ON BIT(5)
102 #define DP83822_WOL_EN BIT(7)
103 #define DP83822_WOL_INDICATION_SEL BIT(8)
104 #define DP83822_WOL_CLR_INDICATION BIT(11)
105
106 /* RCSR bits */
107 #define DP83822_RMII_MODE_EN BIT(5)
108 #define DP83822_RMII_MODE_SEL BIT(7)
109 #define DP83822_RGMII_MODE_EN BIT(9)
110 #define DP83822_RX_CLK_SHIFT BIT(12)
111 #define DP83822_TX_CLK_SHIFT BIT(11)
112
113 /* MLEDCR bits */
114 #define DP83822_MLEDCR_CFG GENMASK(6, 3)
115 #define DP83822_MLEDCR_ROUTE GENMASK(1, 0)
116 #define DP83822_MLEDCR_ROUTE_LED_0 DP83822_MLEDCR_ROUTE
117
118 /* LEDCFG1 bits */
119 #define DP83822_LEDCFG1_LED1_CTRL GENMASK(11, 8)
120 #define DP83822_LEDCFG1_LED3_CTRL GENMASK(7, 4)
121
122 /* IOCTRL bits */
123 #define DP83822_IOCTRL_MAC_IMPEDANCE_CTRL GENMASK(4, 1)
124
125 /* IOCTRL1 bits */
126 #define DP83822_IOCTRL1_GPIO3_CTRL GENMASK(10, 8)
127 #define DP83822_IOCTRL1_GPIO3_CTRL_LED3 BIT(0)
128 #define DP83822_IOCTRL1_GPIO1_CTRL GENMASK(2, 0)
129 #define DP83822_IOCTRL1_GPIO1_CTRL_LED_1 BIT(0)
130
131 /* LDCTRL bits */
132 #define DP83822_100BASE_TX_LINE_DRIVER_SWING GENMASK(7, 4)
133
134 /* IOCTRL2 bits */
135 #define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4)
136 #define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0)
137 #define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0)
138 #define DP83822_IOCTRL2_GPIO2_CTRL_MLED BIT(0)
139
140 #define DP83822_CLK_SRC_MAC_IF 0x0
141 #define DP83822_CLK_SRC_XI 0x1
142 #define DP83822_CLK_SRC_INT_REF 0x2
143 #define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4
144 #define DP83822_CLK_SRC_FREE_RUNNING 0x6
145 #define DP83822_CLK_SRC_RECOVERED 0x7
146
147 #define DP83822_LED_FN_LINK 0x0 /* Link established */
148 #define DP83822_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */
149 #define DP83822_LED_FN_TX 0x2 /* Transmit activity */
150 #define DP83822_LED_FN_RX 0x3 /* Receive activity */
151 #define DP83822_LED_FN_COLLISION 0x4 /* Collision detected */
152 #define DP83822_LED_FN_LINK_100_BTX 0x5 /* 100 BTX link established */
153 #define DP83822_LED_FN_LINK_10_BT 0x6 /* 10BT link established */
154 #define DP83822_LED_FN_FULL_DUPLEX 0x7 /* Full duplex */
155 #define DP83822_LED_FN_LINK_RX_TX 0x8 /* Link established, blink for rx or tx activity */
156 #define DP83822_LED_FN_ACTIVE_STRETCH 0x9 /* Active Stretch Signal */
157 #define DP83822_LED_FN_MII_LINK 0xa /* MII LINK (100BT+FD) */
158 #define DP83822_LED_FN_LPI_MODE 0xb /* LPI Mode (EEE) */
159 #define DP83822_LED_FN_RX_TX_ERR 0xc /* TX/RX MII Error */
160 #define DP83822_LED_FN_LINK_LOST 0xd /* Link Lost */
161 #define DP83822_LED_FN_PRBS_ERR 0xe /* Blink for PRBS error */
162
163 /* SOR1 mode */
164 #define DP83822_STRAP_MODE1 0
165 #define DP83822_STRAP_MODE2 BIT(0)
166 #define DP83822_STRAP_MODE3 BIT(1)
167 #define DP83822_STRAP_MODE4 GENMASK(1, 0)
168
169 #define DP83822_COL_STRAP_MASK GENMASK(11, 10)
170 #define DP83822_COL_SHIFT 10
171 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8)
172 #define DP83822_RX_ER_SHIFT 8
173
174 /* DP83826: VOD_CFG1 & VOD_CFG2 */
175 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12)
176 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6)
177 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12)
178 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6)
179 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0)
180 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4)
181 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0)
182 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625
183 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000
184 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30
185 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10
186
187 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \
188 ADVERTISED_FIBRE | \
189 ADVERTISED_Pause | ADVERTISED_Asym_Pause)
190
191 #define DP83822_MAX_LED_PINS 4
192
193 #define DP83822_LED_INDEX_LED_0 0
194 #define DP83822_LED_INDEX_LED_1_GPIO1 1
195 #define DP83822_LED_INDEX_COL_GPIO2 2
196 #define DP83822_LED_INDEX_RX_D3_GPIO3 3
197
198 struct dp83822_private {
199 bool fx_signal_det_low;
200 int fx_enabled;
201 u16 fx_sd_enable;
202 u8 cfg_dac_minus;
203 u8 cfg_dac_plus;
204 struct ethtool_wolinfo wol;
205 bool set_gpio2_clk_out;
206 u32 gpio2_clk_out;
207 bool led_pin_enable[DP83822_MAX_LED_PINS];
208 int tx_amplitude_100base_tx_index;
209 int mac_termination_index;
210 };
211
dp83822_config_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)212 static int dp83822_config_wol(struct phy_device *phydev,
213 struct ethtool_wolinfo *wol)
214 {
215 struct net_device *ndev = phydev->attached_dev;
216 u16 value;
217 const u8 *mac;
218
219 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
220 mac = (const u8 *)ndev->dev_addr;
221
222 if (!is_valid_ether_addr(mac))
223 return -EINVAL;
224
225 /* MAC addresses start with byte 5, but stored in mac[0].
226 * 822 PHYs store bytes 4|5, 2|3, 0|1
227 */
228 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1,
229 (mac[1] << 8) | mac[0]);
230 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2,
231 (mac[3] << 8) | mac[2]);
232 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3,
233 (mac[5] << 8) | mac[4]);
234
235 value = phy_read_mmd(phydev, MDIO_MMD_VEND2,
236 MII_DP83822_WOL_CFG);
237 if (wol->wolopts & WAKE_MAGIC)
238 value |= DP83822_WOL_MAGIC_EN;
239 else
240 value &= ~DP83822_WOL_MAGIC_EN;
241
242 if (wol->wolopts & WAKE_MAGICSECURE) {
243 phy_write_mmd(phydev, MDIO_MMD_VEND2,
244 MII_DP83822_RXSOP1,
245 (wol->sopass[1] << 8) | wol->sopass[0]);
246 phy_write_mmd(phydev, MDIO_MMD_VEND2,
247 MII_DP83822_RXSOP2,
248 (wol->sopass[3] << 8) | wol->sopass[2]);
249 phy_write_mmd(phydev, MDIO_MMD_VEND2,
250 MII_DP83822_RXSOP3,
251 (wol->sopass[5] << 8) | wol->sopass[4]);
252 value |= DP83822_WOL_SECURE_ON;
253 } else {
254 value &= ~DP83822_WOL_SECURE_ON;
255 }
256
257 /* Clear any pending WoL interrupt */
258 phy_read(phydev, MII_DP83822_MISR2);
259
260 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
261 DP83822_WOL_CLR_INDICATION;
262
263 return phy_write_mmd(phydev, MDIO_MMD_VEND2,
264 MII_DP83822_WOL_CFG, value);
265 } else {
266 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
267 MII_DP83822_WOL_CFG,
268 DP83822_WOL_EN |
269 DP83822_WOL_MAGIC_EN |
270 DP83822_WOL_SECURE_ON);
271 }
272 }
273
dp83822_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)274 static int dp83822_set_wol(struct phy_device *phydev,
275 struct ethtool_wolinfo *wol)
276 {
277 struct dp83822_private *dp83822 = phydev->priv;
278 int ret;
279
280 ret = dp83822_config_wol(phydev, wol);
281 if (!ret)
282 memcpy(&dp83822->wol, wol, sizeof(*wol));
283 return ret;
284 }
285
dp83822_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)286 static void dp83822_get_wol(struct phy_device *phydev,
287 struct ethtool_wolinfo *wol)
288 {
289 int value;
290 u16 sopass_val;
291
292 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
293 wol->wolopts = 0;
294
295 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
296
297 if (value & DP83822_WOL_MAGIC_EN)
298 wol->wolopts |= WAKE_MAGIC;
299
300 if (value & DP83822_WOL_SECURE_ON) {
301 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
302 MII_DP83822_RXSOP1);
303 wol->sopass[0] = (sopass_val & 0xff);
304 wol->sopass[1] = (sopass_val >> 8);
305
306 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
307 MII_DP83822_RXSOP2);
308 wol->sopass[2] = (sopass_val & 0xff);
309 wol->sopass[3] = (sopass_val >> 8);
310
311 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
312 MII_DP83822_RXSOP3);
313 wol->sopass[4] = (sopass_val & 0xff);
314 wol->sopass[5] = (sopass_val >> 8);
315
316 wol->wolopts |= WAKE_MAGICSECURE;
317 }
318
319 /* WoL is not enabled so set wolopts to 0 */
320 if (!(value & DP83822_WOL_EN))
321 wol->wolopts = 0;
322 }
323
dp83822_config_intr(struct phy_device * phydev)324 static int dp83822_config_intr(struct phy_device *phydev)
325 {
326 struct dp83822_private *dp83822 = phydev->priv;
327 int misr_status;
328 int physcr_status;
329 int err;
330
331 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
332 misr_status = phy_read(phydev, MII_DP83822_MISR1);
333 if (misr_status < 0)
334 return misr_status;
335
336 misr_status |= (DP83822_LINK_STAT_INT_EN |
337 DP83822_ENERGY_DET_INT_EN |
338 DP83822_LINK_QUAL_INT_EN);
339
340 if (!dp83822->fx_enabled)
341 misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
342 DP83822_DUP_MODE_CHANGE_INT_EN |
343 DP83822_SPEED_CHANGED_INT_EN;
344
345
346 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
347 if (err < 0)
348 return err;
349
350 misr_status = phy_read(phydev, MII_DP83822_MISR2);
351 if (misr_status < 0)
352 return misr_status;
353
354 misr_status |= (DP83822_JABBER_DET_INT_EN |
355 DP83822_SLEEP_MODE_INT_EN |
356 DP83822_LB_FIFO_INT_EN |
357 DP83822_PAGE_RX_INT_EN |
358 DP83822_EEE_ERROR_CHANGE_INT_EN);
359
360 if (!dp83822->fx_enabled)
361 misr_status |= DP83822_ANEG_ERR_INT_EN |
362 DP83822_WOL_PKT_INT_EN;
363
364 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
365 if (err < 0)
366 return err;
367
368 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
369 if (physcr_status < 0)
370 return physcr_status;
371
372 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
373
374 } else {
375 err = phy_write(phydev, MII_DP83822_MISR1, 0);
376 if (err < 0)
377 return err;
378
379 err = phy_write(phydev, MII_DP83822_MISR2, 0);
380 if (err < 0)
381 return err;
382
383 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
384 if (physcr_status < 0)
385 return physcr_status;
386
387 physcr_status &= ~DP83822_PHYSCR_INTEN;
388 }
389
390 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
391 }
392
dp83822_handle_interrupt(struct phy_device * phydev)393 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
394 {
395 bool trigger_machine = false;
396 int irq_status;
397
398 /* The MISR1 and MISR2 registers are holding the interrupt status in
399 * the upper half (15:8), while the lower half (7:0) is used for
400 * controlling the interrupt enable state of those individual interrupt
401 * sources. To determine the possible interrupt sources, just read the
402 * MISR* register and use it directly to know which interrupts have
403 * been enabled previously or not.
404 */
405 irq_status = phy_read(phydev, MII_DP83822_MISR1);
406 if (irq_status < 0) {
407 phy_error(phydev);
408 return IRQ_NONE;
409 }
410 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
411 trigger_machine = true;
412
413 irq_status = phy_read(phydev, MII_DP83822_MISR2);
414 if (irq_status < 0) {
415 phy_error(phydev);
416 return IRQ_NONE;
417 }
418 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
419 trigger_machine = true;
420
421 if (!trigger_machine)
422 return IRQ_NONE;
423
424 phy_trigger_machine(phydev);
425
426 return IRQ_HANDLED;
427 }
428
dp83822_read_status(struct phy_device * phydev)429 static int dp83822_read_status(struct phy_device *phydev)
430 {
431 struct dp83822_private *dp83822 = phydev->priv;
432 int status = phy_read(phydev, MII_DP83822_PHYSTS);
433 int ctrl2;
434 int ret;
435
436 if (dp83822->fx_enabled) {
437 if (status & DP83822_PHYSTS_LINK) {
438 phydev->speed = SPEED_UNKNOWN;
439 phydev->duplex = DUPLEX_UNKNOWN;
440 } else {
441 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
442 if (ctrl2 < 0)
443 return ctrl2;
444
445 if (!(ctrl2 & DP83822_FX_ENABLE)) {
446 ret = phy_write(phydev, MII_DP83822_CTRL_2,
447 DP83822_FX_ENABLE | ctrl2);
448 if (ret < 0)
449 return ret;
450 }
451 }
452 }
453
454 ret = genphy_read_status(phydev);
455 if (ret)
456 return ret;
457
458 if (status < 0)
459 return status;
460
461 if (status & DP83822_PHYSTS_DUPLEX)
462 phydev->duplex = DUPLEX_FULL;
463 else
464 phydev->duplex = DUPLEX_HALF;
465
466 if (status & DP83822_PHYSTS_10)
467 phydev->speed = SPEED_10;
468 else
469 phydev->speed = SPEED_100;
470
471 return 0;
472 }
473
dp83822_config_init_leds(struct phy_device * phydev)474 static int dp83822_config_init_leds(struct phy_device *phydev)
475 {
476 struct dp83822_private *dp83822 = phydev->priv;
477 int ret;
478
479 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0]) {
480 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR,
481 DP83822_MLEDCR_ROUTE,
482 FIELD_PREP(DP83822_MLEDCR_ROUTE,
483 DP83822_MLEDCR_ROUTE_LED_0));
484 if (ret)
485 return ret;
486 } else if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) {
487 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
488 DP83822_IOCTRL2_GPIO2_CTRL,
489 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL,
490 DP83822_IOCTRL2_GPIO2_CTRL_MLED));
491 if (ret)
492 return ret;
493 }
494
495 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_1_GPIO1]) {
496 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1,
497 DP83822_IOCTRL1_GPIO1_CTRL,
498 FIELD_PREP(DP83822_IOCTRL1_GPIO1_CTRL,
499 DP83822_IOCTRL1_GPIO1_CTRL_LED_1));
500 if (ret)
501 return ret;
502 }
503
504 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3]) {
505 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1,
506 DP83822_IOCTRL1_GPIO3_CTRL,
507 FIELD_PREP(DP83822_IOCTRL1_GPIO3_CTRL,
508 DP83822_IOCTRL1_GPIO3_CTRL_LED3));
509 if (ret)
510 return ret;
511 }
512
513 return 0;
514 }
515
dp83822_config_init(struct phy_device * phydev)516 static int dp83822_config_init(struct phy_device *phydev)
517 {
518 struct dp83822_private *dp83822 = phydev->priv;
519 struct device *dev = &phydev->mdio.dev;
520 int rgmii_delay = 0;
521 s32 rx_int_delay;
522 s32 tx_int_delay;
523 int err = 0;
524 int bmcr;
525
526 if (dp83822->set_gpio2_clk_out)
527 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
528 DP83822_IOCTRL2_GPIO2_CTRL |
529 DP83822_IOCTRL2_GPIO2_CLK_SRC,
530 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL,
531 DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) |
532 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC,
533 dp83822->gpio2_clk_out));
534
535 if (dp83822->tx_amplitude_100base_tx_index >= 0)
536 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LDCTRL,
537 DP83822_100BASE_TX_LINE_DRIVER_SWING,
538 FIELD_PREP(DP83822_100BASE_TX_LINE_DRIVER_SWING,
539 dp83822->tx_amplitude_100base_tx_index));
540
541 if (dp83822->mac_termination_index >= 0)
542 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL,
543 DP83822_IOCTRL_MAC_IMPEDANCE_CTRL,
544 FIELD_PREP(DP83822_IOCTRL_MAC_IMPEDANCE_CTRL,
545 dp83822->mac_termination_index));
546
547 err = dp83822_config_init_leds(phydev);
548 if (err)
549 return err;
550
551 if (phy_interface_is_rgmii(phydev)) {
552 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
553 true);
554
555 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */
556 if (rx_int_delay > 0)
557 rgmii_delay |= DP83822_RX_CLK_SHIFT;
558
559 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
560 false);
561
562 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */
563 if (tx_int_delay <= 0)
564 rgmii_delay |= DP83822_TX_CLK_SHIFT;
565
566 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
567 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay);
568 if (err)
569 return err;
570
571 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
572 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
573
574 if (err)
575 return err;
576 } else {
577 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
578 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
579
580 if (err)
581 return err;
582 }
583
584 if (dp83822->fx_enabled) {
585 err = phy_modify(phydev, MII_DP83822_CTRL_2,
586 DP83822_FX_ENABLE, 1);
587 if (err < 0)
588 return err;
589
590 /* Only allow advertising what this PHY supports */
591 linkmode_and(phydev->advertising, phydev->advertising,
592 phydev->supported);
593
594 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
595 phydev->supported);
596 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
597 phydev->advertising);
598 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
599 phydev->supported);
600 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
601 phydev->supported);
602 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
603 phydev->advertising);
604 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
605 phydev->advertising);
606
607 /* Auto neg is not supported in fiber mode */
608 bmcr = phy_read(phydev, MII_BMCR);
609 if (bmcr < 0)
610 return bmcr;
611
612 if (bmcr & BMCR_ANENABLE) {
613 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
614 if (err < 0)
615 return err;
616 }
617 phydev->autoneg = AUTONEG_DISABLE;
618 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
619 phydev->supported);
620 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
621 phydev->advertising);
622
623 /* Setup fiber advertisement */
624 err = phy_modify_changed(phydev, MII_ADVERTISE,
625 MII_DP83822_FIBER_ADVERTISE,
626 MII_DP83822_FIBER_ADVERTISE);
627
628 if (err < 0)
629 return err;
630
631 if (dp83822->fx_signal_det_low) {
632 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
633 MII_DP83822_GENCFG,
634 DP83822_SIG_DET_LOW);
635 if (err)
636 return err;
637 }
638 }
639 return dp83822_config_wol(phydev, &dp83822->wol);
640 }
641
dp8382x_config_rmii_mode(struct phy_device * phydev)642 static int dp8382x_config_rmii_mode(struct phy_device *phydev)
643 {
644 struct device *dev = &phydev->mdio.dev;
645 const char *of_val;
646 int ret;
647
648 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) {
649 if (strcmp(of_val, "master") == 0) {
650 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
651 DP83822_RMII_MODE_SEL);
652 } else if (strcmp(of_val, "slave") == 0) {
653 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
654 DP83822_RMII_MODE_SEL);
655 } else {
656 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n",
657 of_val);
658 ret = -EINVAL;
659 }
660
661 if (ret)
662 return ret;
663 }
664
665 return 0;
666 }
667
dp83826_config_init(struct phy_device * phydev)668 static int dp83826_config_init(struct phy_device *phydev)
669 {
670 struct dp83822_private *dp83822 = phydev->priv;
671 u16 val, mask;
672 int ret;
673
674 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
675 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
676 DP83822_RMII_MODE_EN);
677 if (ret)
678 return ret;
679
680 ret = dp8382x_config_rmii_mode(phydev);
681 if (ret)
682 return ret;
683 } else {
684 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
685 DP83822_RMII_MODE_EN);
686 if (ret)
687 return ret;
688 }
689
690 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) {
691 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) |
692 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK,
693 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4,
694 dp83822->cfg_dac_minus));
695 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK;
696 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val);
697 if (ret)
698 return ret;
699
700 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK,
701 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0,
702 dp83822->cfg_dac_minus));
703 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK;
704 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
705 if (ret)
706 return ret;
707 }
708
709 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) {
710 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) |
711 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus);
712 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK;
713 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
714 if (ret)
715 return ret;
716 }
717
718 return dp83822_config_wol(phydev, &dp83822->wol);
719 }
720
dp83825_config_init(struct phy_device * phydev)721 static int dp83825_config_init(struct phy_device *phydev)
722 {
723 struct dp83822_private *dp83822 = phydev->priv;
724 int ret;
725
726 ret = dp8382x_config_rmii_mode(phydev);
727 if (ret)
728 return ret;
729
730 return dp83822_config_wol(phydev, &dp83822->wol);
731 }
732
dp83822_phy_reset(struct phy_device * phydev)733 static int dp83822_phy_reset(struct phy_device *phydev)
734 {
735 int err;
736
737 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
738 if (err < 0)
739 return err;
740
741 return phydev->drv->config_init(phydev);
742 }
743
744 #if IS_ENABLED(CONFIG_OF_MDIO)
745 static const u32 tx_amplitude_100base_tx_gain[] = {
746 80, 82, 83, 85, 87, 88, 90, 92,
747 93, 95, 97, 98, 100, 102, 103, 105,
748 };
749
750 static const u32 mac_termination[] = {
751 99, 91, 84, 78, 73, 69, 65, 61, 58, 55, 53, 50, 48, 46, 44, 43,
752 };
753
dp83822_of_init_leds(struct phy_device * phydev)754 static int dp83822_of_init_leds(struct phy_device *phydev)
755 {
756 struct device_node *node = phydev->mdio.dev.of_node;
757 struct dp83822_private *dp83822 = phydev->priv;
758 struct device_node *leds;
759 u32 index;
760 int err;
761
762 if (!node)
763 return 0;
764
765 leds = of_get_child_by_name(node, "leds");
766 if (!leds)
767 return 0;
768
769 for_each_available_child_of_node_scoped(leds, led) {
770 err = of_property_read_u32(led, "reg", &index);
771 if (err) {
772 of_node_put(leds);
773 return err;
774 }
775
776 if (index <= DP83822_LED_INDEX_RX_D3_GPIO3) {
777 dp83822->led_pin_enable[index] = true;
778 } else {
779 of_node_put(leds);
780 return -EINVAL;
781 }
782 }
783
784 of_node_put(leds);
785 /* LED_0 and COL(GPIO2) use the MLED function. MLED can be routed to
786 * only one of these two pins at a time.
787 */
788 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0] &&
789 dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) {
790 phydev_err(phydev, "LED_0 and COL(GPIO2) cannot be used as LED output at the same time\n");
791 return -EINVAL;
792 }
793
794 if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2] &&
795 dp83822->set_gpio2_clk_out) {
796 phydev_err(phydev, "COL(GPIO2) cannot be used as LED output, already used as clock output\n");
797 return -EINVAL;
798 }
799
800 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3] &&
801 phydev->interface != PHY_INTERFACE_MODE_RMII) {
802 phydev_err(phydev, "RX_D3 can only be used as LED output when in RMII mode\n");
803 return -EINVAL;
804 }
805
806 return 0;
807 }
808
dp83822_of_init(struct phy_device * phydev)809 static int dp83822_of_init(struct phy_device *phydev)
810 {
811 struct dp83822_private *dp83822 = phydev->priv;
812 struct device *dev = &phydev->mdio.dev;
813 const char *of_val;
814 int i, ret;
815 u32 val;
816
817 /* Signal detection for the PHY is only enabled if the FX_EN and the
818 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
819 * is strapped otherwise signal detection is disabled for the PHY.
820 */
821 if (dp83822->fx_enabled && dp83822->fx_sd_enable)
822 dp83822->fx_signal_det_low = device_property_present(dev,
823 "ti,link-loss-low");
824 if (!dp83822->fx_enabled)
825 dp83822->fx_enabled = device_property_present(dev,
826 "ti,fiber-mode");
827
828 if (!device_property_read_string(dev, "ti,gpio2-clk-out", &of_val)) {
829 if (strcmp(of_val, "mac-if") == 0) {
830 dp83822->gpio2_clk_out = DP83822_CLK_SRC_MAC_IF;
831 } else if (strcmp(of_val, "xi") == 0) {
832 dp83822->gpio2_clk_out = DP83822_CLK_SRC_XI;
833 } else if (strcmp(of_val, "int-ref") == 0) {
834 dp83822->gpio2_clk_out = DP83822_CLK_SRC_INT_REF;
835 } else if (strcmp(of_val, "rmii-master-mode-ref") == 0) {
836 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RMII_MASTER_MODE_REF;
837 } else if (strcmp(of_val, "free-running") == 0) {
838 dp83822->gpio2_clk_out = DP83822_CLK_SRC_FREE_RUNNING;
839 } else if (strcmp(of_val, "recovered") == 0) {
840 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RECOVERED;
841 } else {
842 phydev_err(phydev,
843 "Invalid value for ti,gpio2-clk-out property (%s)\n",
844 of_val);
845 return -EINVAL;
846 }
847
848 dp83822->set_gpio2_clk_out = true;
849 }
850
851 ret = phy_get_tx_amplitude_gain(phydev, dev,
852 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
853 &val);
854 if (!ret) {
855 for (i = 0; i < ARRAY_SIZE(tx_amplitude_100base_tx_gain); i++) {
856 if (tx_amplitude_100base_tx_gain[i] == val) {
857 dp83822->tx_amplitude_100base_tx_index = i;
858 break;
859 }
860 }
861
862 if (dp83822->tx_amplitude_100base_tx_index < 0) {
863 phydev_err(phydev,
864 "Invalid value for tx-amplitude-100base-tx-percent property (%u)\n",
865 val);
866 return -EINVAL;
867 }
868 }
869
870 ret = phy_get_mac_termination(phydev, dev, &val);
871 if (!ret) {
872 for (i = 0; i < ARRAY_SIZE(mac_termination); i++) {
873 if (mac_termination[i] == val) {
874 dp83822->mac_termination_index = i;
875 break;
876 }
877 }
878
879 if (dp83822->mac_termination_index < 0) {
880 phydev_err(phydev,
881 "Invalid value for mac-termination-ohms property (%u)\n",
882 val);
883 return -EINVAL;
884 }
885 }
886
887 return dp83822_of_init_leds(phydev);
888 }
889
dp83826_to_dac_minus_one_regval(int percent)890 static int dp83826_to_dac_minus_one_regval(int percent)
891 {
892 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent;
893
894 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
895 }
896
dp83826_to_dac_plus_one_regval(int percent)897 static int dp83826_to_dac_plus_one_regval(int percent)
898 {
899 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT;
900
901 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
902 }
903
dp83826_of_init(struct phy_device * phydev)904 static void dp83826_of_init(struct phy_device *phydev)
905 {
906 struct dp83822_private *dp83822 = phydev->priv;
907 struct device *dev = &phydev->mdio.dev;
908 u32 val;
909
910 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT;
911 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val))
912 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val);
913
914 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT;
915 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val))
916 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val);
917 }
918 #else
dp83822_of_init(struct phy_device * phydev)919 static int dp83822_of_init(struct phy_device *phydev)
920 {
921 return 0;
922 }
923
dp83826_of_init(struct phy_device * phydev)924 static void dp83826_of_init(struct phy_device *phydev)
925 {
926 }
927 #endif /* CONFIG_OF_MDIO */
928
dp83822_read_straps(struct phy_device * phydev)929 static int dp83822_read_straps(struct phy_device *phydev)
930 {
931 struct dp83822_private *dp83822 = phydev->priv;
932 int fx_enabled, fx_sd_enable;
933 int val;
934
935 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1);
936 if (val < 0)
937 return val;
938
939 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val);
940
941 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
942 if (fx_enabled == DP83822_STRAP_MODE2 ||
943 fx_enabled == DP83822_STRAP_MODE3)
944 dp83822->fx_enabled = 1;
945
946 if (dp83822->fx_enabled) {
947 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
948 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
949 fx_sd_enable == DP83822_STRAP_MODE4)
950 dp83822->fx_sd_enable = 1;
951 }
952
953 return 0;
954 }
955
dp8382x_probe(struct phy_device * phydev)956 static int dp8382x_probe(struct phy_device *phydev)
957 {
958 struct dp83822_private *dp83822;
959
960 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
961 GFP_KERNEL);
962 if (!dp83822)
963 return -ENOMEM;
964
965 dp83822->tx_amplitude_100base_tx_index = -1;
966 dp83822->mac_termination_index = -1;
967 phydev->priv = dp83822;
968
969 return 0;
970 }
971
dp83822_probe(struct phy_device * phydev)972 static int dp83822_probe(struct phy_device *phydev)
973 {
974 struct dp83822_private *dp83822;
975 int ret;
976
977 ret = dp8382x_probe(phydev);
978 if (ret)
979 return ret;
980
981 dp83822 = phydev->priv;
982
983 ret = dp83822_read_straps(phydev);
984 if (ret)
985 return ret;
986
987 ret = dp83822_of_init(phydev);
988 if (ret)
989 return ret;
990
991 if (dp83822->fx_enabled)
992 phydev->port = PORT_FIBRE;
993
994 return 0;
995 }
996
dp83826_probe(struct phy_device * phydev)997 static int dp83826_probe(struct phy_device *phydev)
998 {
999 int ret;
1000
1001 ret = dp8382x_probe(phydev);
1002 if (ret)
1003 return ret;
1004
1005 dp83826_of_init(phydev);
1006
1007 return 0;
1008 }
1009
dp83822_suspend(struct phy_device * phydev)1010 static int dp83822_suspend(struct phy_device *phydev)
1011 {
1012 int value;
1013
1014 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
1015
1016 if (!(value & DP83822_WOL_EN))
1017 genphy_suspend(phydev);
1018
1019 return 0;
1020 }
1021
dp83822_resume(struct phy_device * phydev)1022 static int dp83822_resume(struct phy_device *phydev)
1023 {
1024 int value;
1025
1026 genphy_resume(phydev);
1027
1028 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
1029
1030 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value |
1031 DP83822_WOL_CLR_INDICATION);
1032
1033 return 0;
1034 }
1035
dp83822_led_mode(u8 index,unsigned long rules)1036 static int dp83822_led_mode(u8 index, unsigned long rules)
1037 {
1038 switch (rules) {
1039 case BIT(TRIGGER_NETDEV_LINK):
1040 return DP83822_LED_FN_LINK;
1041 case BIT(TRIGGER_NETDEV_LINK_10):
1042 return DP83822_LED_FN_LINK_10_BT;
1043 case BIT(TRIGGER_NETDEV_LINK_100):
1044 return DP83822_LED_FN_LINK_100_BTX;
1045 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
1046 return DP83822_LED_FN_FULL_DUPLEX;
1047 case BIT(TRIGGER_NETDEV_TX):
1048 return DP83822_LED_FN_TX;
1049 case BIT(TRIGGER_NETDEV_RX):
1050 return DP83822_LED_FN_RX;
1051 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1052 return DP83822_LED_FN_RX_TX;
1053 case BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR):
1054 return DP83822_LED_FN_RX_TX_ERR;
1055 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1056 return DP83822_LED_FN_LINK_RX_TX;
1057 default:
1058 return -EOPNOTSUPP;
1059 }
1060 }
1061
dp83822_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)1062 static int dp83822_led_hw_is_supported(struct phy_device *phydev, u8 index,
1063 unsigned long rules)
1064 {
1065 int mode;
1066
1067 mode = dp83822_led_mode(index, rules);
1068 if (mode < 0)
1069 return mode;
1070
1071 return 0;
1072 }
1073
dp83822_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)1074 static int dp83822_led_hw_control_set(struct phy_device *phydev, u8 index,
1075 unsigned long rules)
1076 {
1077 int mode;
1078
1079 mode = dp83822_led_mode(index, rules);
1080 if (mode < 0)
1081 return mode;
1082
1083 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2)
1084 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1085 MII_DP83822_MLEDCR, DP83822_MLEDCR_CFG,
1086 FIELD_PREP(DP83822_MLEDCR_CFG, mode));
1087 else if (index == DP83822_LED_INDEX_LED_1_GPIO1)
1088 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1089 MII_DP83822_LEDCFG1,
1090 DP83822_LEDCFG1_LED1_CTRL,
1091 FIELD_PREP(DP83822_LEDCFG1_LED1_CTRL,
1092 mode));
1093 else
1094 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1095 MII_DP83822_LEDCFG1,
1096 DP83822_LEDCFG1_LED3_CTRL,
1097 FIELD_PREP(DP83822_LEDCFG1_LED3_CTRL,
1098 mode));
1099 }
1100
dp83822_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)1101 static int dp83822_led_hw_control_get(struct phy_device *phydev, u8 index,
1102 unsigned long *rules)
1103 {
1104 int val;
1105
1106 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2) {
1107 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR);
1108 if (val < 0)
1109 return val;
1110
1111 val = FIELD_GET(DP83822_MLEDCR_CFG, val);
1112 } else {
1113 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LEDCFG1);
1114 if (val < 0)
1115 return val;
1116
1117 if (index == DP83822_LED_INDEX_LED_1_GPIO1)
1118 val = FIELD_GET(DP83822_LEDCFG1_LED1_CTRL, val);
1119 else
1120 val = FIELD_GET(DP83822_LEDCFG1_LED3_CTRL, val);
1121 }
1122
1123 switch (val) {
1124 case DP83822_LED_FN_LINK:
1125 *rules = BIT(TRIGGER_NETDEV_LINK);
1126 break;
1127 case DP83822_LED_FN_LINK_10_BT:
1128 *rules = BIT(TRIGGER_NETDEV_LINK_10);
1129 break;
1130 case DP83822_LED_FN_LINK_100_BTX:
1131 *rules = BIT(TRIGGER_NETDEV_LINK_100);
1132 break;
1133 case DP83822_LED_FN_FULL_DUPLEX:
1134 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1135 break;
1136 case DP83822_LED_FN_TX:
1137 *rules = BIT(TRIGGER_NETDEV_TX);
1138 break;
1139 case DP83822_LED_FN_RX:
1140 *rules = BIT(TRIGGER_NETDEV_RX);
1141 break;
1142 case DP83822_LED_FN_RX_TX:
1143 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
1144 break;
1145 case DP83822_LED_FN_RX_TX_ERR:
1146 *rules = BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR);
1147 break;
1148 case DP83822_LED_FN_LINK_RX_TX:
1149 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
1150 BIT(TRIGGER_NETDEV_RX);
1151 break;
1152 default:
1153 *rules = 0;
1154 break;
1155 }
1156
1157 return 0;
1158 }
1159
1160 #define DP83822_PHY_DRIVER(_id, _name) \
1161 { \
1162 PHY_ID_MATCH_MODEL(_id), \
1163 .name = (_name), \
1164 /* PHY_BASIC_FEATURES */ \
1165 .probe = dp83822_probe, \
1166 .soft_reset = dp83822_phy_reset, \
1167 .config_init = dp83822_config_init, \
1168 .read_status = dp83822_read_status, \
1169 .get_wol = dp83822_get_wol, \
1170 .set_wol = dp83822_set_wol, \
1171 .config_intr = dp83822_config_intr, \
1172 .handle_interrupt = dp83822_handle_interrupt, \
1173 .suspend = dp83822_suspend, \
1174 .resume = dp83822_resume, \
1175 .led_hw_is_supported = dp83822_led_hw_is_supported, \
1176 .led_hw_control_set = dp83822_led_hw_control_set, \
1177 .led_hw_control_get = dp83822_led_hw_control_get, \
1178 }
1179
1180 #define DP83825_PHY_DRIVER(_id, _name) \
1181 { \
1182 PHY_ID_MATCH_MODEL(_id), \
1183 .name = (_name), \
1184 /* PHY_BASIC_FEATURES */ \
1185 .probe = dp8382x_probe, \
1186 .soft_reset = dp83822_phy_reset, \
1187 .config_init = dp83825_config_init, \
1188 .get_wol = dp83822_get_wol, \
1189 .set_wol = dp83822_set_wol, \
1190 .config_intr = dp83822_config_intr, \
1191 .handle_interrupt = dp83822_handle_interrupt, \
1192 .suspend = dp83822_suspend, \
1193 .resume = dp83822_resume, \
1194 }
1195
1196 #define DP83826_PHY_DRIVER(_id, _name) \
1197 { \
1198 PHY_ID_MATCH_MODEL(_id), \
1199 .name = (_name), \
1200 /* PHY_BASIC_FEATURES */ \
1201 .probe = dp83826_probe, \
1202 .soft_reset = dp83822_phy_reset, \
1203 .config_init = dp83826_config_init, \
1204 .get_wol = dp83822_get_wol, \
1205 .set_wol = dp83822_set_wol, \
1206 .config_intr = dp83822_config_intr, \
1207 .handle_interrupt = dp83822_handle_interrupt, \
1208 .suspend = dp83822_suspend, \
1209 .resume = dp83822_resume, \
1210 }
1211
1212 static struct phy_driver dp83822_driver[] = {
1213 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
1214 DP83825_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
1215 DP83825_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
1216 DP83825_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
1217 DP83825_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
1218 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
1219 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
1220 };
1221 module_phy_driver(dp83822_driver);
1222
1223 static const struct mdio_device_id __maybe_unused dp83822_tbl[] = {
1224 { DP83822_PHY_ID, 0xfffffff0 },
1225 { DP83825I_PHY_ID, 0xfffffff0 },
1226 { DP83826C_PHY_ID, 0xfffffff0 },
1227 { DP83826NC_PHY_ID, 0xfffffff0 },
1228 { DP83825S_PHY_ID, 0xfffffff0 },
1229 { DP83825CM_PHY_ID, 0xfffffff0 },
1230 { DP83825CS_PHY_ID, 0xfffffff0 },
1231 { },
1232 };
1233 MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
1234
1235 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
1236 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
1237 MODULE_LICENSE("GPL v2");
1238