1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #define __forceinline inline 40 41 /** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47 /** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53 /** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59 /** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62 #define SET_ABM_PIPE_NORMAL 1 63 64 /** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67 #define NUM_AMBI_LEVEL 5 68 69 /** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72 #define NUM_AGGR_LEVEL 4 73 74 /** 75 * Number of segments in the gamma curve. 76 */ 77 #define NUM_POWER_FN_SEGS 8 78 79 /** 80 * Number of segments in the backlight curve. 81 */ 82 #define NUM_BL_CURVE_SEGS 16 83 84 /** 85 * Maximum number of segments in ABM ACE curve. 86 */ 87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 88 89 /** 90 * Maximum number of bins in ABM histogram. 91 */ 92 #define ABM_MAX_NUM_OF_HG_BINS 64 93 94 /* Maximum number of SubVP streams */ 95 #define DMUB_MAX_SUBVP_STREAMS 2 96 97 /* Define max FPO streams as 4 for now. Current implementation today 98 * only supports 1, but could be more in the future. Reduce array 99 * size to ensure the command size remains less than 64 bytes if 100 * adding new fields. 101 */ 102 #define DMUB_MAX_FPO_STREAMS 4 103 104 /* Maximum number of streams on any ASIC. */ 105 #define DMUB_MAX_STREAMS 6 106 107 /* Maximum number of planes on any ASIC. */ 108 #define DMUB_MAX_PLANES 6 109 110 /* Maximum number of phantom planes on any ASIC */ 111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 112 113 /* Trace buffer offset for entry */ 114 #define TRACE_BUFFER_ENTRY_OFFSET 16 115 116 /** 117 * Maximum number of dirty rects supported by FW. 118 */ 119 #define DMUB_MAX_DIRTY_RECTS 3 120 121 /** 122 * 123 * PSR control version legacy 124 */ 125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 126 /** 127 * PSR control version with multi edp support 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 130 131 132 /** 133 * ABM control version legacy 134 */ 135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 136 137 /** 138 * ABM control version with multi edp support 139 */ 140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 141 142 /** 143 * Physical framebuffer address location, 64-bit. 144 */ 145 #ifndef PHYSICAL_ADDRESS_LOC 146 #define PHYSICAL_ADDRESS_LOC union large_integer 147 #endif 148 149 /** 150 * OS/FW agnostic memcpy 151 */ 152 #ifndef dmub_memcpy 153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 154 #endif 155 156 /** 157 * OS/FW agnostic memset 158 */ 159 #ifndef dmub_memset 160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 161 #endif 162 163 /** 164 * OS/FW agnostic memcmp 165 */ 166 #ifndef dmub_memcmp 167 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 168 #endif 169 170 /** 171 * OS/FW agnostic udelay 172 */ 173 #ifndef dmub_udelay 174 #define dmub_udelay(microseconds) udelay(microseconds) 175 #endif 176 177 #pragma pack(push, 1) 178 #define ABM_NUM_OF_ACE_SEGMENTS 5 179 180 /** 181 * Debug FW state offset 182 */ 183 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 184 185 union abm_flags { 186 struct { 187 /** 188 * @abm_enabled: Indicates if ABM is enabled. 189 */ 190 unsigned int abm_enabled : 1; 191 192 /** 193 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 194 */ 195 unsigned int disable_abm_requested : 1; 196 197 /** 198 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 199 */ 200 unsigned int disable_abm_immediately : 1; 201 202 /** 203 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 204 * to be disabled immediately and keep gain. 205 */ 206 unsigned int disable_abm_immediate_keep_gain : 1; 207 208 /** 209 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 210 */ 211 unsigned int fractional_pwm : 1; 212 213 /** 214 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 215 * of user backlight level. 216 */ 217 unsigned int abm_gradual_bl_change : 1; 218 219 /** 220 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 221 */ 222 unsigned int abm_new_frame : 1; 223 224 /** 225 * @vb_scaling_enabled: Indicates variBright Scaling Enable 226 */ 227 unsigned int vb_scaling_enabled : 1; 228 } bitfields; 229 230 unsigned int u32All; 231 }; 232 233 struct abm_save_restore { 234 /** 235 * @flags: Misc. ABM flags. 236 */ 237 union abm_flags flags; 238 239 /** 240 * @pause: true: pause ABM and get state 241 * false: unpause ABM after setting state 242 */ 243 uint32_t pause; 244 245 /** 246 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 247 */ 248 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 249 250 /** 251 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 252 */ 253 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 254 255 /** 256 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 257 */ 258 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 259 260 261 /** 262 * @knee_threshold: Current x-position of ACE knee (u0.16). 263 */ 264 uint32_t knee_threshold; 265 /** 266 * @current_gain: Current backlight reduction (u16.16). 267 */ 268 uint32_t current_gain; 269 /** 270 * @curr_bl_level: Current actual backlight level converging to target backlight level. 271 */ 272 uint16_t curr_bl_level; 273 274 /** 275 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 276 */ 277 uint16_t curr_user_bl_level; 278 279 }; 280 281 /** 282 * union dmub_addr - DMUB physical/virtual 64-bit address. 283 */ 284 union dmub_addr { 285 struct { 286 uint32_t low_part; /**< Lower 32 bits */ 287 uint32_t high_part; /**< Upper 32 bits */ 288 } u; /*<< Low/high bit access */ 289 uint64_t quad_part; /*<< 64 bit address */ 290 }; 291 #pragma pack(pop) 292 293 /** 294 * Dirty rect definition. 295 */ 296 struct dmub_rect { 297 /** 298 * Dirty rect x offset. 299 */ 300 uint32_t x; 301 302 /** 303 * Dirty rect y offset. 304 */ 305 uint32_t y; 306 307 /** 308 * Dirty rect width. 309 */ 310 uint32_t width; 311 312 /** 313 * Dirty rect height. 314 */ 315 uint32_t height; 316 }; 317 318 /** 319 * Flags that can be set by driver to change some PSR behaviour. 320 */ 321 union dmub_psr_debug_flags { 322 /** 323 * Debug flags. 324 */ 325 struct { 326 /** 327 * Enable visual confirm in FW. 328 */ 329 uint32_t visual_confirm : 1; 330 331 /** 332 * Force all selective updates to bw full frame updates. 333 */ 334 uint32_t force_full_frame_update : 1; 335 336 /** 337 * Use HW Lock Mgr object to do HW locking in FW. 338 */ 339 uint32_t use_hw_lock_mgr : 1; 340 341 /** 342 * Use TPS3 signal when restore main link. 343 */ 344 uint32_t force_wakeup_by_tps3 : 1; 345 346 /** 347 * Back to back flip, therefore cannot power down PHY 348 */ 349 uint32_t back_to_back_flip : 1; 350 351 /** 352 * Enable visual confirm for IPS 353 */ 354 uint32_t enable_ips_visual_confirm : 1; 355 } bitfields; 356 357 /** 358 * Union for debug flags. 359 */ 360 uint32_t u32All; 361 }; 362 363 /** 364 * Flags that can be set by driver to change some Replay behaviour. 365 */ 366 union replay_debug_flags { 367 struct { 368 /** 369 * 0x1 (bit 0) 370 * Enable visual confirm in FW. 371 */ 372 uint32_t visual_confirm : 1; 373 374 /** 375 * 0x2 (bit 1) 376 * @skip_crc: Set if need to skip CRC. 377 */ 378 uint32_t skip_crc : 1; 379 380 /** 381 * 0x4 (bit 2) 382 * @force_link_power_on: Force disable ALPM control 383 */ 384 uint32_t force_link_power_on : 1; 385 386 /** 387 * 0x8 (bit 3) 388 * @force_phy_power_on: Force phy power on 389 */ 390 uint32_t force_phy_power_on : 1; 391 392 /** 393 * 0x10 (bit 4) 394 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 395 */ 396 uint32_t timing_resync_disabled : 1; 397 398 /** 399 * 0x20 (bit 5) 400 * @skip_crtc_disabled: CRTC disable skipped 401 */ 402 uint32_t skip_crtc_disabled : 1; 403 404 /** 405 * 0x40 (bit 6) 406 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 407 */ 408 uint32_t force_defer_one_frame_update : 1; 409 410 /** 411 * 0x80 (bit 7) 412 * @disable_delay_alpm_on: Force disable delay alpm on 413 */ 414 uint32_t disable_delay_alpm_on : 1; 415 416 /** 417 * 0x100 (bit 8) 418 * @disable_desync_error_check: Force disable desync error check 419 */ 420 uint32_t disable_desync_error_check : 1; 421 422 /** 423 * 0x200 (bit 9) 424 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 425 */ 426 uint32_t force_self_update_when_abm_non_steady : 1; 427 428 /** 429 * 0x400 (bit 10) 430 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 431 * If we enter IPS2, the Visual confirm bar will change to yellow 432 */ 433 uint32_t enable_ips_visual_confirm : 1; 434 435 /** 436 * 0x800 (bit 11) 437 * @enable_ips_residency_profiling: Enable IPS residency profiling 438 */ 439 uint32_t enable_ips_residency_profiling : 1; 440 441 /** 442 * 0x1000 (bit 12) 443 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 444 */ 445 uint32_t enable_coasting_vtotal_check : 1; 446 /** 447 * 0x2000 (bit 13) 448 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 449 */ 450 uint32_t enable_visual_confirm_debug : 1; 451 452 uint32_t reserved : 18; 453 } bitfields; 454 455 uint32_t u32All; 456 }; 457 458 /** 459 * Flags record error state. 460 */ 461 union replay_visual_confirm_error_state_flags { 462 struct { 463 /** 464 * 0x1 (bit 0) - Desync Error flag. 465 */ 466 uint32_t desync_error : 1; 467 468 /** 469 * 0x2 (bit 1) - State Transition Error flag. 470 */ 471 uint32_t state_transition_error : 1; 472 473 /** 474 * 0x4 (bit 2) - Crc Error flag 475 */ 476 uint32_t crc_error : 1; 477 478 /** 479 * 0x8 (bit 3) - Reserved 480 */ 481 uint32_t reserved_3 : 1; 482 483 /** 484 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 485 * Added new debug flag to control DPCD. 486 */ 487 uint32_t incorrect_vtotal_in_static_screen : 1; 488 489 /** 490 * 0x20 (bit 5) - No doubled Refresh Rate. 491 */ 492 uint32_t no_double_rr : 1; 493 494 /** 495 * Reserved bit 6-7 496 */ 497 uint32_t reserved_6_7 : 2; 498 499 /** 500 * Reserved bit 9-31 501 */ 502 uint32_t reserved_9_31 : 24; 503 } bitfields; 504 505 uint32_t u32All; 506 }; 507 508 union replay_hw_flags { 509 struct { 510 /** 511 * @allow_alpm_fw_standby_mode: To indicate whether the 512 * ALPM FW standby mode is allowed 513 */ 514 uint32_t allow_alpm_fw_standby_mode : 1; 515 516 /* 517 * @dsc_enable_status: DSC enable status in driver 518 */ 519 uint32_t dsc_enable_status : 1; 520 521 /** 522 * @fec_enable_status: receive fec enable/disable status from driver 523 */ 524 uint32_t fec_enable_status : 1; 525 526 /* 527 * @smu_optimizations_en: SMU power optimization. 528 * Only when active display is Replay capable and display enters Replay. 529 * Trigger interrupt to SMU to powerup/down. 530 */ 531 uint32_t smu_optimizations_en : 1; 532 533 /** 534 * @phy_power_state: Indicates current phy power state 535 */ 536 uint32_t phy_power_state : 1; 537 538 /** 539 * @link_power_state: Indicates current link power state 540 */ 541 uint32_t link_power_state : 1; 542 /** 543 * Use TPS3 signal when restore main link. 544 */ 545 uint32_t force_wakeup_by_tps3 : 1; 546 /** 547 * @is_alpm_initialized: Indicates whether ALPM is initialized 548 */ 549 uint32_t is_alpm_initialized : 1; 550 } bitfields; 551 552 uint32_t u32All; 553 }; 554 555 union fw_assisted_mclk_switch_version { 556 struct { 557 uint8_t minor : 5; 558 uint8_t major : 3; 559 }; 560 uint8_t ver; 561 }; 562 563 /** 564 * DMUB feature capabilities. 565 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 566 */ 567 struct dmub_feature_caps { 568 /** 569 * Max PSR version supported by FW. 570 */ 571 uint8_t psr; 572 uint8_t fw_assisted_mclk_switch_ver; 573 uint8_t reserved[4]; 574 uint8_t subvp_psr_support; 575 uint8_t gecc_enable; 576 uint8_t replay_supported; 577 uint8_t replay_reserved[3]; 578 uint8_t abm_aux_backlight_support; 579 }; 580 581 struct dmub_visual_confirm_color { 582 /** 583 * Maximum 10 bits color value 584 */ 585 uint16_t color_r_cr; 586 uint16_t color_g_y; 587 uint16_t color_b_cb; 588 uint16_t panel_inst; 589 }; 590 591 //============================================================================== 592 //</DMUB_TYPES>================================================================= 593 //============================================================================== 594 //< DMUB_META>================================================================== 595 //============================================================================== 596 #pragma pack(push, 1) 597 598 /* Magic value for identifying dmub_fw_meta_info */ 599 #define DMUB_FW_META_MAGIC 0x444D5542 600 601 /* Offset from the end of the file to the dmub_fw_meta_info */ 602 #define DMUB_FW_META_OFFSET 0x24 603 604 /** 605 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 606 */ 607 union dmub_fw_meta_feature_bits { 608 struct { 609 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 610 uint32_t reserved : 31; 611 } bits; /**< status bits */ 612 uint32_t all; /**< 32-bit access to status bits */ 613 }; 614 615 /** 616 * struct dmub_fw_meta_info - metadata associated with fw binary 617 * 618 * NOTE: This should be considered a stable API. Fields should 619 * not be repurposed or reordered. New fields should be 620 * added instead to extend the structure. 621 * 622 * @magic_value: magic value identifying DMUB firmware meta info 623 * @fw_region_size: size of the firmware state region 624 * @trace_buffer_size: size of the tracebuffer region 625 * @fw_version: the firmware version information 626 * @dal_fw: 1 if the firmware is DAL 627 * @shared_state_size: size of the shared state region in bytes 628 * @shared_state_features: number of shared state features 629 */ 630 struct dmub_fw_meta_info { 631 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 632 uint32_t fw_region_size; /**< size of the firmware state region */ 633 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 634 uint32_t fw_version; /**< the firmware version information */ 635 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 636 uint8_t reserved[3]; /**< padding bits */ 637 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 638 uint16_t shared_state_features; /**< number of shared state features */ 639 uint16_t reserved2; /**< padding bytes */ 640 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 641 }; 642 643 /** 644 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 645 */ 646 union dmub_fw_meta { 647 struct dmub_fw_meta_info info; /**< metadata info */ 648 uint8_t reserved[64]; /**< padding bits */ 649 }; 650 651 #pragma pack(pop) 652 653 //============================================================================== 654 //< DMUB Trace Buffer>================================================================ 655 //============================================================================== 656 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 657 /** 658 * dmub_trace_code_t - firmware trace code, 32-bits 659 */ 660 typedef uint32_t dmub_trace_code_t; 661 662 /** 663 * struct dmcub_trace_buf_entry - Firmware trace entry 664 */ 665 struct dmcub_trace_buf_entry { 666 dmub_trace_code_t trace_code; /**< trace code for the event */ 667 uint32_t tick_count; /**< the tick count at time of trace */ 668 uint32_t param0; /**< trace defined parameter 0 */ 669 uint32_t param1; /**< trace defined parameter 1 */ 670 }; 671 #endif 672 673 //============================================================================== 674 //< DMUB_STATUS>================================================================ 675 //============================================================================== 676 677 /** 678 * DMCUB scratch registers can be used to determine firmware status. 679 * Current scratch register usage is as follows: 680 * 681 * SCRATCH0: FW Boot Status register 682 * SCRATCH5: LVTMA Status Register 683 * SCRATCH15: FW Boot Options register 684 */ 685 686 /** 687 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 688 */ 689 union dmub_fw_boot_status { 690 struct { 691 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 692 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 693 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 694 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 695 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 696 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 697 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 698 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 699 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 700 } bits; /**< status bits */ 701 uint32_t all; /**< 32-bit access to status bits */ 702 }; 703 704 /** 705 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 706 */ 707 enum dmub_fw_boot_status_bit { 708 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 709 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 710 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 711 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 712 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 713 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 714 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 715 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 716 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 717 }; 718 719 /* Register bit definition for SCRATCH5 */ 720 union dmub_lvtma_status { 721 struct { 722 uint32_t psp_ok : 1; 723 uint32_t edp_on : 1; 724 uint32_t reserved : 30; 725 } bits; 726 uint32_t all; 727 }; 728 729 enum dmub_lvtma_status_bit { 730 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 731 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 732 }; 733 734 enum dmub_ips_disable_type { 735 DMUB_IPS_ENABLE = 0, 736 DMUB_IPS_DISABLE_ALL = 1, 737 DMUB_IPS_DISABLE_IPS1 = 2, 738 DMUB_IPS_DISABLE_IPS2 = 3, 739 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 740 DMUB_IPS_DISABLE_DYNAMIC = 5, 741 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 742 }; 743 744 #define DMUB_IPS1_ALLOW_MASK 0x00000001 745 #define DMUB_IPS2_ALLOW_MASK 0x00000002 746 #define DMUB_IPS1_COMMIT_MASK 0x00000004 747 #define DMUB_IPS2_COMMIT_MASK 0x00000008 748 749 /** 750 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 751 */ 752 union dmub_fw_boot_options { 753 struct { 754 uint32_t pemu_env : 1; /**< 1 if PEMU */ 755 uint32_t fpga_env : 1; /**< 1 if FPGA */ 756 uint32_t optimized_init : 1; /**< 1 if optimized init */ 757 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 758 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 759 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 760 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 761 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 762 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 763 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 764 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 765 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 766 uint32_t power_optimization: 1; 767 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 768 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 769 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 770 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 771 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 772 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 773 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 774 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 775 uint32_t ips_disable: 3; /* options to disable ips support*/ 776 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 777 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 778 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 779 uint32_t reserved : 6; /**< reserved */ 780 } bits; /**< boot bits */ 781 uint32_t all; /**< 32-bit access to bits */ 782 }; 783 784 enum dmub_fw_boot_options_bit { 785 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 786 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 787 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 788 }; 789 790 //============================================================================== 791 //< DMUB_SHARED_STATE>========================================================== 792 //============================================================================== 793 794 /** 795 * Shared firmware state between driver and firmware for lockless communication 796 * in situations where the inbox/outbox may be unavailable. 797 * 798 * Each structure *must* be at most 256-bytes in size. The layout allocation is 799 * described below: 800 * 801 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 802 */ 803 804 /** 805 * enum dmub_shared_state_feature_id - List of shared state features. 806 */ 807 enum dmub_shared_state_feature_id { 808 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 809 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 810 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 811 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 812 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 813 }; 814 815 /** 816 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 817 */ 818 union dmub_shared_state_ips_fw_signals { 819 struct { 820 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 821 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 822 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 823 uint32_t detection_required : 1; /**< 1 if detection is required */ 824 uint32_t reserved_bits : 28; /**< Reversed */ 825 } bits; 826 uint32_t all; 827 }; 828 829 /** 830 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 831 */ 832 union dmub_shared_state_ips_driver_signals { 833 struct { 834 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 835 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 836 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 837 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 838 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 839 uint32_t reserved_bits : 27; /**< Reversed bits */ 840 } bits; 841 uint32_t all; 842 }; 843 844 /** 845 * IPS FW Version 846 */ 847 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 848 849 struct dmub_shared_state_debug_setup { 850 union { 851 struct { 852 uint32_t exclude_points[62]; 853 } profile_mode; 854 }; 855 }; 856 857 /** 858 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 859 */ 860 struct dmub_shared_state_ips_fw { 861 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 862 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 863 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 864 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 865 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 866 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 867 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 868 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 869 }; /* 248-bytes, fixed */ 870 871 /** 872 * IPS Driver Version 873 */ 874 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 875 876 /** 877 * struct dmub_shared_state_ips_driver - Driver state for IPS. 878 */ 879 struct dmub_shared_state_ips_driver { 880 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 881 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 882 }; /* 248-bytes, fixed */ 883 884 /** 885 * enum dmub_shared_state_feature_common - Generic payload. 886 */ 887 struct dmub_shared_state_feature_common { 888 uint32_t padding[62]; 889 }; /* 248-bytes, fixed */ 890 891 /** 892 * enum dmub_shared_state_feature_header - Feature description. 893 */ 894 struct dmub_shared_state_feature_header { 895 uint16_t id; /**< Feature ID */ 896 uint16_t version; /**< Feature version */ 897 uint32_t reserved; /**< Reserved bytes. */ 898 }; /* 8 bytes, fixed */ 899 900 /** 901 * struct dmub_shared_state_feature_block - Feature block. 902 */ 903 struct dmub_shared_state_feature_block { 904 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 905 union dmub_shared_feature_state_union { 906 struct dmub_shared_state_feature_common common; /**< Generic data */ 907 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 908 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 909 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 910 } data; /**< Shared state data. */ 911 }; /* 256-bytes, fixed */ 912 913 /** 914 * Shared state size in bytes. 915 */ 916 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 917 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 918 919 //============================================================================== 920 //</DMUB_STATUS>================================================================ 921 //============================================================================== 922 //< DMUB_VBIOS>================================================================= 923 //============================================================================== 924 925 /* 926 * enum dmub_cmd_vbios_type - VBIOS commands. 927 * 928 * Command IDs should be treated as stable ABI. 929 * Do not reuse or modify IDs. 930 */ 931 enum dmub_cmd_vbios_type { 932 /** 933 * Configures the DIG encoder. 934 */ 935 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 936 /** 937 * Controls the PHY. 938 */ 939 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 940 /** 941 * Sets the pixel clock/symbol clock. 942 */ 943 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 944 /** 945 * Enables or disables power gating. 946 */ 947 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 948 /** 949 * Controls embedded panels. 950 */ 951 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 952 /** 953 * Query DP alt status on a transmitter. 954 */ 955 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 956 /** 957 * Control PHY FSM 958 */ 959 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 960 /** 961 * Controls domain power gating 962 */ 963 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 964 }; 965 966 //============================================================================== 967 //</DMUB_VBIOS>================================================================= 968 //============================================================================== 969 //< DMUB_GPINT>================================================================= 970 //============================================================================== 971 972 /** 973 * The shifts and masks below may alternatively be used to format and read 974 * the command register bits. 975 */ 976 977 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 978 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 979 980 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 981 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 982 983 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 984 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 985 986 /** 987 * Command responses. 988 */ 989 990 /** 991 * Return response for DMUB_GPINT__STOP_FW command. 992 */ 993 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 994 995 /** 996 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 997 */ 998 union dmub_gpint_data_register { 999 struct { 1000 uint32_t param : 16; /**< 16-bit parameter */ 1001 uint32_t command_code : 12; /**< GPINT command */ 1002 uint32_t status : 4; /**< Command status bit */ 1003 } bits; /**< GPINT bit access */ 1004 uint32_t all; /**< GPINT 32-bit access */ 1005 }; 1006 1007 /* 1008 * enum dmub_gpint_command - GPINT command to DMCUB FW 1009 * 1010 * Command IDs should be treated as stable ABI. 1011 * Do not reuse or modify IDs. 1012 */ 1013 enum dmub_gpint_command { 1014 /** 1015 * Invalid command, ignored. 1016 */ 1017 DMUB_GPINT__INVALID_COMMAND = 0, 1018 /** 1019 * DESC: Queries the firmware version. 1020 * RETURN: Firmware version. 1021 */ 1022 DMUB_GPINT__GET_FW_VERSION = 1, 1023 /** 1024 * DESC: Halts the firmware. 1025 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1026 */ 1027 DMUB_GPINT__STOP_FW = 2, 1028 /** 1029 * DESC: Get PSR state from FW. 1030 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1031 */ 1032 DMUB_GPINT__GET_PSR_STATE = 7, 1033 /** 1034 * DESC: Notifies DMCUB of the currently active streams. 1035 * ARGS: Stream mask, 1 bit per active stream index. 1036 */ 1037 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1038 /** 1039 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1040 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1041 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1042 * RETURN: PSR residency in milli-percent. 1043 */ 1044 DMUB_GPINT__PSR_RESIDENCY = 9, 1045 1046 /** 1047 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1048 */ 1049 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1050 1051 /** 1052 * DESC: Get REPLAY state from FW. 1053 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1054 */ 1055 DMUB_GPINT__GET_REPLAY_STATE = 13, 1056 1057 /** 1058 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1059 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1060 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1061 * RETURN: REPLAY residency in milli-percent. 1062 */ 1063 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1064 1065 /** 1066 * DESC: Copy bounding box to the host. 1067 * ARGS: Version of bounding box to copy 1068 * RETURN: Result of copying bounding box 1069 */ 1070 DMUB_GPINT__BB_COPY = 96, 1071 1072 /** 1073 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1074 * ARGS: The word3 for the 64 bit address 1075 */ 1076 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1077 1078 /** 1079 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1080 * ARGS: The word2 for the 64 bit address 1081 */ 1082 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1083 1084 /** 1085 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1086 * ARGS: The word1 for the 64 bit address 1087 */ 1088 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1089 1090 /** 1091 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1092 * ARGS: The word0 for the 64 bit address 1093 */ 1094 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1095 1096 /** 1097 * DESC: Updates the trace buffer lower 32-bit mask. 1098 * ARGS: The new mask 1099 * RETURN: Lower 32-bit mask. 1100 */ 1101 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1102 1103 /** 1104 * DESC: Updates the trace buffer mask bit0~bit15. 1105 * ARGS: The new mask 1106 * RETURN: Lower 32-bit mask. 1107 */ 1108 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1109 1110 /** 1111 * DESC: Updates the trace buffer mask bit16~bit31. 1112 * ARGS: The new mask 1113 * RETURN: Lower 32-bit mask. 1114 */ 1115 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1116 1117 /** 1118 * DESC: Updates the trace buffer mask bit32~bit47. 1119 * ARGS: The new mask 1120 * RETURN: Lower 32-bit mask. 1121 */ 1122 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1123 1124 /** 1125 * DESC: Updates the trace buffer mask bit48~bit63. 1126 * ARGS: The new mask 1127 * RETURN: Lower 32-bit mask. 1128 */ 1129 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1130 1131 /** 1132 * DESC: Read the trace buffer mask bi0~bit15. 1133 */ 1134 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1135 1136 /** 1137 * DESC: Read the trace buffer mask bit16~bit31. 1138 */ 1139 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1140 1141 /** 1142 * DESC: Read the trace buffer mask bi32~bit47. 1143 */ 1144 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1145 1146 /** 1147 * DESC: Updates the trace buffer mask bit32~bit63. 1148 */ 1149 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1150 1151 /** 1152 * DESC: Set IPS residency measurement 1153 * ARGS: 0 - Disable ips measurement 1154 * 1 - Enable ips measurement 1155 */ 1156 DMUB_GPINT__IPS_RESIDENCY = 121, 1157 1158 /** 1159 * DESC: Enable measurements for various task duration 1160 * ARGS: 0 - Disable measurement 1161 * 1 - Enable measurement 1162 */ 1163 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1164 1165 /** 1166 * DESC: Gets IPS residency in microseconds 1167 * ARGS: 0 - Return IPS1 residency 1168 * 1 - Return IPS2 residency 1169 * 2 - Return IPS1_RCG residency 1170 * 3 - Return IPS1_ONO2_ON residency 1171 * RETURN: Total residency in microseconds - lower 32 bits 1172 */ 1173 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1174 1175 /** 1176 * DESC: Gets IPS1 histogram counts 1177 * ARGS: Bucket index 1178 * RETURN: Total count for the bucket 1179 */ 1180 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1181 1182 /** 1183 * DESC: Gets IPS2 histogram counts 1184 * ARGS: Bucket index 1185 * RETURN: Total count for the bucket 1186 */ 1187 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1188 1189 /** 1190 * DESC: Gets IPS residency 1191 * ARGS: 0 - Return IPS1 residency 1192 * 1 - Return IPS2 residency 1193 * 2 - Return IPS1_RCG residency 1194 * 3 - Return IPS1_ONO2_ON residency 1195 * RETURN: Total residency in milli-percent. 1196 */ 1197 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1198 1199 /** 1200 * DESC: Gets IPS1_RCG histogram counts 1201 * ARGS: Bucket index 1202 * RETURN: Total count for the bucket 1203 */ 1204 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1205 1206 /** 1207 * DESC: Gets IPS1_ONO2_ON histogram counts 1208 * ARGS: Bucket index 1209 * RETURN: Total count for the bucket 1210 */ 1211 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1212 1213 /** 1214 * DESC: Gets IPS entry counter during residency measurement 1215 * ARGS: 0 - Return IPS1 entry counts 1216 * 1 - Return IPS2 entry counts 1217 * 2 - Return IPS1_RCG entry counts 1218 * 3 - Return IPS2_ONO2_ON entry counts 1219 * RETURN: Entry counter for selected IPS mode 1220 */ 1221 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1222 1223 /** 1224 * DESC: Gets IPS inactive residency in microseconds 1225 * ARGS: 0 - Return IPS1_MAX residency 1226 * 1 - Return IPS2 residency 1227 * 2 - Return IPS1_RCG residency 1228 * 3 - Return IPS1_ONO2_ON residency 1229 * RETURN: Total inactive residency in microseconds - lower 32 bits 1230 */ 1231 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1232 1233 /** 1234 * DESC: Gets IPS inactive residency in microseconds 1235 * ARGS: 0 - Return IPS1_MAX residency 1236 * 1 - Return IPS2 residency 1237 * 2 - Return IPS1_RCG residency 1238 * 3 - Return IPS1_ONO2_ON residency 1239 * RETURN: Total inactive residency in microseconds - upper 32 bits 1240 */ 1241 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1242 1243 /** 1244 * DESC: Gets IPS residency in microseconds 1245 * ARGS: 0 - Return IPS1 residency 1246 * 1 - Return IPS2 residency 1247 * 2 - Return IPS1_RCG residency 1248 * 3 - Return IPS1_ONO2_ON residency 1249 * RETURN: Total residency in microseconds - upper 32 bits 1250 */ 1251 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1252 /** 1253 * DESC: Setup debug configs. 1254 */ 1255 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1256 }; 1257 1258 /** 1259 * INBOX0 generic command definition 1260 */ 1261 union dmub_inbox0_cmd_common { 1262 struct { 1263 uint32_t command_code: 8; /**< INBOX0 command code */ 1264 uint32_t param: 24; /**< 24-bit parameter */ 1265 } bits; 1266 uint32_t all; 1267 }; 1268 1269 /** 1270 * INBOX0 hw_lock command definition 1271 */ 1272 union dmub_inbox0_cmd_lock_hw { 1273 struct { 1274 uint32_t command_code: 8; 1275 1276 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1277 uint32_t hw_lock_client: 2; 1278 1279 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1280 uint32_t otg_inst: 3; 1281 uint32_t opp_inst: 3; 1282 uint32_t dig_inst: 3; 1283 1284 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1285 uint32_t lock_pipe: 1; 1286 uint32_t lock_cursor: 1; 1287 uint32_t lock_dig: 1; 1288 uint32_t triple_buffer_lock: 1; 1289 1290 uint32_t lock: 1; /**< Lock */ 1291 uint32_t should_release: 1; /**< Release */ 1292 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1293 } bits; 1294 uint32_t all; 1295 }; 1296 1297 union dmub_inbox0_data_register { 1298 union dmub_inbox0_cmd_common inbox0_cmd_common; 1299 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1300 }; 1301 1302 enum dmub_inbox0_command { 1303 /** 1304 * DESC: Invalid command, ignored. 1305 */ 1306 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1307 /** 1308 * DESC: Notification to acquire/release HW lock 1309 * ARGS: 1310 */ 1311 DMUB_INBOX0_CMD__HW_LOCK = 1, 1312 }; 1313 //============================================================================== 1314 //</DMUB_GPINT>================================================================= 1315 //============================================================================== 1316 //< DMUB_CMD>=================================================================== 1317 //============================================================================== 1318 1319 /** 1320 * Size in bytes of each DMUB command. 1321 */ 1322 #define DMUB_RB_CMD_SIZE 64 1323 1324 /** 1325 * Maximum number of items in the DMUB ringbuffer. 1326 */ 1327 #define DMUB_RB_MAX_ENTRY 128 1328 1329 /** 1330 * Ringbuffer size in bytes. 1331 */ 1332 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1333 1334 /** 1335 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1336 */ 1337 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1338 1339 /** 1340 * Ringbuffer size in bytes. 1341 */ 1342 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1343 1344 /** 1345 * REG_SET mask for reg offload. 1346 */ 1347 #define REG_SET_MASK 0xFFFF 1348 1349 /* 1350 * enum dmub_cmd_type - DMUB inbox command. 1351 * 1352 * Command IDs should be treated as stable ABI. 1353 * Do not reuse or modify IDs. 1354 */ 1355 enum dmub_cmd_type { 1356 /** 1357 * Invalid command. 1358 */ 1359 DMUB_CMD__NULL = 0, 1360 /** 1361 * Read modify write register sequence offload. 1362 */ 1363 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1364 /** 1365 * Field update register sequence offload. 1366 */ 1367 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1368 /** 1369 * Burst write sequence offload. 1370 */ 1371 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1372 /** 1373 * Reg wait sequence offload. 1374 */ 1375 DMUB_CMD__REG_REG_WAIT = 4, 1376 /** 1377 * Workaround to avoid HUBP underflow during NV12 playback. 1378 */ 1379 DMUB_CMD__PLAT_54186_WA = 5, 1380 /** 1381 * Command type used to query FW feature caps. 1382 */ 1383 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1384 /** 1385 * Command type used to get visual confirm color. 1386 */ 1387 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1388 /** 1389 * Command type used for all PSR commands. 1390 */ 1391 DMUB_CMD__PSR = 64, 1392 /** 1393 * Command type used for all MALL commands. 1394 */ 1395 DMUB_CMD__MALL = 65, 1396 /** 1397 * Command type used for all ABM commands. 1398 */ 1399 DMUB_CMD__ABM = 66, 1400 /** 1401 * Command type used to update dirty rects in FW. 1402 */ 1403 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1404 /** 1405 * Command type used to update cursor info in FW. 1406 */ 1407 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1408 /** 1409 * Command type used for HW locking in FW. 1410 */ 1411 DMUB_CMD__HW_LOCK = 69, 1412 /** 1413 * Command type used to access DP AUX. 1414 */ 1415 DMUB_CMD__DP_AUX_ACCESS = 70, 1416 /** 1417 * Command type used for OUTBOX1 notification enable 1418 */ 1419 DMUB_CMD__OUTBOX1_ENABLE = 71, 1420 1421 /** 1422 * Command type used for all idle optimization commands. 1423 */ 1424 DMUB_CMD__IDLE_OPT = 72, 1425 /** 1426 * Command type used for all clock manager commands. 1427 */ 1428 DMUB_CMD__CLK_MGR = 73, 1429 /** 1430 * Command type used for all panel control commands. 1431 */ 1432 DMUB_CMD__PANEL_CNTL = 74, 1433 1434 /** 1435 * Command type used for all CAB commands. 1436 */ 1437 DMUB_CMD__CAB_FOR_SS = 75, 1438 1439 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1440 1441 /** 1442 * Command type used for interfacing with DPIA. 1443 */ 1444 DMUB_CMD__DPIA = 77, 1445 /** 1446 * Command type used for EDID CEA parsing 1447 */ 1448 DMUB_CMD__EDID_CEA = 79, 1449 /** 1450 * Command type used for getting usbc cable ID 1451 */ 1452 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1453 /** 1454 * Command type used to query HPD state. 1455 */ 1456 DMUB_CMD__QUERY_HPD_STATE = 82, 1457 /** 1458 * Command type used for all VBIOS interface commands. 1459 */ 1460 /** 1461 * Command type used for all REPLAY commands. 1462 */ 1463 DMUB_CMD__REPLAY = 83, 1464 1465 /** 1466 * Command type used for all SECURE_DISPLAY commands. 1467 */ 1468 DMUB_CMD__SECURE_DISPLAY = 85, 1469 1470 /** 1471 * Command type used to set DPIA HPD interrupt state 1472 */ 1473 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1474 1475 /** 1476 * Command type used for all PSP commands. 1477 */ 1478 DMUB_CMD__PSP = 88, 1479 1480 /** 1481 * Command type used for all Fused IO commands. 1482 */ 1483 DMUB_CMD__FUSED_IO = 89, 1484 1485 DMUB_CMD__VBIOS = 128, 1486 }; 1487 1488 /** 1489 * enum dmub_out_cmd_type - DMUB outbox commands. 1490 */ 1491 enum dmub_out_cmd_type { 1492 /** 1493 * Invalid outbox command, ignored. 1494 */ 1495 DMUB_OUT_CMD__NULL = 0, 1496 /** 1497 * Command type used for DP AUX Reply data notification 1498 */ 1499 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1500 /** 1501 * Command type used for DP HPD event notification 1502 */ 1503 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1504 /** 1505 * Command type used for SET_CONFIG Reply notification 1506 */ 1507 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1508 /** 1509 * Command type used for USB4 DPIA notification 1510 */ 1511 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1512 /** 1513 * Command type used for HPD redetect notification 1514 */ 1515 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1516 /** 1517 * Command type used for Fused IO notification 1518 */ 1519 DMUB_OUT_CMD__FUSED_IO = 7, 1520 }; 1521 1522 /* DMUB_CMD__DPIA command sub-types. */ 1523 enum dmub_cmd_dpia_type { 1524 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1525 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1526 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1527 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1528 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1529 }; 1530 1531 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1532 enum dmub_cmd_dpia_notification_type { 1533 DPIA_NOTIFY__BW_ALLOCATION = 0, 1534 }; 1535 1536 #pragma pack(push, 1) 1537 1538 /** 1539 * struct dmub_cmd_header - Common command header fields. 1540 */ 1541 struct dmub_cmd_header { 1542 unsigned int type : 8; /**< command type */ 1543 unsigned int sub_type : 8; /**< command sub type */ 1544 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1545 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1546 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1547 unsigned int reserved0 : 5; /**< reserved bits */ 1548 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1549 unsigned int reserved1 : 2; /**< reserved bits */ 1550 }; 1551 1552 /* 1553 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1554 * 1555 * 60 payload bytes can hold up to 5 sets of read modify writes, 1556 * each take 3 dwords. 1557 * 1558 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1559 * 1560 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1561 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1562 */ 1563 struct dmub_cmd_read_modify_write_sequence { 1564 uint32_t addr; /**< register address */ 1565 uint32_t modify_mask; /**< modify mask */ 1566 uint32_t modify_value; /**< modify value */ 1567 }; 1568 1569 /** 1570 * Maximum number of ops in read modify write sequence. 1571 */ 1572 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1573 1574 /** 1575 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1576 */ 1577 struct dmub_rb_cmd_read_modify_write { 1578 struct dmub_cmd_header header; /**< command header */ 1579 /** 1580 * Read modify write sequence. 1581 */ 1582 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1583 }; 1584 1585 /* 1586 * Update a register with specified masks and values sequeunce 1587 * 1588 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1589 * 1590 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1591 * 1592 * 1593 * USE CASE: 1594 * 1. auto-increment register where additional read would update pointer and produce wrong result 1595 * 2. toggle a bit without read in the middle 1596 */ 1597 1598 struct dmub_cmd_reg_field_update_sequence { 1599 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1600 uint32_t modify_value; /**< value to update with */ 1601 }; 1602 1603 /** 1604 * Maximum number of ops in field update sequence. 1605 */ 1606 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1607 1608 /** 1609 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1610 */ 1611 struct dmub_rb_cmd_reg_field_update_sequence { 1612 struct dmub_cmd_header header; /**< command header */ 1613 uint32_t addr; /**< register address */ 1614 /** 1615 * Field update sequence. 1616 */ 1617 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1618 }; 1619 1620 1621 /** 1622 * Maximum number of burst write values. 1623 */ 1624 #define DMUB_BURST_WRITE_VALUES__MAX 14 1625 1626 /* 1627 * struct dmub_rb_cmd_burst_write - Burst write 1628 * 1629 * support use case such as writing out LUTs. 1630 * 1631 * 60 payload bytes can hold up to 14 values to write to given address 1632 * 1633 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1634 */ 1635 struct dmub_rb_cmd_burst_write { 1636 struct dmub_cmd_header header; /**< command header */ 1637 uint32_t addr; /**< register start address */ 1638 /** 1639 * Burst write register values. 1640 */ 1641 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1642 }; 1643 1644 /** 1645 * struct dmub_rb_cmd_common - Common command header 1646 */ 1647 struct dmub_rb_cmd_common { 1648 struct dmub_cmd_header header; /**< command header */ 1649 /** 1650 * Padding to RB_CMD_SIZE 1651 */ 1652 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1653 }; 1654 1655 /** 1656 * struct dmub_cmd_reg_wait_data - Register wait data 1657 */ 1658 struct dmub_cmd_reg_wait_data { 1659 uint32_t addr; /**< Register address */ 1660 uint32_t mask; /**< Mask for register bits */ 1661 uint32_t condition_field_value; /**< Value to wait for */ 1662 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1663 }; 1664 1665 /** 1666 * struct dmub_rb_cmd_reg_wait - Register wait command 1667 */ 1668 struct dmub_rb_cmd_reg_wait { 1669 struct dmub_cmd_header header; /**< Command header */ 1670 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1671 }; 1672 1673 /** 1674 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1675 * 1676 * Reprograms surface parameters to avoid underflow. 1677 */ 1678 struct dmub_cmd_PLAT_54186_wa { 1679 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1680 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1681 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1682 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1683 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1684 struct { 1685 uint32_t hubp_inst : 4; /**< HUBP instance */ 1686 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1687 uint32_t immediate :1; /**< Immediate flip */ 1688 uint32_t vmid : 4; /**< VMID */ 1689 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1690 uint32_t reserved : 21; /**< Reserved */ 1691 } flip_params; /**< Pageflip parameters */ 1692 uint32_t reserved[9]; /**< Reserved bits */ 1693 }; 1694 1695 /** 1696 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1697 */ 1698 struct dmub_rb_cmd_PLAT_54186_wa { 1699 struct dmub_cmd_header header; /**< Command header */ 1700 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1701 }; 1702 1703 /** 1704 * enum dmub_cmd_mall_type - MALL commands 1705 */ 1706 enum dmub_cmd_mall_type { 1707 /** 1708 * Allows display refresh from MALL. 1709 */ 1710 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1711 /** 1712 * Disallows display refresh from MALL. 1713 */ 1714 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1715 /** 1716 * Cursor copy for MALL. 1717 */ 1718 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1719 /** 1720 * Controls DF requests. 1721 */ 1722 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1723 }; 1724 1725 /** 1726 * struct dmub_rb_cmd_mall - MALL command data. 1727 */ 1728 struct dmub_rb_cmd_mall { 1729 struct dmub_cmd_header header; /**< Common command header */ 1730 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1731 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1732 uint32_t tmr_delay; /**< Timer delay */ 1733 uint32_t tmr_scale; /**< Timer scale */ 1734 uint16_t cursor_width; /**< Cursor width in pixels */ 1735 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1736 uint16_t cursor_height; /**< Cursor height in pixels */ 1737 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1738 uint8_t debug_bits; /**< Debug bits */ 1739 1740 uint8_t reserved1; /**< Reserved bits */ 1741 uint8_t reserved2; /**< Reserved bits */ 1742 }; 1743 1744 /** 1745 * enum dmub_cmd_cab_type - CAB command data. 1746 */ 1747 enum dmub_cmd_cab_type { 1748 /** 1749 * No idle optimizations (i.e. no CAB) 1750 */ 1751 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1752 /** 1753 * No DCN requests for memory 1754 */ 1755 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1756 /** 1757 * Fit surfaces in CAB (i.e. CAB enable) 1758 */ 1759 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1760 /** 1761 * Do not fit surfaces in CAB (i.e. no CAB) 1762 */ 1763 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1764 }; 1765 1766 /** 1767 * struct dmub_rb_cmd_cab - CAB command data. 1768 */ 1769 struct dmub_rb_cmd_cab_for_ss { 1770 struct dmub_cmd_header header; 1771 uint8_t cab_alloc_ways; /* total number of ways */ 1772 uint8_t debug_bits; /* debug bits */ 1773 }; 1774 1775 /** 1776 * Enum for indicating which MCLK switch mode per pipe 1777 */ 1778 enum mclk_switch_mode { 1779 NONE = 0, 1780 FPO = 1, 1781 SUBVP = 2, 1782 VBLANK = 3, 1783 }; 1784 1785 /* Per pipe struct which stores the MCLK switch mode 1786 * data to be sent to DMUB. 1787 * Named "v2" for now -- once FPO and SUBVP are fully merged 1788 * the type name can be updated 1789 */ 1790 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1791 union { 1792 struct { 1793 uint32_t pix_clk_100hz; 1794 uint16_t main_vblank_start; 1795 uint16_t main_vblank_end; 1796 uint16_t mall_region_lines; 1797 uint16_t prefetch_lines; 1798 uint16_t prefetch_to_mall_start_lines; 1799 uint16_t processing_delay_lines; 1800 uint16_t htotal; // required to calculate line time for multi-display cases 1801 uint16_t vtotal; 1802 uint8_t main_pipe_index; 1803 uint8_t phantom_pipe_index; 1804 /* Since the microschedule is calculated in terms of OTG lines, 1805 * include any scaling factors to make sure when we get accurate 1806 * conversion when programming MALL_START_LINE (which is in terms 1807 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1808 * is 1/2 (numerator = 1, denominator = 2). 1809 */ 1810 uint8_t scale_factor_numerator; 1811 uint8_t scale_factor_denominator; 1812 uint8_t is_drr; 1813 uint8_t main_split_pipe_index; 1814 uint8_t phantom_split_pipe_index; 1815 } subvp_data; 1816 1817 struct { 1818 uint32_t pix_clk_100hz; 1819 uint16_t vblank_start; 1820 uint16_t vblank_end; 1821 uint16_t vstartup_start; 1822 uint16_t vtotal; 1823 uint16_t htotal; 1824 uint8_t vblank_pipe_index; 1825 uint8_t padding[1]; 1826 struct { 1827 uint8_t drr_in_use; 1828 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1829 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1830 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1831 uint8_t use_ramping; // Use ramping or not 1832 uint8_t drr_vblank_start_margin; 1833 } drr_info; // DRR considered as part of SubVP + VBLANK case 1834 } vblank_data; 1835 } pipe_config; 1836 1837 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1838 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1839 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1840 */ 1841 uint8_t mode; // enum mclk_switch_mode 1842 }; 1843 1844 /** 1845 * Config data for Sub-VP and FPO 1846 * Named "v2" for now -- once FPO and SUBVP are fully merged 1847 * the type name can be updated 1848 */ 1849 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1850 uint16_t watermark_a_cache; 1851 uint8_t vertical_int_margin_us; 1852 uint8_t pstate_allow_width_us; 1853 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1854 }; 1855 1856 /** 1857 * DMUB rb command definition for Sub-VP and FPO 1858 * Named "v2" for now -- once FPO and SUBVP are fully merged 1859 * the type name can be updated 1860 */ 1861 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1862 struct dmub_cmd_header header; 1863 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1864 }; 1865 1866 struct dmub_flip_addr_info { 1867 uint32_t surf_addr_lo; 1868 uint32_t surf_addr_c_lo; 1869 uint32_t meta_addr_lo; 1870 uint32_t meta_addr_c_lo; 1871 uint16_t surf_addr_hi; 1872 uint16_t surf_addr_c_hi; 1873 uint16_t meta_addr_hi; 1874 uint16_t meta_addr_c_hi; 1875 }; 1876 1877 struct dmub_fams2_flip_info { 1878 union { 1879 struct { 1880 uint8_t is_immediate: 1; 1881 } bits; 1882 uint8_t all; 1883 } config; 1884 uint8_t otg_inst; 1885 uint8_t pipe_mask; 1886 uint8_t pad; 1887 struct dmub_flip_addr_info addr_info; 1888 }; 1889 1890 struct dmub_rb_cmd_fams2_flip { 1891 struct dmub_cmd_header header; 1892 struct dmub_fams2_flip_info flip_info; 1893 }; 1894 1895 struct dmub_optc_state_v2 { 1896 uint32_t v_total_min; 1897 uint32_t v_total_max; 1898 uint32_t v_total_mid; 1899 uint32_t v_total_mid_frame_num; 1900 uint8_t program_manual_trigger; 1901 uint8_t tg_inst; 1902 uint8_t pad[2]; 1903 }; 1904 1905 struct dmub_optc_position { 1906 uint32_t vpos; 1907 uint32_t hpos; 1908 uint32_t frame; 1909 }; 1910 1911 struct dmub_rb_cmd_fams2_drr_update { 1912 struct dmub_cmd_header header; 1913 struct dmub_optc_state_v2 dmub_optc_state_req; 1914 }; 1915 1916 /* HW and FW global configuration data for FAMS2 */ 1917 /* FAMS2 types and structs */ 1918 enum fams2_stream_type { 1919 FAMS2_STREAM_TYPE_NONE = 0, 1920 FAMS2_STREAM_TYPE_VBLANK = 1, 1921 FAMS2_STREAM_TYPE_VACTIVE = 2, 1922 FAMS2_STREAM_TYPE_DRR = 3, 1923 FAMS2_STREAM_TYPE_SUBVP = 4, 1924 }; 1925 1926 /* static stream state */ 1927 struct dmub_fams2_legacy_stream_static_state { 1928 uint8_t vactive_det_fill_delay_otg_vlines; 1929 uint8_t programming_delay_otg_vlines; 1930 }; //v0 1931 1932 struct dmub_fams2_subvp_stream_static_state { 1933 uint16_t vratio_numerator; 1934 uint16_t vratio_denominator; 1935 uint16_t phantom_vtotal; 1936 uint16_t phantom_vactive; 1937 union { 1938 struct { 1939 uint8_t is_multi_planar : 1; 1940 uint8_t is_yuv420 : 1; 1941 } bits; 1942 uint8_t all; 1943 } config; 1944 uint8_t programming_delay_otg_vlines; 1945 uint8_t prefetch_to_mall_otg_vlines; 1946 uint8_t phantom_otg_inst; 1947 uint8_t phantom_pipe_mask; 1948 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1949 }; //v0 1950 1951 struct dmub_fams2_drr_stream_static_state { 1952 uint16_t nom_stretched_vtotal; 1953 uint8_t programming_delay_otg_vlines; 1954 uint8_t only_stretch_if_required; 1955 uint8_t pad[2]; 1956 }; //v0 1957 1958 struct dmub_fams2_cmd_legacy_stream_static_state { 1959 uint16_t vactive_det_fill_delay_otg_vlines; 1960 uint16_t programming_delay_otg_vlines; 1961 }; //v1 1962 1963 struct dmub_fams2_cmd_subvp_stream_static_state { 1964 uint16_t vratio_numerator; 1965 uint16_t vratio_denominator; 1966 uint16_t phantom_vtotal; 1967 uint16_t phantom_vactive; 1968 uint16_t programming_delay_otg_vlines; 1969 uint16_t prefetch_to_mall_otg_vlines; 1970 union { 1971 struct { 1972 uint8_t is_multi_planar : 1; 1973 uint8_t is_yuv420 : 1; 1974 } bits; 1975 uint8_t all; 1976 } config; 1977 uint8_t phantom_otg_inst; 1978 uint8_t phantom_pipe_mask; 1979 uint8_t pad0; 1980 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1981 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 1982 }; //v1 1983 1984 struct dmub_fams2_cmd_drr_stream_static_state { 1985 uint16_t nom_stretched_vtotal; 1986 uint16_t programming_delay_otg_vlines; 1987 uint8_t only_stretch_if_required; 1988 uint8_t pad[3]; 1989 }; //v1 1990 1991 union dmub_fams2_stream_static_sub_state { 1992 struct dmub_fams2_legacy_stream_static_state legacy; 1993 struct dmub_fams2_subvp_stream_static_state subvp; 1994 struct dmub_fams2_drr_stream_static_state drr; 1995 }; //v0 1996 1997 union dmub_fams2_cmd_stream_static_sub_state { 1998 struct dmub_fams2_cmd_legacy_stream_static_state legacy; 1999 struct dmub_fams2_cmd_subvp_stream_static_state subvp; 2000 struct dmub_fams2_cmd_drr_stream_static_state drr; 2001 }; //v1 2002 2003 struct dmub_fams2_stream_static_state { 2004 enum fams2_stream_type type; 2005 uint32_t otg_vline_time_ns; 2006 uint32_t otg_vline_time_ticks; 2007 uint16_t htotal; 2008 uint16_t vtotal; // nominal vtotal 2009 uint16_t vblank_start; 2010 uint16_t vblank_end; 2011 uint16_t max_vtotal; 2012 uint16_t allow_start_otg_vline; 2013 uint16_t allow_end_otg_vline; 2014 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2015 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2016 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2017 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2018 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2019 union { 2020 struct { 2021 uint8_t is_drr: 1; // stream is DRR enabled 2022 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2023 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2024 } bits; 2025 uint8_t all; 2026 } config; 2027 uint8_t otg_inst; 2028 uint8_t pipe_mask; // pipe mask for the whole config 2029 uint8_t num_planes; 2030 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2031 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2032 union dmub_fams2_stream_static_sub_state sub_state; 2033 }; //v0 2034 2035 struct dmub_fams2_cmd_stream_static_base_state { 2036 enum fams2_stream_type type; 2037 uint32_t otg_vline_time_ns; 2038 uint32_t otg_vline_time_ticks; 2039 uint16_t htotal; 2040 uint16_t vtotal; // nominal vtotal 2041 uint16_t vblank_start; 2042 uint16_t vblank_end; 2043 uint16_t max_vtotal; 2044 uint16_t allow_start_otg_vline; 2045 uint16_t allow_end_otg_vline; 2046 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2047 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2048 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2049 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2050 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2051 union { 2052 struct { 2053 uint8_t is_drr : 1; // stream is DRR enabled 2054 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2055 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2056 } bits; 2057 uint8_t all; 2058 } config; 2059 uint8_t otg_inst; 2060 uint8_t pipe_mask; // pipe mask for the whole config 2061 uint8_t num_planes; 2062 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2063 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2064 }; //v1 2065 2066 struct dmub_fams2_stream_static_state_v1 { 2067 struct dmub_fams2_cmd_stream_static_base_state base; 2068 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2069 }; //v1 2070 2071 /** 2072 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2073 * p-state request to allow latency 2074 */ 2075 enum dmub_fams2_allow_delay_check_mode { 2076 /* No check for request to allow delay */ 2077 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2078 /* Check for request to allow delay */ 2079 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2080 /* Check for prepare to allow delay */ 2081 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2082 }; 2083 2084 union dmub_fams2_global_feature_config { 2085 struct { 2086 uint32_t enable: 1; 2087 uint32_t enable_ppt_check: 1; 2088 uint32_t enable_stall_recovery: 1; 2089 uint32_t enable_debug: 1; 2090 uint32_t enable_offload_flip: 1; 2091 uint32_t enable_visual_confirm: 1; 2092 uint32_t allow_delay_check_mode: 2; 2093 uint32_t reserved: 24; 2094 } bits; 2095 uint32_t all; 2096 }; 2097 2098 struct dmub_cmd_fams2_global_config { 2099 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2100 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2101 uint32_t num_streams; 2102 union dmub_fams2_global_feature_config features; 2103 uint32_t recovery_timeout_us; 2104 uint32_t hwfq_flip_programming_delay_us; 2105 }; 2106 2107 union dmub_cmd_fams2_config { 2108 struct dmub_cmd_fams2_global_config global; 2109 struct dmub_fams2_stream_static_state stream; //v0 2110 union { 2111 struct dmub_fams2_cmd_stream_static_base_state base; 2112 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2113 } stream_v1; //v1 2114 }; 2115 2116 /** 2117 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2118 */ 2119 struct dmub_rb_cmd_fams2 { 2120 struct dmub_cmd_header header; 2121 union dmub_cmd_fams2_config config; 2122 }; 2123 2124 /** 2125 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2126 */ 2127 enum dmub_cmd_idle_opt_type { 2128 /** 2129 * DCN hardware restore. 2130 */ 2131 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2132 2133 /** 2134 * DCN hardware save. 2135 */ 2136 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2137 2138 /** 2139 * DCN hardware notify idle. 2140 */ 2141 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2142 2143 /** 2144 * DCN hardware notify power state. 2145 */ 2146 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2147 }; 2148 2149 /** 2150 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2151 */ 2152 struct dmub_rb_cmd_idle_opt_dcn_restore { 2153 struct dmub_cmd_header header; /**< header */ 2154 }; 2155 2156 /** 2157 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2158 */ 2159 struct dmub_dcn_notify_idle_cntl_data { 2160 uint8_t driver_idle; 2161 uint8_t skip_otg_disable; 2162 uint8_t reserved[58]; 2163 }; 2164 2165 /** 2166 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2167 */ 2168 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2169 struct dmub_cmd_header header; /**< header */ 2170 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2171 }; 2172 2173 /** 2174 * enum dmub_idle_opt_dc_power_state - DC power states. 2175 */ 2176 enum dmub_idle_opt_dc_power_state { 2177 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2178 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2179 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2180 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2181 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2182 }; 2183 2184 /** 2185 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2186 */ 2187 struct dmub_idle_opt_set_dc_power_state_data { 2188 uint8_t power_state; /**< power state */ 2189 uint8_t pad[3]; /**< padding */ 2190 }; 2191 2192 /** 2193 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2194 */ 2195 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2196 struct dmub_cmd_header header; /**< header */ 2197 struct dmub_idle_opt_set_dc_power_state_data data; 2198 }; 2199 2200 /** 2201 * struct dmub_clocks - Clock update notification. 2202 */ 2203 struct dmub_clocks { 2204 uint32_t dispclk_khz; /**< dispclk kHz */ 2205 uint32_t dppclk_khz; /**< dppclk kHz */ 2206 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2207 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2208 }; 2209 2210 /** 2211 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2212 */ 2213 enum dmub_cmd_clk_mgr_type { 2214 /** 2215 * Notify DMCUB of clock update. 2216 */ 2217 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2218 }; 2219 2220 /** 2221 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2222 */ 2223 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2224 struct dmub_cmd_header header; /**< header */ 2225 struct dmub_clocks clocks; /**< clock data */ 2226 }; 2227 2228 /** 2229 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2230 */ 2231 struct dmub_cmd_digx_encoder_control_data { 2232 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2233 }; 2234 2235 /** 2236 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2237 */ 2238 struct dmub_rb_cmd_digx_encoder_control { 2239 struct dmub_cmd_header header; /**< header */ 2240 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2241 }; 2242 2243 /** 2244 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2245 */ 2246 struct dmub_cmd_set_pixel_clock_data { 2247 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2248 }; 2249 2250 /** 2251 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2252 */ 2253 struct dmub_rb_cmd_set_pixel_clock { 2254 struct dmub_cmd_header header; /**< header */ 2255 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2256 }; 2257 2258 /** 2259 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2260 */ 2261 struct dmub_cmd_enable_disp_power_gating_data { 2262 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2263 }; 2264 2265 /** 2266 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2267 */ 2268 struct dmub_rb_cmd_enable_disp_power_gating { 2269 struct dmub_cmd_header header; /**< header */ 2270 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2271 }; 2272 2273 /** 2274 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2275 */ 2276 struct dmub_dig_transmitter_control_data_v1_7 { 2277 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2278 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2279 union { 2280 uint8_t digmode; /**< enum atom_encode_mode_def */ 2281 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2282 } mode_laneset; 2283 uint8_t lanenum; /**< Number of lanes */ 2284 union { 2285 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2286 } symclk_units; 2287 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2288 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2289 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2290 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2291 uint8_t reserved1; /**< For future use */ 2292 uint8_t reserved2[3]; /**< For future use */ 2293 uint32_t reserved3[11]; /**< For future use */ 2294 }; 2295 2296 /** 2297 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2298 */ 2299 union dmub_cmd_dig1_transmitter_control_data { 2300 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2301 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2302 }; 2303 2304 /** 2305 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2306 */ 2307 struct dmub_rb_cmd_dig1_transmitter_control { 2308 struct dmub_cmd_header header; /**< header */ 2309 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2310 }; 2311 2312 /** 2313 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2314 */ 2315 struct dmub_rb_cmd_domain_control_data { 2316 uint8_t inst : 6; /**< DOMAIN instance to control */ 2317 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2318 uint8_t reserved[3]; /**< Reserved for future use */ 2319 }; 2320 2321 /** 2322 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2323 */ 2324 struct dmub_rb_cmd_domain_control { 2325 struct dmub_cmd_header header; /**< header */ 2326 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2327 }; 2328 2329 /** 2330 * DPIA tunnel command parameters. 2331 */ 2332 struct dmub_cmd_dig_dpia_control_data { 2333 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2334 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2335 union { 2336 uint8_t digmode; /** enum atom_encode_mode_def */ 2337 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2338 } mode_laneset; 2339 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2340 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2341 uint8_t hpdsel; /** =0: HPD is not assigned */ 2342 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2343 uint8_t dpia_id; /** Index of DPIA */ 2344 uint8_t fec_rdy : 1; 2345 uint8_t reserved : 7; 2346 uint32_t reserved1; 2347 }; 2348 2349 /** 2350 * DMUB command for DPIA tunnel control. 2351 */ 2352 struct dmub_rb_cmd_dig1_dpia_control { 2353 struct dmub_cmd_header header; 2354 struct dmub_cmd_dig_dpia_control_data dpia_control; 2355 }; 2356 2357 /** 2358 * SET_CONFIG Command Payload (deprecated) 2359 */ 2360 struct set_config_cmd_payload { 2361 uint8_t msg_type; /* set config message type */ 2362 uint8_t msg_data; /* set config message data */ 2363 }; 2364 2365 /** 2366 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2367 */ 2368 struct dmub_cmd_set_config_control_data { 2369 struct set_config_cmd_payload cmd_pkt; 2370 uint8_t instance; /* DPIA instance */ 2371 uint8_t immed_status; /* Immediate status returned in case of error */ 2372 }; 2373 2374 /** 2375 * SET_CONFIG Request Command Payload 2376 */ 2377 struct set_config_request_cmd_payload { 2378 uint8_t instance; /* DPIA instance */ 2379 uint8_t immed_status; /* Immediate status returned in case of error */ 2380 uint8_t msg_type; /* set config message type */ 2381 uint8_t reserved; 2382 uint32_t msg_data; /* set config message data */ 2383 }; 2384 2385 /** 2386 * DMUB command structure for SET_CONFIG command. 2387 */ 2388 struct dmub_rb_cmd_set_config_access { 2389 struct dmub_cmd_header header; /* header */ 2390 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2391 }; 2392 2393 /** 2394 * DMUB command structure for SET_CONFIG request command. 2395 */ 2396 struct dmub_rb_cmd_set_config_request { 2397 struct dmub_cmd_header header; /* header */ 2398 struct set_config_request_cmd_payload payload; /* set config request payload */ 2399 }; 2400 2401 /** 2402 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2403 */ 2404 struct dmub_cmd_mst_alloc_slots_control_data { 2405 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2406 uint8_t instance; /* DPIA instance */ 2407 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2408 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2409 }; 2410 2411 /** 2412 * DMUB command structure for SET_ command. 2413 */ 2414 struct dmub_rb_cmd_set_mst_alloc_slots { 2415 struct dmub_cmd_header header; /* header */ 2416 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2417 }; 2418 2419 /** 2420 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2421 */ 2422 struct dmub_cmd_tps_notification_data { 2423 uint8_t instance; /* DPIA instance */ 2424 uint8_t tps; /* requested training pattern */ 2425 uint8_t reserved1; 2426 uint8_t reserved2; 2427 }; 2428 2429 /** 2430 * DMUB command structure for SET_TPS_NOTIFICATION command. 2431 */ 2432 struct dmub_rb_cmd_set_tps_notification { 2433 struct dmub_cmd_header header; /* header */ 2434 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2435 }; 2436 2437 /** 2438 * DMUB command structure for DPIA HPD int enable control. 2439 */ 2440 struct dmub_rb_cmd_dpia_hpd_int_enable { 2441 struct dmub_cmd_header header; /* header */ 2442 uint32_t enable; /* dpia hpd interrupt enable */ 2443 }; 2444 2445 /** 2446 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2447 */ 2448 struct dmub_rb_cmd_dpphy_init { 2449 struct dmub_cmd_header header; /**< header */ 2450 uint8_t reserved[60]; /**< reserved bits */ 2451 }; 2452 2453 /** 2454 * enum dp_aux_request_action - DP AUX request command listing. 2455 * 2456 * 4 AUX request command bits are shifted to high nibble. 2457 */ 2458 enum dp_aux_request_action { 2459 /** I2C-over-AUX write request */ 2460 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2461 /** I2C-over-AUX read request */ 2462 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2463 /** I2C-over-AUX write status request */ 2464 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2465 /** I2C-over-AUX write request with MOT=1 */ 2466 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2467 /** I2C-over-AUX read request with MOT=1 */ 2468 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2469 /** I2C-over-AUX write status request with MOT=1 */ 2470 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2471 /** Native AUX write request */ 2472 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2473 /** Native AUX read request */ 2474 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2475 }; 2476 2477 /** 2478 * enum aux_return_code_type - DP AUX process return code listing. 2479 */ 2480 enum aux_return_code_type { 2481 /** AUX process succeeded */ 2482 AUX_RET_SUCCESS = 0, 2483 /** AUX process failed with unknown reason */ 2484 AUX_RET_ERROR_UNKNOWN, 2485 /** AUX process completed with invalid reply */ 2486 AUX_RET_ERROR_INVALID_REPLY, 2487 /** AUX process timed out */ 2488 AUX_RET_ERROR_TIMEOUT, 2489 /** HPD was low during AUX process */ 2490 AUX_RET_ERROR_HPD_DISCON, 2491 /** Failed to acquire AUX engine */ 2492 AUX_RET_ERROR_ENGINE_ACQUIRE, 2493 /** AUX request not supported */ 2494 AUX_RET_ERROR_INVALID_OPERATION, 2495 /** AUX process not available */ 2496 AUX_RET_ERROR_PROTOCOL_ERROR, 2497 }; 2498 2499 /** 2500 * enum aux_channel_type - DP AUX channel type listing. 2501 */ 2502 enum aux_channel_type { 2503 /** AUX thru Legacy DP AUX */ 2504 AUX_CHANNEL_LEGACY_DDC, 2505 /** AUX thru DPIA DP tunneling */ 2506 AUX_CHANNEL_DPIA 2507 }; 2508 2509 /** 2510 * struct aux_transaction_parameters - DP AUX request transaction data 2511 */ 2512 struct aux_transaction_parameters { 2513 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2514 uint8_t action; /**< enum dp_aux_request_action */ 2515 uint8_t length; /**< DP AUX request data length */ 2516 uint8_t reserved; /**< For future use */ 2517 uint32_t address; /**< DP AUX address */ 2518 uint8_t data[16]; /**< DP AUX write data */ 2519 }; 2520 2521 /** 2522 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2523 */ 2524 struct dmub_cmd_dp_aux_control_data { 2525 uint8_t instance; /**< AUX instance or DPIA instance */ 2526 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2527 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2528 uint8_t reserved0; /**< For future use */ 2529 uint16_t timeout; /**< timeout time in us */ 2530 uint16_t reserved1; /**< For future use */ 2531 enum aux_channel_type type; /**< enum aux_channel_type */ 2532 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2533 }; 2534 2535 /** 2536 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2537 */ 2538 struct dmub_rb_cmd_dp_aux_access { 2539 /** 2540 * Command header. 2541 */ 2542 struct dmub_cmd_header header; 2543 /** 2544 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2545 */ 2546 struct dmub_cmd_dp_aux_control_data aux_control; 2547 }; 2548 2549 /** 2550 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2551 */ 2552 struct dmub_rb_cmd_outbox1_enable { 2553 /** 2554 * Command header. 2555 */ 2556 struct dmub_cmd_header header; 2557 /** 2558 * enable: 0x0 -> disable outbox1 notification (default value) 2559 * 0x1 -> enable outbox1 notification 2560 */ 2561 uint32_t enable; 2562 }; 2563 2564 /* DP AUX Reply command - OutBox Cmd */ 2565 /** 2566 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2567 */ 2568 struct aux_reply_data { 2569 /** 2570 * Aux cmd 2571 */ 2572 uint8_t command; 2573 /** 2574 * Aux reply data length (max: 16 bytes) 2575 */ 2576 uint8_t length; 2577 /** 2578 * Alignment only 2579 */ 2580 uint8_t pad[2]; 2581 /** 2582 * Aux reply data 2583 */ 2584 uint8_t data[16]; 2585 }; 2586 2587 /** 2588 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2589 */ 2590 struct aux_reply_control_data { 2591 /** 2592 * Reserved for future use 2593 */ 2594 uint32_t handle; 2595 /** 2596 * Aux Instance 2597 */ 2598 uint8_t instance; 2599 /** 2600 * Aux transaction result: definition in enum aux_return_code_type 2601 */ 2602 uint8_t result; 2603 /** 2604 * Alignment only 2605 */ 2606 uint16_t pad; 2607 }; 2608 2609 /** 2610 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2611 */ 2612 struct dmub_rb_cmd_dp_aux_reply { 2613 /** 2614 * Command header. 2615 */ 2616 struct dmub_cmd_header header; 2617 /** 2618 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2619 */ 2620 struct aux_reply_control_data control; 2621 /** 2622 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2623 */ 2624 struct aux_reply_data reply_data; 2625 }; 2626 2627 /* DP HPD Notify command - OutBox Cmd */ 2628 /** 2629 * DP HPD Type 2630 */ 2631 enum dp_hpd_type { 2632 /** 2633 * Normal DP HPD 2634 */ 2635 DP_HPD = 0, 2636 /** 2637 * DP HPD short pulse 2638 */ 2639 DP_IRQ 2640 }; 2641 2642 /** 2643 * DP HPD Status 2644 */ 2645 enum dp_hpd_status { 2646 /** 2647 * DP_HPD status low 2648 */ 2649 DP_HPD_UNPLUG = 0, 2650 /** 2651 * DP_HPD status high 2652 */ 2653 DP_HPD_PLUG 2654 }; 2655 2656 /** 2657 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2658 */ 2659 struct dp_hpd_data { 2660 /** 2661 * DP HPD instance 2662 */ 2663 uint8_t instance; 2664 /** 2665 * HPD type 2666 */ 2667 uint8_t hpd_type; 2668 /** 2669 * HPD status: only for type: DP_HPD to indicate status 2670 */ 2671 uint8_t hpd_status; 2672 /** 2673 * Alignment only 2674 */ 2675 uint8_t pad; 2676 }; 2677 2678 /** 2679 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2680 */ 2681 struct dmub_rb_cmd_dp_hpd_notify { 2682 /** 2683 * Command header. 2684 */ 2685 struct dmub_cmd_header header; 2686 /** 2687 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2688 */ 2689 struct dp_hpd_data hpd_data; 2690 }; 2691 2692 /** 2693 * Definition of a SET_CONFIG reply from DPOA. 2694 */ 2695 enum set_config_status { 2696 SET_CONFIG_PENDING = 0, 2697 SET_CONFIG_ACK_RECEIVED, 2698 SET_CONFIG_RX_TIMEOUT, 2699 SET_CONFIG_UNKNOWN_ERROR, 2700 }; 2701 2702 /** 2703 * Definition of a set_config reply 2704 */ 2705 struct set_config_reply_control_data { 2706 uint8_t instance; /* DPIA Instance */ 2707 uint8_t status; /* Set Config reply */ 2708 uint16_t pad; /* Alignment */ 2709 }; 2710 2711 /** 2712 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2713 */ 2714 struct dmub_rb_cmd_dp_set_config_reply { 2715 struct dmub_cmd_header header; 2716 struct set_config_reply_control_data set_config_reply_control; 2717 }; 2718 2719 /** 2720 * Definition of a DPIA notification header 2721 */ 2722 struct dpia_notification_header { 2723 uint8_t instance; /**< DPIA Instance */ 2724 uint8_t reserved[3]; 2725 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2726 }; 2727 2728 /** 2729 * Definition of the common data struct of DPIA notification 2730 */ 2731 struct dpia_notification_common { 2732 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2733 - sizeof(struct dpia_notification_header)]; 2734 }; 2735 2736 /** 2737 * Definition of a DPIA notification data 2738 */ 2739 struct dpia_bw_allocation_notify_data { 2740 union { 2741 struct { 2742 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2743 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2744 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2745 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2746 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2747 uint16_t reserved: 11; /**< Reserved */ 2748 } bits; 2749 2750 uint16_t flags; 2751 }; 2752 2753 uint8_t cm_id; /**< CM ID */ 2754 uint8_t group_id; /**< Group ID */ 2755 uint8_t granularity; /**< BW Allocation Granularity */ 2756 uint8_t estimated_bw; /**< Estimated_BW */ 2757 uint8_t allocated_bw; /**< Allocated_BW */ 2758 uint8_t reserved; 2759 }; 2760 2761 /** 2762 * union dpia_notify_data_type - DPIA Notification in Outbox command 2763 */ 2764 union dpia_notification_data { 2765 /** 2766 * DPIA Notification for common data struct 2767 */ 2768 struct dpia_notification_common common_data; 2769 2770 /** 2771 * DPIA Notification for DP BW Allocation support 2772 */ 2773 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2774 }; 2775 2776 /** 2777 * Definition of a DPIA notification payload 2778 */ 2779 struct dpia_notification_payload { 2780 struct dpia_notification_header header; 2781 union dpia_notification_data data; /**< DPIA notification payload data */ 2782 }; 2783 2784 /** 2785 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2786 */ 2787 struct dmub_rb_cmd_dpia_notification { 2788 struct dmub_cmd_header header; /**< DPIA notification header */ 2789 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2790 }; 2791 2792 /** 2793 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2794 */ 2795 struct dmub_cmd_hpd_state_query_data { 2796 uint8_t instance; /**< HPD instance or DPIA instance */ 2797 uint8_t result; /**< For returning HPD state */ 2798 uint16_t pad; /** < Alignment */ 2799 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2800 enum aux_return_code_type status; /**< for returning the status of command */ 2801 }; 2802 2803 /** 2804 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2805 */ 2806 struct dmub_rb_cmd_query_hpd_state { 2807 /** 2808 * Command header. 2809 */ 2810 struct dmub_cmd_header header; 2811 /** 2812 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2813 */ 2814 struct dmub_cmd_hpd_state_query_data data; 2815 }; 2816 2817 /** 2818 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2819 */ 2820 struct dmub_rb_cmd_hpd_sense_notify_data { 2821 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2822 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2823 }; 2824 2825 /** 2826 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2827 */ 2828 struct dmub_rb_cmd_hpd_sense_notify { 2829 struct dmub_cmd_header header; /**< header */ 2830 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2831 }; 2832 2833 /* 2834 * Command IDs should be treated as stable ABI. 2835 * Do not reuse or modify IDs. 2836 */ 2837 2838 /** 2839 * PSR command sub-types. 2840 */ 2841 enum dmub_cmd_psr_type { 2842 /** 2843 * Set PSR version support. 2844 */ 2845 DMUB_CMD__PSR_SET_VERSION = 0, 2846 /** 2847 * Copy driver-calculated parameters to PSR state. 2848 */ 2849 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2850 /** 2851 * Enable PSR. 2852 */ 2853 DMUB_CMD__PSR_ENABLE = 2, 2854 2855 /** 2856 * Disable PSR. 2857 */ 2858 DMUB_CMD__PSR_DISABLE = 3, 2859 2860 /** 2861 * Set PSR level. 2862 * PSR level is a 16-bit value dicated by driver that 2863 * will enable/disable different functionality. 2864 */ 2865 DMUB_CMD__PSR_SET_LEVEL = 4, 2866 2867 /** 2868 * Forces PSR enabled until an explicit PSR disable call. 2869 */ 2870 DMUB_CMD__PSR_FORCE_STATIC = 5, 2871 /** 2872 * Set vtotal in psr active for FreeSync PSR. 2873 */ 2874 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2875 /** 2876 * Set PSR power option 2877 */ 2878 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2879 }; 2880 2881 /** 2882 * Different PSR residency modes. 2883 * Different modes change the definition of PSR residency. 2884 */ 2885 enum psr_residency_mode { 2886 PSR_RESIDENCY_MODE_PHY = 0, 2887 PSR_RESIDENCY_MODE_ALPM, 2888 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2889 /* Do not add below. */ 2890 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2891 }; 2892 2893 enum dmub_cmd_fams_type { 2894 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2895 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2896 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2897 /** 2898 * For SubVP set manual trigger in FW because it 2899 * triggers DRR_UPDATE_PENDING which SubVP relies 2900 * on (for any SubVP cases that use a DRR display) 2901 */ 2902 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2903 DMUB_CMD__FAMS2_CONFIG = 4, 2904 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2905 DMUB_CMD__FAMS2_FLIP = 6, 2906 }; 2907 2908 /** 2909 * PSR versions. 2910 */ 2911 enum psr_version { 2912 /** 2913 * PSR version 1. 2914 */ 2915 PSR_VERSION_1 = 0, 2916 /** 2917 * Freesync PSR SU. 2918 */ 2919 PSR_VERSION_SU_1 = 1, 2920 /** 2921 * PSR not supported. 2922 */ 2923 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2924 }; 2925 2926 /** 2927 * PHY Link rate for DP. 2928 */ 2929 enum phy_link_rate { 2930 /** 2931 * not supported. 2932 */ 2933 PHY_RATE_UNKNOWN = 0, 2934 /** 2935 * Rate_1 (RBR) - 1.62 Gbps/Lane 2936 */ 2937 PHY_RATE_162 = 1, 2938 /** 2939 * Rate_2 - 2.16 Gbps/Lane 2940 */ 2941 PHY_RATE_216 = 2, 2942 /** 2943 * Rate_3 - 2.43 Gbps/Lane 2944 */ 2945 PHY_RATE_243 = 3, 2946 /** 2947 * Rate_4 (HBR) - 2.70 Gbps/Lane 2948 */ 2949 PHY_RATE_270 = 4, 2950 /** 2951 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2952 */ 2953 PHY_RATE_324 = 5, 2954 /** 2955 * Rate_6 - 4.32 Gbps/Lane 2956 */ 2957 PHY_RATE_432 = 6, 2958 /** 2959 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2960 */ 2961 PHY_RATE_540 = 7, 2962 /** 2963 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2964 */ 2965 PHY_RATE_810 = 8, 2966 /** 2967 * UHBR10 - 10.0 Gbps/Lane 2968 */ 2969 PHY_RATE_1000 = 9, 2970 /** 2971 * UHBR13.5 - 13.5 Gbps/Lane 2972 */ 2973 PHY_RATE_1350 = 10, 2974 /** 2975 * UHBR10 - 20.0 Gbps/Lane 2976 */ 2977 PHY_RATE_2000 = 11, 2978 2979 PHY_RATE_675 = 12, 2980 /** 2981 * Rate 12 - 6.75 Gbps/Lane 2982 */ 2983 }; 2984 2985 /** 2986 * enum dmub_phy_fsm_state - PHY FSM states. 2987 * PHY FSM state to transit to during PSR enable/disable. 2988 */ 2989 enum dmub_phy_fsm_state { 2990 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2991 DMUB_PHY_FSM_RESET, 2992 DMUB_PHY_FSM_RESET_RELEASED, 2993 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2994 DMUB_PHY_FSM_INITIALIZED, 2995 DMUB_PHY_FSM_CALIBRATED, 2996 DMUB_PHY_FSM_CALIBRATED_LP, 2997 DMUB_PHY_FSM_CALIBRATED_PG, 2998 DMUB_PHY_FSM_POWER_DOWN, 2999 DMUB_PHY_FSM_PLL_EN, 3000 DMUB_PHY_FSM_TX_EN, 3001 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3002 DMUB_PHY_FSM_FAST_LP, 3003 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3004 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3005 DMUB_PHY_FSM_P2_PLL_OFF, 3006 DMUB_PHY_FSM_P2_PLL_ON, 3007 }; 3008 3009 /** 3010 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3011 */ 3012 struct dmub_cmd_psr_copy_settings_data { 3013 /** 3014 * Flags that can be set by driver to change some PSR behaviour. 3015 */ 3016 union dmub_psr_debug_flags debug; 3017 /** 3018 * 16-bit value dicated by driver that will enable/disable different functionality. 3019 */ 3020 uint16_t psr_level; 3021 /** 3022 * DPP HW instance. 3023 */ 3024 uint8_t dpp_inst; 3025 /** 3026 * MPCC HW instance. 3027 * Not used in dmub fw, 3028 * dmub fw will get active opp by reading odm registers. 3029 */ 3030 uint8_t mpcc_inst; 3031 /** 3032 * OPP HW instance. 3033 * Not used in dmub fw, 3034 * dmub fw will get active opp by reading odm registers. 3035 */ 3036 uint8_t opp_inst; 3037 /** 3038 * OTG HW instance. 3039 */ 3040 uint8_t otg_inst; 3041 /** 3042 * DIG FE HW instance. 3043 */ 3044 uint8_t digfe_inst; 3045 /** 3046 * DIG BE HW instance. 3047 */ 3048 uint8_t digbe_inst; 3049 /** 3050 * DP PHY HW instance. 3051 */ 3052 uint8_t dpphy_inst; 3053 /** 3054 * AUX HW instance. 3055 */ 3056 uint8_t aux_inst; 3057 /** 3058 * Determines if SMU optimzations are enabled/disabled. 3059 */ 3060 uint8_t smu_optimizations_en; 3061 /** 3062 * Unused. 3063 * TODO: Remove. 3064 */ 3065 uint8_t frame_delay; 3066 /** 3067 * If RFB setup time is greater than the total VBLANK time, 3068 * it is not possible for the sink to capture the video frame 3069 * in the same frame the SDP is sent. In this case, 3070 * the frame capture indication bit should be set and an extra 3071 * static frame should be transmitted to the sink. 3072 */ 3073 uint8_t frame_cap_ind; 3074 /** 3075 * Granularity of Y offset supported by sink. 3076 */ 3077 uint8_t su_y_granularity; 3078 /** 3079 * Indicates whether sink should start capturing 3080 * immediately following active scan line, 3081 * or starting with the 2nd active scan line. 3082 */ 3083 uint8_t line_capture_indication; 3084 /** 3085 * Multi-display optimizations are implemented on certain ASICs. 3086 */ 3087 uint8_t multi_disp_optimizations_en; 3088 /** 3089 * The last possible line SDP may be transmitted without violating 3090 * the RFB setup time or entering the active video frame. 3091 */ 3092 uint16_t init_sdp_deadline; 3093 /** 3094 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3095 */ 3096 uint8_t rate_control_caps ; 3097 /* 3098 * Force PSRSU always doing full frame update 3099 */ 3100 uint8_t force_ffu_mode; 3101 /** 3102 * Length of each horizontal line in us. 3103 */ 3104 uint32_t line_time_in_us; 3105 /** 3106 * FEC enable status in driver 3107 */ 3108 uint8_t fec_enable_status; 3109 /** 3110 * FEC re-enable delay when PSR exit. 3111 * unit is 100us, range form 0~255(0xFF). 3112 */ 3113 uint8_t fec_enable_delay_in100us; 3114 /** 3115 * PSR control version. 3116 */ 3117 uint8_t cmd_version; 3118 /** 3119 * Panel Instance. 3120 * Panel instance to identify which psr_state to use 3121 * Currently the support is only for 0 or 1 3122 */ 3123 uint8_t panel_inst; 3124 /* 3125 * DSC enable status in driver 3126 */ 3127 uint8_t dsc_enable_status; 3128 /* 3129 * Use FSM state for PSR power up/down 3130 */ 3131 uint8_t use_phy_fsm; 3132 /** 3133 * frame delay for frame re-lock 3134 */ 3135 uint8_t relock_delay_frame_cnt; 3136 /** 3137 * esd recovery indicate. 3138 */ 3139 uint8_t esd_recovery; 3140 /** 3141 * DSC Slice height. 3142 */ 3143 uint16_t dsc_slice_height; 3144 /** 3145 * Some panels request main link off before xth vertical line 3146 */ 3147 uint16_t poweroff_before_vertical_line; 3148 /** 3149 * Some panels cannot handle idle pattern during PSR entry. 3150 * To power down phy before disable stream to avoid sending 3151 * idle pattern. 3152 */ 3153 uint8_t power_down_phy_before_disable_stream; 3154 }; 3155 3156 /** 3157 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3158 */ 3159 struct dmub_rb_cmd_psr_copy_settings { 3160 /** 3161 * Command header. 3162 */ 3163 struct dmub_cmd_header header; 3164 /** 3165 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3166 */ 3167 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3168 }; 3169 3170 /** 3171 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3172 */ 3173 struct dmub_cmd_psr_set_level_data { 3174 /** 3175 * 16-bit value dicated by driver that will enable/disable different functionality. 3176 */ 3177 uint16_t psr_level; 3178 /** 3179 * PSR control version. 3180 */ 3181 uint8_t cmd_version; 3182 /** 3183 * Panel Instance. 3184 * Panel instance to identify which psr_state to use 3185 * Currently the support is only for 0 or 1 3186 */ 3187 uint8_t panel_inst; 3188 }; 3189 3190 /** 3191 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3192 */ 3193 struct dmub_rb_cmd_psr_set_level { 3194 /** 3195 * Command header. 3196 */ 3197 struct dmub_cmd_header header; 3198 /** 3199 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3200 */ 3201 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3202 }; 3203 3204 struct dmub_rb_cmd_psr_enable_data { 3205 /** 3206 * PSR control version. 3207 */ 3208 uint8_t cmd_version; 3209 /** 3210 * Panel Instance. 3211 * Panel instance to identify which psr_state to use 3212 * Currently the support is only for 0 or 1 3213 */ 3214 uint8_t panel_inst; 3215 /** 3216 * Phy state to enter. 3217 * Values to use are defined in dmub_phy_fsm_state 3218 */ 3219 uint8_t phy_fsm_state; 3220 /** 3221 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3222 * Set this using enum phy_link_rate. 3223 * This does not support HDMI/DP2 for now. 3224 */ 3225 uint8_t phy_rate; 3226 }; 3227 3228 /** 3229 * Definition of a DMUB_CMD__PSR_ENABLE command. 3230 * PSR enable/disable is controlled using the sub_type. 3231 */ 3232 struct dmub_rb_cmd_psr_enable { 3233 /** 3234 * Command header. 3235 */ 3236 struct dmub_cmd_header header; 3237 3238 struct dmub_rb_cmd_psr_enable_data data; 3239 }; 3240 3241 /** 3242 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3243 */ 3244 struct dmub_cmd_psr_set_version_data { 3245 /** 3246 * PSR version that FW should implement. 3247 */ 3248 enum psr_version version; 3249 /** 3250 * PSR control version. 3251 */ 3252 uint8_t cmd_version; 3253 /** 3254 * Panel Instance. 3255 * Panel instance to identify which psr_state to use 3256 * Currently the support is only for 0 or 1 3257 */ 3258 uint8_t panel_inst; 3259 /** 3260 * Explicit padding to 4 byte boundary. 3261 */ 3262 uint8_t pad[2]; 3263 }; 3264 3265 /** 3266 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3267 */ 3268 struct dmub_rb_cmd_psr_set_version { 3269 /** 3270 * Command header. 3271 */ 3272 struct dmub_cmd_header header; 3273 /** 3274 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3275 */ 3276 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3277 }; 3278 3279 struct dmub_cmd_psr_force_static_data { 3280 /** 3281 * PSR control version. 3282 */ 3283 uint8_t cmd_version; 3284 /** 3285 * Panel Instance. 3286 * Panel instance to identify which psr_state to use 3287 * Currently the support is only for 0 or 1 3288 */ 3289 uint8_t panel_inst; 3290 /** 3291 * Explicit padding to 4 byte boundary. 3292 */ 3293 uint8_t pad[2]; 3294 }; 3295 3296 /** 3297 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3298 */ 3299 struct dmub_rb_cmd_psr_force_static { 3300 /** 3301 * Command header. 3302 */ 3303 struct dmub_cmd_header header; 3304 /** 3305 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3306 */ 3307 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3308 }; 3309 3310 /** 3311 * PSR SU debug flags. 3312 */ 3313 union dmub_psr_su_debug_flags { 3314 /** 3315 * PSR SU debug flags. 3316 */ 3317 struct { 3318 /** 3319 * Update dirty rect in SW only. 3320 */ 3321 uint8_t update_dirty_rect_only : 1; 3322 /** 3323 * Reset the cursor/plane state before processing the call. 3324 */ 3325 uint8_t reset_state : 1; 3326 } bitfields; 3327 3328 /** 3329 * Union for debug flags. 3330 */ 3331 uint32_t u32All; 3332 }; 3333 3334 /** 3335 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3336 * This triggers a selective update for PSR SU. 3337 */ 3338 struct dmub_cmd_update_dirty_rect_data { 3339 /** 3340 * Dirty rects from OS. 3341 */ 3342 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3343 /** 3344 * PSR SU debug flags. 3345 */ 3346 union dmub_psr_su_debug_flags debug_flags; 3347 /** 3348 * OTG HW instance. 3349 */ 3350 uint8_t pipe_idx; 3351 /** 3352 * Number of dirty rects. 3353 */ 3354 uint8_t dirty_rect_count; 3355 /** 3356 * PSR control version. 3357 */ 3358 uint8_t cmd_version; 3359 /** 3360 * Panel Instance. 3361 * Panel instance to identify which psr_state to use 3362 * Currently the support is only for 0 or 1 3363 */ 3364 uint8_t panel_inst; 3365 }; 3366 3367 /** 3368 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3369 */ 3370 struct dmub_rb_cmd_update_dirty_rect { 3371 /** 3372 * Command header. 3373 */ 3374 struct dmub_cmd_header header; 3375 /** 3376 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3377 */ 3378 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3379 }; 3380 3381 /** 3382 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3383 */ 3384 union dmub_reg_cursor_control_cfg { 3385 struct { 3386 uint32_t cur_enable: 1; 3387 uint32_t reser0: 3; 3388 uint32_t cur_2x_magnify: 1; 3389 uint32_t reser1: 3; 3390 uint32_t mode: 3; 3391 uint32_t reser2: 5; 3392 uint32_t pitch: 2; 3393 uint32_t reser3: 6; 3394 uint32_t line_per_chunk: 5; 3395 uint32_t reser4: 3; 3396 } bits; 3397 uint32_t raw; 3398 }; 3399 struct dmub_cursor_position_cache_hubp { 3400 union dmub_reg_cursor_control_cfg cur_ctl; 3401 union dmub_reg_position_cfg { 3402 struct { 3403 uint32_t cur_x_pos: 16; 3404 uint32_t cur_y_pos: 16; 3405 } bits; 3406 uint32_t raw; 3407 } position; 3408 union dmub_reg_hot_spot_cfg { 3409 struct { 3410 uint32_t hot_x: 16; 3411 uint32_t hot_y: 16; 3412 } bits; 3413 uint32_t raw; 3414 } hot_spot; 3415 union dmub_reg_dst_offset_cfg { 3416 struct { 3417 uint32_t dst_x_offset: 13; 3418 uint32_t reserved: 19; 3419 } bits; 3420 uint32_t raw; 3421 } dst_offset; 3422 }; 3423 3424 union dmub_reg_cur0_control_cfg { 3425 struct { 3426 uint32_t cur0_enable: 1; 3427 uint32_t expansion_mode: 1; 3428 uint32_t reser0: 1; 3429 uint32_t cur0_rom_en: 1; 3430 uint32_t mode: 3; 3431 uint32_t reserved: 25; 3432 } bits; 3433 uint32_t raw; 3434 }; 3435 struct dmub_cursor_position_cache_dpp { 3436 union dmub_reg_cur0_control_cfg cur0_ctl; 3437 }; 3438 struct dmub_cursor_position_cfg { 3439 struct dmub_cursor_position_cache_hubp pHubp; 3440 struct dmub_cursor_position_cache_dpp pDpp; 3441 uint8_t pipe_idx; 3442 /* 3443 * Padding is required. To be 4 Bytes Aligned. 3444 */ 3445 uint8_t padding[3]; 3446 }; 3447 3448 struct dmub_cursor_attribute_cache_hubp { 3449 uint32_t SURFACE_ADDR_HIGH; 3450 uint32_t SURFACE_ADDR; 3451 union dmub_reg_cursor_control_cfg cur_ctl; 3452 union dmub_reg_cursor_size_cfg { 3453 struct { 3454 uint32_t width: 16; 3455 uint32_t height: 16; 3456 } bits; 3457 uint32_t raw; 3458 } size; 3459 union dmub_reg_cursor_settings_cfg { 3460 struct { 3461 uint32_t dst_y_offset: 8; 3462 uint32_t chunk_hdl_adjust: 2; 3463 uint32_t reserved: 22; 3464 } bits; 3465 uint32_t raw; 3466 } settings; 3467 }; 3468 struct dmub_cursor_attribute_cache_dpp { 3469 union dmub_reg_cur0_control_cfg cur0_ctl; 3470 }; 3471 struct dmub_cursor_attributes_cfg { 3472 struct dmub_cursor_attribute_cache_hubp aHubp; 3473 struct dmub_cursor_attribute_cache_dpp aDpp; 3474 }; 3475 3476 struct dmub_cmd_update_cursor_payload0 { 3477 /** 3478 * Cursor dirty rects. 3479 */ 3480 struct dmub_rect cursor_rect; 3481 /** 3482 * PSR SU debug flags. 3483 */ 3484 union dmub_psr_su_debug_flags debug_flags; 3485 /** 3486 * Cursor enable/disable. 3487 */ 3488 uint8_t enable; 3489 /** 3490 * OTG HW instance. 3491 */ 3492 uint8_t pipe_idx; 3493 /** 3494 * PSR control version. 3495 */ 3496 uint8_t cmd_version; 3497 /** 3498 * Panel Instance. 3499 * Panel instance to identify which psr_state to use 3500 * Currently the support is only for 0 or 1 3501 */ 3502 uint8_t panel_inst; 3503 /** 3504 * Cursor Position Register. 3505 * Registers contains Hubp & Dpp modules 3506 */ 3507 struct dmub_cursor_position_cfg position_cfg; 3508 }; 3509 3510 struct dmub_cmd_update_cursor_payload1 { 3511 struct dmub_cursor_attributes_cfg attribute_cfg; 3512 }; 3513 3514 union dmub_cmd_update_cursor_info_data { 3515 struct dmub_cmd_update_cursor_payload0 payload0; 3516 struct dmub_cmd_update_cursor_payload1 payload1; 3517 }; 3518 /** 3519 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3520 */ 3521 struct dmub_rb_cmd_update_cursor_info { 3522 /** 3523 * Command header. 3524 */ 3525 struct dmub_cmd_header header; 3526 /** 3527 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3528 */ 3529 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3530 }; 3531 3532 /** 3533 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3534 */ 3535 struct dmub_cmd_psr_set_vtotal_data { 3536 /** 3537 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3538 */ 3539 uint16_t psr_vtotal_idle; 3540 /** 3541 * PSR control version. 3542 */ 3543 uint8_t cmd_version; 3544 /** 3545 * Panel Instance. 3546 * Panel instance to identify which psr_state to use 3547 * Currently the support is only for 0 or 1 3548 */ 3549 uint8_t panel_inst; 3550 /* 3551 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3552 */ 3553 uint16_t psr_vtotal_su; 3554 /** 3555 * Explicit padding to 4 byte boundary. 3556 */ 3557 uint8_t pad2[2]; 3558 }; 3559 3560 /** 3561 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3562 */ 3563 struct dmub_rb_cmd_psr_set_vtotal { 3564 /** 3565 * Command header. 3566 */ 3567 struct dmub_cmd_header header; 3568 /** 3569 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3570 */ 3571 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3572 }; 3573 3574 /** 3575 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3576 */ 3577 struct dmub_cmd_psr_set_power_opt_data { 3578 /** 3579 * PSR control version. 3580 */ 3581 uint8_t cmd_version; 3582 /** 3583 * Panel Instance. 3584 * Panel instance to identify which psr_state to use 3585 * Currently the support is only for 0 or 1 3586 */ 3587 uint8_t panel_inst; 3588 /** 3589 * Explicit padding to 4 byte boundary. 3590 */ 3591 uint8_t pad[2]; 3592 /** 3593 * PSR power option 3594 */ 3595 uint32_t power_opt; 3596 }; 3597 3598 /** 3599 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3600 */ 3601 struct dmub_rb_cmd_psr_set_power_opt { 3602 /** 3603 * Command header. 3604 */ 3605 struct dmub_cmd_header header; 3606 /** 3607 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3608 */ 3609 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3610 }; 3611 3612 /** 3613 * Definition of Replay Residency GPINT command. 3614 * Bit[0] - Residency mode for Revision 0 3615 * Bit[1] - Enable/Disable state 3616 * Bit[2-3] - Revision number 3617 * Bit[4-7] - Residency mode for Revision 1 3618 * Bit[8] - Panel instance 3619 * Bit[9-15] - Reserved 3620 */ 3621 3622 enum pr_residency_mode { 3623 PR_RESIDENCY_MODE_PHY = 0x0, 3624 PR_RESIDENCY_MODE_ALPM, 3625 PR_RESIDENCY_MODE_IPS2, 3626 PR_RESIDENCY_MODE_FRAME_CNT, 3627 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3628 }; 3629 3630 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3631 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3632 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3633 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3634 3635 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3636 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3637 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3638 3639 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3640 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3641 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3642 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3643 3644 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3645 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3646 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3647 3648 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3649 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3650 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3651 3652 /** 3653 * Definition of a replay_state. 3654 */ 3655 enum replay_state { 3656 REPLAY_STATE_0 = 0x0, 3657 REPLAY_STATE_1 = 0x10, 3658 REPLAY_STATE_1A = 0x11, 3659 REPLAY_STATE_2 = 0x20, 3660 REPLAY_STATE_2A = 0x21, 3661 REPLAY_STATE_3 = 0x30, 3662 REPLAY_STATE_3INIT = 0x31, 3663 REPLAY_STATE_4 = 0x40, 3664 REPLAY_STATE_4A = 0x41, 3665 REPLAY_STATE_4B = 0x42, 3666 REPLAY_STATE_4C = 0x43, 3667 REPLAY_STATE_4D = 0x44, 3668 REPLAY_STATE_4E = 0x45, 3669 REPLAY_STATE_4B_LOCKED = 0x4A, 3670 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3671 REPLAY_STATE_5 = 0x50, 3672 REPLAY_STATE_5A = 0x51, 3673 REPLAY_STATE_5B = 0x52, 3674 REPLAY_STATE_5A_LOCKED = 0x5A, 3675 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3676 REPLAY_STATE_6 = 0x60, 3677 REPLAY_STATE_6A = 0x61, 3678 REPLAY_STATE_6B = 0x62, 3679 REPLAY_STATE_INVALID = 0xFF, 3680 }; 3681 3682 /** 3683 * Replay command sub-types. 3684 */ 3685 enum dmub_cmd_replay_type { 3686 /** 3687 * Copy driver-calculated parameters to REPLAY state. 3688 */ 3689 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3690 /** 3691 * Enable REPLAY. 3692 */ 3693 DMUB_CMD__REPLAY_ENABLE = 1, 3694 /** 3695 * Set Replay power option. 3696 */ 3697 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3698 /** 3699 * Set coasting vtotal. 3700 */ 3701 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3702 /** 3703 * Set power opt and coasting vtotal. 3704 */ 3705 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3706 /** 3707 * Set disabled iiming sync. 3708 */ 3709 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3710 /** 3711 * Set Residency Frameupdate Timer. 3712 */ 3713 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3714 /** 3715 * Set pseudo vtotal 3716 */ 3717 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3718 /** 3719 * Set adaptive sync sdp enabled 3720 */ 3721 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3722 /** 3723 * Set Replay General command. 3724 */ 3725 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3726 }; 3727 3728 /** 3729 * Replay general command sub-types. 3730 */ 3731 enum dmub_cmd_replay_general_subtype { 3732 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3733 /** 3734 * TODO: For backward compatible, allow new command only. 3735 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3736 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3737 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3738 */ 3739 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3740 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3741 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 3742 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 3743 }; 3744 3745 /** 3746 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3747 */ 3748 struct dmub_cmd_replay_copy_settings_data { 3749 /** 3750 * Flags that can be set by driver to change some replay behaviour. 3751 */ 3752 union replay_debug_flags debug; 3753 3754 /** 3755 * @flags: Flags used to determine feature functionality. 3756 */ 3757 union replay_hw_flags flags; 3758 3759 /** 3760 * DPP HW instance. 3761 */ 3762 uint8_t dpp_inst; 3763 /** 3764 * OTG HW instance. 3765 */ 3766 uint8_t otg_inst; 3767 /** 3768 * DIG FE HW instance. 3769 */ 3770 uint8_t digfe_inst; 3771 /** 3772 * DIG BE HW instance. 3773 */ 3774 uint8_t digbe_inst; 3775 /** 3776 * AUX HW instance. 3777 */ 3778 uint8_t aux_inst; 3779 /** 3780 * Panel Instance. 3781 * Panel isntance to identify which psr_state to use 3782 * Currently the support is only for 0 or 1 3783 */ 3784 uint8_t panel_inst; 3785 /** 3786 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3787 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3788 */ 3789 uint8_t pixel_deviation_per_line; 3790 /** 3791 * @max_deviation_line: The max number of deviation line that can keep the timing 3792 * synchronized between the Source and Sink during Replay normal sleep mode. 3793 */ 3794 uint8_t max_deviation_line; 3795 /** 3796 * Length of each horizontal line in ns. 3797 */ 3798 uint32_t line_time_in_ns; 3799 /** 3800 * PHY instance. 3801 */ 3802 uint8_t dpphy_inst; 3803 /** 3804 * Determines if SMU optimzations are enabled/disabled. 3805 */ 3806 uint8_t smu_optimizations_en; 3807 /** 3808 * Determines if timing sync are enabled/disabled. 3809 */ 3810 uint8_t replay_timing_sync_supported; 3811 /* 3812 * Use FSM state for Replay power up/down 3813 */ 3814 uint8_t use_phy_fsm; 3815 }; 3816 3817 /** 3818 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3819 */ 3820 struct dmub_rb_cmd_replay_copy_settings { 3821 /** 3822 * Command header. 3823 */ 3824 struct dmub_cmd_header header; 3825 /** 3826 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3827 */ 3828 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3829 }; 3830 3831 /** 3832 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3833 */ 3834 enum replay_enable { 3835 /** 3836 * Disable REPLAY. 3837 */ 3838 REPLAY_DISABLE = 0, 3839 /** 3840 * Enable REPLAY. 3841 */ 3842 REPLAY_ENABLE = 1, 3843 }; 3844 3845 /** 3846 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3847 */ 3848 struct dmub_rb_cmd_replay_enable_data { 3849 /** 3850 * Replay enable or disable. 3851 */ 3852 uint8_t enable; 3853 /** 3854 * Panel Instance. 3855 * Panel isntance to identify which replay_state to use 3856 * Currently the support is only for 0 or 1 3857 */ 3858 uint8_t panel_inst; 3859 /** 3860 * Phy state to enter. 3861 * Values to use are defined in dmub_phy_fsm_state 3862 */ 3863 uint8_t phy_fsm_state; 3864 /** 3865 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3866 * Set this using enum phy_link_rate. 3867 * This does not support HDMI/DP2 for now. 3868 */ 3869 uint8_t phy_rate; 3870 }; 3871 3872 /** 3873 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3874 * Replay enable/disable is controlled using action in data. 3875 */ 3876 struct dmub_rb_cmd_replay_enable { 3877 /** 3878 * Command header. 3879 */ 3880 struct dmub_cmd_header header; 3881 3882 struct dmub_rb_cmd_replay_enable_data data; 3883 }; 3884 3885 /** 3886 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3887 */ 3888 struct dmub_cmd_replay_set_power_opt_data { 3889 /** 3890 * Panel Instance. 3891 * Panel isntance to identify which replay_state to use 3892 * Currently the support is only for 0 or 1 3893 */ 3894 uint8_t panel_inst; 3895 /** 3896 * Explicit padding to 4 byte boundary. 3897 */ 3898 uint8_t pad[3]; 3899 /** 3900 * REPLAY power option 3901 */ 3902 uint32_t power_opt; 3903 }; 3904 3905 /** 3906 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3907 */ 3908 struct dmub_cmd_replay_set_timing_sync_data { 3909 /** 3910 * Panel Instance. 3911 * Panel isntance to identify which replay_state to use 3912 * Currently the support is only for 0 or 1 3913 */ 3914 uint8_t panel_inst; 3915 /** 3916 * REPLAY set_timing_sync 3917 */ 3918 uint8_t timing_sync_supported; 3919 /** 3920 * Explicit padding to 4 byte boundary. 3921 */ 3922 uint8_t pad[2]; 3923 }; 3924 3925 /** 3926 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3927 */ 3928 struct dmub_cmd_replay_set_pseudo_vtotal { 3929 /** 3930 * Panel Instance. 3931 * Panel isntance to identify which replay_state to use 3932 * Currently the support is only for 0 or 1 3933 */ 3934 uint8_t panel_inst; 3935 /** 3936 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3937 */ 3938 uint16_t vtotal; 3939 /** 3940 * Explicit padding to 4 byte boundary. 3941 */ 3942 uint8_t pad; 3943 }; 3944 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3945 /** 3946 * Panel Instance. 3947 * Panel isntance to identify which replay_state to use 3948 * Currently the support is only for 0 or 1 3949 */ 3950 uint8_t panel_inst; 3951 /** 3952 * enabled: set adaptive sync sdp enabled 3953 */ 3954 uint8_t force_disabled; 3955 3956 uint8_t pad[2]; 3957 }; 3958 struct dmub_cmd_replay_set_general_cmd_data { 3959 /** 3960 * Panel Instance. 3961 * Panel isntance to identify which replay_state to use 3962 * Currently the support is only for 0 or 1 3963 */ 3964 uint8_t panel_inst; 3965 /** 3966 * subtype: replay general cmd sub type 3967 */ 3968 uint8_t subtype; 3969 3970 uint8_t pad[2]; 3971 /** 3972 * config data with param1 and param2 3973 */ 3974 uint32_t param1; 3975 3976 uint32_t param2; 3977 }; 3978 3979 /** 3980 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3981 */ 3982 struct dmub_rb_cmd_replay_set_power_opt { 3983 /** 3984 * Command header. 3985 */ 3986 struct dmub_cmd_header header; 3987 /** 3988 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3989 */ 3990 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3991 }; 3992 3993 /** 3994 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3995 */ 3996 struct dmub_cmd_replay_set_coasting_vtotal_data { 3997 /** 3998 * 16-bit value dicated by driver that indicates the coasting vtotal. 3999 */ 4000 uint16_t coasting_vtotal; 4001 /** 4002 * REPLAY control version. 4003 */ 4004 uint8_t cmd_version; 4005 /** 4006 * Panel Instance. 4007 * Panel isntance to identify which replay_state to use 4008 * Currently the support is only for 0 or 1 4009 */ 4010 uint8_t panel_inst; 4011 /** 4012 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4013 */ 4014 uint16_t coasting_vtotal_high; 4015 /** 4016 * Explicit padding to 4 byte boundary. 4017 */ 4018 uint8_t pad[2]; 4019 }; 4020 4021 /** 4022 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4023 */ 4024 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4025 /** 4026 * Command header. 4027 */ 4028 struct dmub_cmd_header header; 4029 /** 4030 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4031 */ 4032 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4033 }; 4034 4035 /** 4036 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4037 */ 4038 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4039 /** 4040 * Command header. 4041 */ 4042 struct dmub_cmd_header header; 4043 /** 4044 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4045 */ 4046 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4047 /** 4048 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4049 */ 4050 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4051 }; 4052 4053 /** 4054 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4055 */ 4056 struct dmub_rb_cmd_replay_set_timing_sync { 4057 /** 4058 * Command header. 4059 */ 4060 struct dmub_cmd_header header; 4061 /** 4062 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4063 */ 4064 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4065 }; 4066 4067 /** 4068 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4069 */ 4070 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4071 /** 4072 * Command header. 4073 */ 4074 struct dmub_cmd_header header; 4075 /** 4076 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4077 */ 4078 struct dmub_cmd_replay_set_pseudo_vtotal data; 4079 }; 4080 4081 /** 4082 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4083 */ 4084 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4085 /** 4086 * Command header. 4087 */ 4088 struct dmub_cmd_header header; 4089 /** 4090 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4091 */ 4092 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4093 }; 4094 4095 /** 4096 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4097 */ 4098 struct dmub_rb_cmd_replay_set_general_cmd { 4099 /** 4100 * Command header. 4101 */ 4102 struct dmub_cmd_header header; 4103 /** 4104 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4105 */ 4106 struct dmub_cmd_replay_set_general_cmd_data data; 4107 }; 4108 4109 /** 4110 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4111 */ 4112 struct dmub_cmd_replay_frameupdate_timer_data { 4113 /** 4114 * Panel Instance. 4115 * Panel isntance to identify which replay_state to use 4116 * Currently the support is only for 0 or 1 4117 */ 4118 uint8_t panel_inst; 4119 /** 4120 * Replay Frameupdate Timer Enable or not 4121 */ 4122 uint8_t enable; 4123 /** 4124 * REPLAY force reflash frame update number 4125 */ 4126 uint16_t frameupdate_count; 4127 }; 4128 /** 4129 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4130 */ 4131 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4132 /** 4133 * Command header. 4134 */ 4135 struct dmub_cmd_header header; 4136 /** 4137 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4138 */ 4139 struct dmub_cmd_replay_frameupdate_timer_data data; 4140 }; 4141 4142 /** 4143 * Definition union of replay command set 4144 */ 4145 union dmub_replay_cmd_set { 4146 /** 4147 * Panel Instance. 4148 * Panel isntance to identify which replay_state to use 4149 * Currently the support is only for 0 or 1 4150 */ 4151 uint8_t panel_inst; 4152 /** 4153 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4154 */ 4155 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4156 /** 4157 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4158 */ 4159 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4160 /** 4161 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4162 */ 4163 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4164 /** 4165 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4166 */ 4167 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4168 /** 4169 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4170 */ 4171 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4172 }; 4173 4174 /** 4175 * Set of HW components that can be locked. 4176 * 4177 * Note: If updating with more HW components, fields 4178 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4179 */ 4180 union dmub_hw_lock_flags { 4181 /** 4182 * Set of HW components that can be locked. 4183 */ 4184 struct { 4185 /** 4186 * Lock/unlock OTG master update lock. 4187 */ 4188 uint8_t lock_pipe : 1; 4189 /** 4190 * Lock/unlock cursor. 4191 */ 4192 uint8_t lock_cursor : 1; 4193 /** 4194 * Lock/unlock global update lock. 4195 */ 4196 uint8_t lock_dig : 1; 4197 /** 4198 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4199 */ 4200 uint8_t triple_buffer_lock : 1; 4201 } bits; 4202 4203 /** 4204 * Union for HW Lock flags. 4205 */ 4206 uint8_t u8All; 4207 }; 4208 4209 /** 4210 * Instances of HW to be locked. 4211 * 4212 * Note: If updating with more HW components, fields 4213 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4214 */ 4215 struct dmub_hw_lock_inst_flags { 4216 /** 4217 * OTG HW instance for OTG master update lock. 4218 */ 4219 uint8_t otg_inst; 4220 /** 4221 * OPP instance for cursor lock. 4222 */ 4223 uint8_t opp_inst; 4224 /** 4225 * OTG HW instance for global update lock. 4226 * TODO: Remove, and re-use otg_inst. 4227 */ 4228 uint8_t dig_inst; 4229 /** 4230 * Explicit pad to 4 byte boundary. 4231 */ 4232 uint8_t pad; 4233 }; 4234 4235 /** 4236 * Clients that can acquire the HW Lock Manager. 4237 * 4238 * Note: If updating with more clients, fields in 4239 * dmub_inbox0_cmd_lock_hw must be updated to match. 4240 */ 4241 enum hw_lock_client { 4242 /** 4243 * Driver is the client of HW Lock Manager. 4244 */ 4245 HW_LOCK_CLIENT_DRIVER = 0, 4246 /** 4247 * PSR SU is the client of HW Lock Manager. 4248 */ 4249 HW_LOCK_CLIENT_PSR_SU = 1, 4250 HW_LOCK_CLIENT_SUBVP = 3, 4251 /** 4252 * Replay is the client of HW Lock Manager. 4253 */ 4254 HW_LOCK_CLIENT_REPLAY = 4, 4255 HW_LOCK_CLIENT_FAMS2 = 5, 4256 /** 4257 * Invalid client. 4258 */ 4259 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4260 }; 4261 4262 /** 4263 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4264 */ 4265 struct dmub_cmd_lock_hw_data { 4266 /** 4267 * Specifies the client accessing HW Lock Manager. 4268 */ 4269 enum hw_lock_client client; 4270 /** 4271 * HW instances to be locked. 4272 */ 4273 struct dmub_hw_lock_inst_flags inst_flags; 4274 /** 4275 * Which components to be locked. 4276 */ 4277 union dmub_hw_lock_flags hw_locks; 4278 /** 4279 * Specifies lock/unlock. 4280 */ 4281 uint8_t lock; 4282 /** 4283 * HW can be unlocked separately from releasing the HW Lock Mgr. 4284 * This flag is set if the client wishes to release the object. 4285 */ 4286 uint8_t should_release; 4287 /** 4288 * Explicit padding to 4 byte boundary. 4289 */ 4290 uint8_t pad; 4291 }; 4292 4293 /** 4294 * Definition of a DMUB_CMD__HW_LOCK command. 4295 * Command is used by driver and FW. 4296 */ 4297 struct dmub_rb_cmd_lock_hw { 4298 /** 4299 * Command header. 4300 */ 4301 struct dmub_cmd_header header; 4302 /** 4303 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4304 */ 4305 struct dmub_cmd_lock_hw_data lock_hw_data; 4306 }; 4307 4308 /** 4309 * ABM command sub-types. 4310 */ 4311 enum dmub_cmd_abm_type { 4312 /** 4313 * Initialize parameters for ABM algorithm. 4314 * Data is passed through an indirect buffer. 4315 */ 4316 DMUB_CMD__ABM_INIT_CONFIG = 0, 4317 /** 4318 * Set OTG and panel HW instance. 4319 */ 4320 DMUB_CMD__ABM_SET_PIPE = 1, 4321 /** 4322 * Set user requested backklight level. 4323 */ 4324 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4325 /** 4326 * Set ABM operating/aggression level. 4327 */ 4328 DMUB_CMD__ABM_SET_LEVEL = 3, 4329 /** 4330 * Set ambient light level. 4331 */ 4332 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4333 /** 4334 * Enable/disable fractional duty cycle for backlight PWM. 4335 */ 4336 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4337 4338 /** 4339 * unregister vertical interrupt after steady state is reached 4340 */ 4341 DMUB_CMD__ABM_PAUSE = 6, 4342 4343 /** 4344 * Save and Restore ABM state. On save we save parameters, and 4345 * on restore we update state with passed in data. 4346 */ 4347 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4348 4349 /** 4350 * Query ABM caps. 4351 */ 4352 DMUB_CMD__ABM_QUERY_CAPS = 8, 4353 4354 /** 4355 * Set ABM Events 4356 */ 4357 DMUB_CMD__ABM_SET_EVENT = 9, 4358 4359 /** 4360 * Get the current ACE curve. 4361 */ 4362 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4363 }; 4364 4365 struct abm_ace_curve { 4366 /** 4367 * @offsets: ACE curve offsets. 4368 */ 4369 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4370 4371 /** 4372 * @thresholds: ACE curve thresholds. 4373 */ 4374 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4375 4376 /** 4377 * @slopes: ACE curve slopes. 4378 */ 4379 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4380 }; 4381 4382 struct fixed_pt_format { 4383 /** 4384 * @sign_bit: Indicates whether one bit is reserved for the sign. 4385 */ 4386 bool sign_bit; 4387 4388 /** 4389 * @num_int_bits: Number of bits used for integer part. 4390 */ 4391 uint8_t num_int_bits; 4392 4393 /** 4394 * @num_frac_bits: Number of bits used for fractional part. 4395 */ 4396 uint8_t num_frac_bits; 4397 4398 /** 4399 * @pad: Explicit padding to 4 byte boundary. 4400 */ 4401 uint8_t pad; 4402 }; 4403 4404 struct abm_caps { 4405 /** 4406 * @num_hg_bins: Number of histogram bins. 4407 */ 4408 uint8_t num_hg_bins; 4409 4410 /** 4411 * @num_ace_segments: Number of ACE curve segments. 4412 */ 4413 uint8_t num_ace_segments; 4414 4415 /** 4416 * @pad: Explicit padding to 4 byte boundary. 4417 */ 4418 uint8_t pad[2]; 4419 4420 /** 4421 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4422 */ 4423 struct fixed_pt_format ace_thresholds_format; 4424 4425 /** 4426 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4427 */ 4428 struct fixed_pt_format ace_offsets_format; 4429 4430 /** 4431 * @ace_slopes_format: Format of the ACE slopes. 4432 */ 4433 struct fixed_pt_format ace_slopes_format; 4434 }; 4435 4436 /** 4437 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4438 * Requirements: 4439 * - Padded explicitly to 32-bit boundary. 4440 * - Must ensure this structure matches the one on driver-side, 4441 * otherwise it won't be aligned. 4442 */ 4443 struct abm_config_table { 4444 /** 4445 * Gamma curve thresholds, used for crgb conversion. 4446 */ 4447 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4448 /** 4449 * Gamma curve offsets, used for crgb conversion. 4450 */ 4451 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4452 /** 4453 * Gamma curve slopes, used for crgb conversion. 4454 */ 4455 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4456 /** 4457 * Custom backlight curve thresholds. 4458 */ 4459 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4460 /** 4461 * Custom backlight curve offsets. 4462 */ 4463 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4464 /** 4465 * Ambient light thresholds. 4466 */ 4467 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4468 /** 4469 * Minimum programmable backlight. 4470 */ 4471 uint16_t min_abm_backlight; // 122B 4472 /** 4473 * Minimum reduction values. 4474 */ 4475 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4476 /** 4477 * Maximum reduction values. 4478 */ 4479 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4480 /** 4481 * Bright positive gain. 4482 */ 4483 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4484 /** 4485 * Dark negative gain. 4486 */ 4487 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4488 /** 4489 * Hybrid factor. 4490 */ 4491 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4492 /** 4493 * Contrast factor. 4494 */ 4495 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4496 /** 4497 * Deviation gain. 4498 */ 4499 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4500 /** 4501 * Minimum knee. 4502 */ 4503 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4504 /** 4505 * Maximum knee. 4506 */ 4507 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4508 /** 4509 * Unused. 4510 */ 4511 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4512 /** 4513 * Explicit padding to 4 byte boundary. 4514 */ 4515 uint8_t pad3[3]; // 229B 4516 /** 4517 * Backlight ramp reduction. 4518 */ 4519 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4520 /** 4521 * Backlight ramp start. 4522 */ 4523 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4524 }; 4525 4526 /** 4527 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4528 */ 4529 struct dmub_cmd_abm_set_pipe_data { 4530 /** 4531 * OTG HW instance. 4532 */ 4533 uint8_t otg_inst; 4534 4535 /** 4536 * Panel Control HW instance. 4537 */ 4538 uint8_t panel_inst; 4539 4540 /** 4541 * Controls how ABM will interpret a set pipe or set level command. 4542 */ 4543 uint8_t set_pipe_option; 4544 4545 /** 4546 * Unused. 4547 * TODO: Remove. 4548 */ 4549 uint8_t ramping_boundary; 4550 4551 /** 4552 * PwrSeq HW Instance. 4553 */ 4554 uint8_t pwrseq_inst; 4555 4556 /** 4557 * Explicit padding to 4 byte boundary. 4558 */ 4559 uint8_t pad[3]; 4560 }; 4561 4562 /** 4563 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4564 */ 4565 struct dmub_rb_cmd_abm_set_pipe { 4566 /** 4567 * Command header. 4568 */ 4569 struct dmub_cmd_header header; 4570 4571 /** 4572 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4573 */ 4574 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4575 }; 4576 4577 /** 4578 * Type of backlight control method to be used by ABM module 4579 */ 4580 enum dmub_backlight_control_type { 4581 /** 4582 * PWM Backlight control 4583 */ 4584 DMU_BACKLIGHT_CONTROL_PWM = 0, 4585 /** 4586 * VESA Aux-based backlight control 4587 */ 4588 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4589 /** 4590 * AMD DPCD Aux-based backlight control 4591 */ 4592 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4593 }; 4594 4595 /** 4596 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4597 */ 4598 struct dmub_cmd_abm_set_backlight_data { 4599 /** 4600 * Number of frames to ramp to backlight user level. 4601 */ 4602 uint32_t frame_ramp; 4603 4604 /** 4605 * Requested backlight level from user. 4606 */ 4607 uint32_t backlight_user_level; 4608 4609 /** 4610 * ABM control version. 4611 */ 4612 uint8_t version; 4613 4614 /** 4615 * Panel Control HW instance mask. 4616 * Bit 0 is Panel Control HW instance 0. 4617 * Bit 1 is Panel Control HW instance 1. 4618 */ 4619 uint8_t panel_mask; 4620 4621 /** 4622 * AUX HW Instance. 4623 */ 4624 uint8_t aux_inst; 4625 4626 /** 4627 * Explicit padding to 4 byte boundary. 4628 */ 4629 uint8_t pad[1]; 4630 4631 /** 4632 * Backlight control type. 4633 * Value 0 is PWM backlight control. 4634 * Value 1 is VAUX backlight control. 4635 * Value 2 is AMD DPCD AUX backlight control. 4636 */ 4637 enum dmub_backlight_control_type backlight_control_type; 4638 4639 /** 4640 * Minimum luminance in nits. 4641 */ 4642 uint32_t min_luminance; 4643 4644 /** 4645 * Maximum luminance in nits. 4646 */ 4647 uint32_t max_luminance; 4648 4649 /** 4650 * Minimum backlight in pwm. 4651 */ 4652 uint32_t min_backlight_pwm; 4653 4654 /** 4655 * Maximum backlight in pwm. 4656 */ 4657 uint32_t max_backlight_pwm; 4658 }; 4659 4660 /** 4661 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4662 */ 4663 struct dmub_rb_cmd_abm_set_backlight { 4664 /** 4665 * Command header. 4666 */ 4667 struct dmub_cmd_header header; 4668 4669 /** 4670 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4671 */ 4672 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4673 }; 4674 4675 /** 4676 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4677 */ 4678 struct dmub_cmd_abm_set_level_data { 4679 /** 4680 * Set current ABM operating/aggression level. 4681 */ 4682 uint32_t level; 4683 4684 /** 4685 * ABM control version. 4686 */ 4687 uint8_t version; 4688 4689 /** 4690 * Panel Control HW instance mask. 4691 * Bit 0 is Panel Control HW instance 0. 4692 * Bit 1 is Panel Control HW instance 1. 4693 */ 4694 uint8_t panel_mask; 4695 4696 /** 4697 * Explicit padding to 4 byte boundary. 4698 */ 4699 uint8_t pad[2]; 4700 }; 4701 4702 /** 4703 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4704 */ 4705 struct dmub_rb_cmd_abm_set_level { 4706 /** 4707 * Command header. 4708 */ 4709 struct dmub_cmd_header header; 4710 4711 /** 4712 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4713 */ 4714 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4715 }; 4716 4717 /** 4718 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4719 */ 4720 struct dmub_cmd_abm_set_ambient_level_data { 4721 /** 4722 * Ambient light sensor reading from OS. 4723 */ 4724 uint32_t ambient_lux; 4725 4726 /** 4727 * ABM control version. 4728 */ 4729 uint8_t version; 4730 4731 /** 4732 * Panel Control HW instance mask. 4733 * Bit 0 is Panel Control HW instance 0. 4734 * Bit 1 is Panel Control HW instance 1. 4735 */ 4736 uint8_t panel_mask; 4737 4738 /** 4739 * Explicit padding to 4 byte boundary. 4740 */ 4741 uint8_t pad[2]; 4742 }; 4743 4744 /** 4745 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4746 */ 4747 struct dmub_rb_cmd_abm_set_ambient_level { 4748 /** 4749 * Command header. 4750 */ 4751 struct dmub_cmd_header header; 4752 4753 /** 4754 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4755 */ 4756 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4757 }; 4758 4759 /** 4760 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4761 */ 4762 struct dmub_cmd_abm_set_pwm_frac_data { 4763 /** 4764 * Enable/disable fractional duty cycle for backlight PWM. 4765 * TODO: Convert to uint8_t. 4766 */ 4767 uint32_t fractional_pwm; 4768 4769 /** 4770 * ABM control version. 4771 */ 4772 uint8_t version; 4773 4774 /** 4775 * Panel Control HW instance mask. 4776 * Bit 0 is Panel Control HW instance 0. 4777 * Bit 1 is Panel Control HW instance 1. 4778 */ 4779 uint8_t panel_mask; 4780 4781 /** 4782 * Explicit padding to 4 byte boundary. 4783 */ 4784 uint8_t pad[2]; 4785 }; 4786 4787 /** 4788 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4789 */ 4790 struct dmub_rb_cmd_abm_set_pwm_frac { 4791 /** 4792 * Command header. 4793 */ 4794 struct dmub_cmd_header header; 4795 4796 /** 4797 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4798 */ 4799 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4800 }; 4801 4802 /** 4803 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4804 */ 4805 struct dmub_cmd_abm_init_config_data { 4806 /** 4807 * Location of indirect buffer used to pass init data to ABM. 4808 */ 4809 union dmub_addr src; 4810 4811 /** 4812 * Indirect buffer length. 4813 */ 4814 uint16_t bytes; 4815 4816 4817 /** 4818 * ABM control version. 4819 */ 4820 uint8_t version; 4821 4822 /** 4823 * Panel Control HW instance mask. 4824 * Bit 0 is Panel Control HW instance 0. 4825 * Bit 1 is Panel Control HW instance 1. 4826 */ 4827 uint8_t panel_mask; 4828 4829 /** 4830 * Explicit padding to 4 byte boundary. 4831 */ 4832 uint8_t pad[2]; 4833 }; 4834 4835 /** 4836 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4837 */ 4838 struct dmub_rb_cmd_abm_init_config { 4839 /** 4840 * Command header. 4841 */ 4842 struct dmub_cmd_header header; 4843 4844 /** 4845 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4846 */ 4847 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4848 }; 4849 4850 /** 4851 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4852 */ 4853 4854 struct dmub_cmd_abm_pause_data { 4855 4856 /** 4857 * Panel Control HW instance mask. 4858 * Bit 0 is Panel Control HW instance 0. 4859 * Bit 1 is Panel Control HW instance 1. 4860 */ 4861 uint8_t panel_mask; 4862 4863 /** 4864 * OTG hw instance 4865 */ 4866 uint8_t otg_inst; 4867 4868 /** 4869 * Enable or disable ABM pause 4870 */ 4871 uint8_t enable; 4872 4873 /** 4874 * Explicit padding to 4 byte boundary. 4875 */ 4876 uint8_t pad[1]; 4877 }; 4878 4879 /** 4880 * Definition of a DMUB_CMD__ABM_PAUSE command. 4881 */ 4882 struct dmub_rb_cmd_abm_pause { 4883 /** 4884 * Command header. 4885 */ 4886 struct dmub_cmd_header header; 4887 4888 /** 4889 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4890 */ 4891 struct dmub_cmd_abm_pause_data abm_pause_data; 4892 }; 4893 4894 /** 4895 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4896 */ 4897 struct dmub_cmd_abm_query_caps_in { 4898 /** 4899 * Panel instance. 4900 */ 4901 uint8_t panel_inst; 4902 4903 /** 4904 * Explicit padding to 4 byte boundary. 4905 */ 4906 uint8_t pad[3]; 4907 }; 4908 4909 /** 4910 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4911 */ 4912 struct dmub_cmd_abm_query_caps_out { 4913 /** 4914 * SW Algorithm caps. 4915 */ 4916 struct abm_caps sw_caps; 4917 4918 /** 4919 * ABM HW caps. 4920 */ 4921 struct abm_caps hw_caps; 4922 }; 4923 4924 /** 4925 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4926 */ 4927 struct dmub_rb_cmd_abm_query_caps { 4928 /** 4929 * Command header. 4930 */ 4931 struct dmub_cmd_header header; 4932 4933 /** 4934 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4935 */ 4936 union { 4937 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4938 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4939 } data; 4940 }; 4941 4942 /** 4943 * enum dmub_abm_ace_curve_type - ACE curve type. 4944 */ 4945 enum dmub_abm_ace_curve_type { 4946 /** 4947 * ACE curve as defined by the SW layer. 4948 */ 4949 ABM_ACE_CURVE_TYPE__SW = 0, 4950 /** 4951 * ACE curve as defined by the SW to HW translation interface layer. 4952 */ 4953 ABM_ACE_CURVE_TYPE__SW_IF = 1, 4954 }; 4955 4956 /** 4957 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 4958 */ 4959 struct dmub_rb_cmd_abm_get_ace_curve { 4960 /** 4961 * Command header. 4962 */ 4963 struct dmub_cmd_header header; 4964 4965 /** 4966 * Address where ACE curve should be copied. 4967 */ 4968 union dmub_addr dest; 4969 4970 /** 4971 * Type of ACE curve being queried. 4972 */ 4973 enum dmub_abm_ace_curve_type ace_type; 4974 4975 /** 4976 * Indirect buffer length. 4977 */ 4978 uint16_t bytes; 4979 4980 /** 4981 * eDP panel instance. 4982 */ 4983 uint8_t panel_inst; 4984 4985 /** 4986 * Explicit padding to 4 byte boundary. 4987 */ 4988 uint8_t pad; 4989 }; 4990 4991 /** 4992 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4993 */ 4994 struct dmub_rb_cmd_abm_save_restore { 4995 /** 4996 * Command header. 4997 */ 4998 struct dmub_cmd_header header; 4999 5000 /** 5001 * OTG hw instance 5002 */ 5003 uint8_t otg_inst; 5004 5005 /** 5006 * Enable or disable ABM pause 5007 */ 5008 uint8_t freeze; 5009 5010 /** 5011 * Explicit padding to 4 byte boundary. 5012 */ 5013 uint8_t debug; 5014 5015 /** 5016 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5017 */ 5018 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5019 }; 5020 5021 /** 5022 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5023 */ 5024 5025 struct dmub_cmd_abm_set_event_data { 5026 5027 /** 5028 * VB Scaling Init. Strength Mapping 5029 * Byte 0: 0~255 for VB level 0 5030 * Byte 1: 0~255 for VB level 1 5031 * Byte 2: 0~255 for VB level 2 5032 * Byte 3: 0~255 for VB level 3 5033 */ 5034 uint32_t vb_scaling_strength_mapping; 5035 /** 5036 * VariBright Scaling Enable 5037 */ 5038 uint8_t vb_scaling_enable; 5039 /** 5040 * Panel Control HW instance mask. 5041 * Bit 0 is Panel Control HW instance 0. 5042 * Bit 1 is Panel Control HW instance 1. 5043 */ 5044 uint8_t panel_mask; 5045 5046 /** 5047 * Explicit padding to 4 byte boundary. 5048 */ 5049 uint8_t pad[2]; 5050 }; 5051 5052 /** 5053 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5054 */ 5055 struct dmub_rb_cmd_abm_set_event { 5056 /** 5057 * Command header. 5058 */ 5059 struct dmub_cmd_header header; 5060 5061 /** 5062 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5063 */ 5064 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5065 }; 5066 5067 /** 5068 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5069 */ 5070 struct dmub_cmd_query_feature_caps_data { 5071 /** 5072 * DMUB feature capabilities. 5073 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5074 */ 5075 struct dmub_feature_caps feature_caps; 5076 }; 5077 5078 /** 5079 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5080 */ 5081 struct dmub_rb_cmd_query_feature_caps { 5082 /** 5083 * Command header. 5084 */ 5085 struct dmub_cmd_header header; 5086 /** 5087 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5088 */ 5089 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5090 }; 5091 5092 /** 5093 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5094 */ 5095 struct dmub_cmd_visual_confirm_color_data { 5096 /** 5097 * DMUB visual confirm color 5098 */ 5099 struct dmub_visual_confirm_color visual_confirm_color; 5100 }; 5101 5102 /** 5103 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5104 */ 5105 struct dmub_rb_cmd_get_visual_confirm_color { 5106 /** 5107 * Command header. 5108 */ 5109 struct dmub_cmd_header header; 5110 /** 5111 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5112 */ 5113 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5114 }; 5115 5116 /** 5117 * enum dmub_cmd_panel_cntl_type - Panel control command. 5118 */ 5119 enum dmub_cmd_panel_cntl_type { 5120 /** 5121 * Initializes embedded panel hardware blocks. 5122 */ 5123 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5124 /** 5125 * Queries backlight info for the embedded panel. 5126 */ 5127 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5128 /** 5129 * Sets the PWM Freq as per user's requirement. 5130 */ 5131 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5132 }; 5133 5134 /** 5135 * struct dmub_cmd_panel_cntl_data - Panel control data. 5136 */ 5137 struct dmub_cmd_panel_cntl_data { 5138 uint32_t pwrseq_inst; /**< pwrseq instance */ 5139 uint32_t current_backlight; /* in/out */ 5140 uint32_t bl_pwm_cntl; /* in/out */ 5141 uint32_t bl_pwm_period_cntl; /* in/out */ 5142 uint32_t bl_pwm_ref_div1; /* in/out */ 5143 uint8_t is_backlight_on : 1; /* in/out */ 5144 uint8_t is_powered_on : 1; /* in/out */ 5145 uint8_t padding[3]; 5146 uint32_t bl_pwm_ref_div2; /* in/out */ 5147 uint8_t reserved[4]; 5148 }; 5149 5150 /** 5151 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5152 */ 5153 struct dmub_rb_cmd_panel_cntl { 5154 struct dmub_cmd_header header; /**< header */ 5155 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5156 }; 5157 5158 struct dmub_optc_state { 5159 uint32_t v_total_max; 5160 uint32_t v_total_min; 5161 uint32_t tg_inst; 5162 }; 5163 5164 struct dmub_rb_cmd_drr_update { 5165 struct dmub_cmd_header header; 5166 struct dmub_optc_state dmub_optc_state_req; 5167 }; 5168 5169 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5170 uint32_t pix_clk_100hz; 5171 uint8_t max_ramp_step; 5172 uint8_t pipes; 5173 uint8_t min_refresh_in_hz; 5174 uint8_t pipe_count; 5175 uint8_t pipe_index[4]; 5176 }; 5177 5178 struct dmub_cmd_fw_assisted_mclk_switch_config { 5179 uint8_t fams_enabled; 5180 uint8_t visual_confirm_enabled; 5181 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5182 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5183 }; 5184 5185 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5186 struct dmub_cmd_header header; 5187 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5188 }; 5189 5190 /** 5191 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5192 */ 5193 struct dmub_cmd_lvtma_control_data { 5194 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5195 uint8_t bypass_panel_control_wait; 5196 uint8_t reserved_0[2]; /**< For future use */ 5197 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5198 uint8_t reserved_1[3]; /**< For future use */ 5199 }; 5200 5201 /** 5202 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5203 */ 5204 struct dmub_rb_cmd_lvtma_control { 5205 /** 5206 * Command header. 5207 */ 5208 struct dmub_cmd_header header; 5209 /** 5210 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5211 */ 5212 struct dmub_cmd_lvtma_control_data data; 5213 }; 5214 5215 /** 5216 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5217 */ 5218 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5219 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5220 uint8_t is_usb; /**< is phy is usb */ 5221 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5222 uint8_t is_dp4; /**< is dp in 4 lane */ 5223 }; 5224 5225 /** 5226 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5227 */ 5228 struct dmub_rb_cmd_transmitter_query_dp_alt { 5229 struct dmub_cmd_header header; /**< header */ 5230 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5231 }; 5232 5233 struct phy_test_mode { 5234 uint8_t mode; 5235 uint8_t pat0; 5236 uint8_t pad[2]; 5237 }; 5238 5239 /** 5240 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5241 */ 5242 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5243 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5244 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5245 uint8_t lane_num; /**< Number of lanes */ 5246 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5247 struct phy_test_mode test_mode; 5248 enum dmub_phy_fsm_state state; 5249 uint32_t status; 5250 uint8_t pad; 5251 }; 5252 5253 /** 5254 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5255 */ 5256 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5257 struct dmub_cmd_header header; /**< header */ 5258 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5259 }; 5260 5261 /** 5262 * Maximum number of bytes a chunk sent to DMUB for parsing 5263 */ 5264 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5265 5266 /** 5267 * Represent a chunk of CEA blocks sent to DMUB for parsing 5268 */ 5269 struct dmub_cmd_send_edid_cea { 5270 uint16_t offset; /**< offset into the CEA block */ 5271 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5272 uint16_t cea_total_length; /**< total length of the CEA block */ 5273 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5274 uint8_t pad[3]; /**< padding and for future expansion */ 5275 }; 5276 5277 /** 5278 * Result of VSDB parsing from CEA block 5279 */ 5280 struct dmub_cmd_edid_cea_amd_vsdb { 5281 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5282 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5283 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5284 uint16_t min_frame_rate; /**< Maximum frame rate */ 5285 uint16_t max_frame_rate; /**< Minimum frame rate */ 5286 }; 5287 5288 /** 5289 * Result of sending a CEA chunk 5290 */ 5291 struct dmub_cmd_edid_cea_ack { 5292 uint16_t offset; /**< offset of the chunk into the CEA block */ 5293 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5294 uint8_t pad; /**< padding and for future expansion */ 5295 }; 5296 5297 /** 5298 * Specify whether the result is an ACK/NACK or the parsing has finished 5299 */ 5300 enum dmub_cmd_edid_cea_reply_type { 5301 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5302 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5303 }; 5304 5305 /** 5306 * Definition of a DMUB_CMD__EDID_CEA command. 5307 */ 5308 struct dmub_rb_cmd_edid_cea { 5309 struct dmub_cmd_header header; /**< Command header */ 5310 union dmub_cmd_edid_cea_data { 5311 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5312 struct dmub_cmd_edid_cea_output { /**< output with results */ 5313 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5314 union { 5315 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5316 struct dmub_cmd_edid_cea_ack ack; 5317 }; 5318 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5319 } data; /**< Command data */ 5320 5321 }; 5322 5323 /** 5324 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5325 */ 5326 struct dmub_cmd_cable_id_input { 5327 uint8_t phy_inst; /**< phy inst for cable id data */ 5328 }; 5329 5330 /** 5331 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5332 */ 5333 struct dmub_cmd_cable_id_output { 5334 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5335 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5336 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5337 uint8_t RESERVED :2; /**< reserved means not defined */ 5338 }; 5339 5340 /** 5341 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5342 */ 5343 struct dmub_rb_cmd_get_usbc_cable_id { 5344 struct dmub_cmd_header header; /**< Command header */ 5345 /** 5346 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5347 */ 5348 union dmub_cmd_cable_id_data { 5349 struct dmub_cmd_cable_id_input input; /**< Input */ 5350 struct dmub_cmd_cable_id_output output; /**< Output */ 5351 uint8_t output_raw; /**< Raw data output */ 5352 } data; 5353 }; 5354 5355 enum dmub_cmd_fused_io_sub_type { 5356 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5357 DMUB_CMD__FUSED_IO_ABORT = 1, 5358 }; 5359 5360 enum dmub_cmd_fused_request_type { 5361 FUSED_REQUEST_READ, 5362 FUSED_REQUEST_WRITE, 5363 FUSED_REQUEST_POLL, 5364 }; 5365 5366 enum dmub_cmd_fused_request_status { 5367 FUSED_REQUEST_STATUS_SUCCESS, 5368 FUSED_REQUEST_STATUS_BEGIN, 5369 FUSED_REQUEST_STATUS_SUBMIT, 5370 FUSED_REQUEST_STATUS_REPLY, 5371 FUSED_REQUEST_STATUS_POLL, 5372 FUSED_REQUEST_STATUS_ABORTED, 5373 FUSED_REQUEST_STATUS_FAILED = 0x80, 5374 FUSED_REQUEST_STATUS_INVALID, 5375 FUSED_REQUEST_STATUS_BUSY, 5376 FUSED_REQUEST_STATUS_TIMEOUT, 5377 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5378 }; 5379 5380 struct dmub_cmd_fused_request { 5381 uint8_t status; 5382 uint8_t type : 2; 5383 uint8_t _reserved0 : 3; 5384 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5385 uint8_t identifier; 5386 uint8_t _reserved1; 5387 uint32_t timeout_us; 5388 union dmub_cmd_fused_request_location { 5389 struct dmub_cmd_fused_request_location_i2c { 5390 uint8_t is_aux : 1; // False 5391 uint8_t ddc_line : 3; 5392 uint8_t _reserved0 : 4; 5393 uint8_t address; 5394 uint8_t offset; 5395 uint8_t length; 5396 } i2c; 5397 struct dmub_cmd_fused_request_location_aux { 5398 uint32_t is_aux : 1; // True 5399 uint32_t ddc_line : 3; 5400 uint32_t address : 20; 5401 uint32_t length : 8; // Automatically split into 16B transactions 5402 } aux; 5403 } u; 5404 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5405 }; 5406 5407 struct dmub_rb_cmd_fused_io { 5408 struct dmub_cmd_header header; 5409 struct dmub_cmd_fused_request request; 5410 }; 5411 5412 /** 5413 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5414 */ 5415 enum dmub_cmd_secure_display_type { 5416 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5417 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5418 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5419 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5420 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5421 }; 5422 5423 #define MAX_ROI_NUM 2 5424 5425 struct dmub_cmd_roi_info { 5426 uint16_t x_start; 5427 uint16_t x_end; 5428 uint16_t y_start; 5429 uint16_t y_end; 5430 uint8_t otg_id; 5431 uint8_t phy_id; 5432 }; 5433 5434 struct dmub_cmd_roi_window_ctl { 5435 uint16_t x_start; 5436 uint16_t x_end; 5437 uint16_t y_start; 5438 uint16_t y_end; 5439 bool enable; 5440 }; 5441 5442 struct dmub_cmd_roi_ctl_info { 5443 uint8_t otg_id; 5444 uint8_t phy_id; 5445 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5446 }; 5447 5448 /** 5449 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5450 */ 5451 struct dmub_rb_cmd_secure_display { 5452 struct dmub_cmd_header header; 5453 /** 5454 * Data passed from driver to dmub firmware. 5455 */ 5456 struct dmub_cmd_roi_info roi_info; 5457 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5458 }; 5459 5460 /** 5461 * Command type of a DMUB_CMD__PSP command 5462 */ 5463 enum dmub_cmd_psp_type { 5464 DMUB_CMD__PSP_ASSR_ENABLE = 0 5465 }; 5466 5467 /** 5468 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5469 */ 5470 struct dmub_cmd_assr_enable_data { 5471 /** 5472 * ASSR enable or disable. 5473 */ 5474 uint8_t enable; 5475 /** 5476 * PHY port type. 5477 * Indicates eDP / non-eDP port type 5478 */ 5479 uint8_t phy_port_type; 5480 /** 5481 * PHY port ID. 5482 */ 5483 uint8_t phy_port_id; 5484 /** 5485 * Link encoder index. 5486 */ 5487 uint8_t link_enc_index; 5488 /** 5489 * HPO mode. 5490 */ 5491 uint8_t hpo_mode; 5492 5493 /** 5494 * Reserved field. 5495 */ 5496 uint8_t reserved[7]; 5497 }; 5498 5499 /** 5500 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5501 */ 5502 struct dmub_rb_cmd_assr_enable { 5503 /** 5504 * Command header. 5505 */ 5506 struct dmub_cmd_header header; 5507 5508 /** 5509 * Assr data. 5510 */ 5511 struct dmub_cmd_assr_enable_data assr_data; 5512 5513 /** 5514 * Reserved field. 5515 */ 5516 uint32_t reserved[3]; 5517 }; 5518 5519 /** 5520 * union dmub_rb_cmd - DMUB inbox command. 5521 */ 5522 union dmub_rb_cmd { 5523 /** 5524 * Elements shared with all commands. 5525 */ 5526 struct dmub_rb_cmd_common cmd_common; 5527 /** 5528 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5529 */ 5530 struct dmub_rb_cmd_read_modify_write read_modify_write; 5531 /** 5532 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5533 */ 5534 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5535 /** 5536 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5537 */ 5538 struct dmub_rb_cmd_burst_write burst_write; 5539 /** 5540 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5541 */ 5542 struct dmub_rb_cmd_reg_wait reg_wait; 5543 /** 5544 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5545 */ 5546 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5547 /** 5548 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5549 */ 5550 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5551 /** 5552 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5553 */ 5554 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5555 /** 5556 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5557 */ 5558 struct dmub_rb_cmd_dpphy_init dpphy_init; 5559 /** 5560 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5561 */ 5562 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5563 /** 5564 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5565 */ 5566 struct dmub_rb_cmd_domain_control domain_control; 5567 /** 5568 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5569 */ 5570 struct dmub_rb_cmd_psr_set_version psr_set_version; 5571 /** 5572 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5573 */ 5574 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5575 /** 5576 * Definition of a DMUB_CMD__PSR_ENABLE command. 5577 */ 5578 struct dmub_rb_cmd_psr_enable psr_enable; 5579 /** 5580 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5581 */ 5582 struct dmub_rb_cmd_psr_set_level psr_set_level; 5583 /** 5584 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5585 */ 5586 struct dmub_rb_cmd_psr_force_static psr_force_static; 5587 /** 5588 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5589 */ 5590 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5591 /** 5592 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5593 */ 5594 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5595 /** 5596 * Definition of a DMUB_CMD__HW_LOCK command. 5597 * Command is used by driver and FW. 5598 */ 5599 struct dmub_rb_cmd_lock_hw lock_hw; 5600 /** 5601 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5602 */ 5603 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5604 /** 5605 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5606 */ 5607 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5608 /** 5609 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5610 */ 5611 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5612 /** 5613 * Definition of a DMUB_CMD__MALL command. 5614 */ 5615 struct dmub_rb_cmd_mall mall; 5616 5617 /** 5618 * Definition of a DMUB_CMD__CAB command. 5619 */ 5620 struct dmub_rb_cmd_cab_for_ss cab; 5621 5622 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5623 5624 /** 5625 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5626 */ 5627 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5628 5629 /** 5630 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5631 */ 5632 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5633 5634 /** 5635 * Definition of DMUB_CMD__PANEL_CNTL commands. 5636 */ 5637 struct dmub_rb_cmd_panel_cntl panel_cntl; 5638 5639 /** 5640 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5641 */ 5642 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5643 5644 /** 5645 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5646 */ 5647 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5648 5649 /** 5650 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5651 */ 5652 struct dmub_rb_cmd_abm_set_level abm_set_level; 5653 5654 /** 5655 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5656 */ 5657 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5658 5659 /** 5660 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5661 */ 5662 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5663 5664 /** 5665 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5666 */ 5667 struct dmub_rb_cmd_abm_init_config abm_init_config; 5668 5669 /** 5670 * Definition of a DMUB_CMD__ABM_PAUSE command. 5671 */ 5672 struct dmub_rb_cmd_abm_pause abm_pause; 5673 5674 /** 5675 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5676 */ 5677 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5678 5679 /** 5680 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5681 */ 5682 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5683 5684 /** 5685 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5686 */ 5687 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5688 5689 /** 5690 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5691 */ 5692 struct dmub_rb_cmd_abm_set_event abm_set_event; 5693 5694 /** 5695 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5696 */ 5697 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5698 5699 /** 5700 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5701 */ 5702 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5703 5704 /** 5705 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5706 */ 5707 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5708 5709 /** 5710 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5711 */ 5712 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5713 struct dmub_rb_cmd_drr_update drr_update; 5714 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5715 5716 /** 5717 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5718 */ 5719 struct dmub_rb_cmd_lvtma_control lvtma_control; 5720 /** 5721 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5722 */ 5723 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5724 /** 5725 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5726 */ 5727 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5728 /** 5729 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5730 */ 5731 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5732 /** 5733 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5734 */ 5735 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 5736 /** 5737 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5738 */ 5739 struct dmub_rb_cmd_set_config_request set_config_request; 5740 /** 5741 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5742 */ 5743 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5744 /** 5745 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 5746 */ 5747 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 5748 /** 5749 * Definition of a DMUB_CMD__EDID_CEA command. 5750 */ 5751 struct dmub_rb_cmd_edid_cea edid_cea; 5752 /** 5753 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5754 */ 5755 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5756 5757 /** 5758 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5759 */ 5760 struct dmub_rb_cmd_query_hpd_state query_hpd; 5761 /** 5762 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5763 */ 5764 struct dmub_rb_cmd_secure_display secure_display; 5765 5766 /** 5767 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5768 */ 5769 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5770 /** 5771 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5772 */ 5773 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5774 /** 5775 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 5776 */ 5777 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 5778 /* 5779 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5780 */ 5781 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5782 /** 5783 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5784 */ 5785 struct dmub_rb_cmd_replay_enable replay_enable; 5786 /** 5787 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5788 */ 5789 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5790 /** 5791 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5792 */ 5793 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5794 /** 5795 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5796 */ 5797 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5798 5799 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5800 /** 5801 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5802 */ 5803 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5804 /** 5805 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5806 */ 5807 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5808 /** 5809 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5810 */ 5811 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5812 /** 5813 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5814 */ 5815 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5816 /** 5817 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5818 */ 5819 struct dmub_rb_cmd_assr_enable assr_enable; 5820 struct dmub_rb_cmd_fams2 fams2_config; 5821 5822 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5823 5824 struct dmub_rb_cmd_fams2_flip fams2_flip; 5825 5826 struct dmub_rb_cmd_fused_io fused_io; 5827 }; 5828 5829 /** 5830 * union dmub_rb_out_cmd - Outbox command 5831 */ 5832 union dmub_rb_out_cmd { 5833 /** 5834 * Parameters common to every command. 5835 */ 5836 struct dmub_rb_cmd_common cmd_common; 5837 /** 5838 * AUX reply command. 5839 */ 5840 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5841 /** 5842 * HPD notify command. 5843 */ 5844 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5845 /** 5846 * SET_CONFIG reply command. 5847 */ 5848 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5849 /** 5850 * DPIA notification command. 5851 */ 5852 struct dmub_rb_cmd_dpia_notification dpia_notification; 5853 /** 5854 * HPD sense notification command. 5855 */ 5856 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5857 struct dmub_rb_cmd_fused_io fused_io; 5858 }; 5859 #pragma pack(pop) 5860 5861 5862 //============================================================================== 5863 //</DMUB_CMD>=================================================================== 5864 //============================================================================== 5865 //< DMUB_RB>==================================================================== 5866 //============================================================================== 5867 5868 /** 5869 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5870 */ 5871 struct dmub_rb_init_params { 5872 void *ctx; /**< Caller provided context pointer */ 5873 void *base_address; /**< CPU base address for ring's data */ 5874 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5875 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5876 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5877 }; 5878 5879 /** 5880 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5881 */ 5882 struct dmub_rb { 5883 void *base_address; /**< CPU address for the ring's data */ 5884 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5885 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5886 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5887 5888 void *ctx; /**< Caller provided context pointer */ 5889 void *dmub; /**< Pointer to the DMUB interface */ 5890 }; 5891 5892 /** 5893 * @brief Checks if the ringbuffer is empty. 5894 * 5895 * @param rb DMUB Ringbuffer 5896 * @return true if empty 5897 * @return false otherwise 5898 */ 5899 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5900 { 5901 return (rb->wrpt == rb->rptr); 5902 } 5903 5904 /** 5905 * @brief gets number of outstanding requests in the RB 5906 * 5907 * @param rb DMUB Ringbuffer 5908 * @return true if full 5909 */ 5910 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 5911 { 5912 uint32_t data_count; 5913 5914 if (rb->wrpt >= rb->rptr) 5915 data_count = rb->wrpt - rb->rptr; 5916 else 5917 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5918 5919 return data_count / DMUB_RB_CMD_SIZE; 5920 } 5921 5922 /** 5923 * @brief gets number of free buffers in the RB 5924 * 5925 * @param rb DMUB Ringbuffer 5926 * @return true if full 5927 */ 5928 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 5929 { 5930 uint32_t data_count; 5931 5932 if (rb->wrpt >= rb->rptr) 5933 data_count = rb->wrpt - rb->rptr; 5934 else 5935 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5936 5937 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 5938 } 5939 5940 /** 5941 * @brief Checks if the ringbuffer is full 5942 * 5943 * @param rb DMUB Ringbuffer 5944 * @return true if full 5945 * @return false otherwise 5946 */ 5947 static inline bool dmub_rb_full(struct dmub_rb *rb) 5948 { 5949 uint32_t data_count; 5950 5951 if (rb->wrpt >= rb->rptr) 5952 data_count = rb->wrpt - rb->rptr; 5953 else 5954 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5955 5956 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 5957 } 5958 5959 /** 5960 * @brief Pushes a command into the ringbuffer 5961 * 5962 * @param rb DMUB ringbuffer 5963 * @param cmd The command to push 5964 * @return true if the ringbuffer was not full 5965 * @return false otherwise 5966 */ 5967 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 5968 const union dmub_rb_cmd *cmd) 5969 { 5970 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 5971 const uint64_t *src = (const uint64_t *)cmd; 5972 uint8_t i; 5973 5974 if (dmub_rb_full(rb)) 5975 return false; 5976 5977 // copying data 5978 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 5979 *dst++ = *src++; 5980 5981 rb->wrpt += DMUB_RB_CMD_SIZE; 5982 5983 if (rb->wrpt >= rb->capacity) 5984 rb->wrpt %= rb->capacity; 5985 5986 return true; 5987 } 5988 5989 /** 5990 * @brief Pushes a command into the DMUB outbox ringbuffer 5991 * 5992 * @param rb DMUB outbox ringbuffer 5993 * @param cmd Outbox command 5994 * @return true if not full 5995 * @return false otherwise 5996 */ 5997 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 5998 const union dmub_rb_out_cmd *cmd) 5999 { 6000 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6001 const uint8_t *src = (const uint8_t *)cmd; 6002 6003 if (dmub_rb_full(rb)) 6004 return false; 6005 6006 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6007 6008 rb->wrpt += DMUB_RB_CMD_SIZE; 6009 6010 if (rb->wrpt >= rb->capacity) 6011 rb->wrpt %= rb->capacity; 6012 6013 return true; 6014 } 6015 6016 /** 6017 * @brief Returns the next unprocessed command in the ringbuffer. 6018 * 6019 * @param rb DMUB ringbuffer 6020 * @param cmd The command to return 6021 * @return true if not empty 6022 * @return false otherwise 6023 */ 6024 static inline bool dmub_rb_front(struct dmub_rb *rb, 6025 union dmub_rb_cmd **cmd) 6026 { 6027 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6028 6029 if (dmub_rb_empty(rb)) 6030 return false; 6031 6032 *cmd = (union dmub_rb_cmd *)rb_cmd; 6033 6034 return true; 6035 } 6036 6037 /** 6038 * @brief Determines the next ringbuffer offset. 6039 * 6040 * @param rb DMUB inbox ringbuffer 6041 * @param num_cmds Number of commands 6042 * @param next_rptr The next offset in the ringbuffer 6043 */ 6044 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6045 uint32_t num_cmds, 6046 uint32_t *next_rptr) 6047 { 6048 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6049 6050 if (*next_rptr >= rb->capacity) 6051 *next_rptr %= rb->capacity; 6052 } 6053 6054 /** 6055 * @brief Returns a pointer to a command in the inbox. 6056 * 6057 * @param rb DMUB inbox ringbuffer 6058 * @param cmd The inbox command to return 6059 * @param rptr The ringbuffer offset 6060 * @return true if not empty 6061 * @return false otherwise 6062 */ 6063 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6064 union dmub_rb_cmd **cmd, 6065 uint32_t rptr) 6066 { 6067 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6068 6069 if (dmub_rb_empty(rb)) 6070 return false; 6071 6072 *cmd = (union dmub_rb_cmd *)rb_cmd; 6073 6074 return true; 6075 } 6076 6077 /** 6078 * @brief Returns the next unprocessed command in the outbox. 6079 * 6080 * @param rb DMUB outbox ringbuffer 6081 * @param cmd The outbox command to return 6082 * @return true if not empty 6083 * @return false otherwise 6084 */ 6085 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6086 union dmub_rb_out_cmd *cmd) 6087 { 6088 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6089 uint64_t *dst = (uint64_t *)cmd; 6090 uint8_t i; 6091 6092 if (dmub_rb_empty(rb)) 6093 return false; 6094 6095 // copying data 6096 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6097 *dst++ = *src++; 6098 6099 return true; 6100 } 6101 6102 /** 6103 * @brief Removes the front entry in the ringbuffer. 6104 * 6105 * @param rb DMUB ringbuffer 6106 * @return true if the command was removed 6107 * @return false if there were no commands 6108 */ 6109 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6110 { 6111 if (dmub_rb_empty(rb)) 6112 return false; 6113 6114 rb->rptr += DMUB_RB_CMD_SIZE; 6115 6116 if (rb->rptr >= rb->capacity) 6117 rb->rptr %= rb->capacity; 6118 6119 return true; 6120 } 6121 6122 /** 6123 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6124 * 6125 * Avoids a race condition where DMCUB accesses memory while 6126 * there are still writes in flight to framebuffer. 6127 * 6128 * @param rb DMUB ringbuffer 6129 */ 6130 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6131 { 6132 uint32_t rptr = rb->rptr; 6133 uint32_t wptr = rb->wrpt; 6134 6135 while (rptr != wptr) { 6136 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6137 uint8_t i; 6138 6139 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6140 (void)READ_ONCE(*data++); 6141 6142 rptr += DMUB_RB_CMD_SIZE; 6143 if (rptr >= rb->capacity) 6144 rptr %= rb->capacity; 6145 } 6146 } 6147 6148 /** 6149 * @brief Initializes a DMCUB ringbuffer 6150 * 6151 * @param rb DMUB ringbuffer 6152 * @param init_params initial configuration for the ringbuffer 6153 */ 6154 static inline void dmub_rb_init(struct dmub_rb *rb, 6155 struct dmub_rb_init_params *init_params) 6156 { 6157 rb->base_address = init_params->base_address; 6158 rb->capacity = init_params->capacity; 6159 rb->rptr = init_params->read_ptr; 6160 rb->wrpt = init_params->write_ptr; 6161 } 6162 6163 /** 6164 * @brief Copies output data from in/out commands into the given command. 6165 * 6166 * @param rb DMUB ringbuffer 6167 * @param cmd Command to copy data into 6168 */ 6169 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6170 union dmub_rb_cmd *cmd) 6171 { 6172 // Copy rb entry back into command 6173 uint8_t *rd_ptr = (rb->rptr == 0) ? 6174 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6175 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6176 6177 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6178 } 6179 6180 //============================================================================== 6181 //</DMUB_RB>==================================================================== 6182 //============================================================================== 6183 #endif /* _DMUB_CMD_H_ */ 6184