1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef _LINUX_QCOM_GENI_SE 8 #define _LINUX_QCOM_GENI_SE 9 10 #include <linux/interconnect.h> 11 12 /** 13 * enum geni_se_xfer_mode: Transfer modes supported by Serial Engines 14 * 15 * @GENI_SE_INVALID: Invalid mode 16 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO 17 * by programmed IO method 18 * @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred 19 * with SE by DMAengine internal to SE 20 * @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine 21 * configured by a firmware residing on a GSI engine. This DMA name is 22 * interchangeably used as GSI or GPI which seem to imply the same DMAengine 23 */ 24 25 enum geni_se_xfer_mode { 26 GENI_SE_INVALID, 27 GENI_SE_FIFO, 28 GENI_SE_DMA, 29 GENI_GPI_DMA, 30 }; 31 32 /* Protocols supported by GENI Serial Engines */ 33 enum geni_se_protocol_type { 34 GENI_SE_NONE, 35 GENI_SE_SPI, 36 GENI_SE_UART, 37 GENI_SE_I2C, 38 GENI_SE_I3C, 39 GENI_SE_SPI_SLAVE, 40 GENI_SE_INVALID_PROTO = 255, 41 }; 42 43 struct geni_wrapper; 44 struct clk; 45 46 enum geni_icc_path_index { 47 GENI_TO_CORE, 48 CPU_TO_GENI, 49 GENI_TO_DDR 50 }; 51 52 struct geni_icc_path { 53 struct icc_path *path; 54 unsigned int avg_bw; 55 }; 56 57 /** 58 * struct geni_se - GENI Serial Engine 59 * @base: Base Address of the Serial Engine's register block 60 * @dev: Pointer to the Serial Engine device 61 * @wrapper: Pointer to the parent QUP Wrapper core 62 * @clk: Handle to the core serial engine clock 63 * @core_clk: Auxiliary clock, which may be required by a protocol 64 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl 65 * @clk_perf_tbl: Table of clock frequency input to serial engine clock 66 * @icc_paths: Array of ICC paths for SE 67 * @pd_list: Power domain list for managing power domains 68 * @has_opp: Indicates if OPP is supported 69 */ 70 struct geni_se { 71 void __iomem *base; 72 struct device *dev; 73 struct geni_wrapper *wrapper; 74 struct clk *clk; 75 struct clk *core_clk; 76 unsigned int num_clk_levels; 77 unsigned long *clk_perf_tbl; 78 struct geni_icc_path icc_paths[3]; 79 struct dev_pm_domain_list *pd_list; 80 bool has_opp; 81 }; 82 83 /* Common SE registers */ 84 #define GENI_GENERAL_CFG 0x10 85 #define GENI_FORCE_DEFAULT_REG 0x20 86 #define GENI_OUTPUT_CTRL 0x24 87 #define SE_GENI_STATUS 0x40 88 #define GENI_SER_M_CLK_CFG 0x48 89 #define GENI_SER_S_CLK_CFG 0x4c 90 #define GENI_CLK_CTRL_RO 0x60 91 #define GENI_IF_DISABLE_RO 0x64 92 #define GENI_FW_REVISION_RO 0x68 93 #define GENI_FW_MULTILOCK_MSA_RO 0x74 94 #define SE_GENI_CLK_SEL 0x7c 95 #define SE_GENI_CFG_SEQ_START 0x84 96 #define SE_GENI_DMA_MODE_EN 0x258 97 #define SE_GENI_M_CMD0 0x600 98 #define SE_GENI_M_CMD_CTRL_REG 0x604 99 #define SE_GENI_M_IRQ_STATUS 0x610 100 #define SE_GENI_M_IRQ_EN 0x614 101 #define SE_GENI_M_IRQ_CLEAR 0x618 102 #define SE_GENI_M_IRQ_EN_SET 0x61c 103 #define SE_GENI_M_IRQ_EN_CLEAR 0x620 104 #define M_CMD_ERR_STATUS 0x624 105 #define M_FW_ERR_STATUS 0x628 106 #define SE_GENI_S_CMD0 0x630 107 #define SE_GENI_S_CMD_CTRL_REG 0x634 108 #define SE_GENI_S_IRQ_STATUS 0x640 109 #define SE_GENI_S_IRQ_EN 0x644 110 #define SE_GENI_S_IRQ_CLEAR 0x648 111 #define SE_GENI_S_IRQ_EN_SET 0x64c 112 #define SE_GENI_S_IRQ_EN_CLEAR 0x650 113 #define SE_GENI_TX_FIFOn 0x700 114 #define SE_GENI_RX_FIFOn 0x780 115 #define SE_GENI_TX_FIFO_STATUS 0x800 116 #define SE_GENI_RX_FIFO_STATUS 0x804 117 #define SE_GENI_TX_WATERMARK_REG 0x80c 118 #define SE_GENI_RX_WATERMARK_REG 0x810 119 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814 120 #define SE_GENI_IOS 0x908 121 #define SE_GENI_M_GP_LENGTH 0x910 122 #define SE_GENI_S_GP_LENGTH 0x914 123 /* TX DMA registers */ 124 #define SE_DMA_TX_PTR_L 0xc30 125 #define SE_DMA_TX_PTR_H 0xc34 126 #define SE_DMA_TX_ATTR 0xc38 127 #define SE_DMA_TX_LEN 0xc3c 128 #define SE_DMA_TX_IRQ_STAT 0xc40 129 #define SE_DMA_TX_IRQ_CLR 0xc44 130 #define SE_DMA_TX_IRQ_EN 0xc48 131 #define SE_DMA_TX_IRQ_EN_SET 0xc4c 132 #define SE_DMA_TX_IRQ_EN_CLR 0xc50 133 #define SE_DMA_TX_LEN_IN 0xc54 134 #define SE_DMA_TX_FSM_RST 0xc58 135 #define SE_DMA_TX_MAX_BURST 0xc5c 136 /* RX DMA registers */ 137 #define SE_DMA_RX_PTR_L 0xd30 138 #define SE_DMA_RX_PTR_H 0xd34 139 #define SE_DMA_RX_ATTR 0xd38 140 #define SE_DMA_RX_LEN 0xd3c 141 #define SE_DMA_RX_IRQ_STAT 0xd40 142 #define SE_DMA_RX_IRQ_CLR 0xd44 143 #define SE_DMA_RX_IRQ_EN 0xd48 144 #define SE_DMA_RX_IRQ_EN_SET 0xd4c 145 #define SE_DMA_RX_IRQ_EN_CLR 0xd50 146 #define SE_DMA_RX_LEN_IN 0xd54 147 #define SE_DMA_RX_FSM_RST 0xd58 148 #define SE_DMA_RX_MAX_BURST 0xd5c 149 /* DMA general / debug registers */ 150 #define SE_GSI_EVENT_EN 0xe18 151 #define SE_IRQ_EN 0xe1c 152 #define DMA_IF_EN_RO 0xe20 153 #define SE_HW_PARAM_0 0xe24 154 #define SE_HW_PARAM_1 0xe28 155 #define SE_HW_PARAM_2 0xe2c 156 #define DMA_GENERAL_CFG 0xe30 157 #define SE_DMA_QSB_TRANS_CFG 0xe38 158 #define SE_DMA_DEBUG_REG0 0xe40 159 #define SE_DMA_IF_EN 0x2004 160 161 /* GENI_FORCE_DEFAULT_REG fields */ 162 #define FORCE_DEFAULT BIT(0) 163 164 /* GENI_OUTPUT_CTRL fields */ 165 #define GENI_IO_MUX_0_EN BIT(0) 166 167 /* GENI_STATUS fields */ 168 #define M_GENI_CMD_ACTIVE BIT(0) 169 #define S_GENI_CMD_ACTIVE BIT(12) 170 171 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ 172 #define SER_CLK_EN BIT(0) 173 #define CLK_DIV_MSK GENMASK(15, 4) 174 #define CLK_DIV_SHFT 4 175 176 /* GENI_IF_DISABLE_RO fields */ 177 #define FIFO_IF_DISABLE (BIT(0)) 178 179 /* GENI_FW_REVISION_RO fields */ 180 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8) 181 #define FW_REV_PROTOCOL_SHFT 8 182 183 /* GENI_CLK_SEL fields */ 184 #define CLK_SEL_MSK GENMASK(2, 0) 185 186 /* SE_GENI_CFG_SEQ_START fields */ 187 #define START_TRIGGER BIT(0) 188 189 /* SE_GENI_DMA_MODE_EN */ 190 #define GENI_DMA_MODE_EN BIT(0) 191 192 /* GENI_M_CMD0 fields */ 193 #define M_OPCODE_MSK GENMASK(31, 27) 194 #define M_OPCODE_SHFT 27 195 #define M_PARAMS_MSK GENMASK(26, 0) 196 197 /* GENI_M_CMD_CTRL_REG */ 198 #define M_GENI_CMD_CANCEL BIT(2) 199 #define M_GENI_CMD_ABORT BIT(1) 200 #define M_GENI_DISABLE BIT(0) 201 202 /* GENI_S_CMD0 fields */ 203 #define S_OPCODE_MSK GENMASK(31, 27) 204 #define S_OPCODE_SHFT 27 205 #define S_PARAMS_MSK GENMASK(26, 0) 206 207 /* GENI_S_CMD_CTRL_REG */ 208 #define S_GENI_CMD_CANCEL BIT(2) 209 #define S_GENI_CMD_ABORT BIT(1) 210 #define S_GENI_DISABLE BIT(0) 211 212 /* GENI_M_IRQ_EN fields */ 213 #define M_CMD_DONE_EN BIT(0) 214 #define M_CMD_OVERRUN_EN BIT(1) 215 #define M_ILLEGAL_CMD_EN BIT(2) 216 #define M_CMD_FAILURE_EN BIT(3) 217 #define M_CMD_CANCEL_EN BIT(4) 218 #define M_CMD_ABORT_EN BIT(5) 219 #define M_TIMESTAMP_EN BIT(6) 220 #define M_RX_IRQ_EN BIT(7) 221 #define M_GP_SYNC_IRQ_0_EN BIT(8) 222 #define M_GP_IRQ_0_EN BIT(9) 223 #define M_GP_IRQ_1_EN BIT(10) 224 #define M_GP_IRQ_2_EN BIT(11) 225 #define M_GP_IRQ_3_EN BIT(12) 226 #define M_GP_IRQ_4_EN BIT(13) 227 #define M_GP_IRQ_5_EN BIT(14) 228 #define M_TX_FIFO_NOT_EMPTY_EN BIT(21) 229 #define M_IO_DATA_DEASSERT_EN BIT(22) 230 #define M_IO_DATA_ASSERT_EN BIT(23) 231 #define M_RX_FIFO_RD_ERR_EN BIT(24) 232 #define M_RX_FIFO_WR_ERR_EN BIT(25) 233 #define M_RX_FIFO_WATERMARK_EN BIT(26) 234 #define M_RX_FIFO_LAST_EN BIT(27) 235 #define M_TX_FIFO_RD_ERR_EN BIT(28) 236 #define M_TX_FIFO_WR_ERR_EN BIT(29) 237 #define M_TX_FIFO_WATERMARK_EN BIT(30) 238 #define M_SEC_IRQ_EN BIT(31) 239 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ 240 M_IO_DATA_DEASSERT_EN | \ 241 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ 242 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ 243 M_TX_FIFO_WR_ERR_EN) 244 245 /* GENI_S_IRQ_EN fields */ 246 #define S_CMD_DONE_EN BIT(0) 247 #define S_CMD_OVERRUN_EN BIT(1) 248 #define S_ILLEGAL_CMD_EN BIT(2) 249 #define S_CMD_FAILURE_EN BIT(3) 250 #define S_CMD_CANCEL_EN BIT(4) 251 #define S_CMD_ABORT_EN BIT(5) 252 #define S_GP_SYNC_IRQ_0_EN BIT(8) 253 #define S_GP_IRQ_0_EN BIT(9) 254 #define S_GP_IRQ_1_EN BIT(10) 255 #define S_GP_IRQ_2_EN BIT(11) 256 #define S_GP_IRQ_3_EN BIT(12) 257 #define S_GP_IRQ_4_EN BIT(13) 258 #define S_GP_IRQ_5_EN BIT(14) 259 #define S_IO_DATA_DEASSERT_EN BIT(22) 260 #define S_IO_DATA_ASSERT_EN BIT(23) 261 #define S_RX_FIFO_RD_ERR_EN BIT(24) 262 #define S_RX_FIFO_WR_ERR_EN BIT(25) 263 #define S_RX_FIFO_WATERMARK_EN BIT(26) 264 #define S_RX_FIFO_LAST_EN BIT(27) 265 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ 266 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) 267 268 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ 269 #define WATERMARK_MSK GENMASK(5, 0) 270 271 /* GENI_TX_FIFO_STATUS fields */ 272 #define TX_FIFO_WC GENMASK(27, 0) 273 274 /* GENI_RX_FIFO_STATUS fields */ 275 #define RX_LAST BIT(31) 276 #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) 277 #define RX_LAST_BYTE_VALID_SHFT 28 278 #define RX_FIFO_WC_MSK GENMASK(24, 0) 279 280 /* SE_GENI_IOS fields */ 281 #define IO2_DATA_IN BIT(1) 282 #define RX_DATA_IN BIT(0) 283 284 /* SE_GENI_M_GP_LENGTH and SE_GENI_S_GP_LENGTH fields */ 285 #define GP_LENGTH GENMASK(31, 0) 286 287 /* SE_DMA_TX_IRQ_STAT Register fields */ 288 #define TX_DMA_DONE BIT(0) 289 #define TX_EOT BIT(1) 290 #define TX_SBE BIT(2) 291 #define TX_RESET_DONE BIT(3) 292 293 /* SE_DMA_RX_IRQ_STAT Register fields */ 294 #define RX_DMA_DONE BIT(0) 295 #define RX_EOT BIT(1) 296 #define RX_SBE BIT(2) 297 #define RX_RESET_DONE BIT(3) 298 #define RX_FLUSH_DONE BIT(4) 299 #define RX_DMA_PARITY_ERR BIT(5) 300 #define RX_DMA_BREAK GENMASK(8, 7) 301 #define RX_GENI_GP_IRQ GENMASK(10, 5) 302 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) 303 #define RX_GENI_CANCEL_IRQ BIT(14) 304 305 /* SE_DMA_DEBUG_REG0 fields */ 306 #define DMA_TX_ACTIVE BIT(0) 307 #define DMA_RX_ACTIVE BIT(1) 308 #define DMA_TX_STATE GENMASK(7, 4) 309 #define DMA_RX_STATE GENMASK(11, 8) 310 311 /* SE_HW_PARAM_0 fields */ 312 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) 313 #define TX_FIFO_WIDTH_SHFT 24 314 /* 315 * For QUP HW Version >= 3.10 Tx fifo depth support is increased 316 * to 256bytes and corresponding bits are 16 to 23 317 */ 318 #define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 319 #define TX_FIFO_DEPTH_MSK GENMASK(21, 16) 320 #define TX_FIFO_DEPTH_SHFT 16 321 322 /* SE_HW_PARAM_1 fields */ 323 #define RX_FIFO_WIDTH_MSK GENMASK(29, 24) 324 #define RX_FIFO_WIDTH_SHFT 24 325 /* 326 * For QUP HW Version >= 3.10 Rx fifo depth support is increased 327 * to 256bytes and corresponding bits are 16 to 23 328 */ 329 #define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 330 #define RX_FIFO_DEPTH_MSK GENMASK(21, 16) 331 #define RX_FIFO_DEPTH_SHFT 16 332 333 /* SE_HW_PARAM_2 fields */ 334 #define PROG_RAM_DEPTH_MSK GENMASK(10, 0) 335 336 #define HW_VER_MAJOR_MASK GENMASK(31, 28) 337 #define HW_VER_MAJOR_SHFT 28 338 #define HW_VER_MINOR_MASK GENMASK(27, 16) 339 #define HW_VER_MINOR_SHFT 16 340 #define HW_VER_STEP_MASK GENMASK(15, 0) 341 342 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT) 343 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) 344 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) 345 346 /* QUP SE VERSION value for major number 2 and minor number 5 */ 347 #define QUP_SE_VERSION_2_5 0x20050000 348 349 /* 350 * ICC bandwidth values in Bps for the GENI_TO_CORE ("qup-core") path. 351 * Convert them with Bps_to_icc() before setting avg_bw. The QUP ICC provider 352 * maps each threshold to the Core 2X rate named by the macro suffix. 353 * 354 * These values are core clock votes, not GENI transfer bandwidths. 355 */ 356 #define CORE_2X_19_2_MHZ 9600000 357 #define CORE_2X_50_MHZ 25000000 358 #define CORE_2X_100_MHZ 50000000 359 #define CORE_2X_150_MHZ 75000000 360 #define CORE_2X_200_MHZ 100000000 361 #define CORE_2X_236_MHZ 118000000 362 363 #define GENI_DEFAULT_BW Bps_to_icc(1000) 364 365 #if IS_ENABLED(CONFIG_QCOM_GENI_SE) 366 367 u32 geni_se_get_qup_hw_version(struct geni_se *se); 368 369 /** 370 * geni_se_read_proto() - Read the protocol configured for a serial engine 371 * @se: Pointer to the concerned serial engine. 372 * 373 * Return: Protocol value as configured in the serial engine. 374 */ 375 static inline u32 geni_se_read_proto(struct geni_se *se) 376 { 377 u32 val; 378 379 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); 380 381 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT; 382 } 383 384 /** 385 * geni_se_setup_m_cmd() - Setup the primary sequencer 386 * @se: Pointer to the concerned serial engine. 387 * @cmd: Command/Operation to setup in the primary sequencer. 388 * @params: Parameter for the sequencer command. 389 * 390 * This function is used to configure the primary sequencer with the 391 * command and its associated parameters. 392 */ 393 static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params) 394 { 395 u32 m_cmd; 396 397 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK); 398 writel(m_cmd, se->base + SE_GENI_M_CMD0); 399 } 400 401 /** 402 * geni_se_setup_s_cmd() - Setup the secondary sequencer 403 * @se: Pointer to the concerned serial engine. 404 * @cmd: Command/Operation to setup in the secondary sequencer. 405 * @params: Parameter for the sequencer command. 406 * 407 * This function is used to configure the secondary sequencer with the 408 * command and its associated parameters. 409 */ 410 static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params) 411 { 412 u32 s_cmd; 413 414 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); 415 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); 416 s_cmd |= (cmd << S_OPCODE_SHFT); 417 s_cmd |= (params & S_PARAMS_MSK); 418 writel(s_cmd, se->base + SE_GENI_S_CMD0); 419 } 420 421 /** 422 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary 423 * sequencer 424 * @se: Pointer to the concerned serial engine. 425 * 426 * This function is used to cancel the currently configured command in the 427 * primary sequencer. 428 */ 429 static inline void geni_se_cancel_m_cmd(struct geni_se *se) 430 { 431 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG); 432 } 433 434 /** 435 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary 436 * sequencer 437 * @se: Pointer to the concerned serial engine. 438 * 439 * This function is used to cancel the currently configured command in the 440 * secondary sequencer. 441 */ 442 static inline void geni_se_cancel_s_cmd(struct geni_se *se) 443 { 444 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG); 445 } 446 447 /** 448 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer 449 * @se: Pointer to the concerned serial engine. 450 * 451 * This function is used to force abort the currently configured command in the 452 * primary sequencer. 453 */ 454 static inline void geni_se_abort_m_cmd(struct geni_se *se) 455 { 456 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG); 457 } 458 459 /** 460 * geni_se_abort_s_cmd() - Abort the command configured in the secondary 461 * sequencer 462 * @se: Pointer to the concerned serial engine. 463 * 464 * This function is used to force abort the currently configured command in the 465 * secondary sequencer. 466 */ 467 static inline void geni_se_abort_s_cmd(struct geni_se *se) 468 { 469 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG); 470 } 471 472 /** 473 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine 474 * based on QUP HW version 475 * @se: Pointer to the concerned serial engine. 476 * 477 * This function is used to get the depth i.e. number of elements in the 478 * TX fifo of the serial engine. 479 * 480 * Return: TX fifo depth in units of FIFO words. 481 */ 482 static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) 483 { 484 u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask; 485 486 hw_version = geni_se_get_qup_hw_version(se); 487 hw_major = GENI_SE_VERSION_MAJOR(hw_version); 488 hw_minor = GENI_SE_VERSION_MINOR(hw_version); 489 490 if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) 491 tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES; 492 else 493 tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK; 494 495 val = readl_relaxed(se->base + SE_HW_PARAM_0); 496 497 return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT; 498 } 499 500 /** 501 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine 502 * @se: Pointer to the concerned serial engine. 503 * 504 * This function is used to get the width i.e. word size per element in the 505 * TX fifo of the serial engine. 506 * 507 * Return: TX fifo width in bits 508 */ 509 static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) 510 { 511 u32 val; 512 513 val = readl_relaxed(se->base + SE_HW_PARAM_0); 514 515 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT; 516 } 517 518 /** 519 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine 520 * based on QUP HW version 521 * @se: Pointer to the concerned serial engine. 522 * 523 * This function is used to get the depth i.e. number of elements in the 524 * RX fifo of the serial engine. 525 * 526 * Return: RX fifo depth in units of FIFO words 527 */ 528 static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) 529 { 530 u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask; 531 532 hw_version = geni_se_get_qup_hw_version(se); 533 hw_major = GENI_SE_VERSION_MAJOR(hw_version); 534 hw_minor = GENI_SE_VERSION_MINOR(hw_version); 535 536 if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) 537 rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES; 538 else 539 rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK; 540 541 val = readl_relaxed(se->base + SE_HW_PARAM_1); 542 543 return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT; 544 } 545 546 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr); 547 548 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode); 549 550 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 551 bool msb_to_lsb, bool tx_cfg, bool rx_cfg); 552 553 int geni_se_resources_off(struct geni_se *se); 554 555 int geni_se_resources_on(struct geni_se *se); 556 557 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl); 558 559 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 560 unsigned int *index, unsigned long *res_freq, 561 bool exact); 562 563 void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); 564 565 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 566 dma_addr_t *iova); 567 568 void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); 569 570 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 571 dma_addr_t *iova); 572 573 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 574 575 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 576 577 int geni_icc_get(struct geni_se *se); 578 579 int geni_icc_set_bw(struct geni_se *se); 580 int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 ddr_ab); 581 void geni_icc_set_tag(struct geni_se *se, u32 tag); 582 583 int geni_icc_enable(struct geni_se *se); 584 585 int geni_icc_disable(struct geni_se *se); 586 587 int geni_se_resources_init(struct geni_se *se); 588 589 int geni_se_resources_activate(struct geni_se *se); 590 591 int geni_se_resources_deactivate(struct geni_se *se); 592 593 int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol); 594 595 int geni_se_domain_attach(struct geni_se *se); 596 597 int geni_se_set_perf_level(struct geni_se *se, unsigned long level); 598 599 int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq); 600 #endif 601 #endif 602