1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2025 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <net/arp.h> 27 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/netdevice.h> 31 #include <linux/inetdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/in.h> 35 #include <linux/ip.h> 36 #include <linux/ipv6.h> 37 #include <linux/phy.h> 38 39 #include <linux/unaligned.h> 40 41 #include "bcmgenet.h" 42 43 #define GENET_Q0_WEIGHT 1 44 #define GENET_Q1_WEIGHT 4 45 46 #define GENET_Q0_RX_BD_CNT \ 47 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 48 #define GENET_Q0_TX_BD_CNT \ 49 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 50 51 #define RX_BUF_LENGTH 2048 52 #define SKB_ALIGNMENT 32 53 54 /* Page pool RX buffer layout: 55 * RSB(64) + pad(2) | frame data | skb_shared_info 56 * The HW writes the 64B RSB + 2B alignment padding before the frame. 57 */ 58 #define GENET_RSB_PAD (sizeof(struct status_64) + 2) 59 60 /* RX buffer plus the skb_shared_info napi_build_skb() places behind it */ 61 #define GENET_RX_BUF_SIZE SKB_HEAD_ALIGN(RX_BUF_LENGTH) 62 63 /* Tx/Rx DMA register offset, skip 256 descriptors */ 64 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 65 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 66 67 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 68 TOTAL_DESC * DMA_DESC_SIZE) 69 70 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 71 TOTAL_DESC * DMA_DESC_SIZE) 72 73 /* Forward declarations */ 74 static void bcmgenet_set_rx_mode(struct net_device *dev); 75 76 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 77 { 78 /* MIPS chips strapped for BE will automagically configure the 79 * peripheral registers for CPU-native byte order. 80 */ 81 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 82 __raw_writel(value, offset); 83 else 84 writel_relaxed(value, offset); 85 } 86 87 static inline u32 bcmgenet_readl(void __iomem *offset) 88 { 89 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 90 return __raw_readl(offset); 91 else 92 return readl_relaxed(offset); 93 } 94 95 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 96 void __iomem *d, u32 value) 97 { 98 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 99 } 100 101 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 102 void __iomem *d, 103 dma_addr_t addr) 104 { 105 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 106 107 /* Register writes to GISB bus can take couple hundred nanoseconds 108 * and are done for each packet, save these expensive writes unless 109 * the platform is explicitly configured for 64-bits/LPAE. 110 */ 111 #ifdef CONFIG_PHYS_ADDR_T_64BIT 112 if (bcmgenet_has_40bits(priv)) 113 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 114 #endif 115 } 116 117 /* Combined address + length/status setter */ 118 static inline void dmadesc_set(struct bcmgenet_priv *priv, 119 void __iomem *d, dma_addr_t addr, u32 val) 120 { 121 dmadesc_set_addr(priv, d, addr); 122 dmadesc_set_length_status(priv, d, val); 123 } 124 125 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 126 127 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 128 NETIF_MSG_LINK) 129 130 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 131 { 132 if (GENET_IS_V1(priv)) 133 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 134 else 135 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 136 } 137 138 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 139 { 140 if (GENET_IS_V1(priv)) 141 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 142 else 143 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 144 } 145 146 /* These macros are defined to deal with register map change 147 * between GENET1.1 and GENET2. Only those currently being used 148 * by driver are defined. 149 */ 150 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 151 { 152 if (GENET_IS_V1(priv)) 153 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 154 else 155 return bcmgenet_readl(priv->base + 156 priv->hw_params->tbuf_offset + TBUF_CTRL); 157 } 158 159 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 160 { 161 if (GENET_IS_V1(priv)) 162 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 163 else 164 bcmgenet_writel(val, priv->base + 165 priv->hw_params->tbuf_offset + TBUF_CTRL); 166 } 167 168 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 169 { 170 if (GENET_IS_V1(priv)) 171 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 172 else 173 return bcmgenet_readl(priv->base + 174 priv->hw_params->tbuf_offset + TBUF_BP_MC); 175 } 176 177 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 178 { 179 if (GENET_IS_V1(priv)) 180 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 181 else 182 bcmgenet_writel(val, priv->base + 183 priv->hw_params->tbuf_offset + TBUF_BP_MC); 184 } 185 186 /* RX/TX DMA register accessors */ 187 enum dma_reg { 188 DMA_RING_CFG = 0, 189 DMA_CTRL, 190 DMA_STATUS, 191 DMA_SCB_BURST_SIZE, 192 DMA_ARB_CTRL, 193 DMA_PRIORITY_0, 194 DMA_PRIORITY_1, 195 DMA_PRIORITY_2, 196 DMA_INDEX2RING_0, 197 DMA_INDEX2RING_1, 198 DMA_INDEX2RING_2, 199 DMA_INDEX2RING_3, 200 DMA_INDEX2RING_4, 201 DMA_INDEX2RING_5, 202 DMA_INDEX2RING_6, 203 DMA_INDEX2RING_7, 204 DMA_RING0_TIMEOUT, 205 DMA_RING1_TIMEOUT, 206 DMA_RING2_TIMEOUT, 207 DMA_RING3_TIMEOUT, 208 DMA_RING4_TIMEOUT, 209 DMA_RING5_TIMEOUT, 210 DMA_RING6_TIMEOUT, 211 DMA_RING7_TIMEOUT, 212 DMA_RING8_TIMEOUT, 213 DMA_RING9_TIMEOUT, 214 DMA_RING10_TIMEOUT, 215 DMA_RING11_TIMEOUT, 216 DMA_RING12_TIMEOUT, 217 DMA_RING13_TIMEOUT, 218 DMA_RING14_TIMEOUT, 219 DMA_RING15_TIMEOUT, 220 DMA_RING16_TIMEOUT, 221 }; 222 223 static const u8 bcmgenet_dma_regs_v3plus[] = { 224 [DMA_RING_CFG] = 0x00, 225 [DMA_CTRL] = 0x04, 226 [DMA_STATUS] = 0x08, 227 [DMA_SCB_BURST_SIZE] = 0x0C, 228 [DMA_ARB_CTRL] = 0x2C, 229 [DMA_PRIORITY_0] = 0x30, 230 [DMA_PRIORITY_1] = 0x34, 231 [DMA_PRIORITY_2] = 0x38, 232 [DMA_RING0_TIMEOUT] = 0x2C, 233 [DMA_RING1_TIMEOUT] = 0x30, 234 [DMA_RING2_TIMEOUT] = 0x34, 235 [DMA_RING3_TIMEOUT] = 0x38, 236 [DMA_RING4_TIMEOUT] = 0x3c, 237 [DMA_RING5_TIMEOUT] = 0x40, 238 [DMA_RING6_TIMEOUT] = 0x44, 239 [DMA_RING7_TIMEOUT] = 0x48, 240 [DMA_RING8_TIMEOUT] = 0x4c, 241 [DMA_RING9_TIMEOUT] = 0x50, 242 [DMA_RING10_TIMEOUT] = 0x54, 243 [DMA_RING11_TIMEOUT] = 0x58, 244 [DMA_RING12_TIMEOUT] = 0x5c, 245 [DMA_RING13_TIMEOUT] = 0x60, 246 [DMA_RING14_TIMEOUT] = 0x64, 247 [DMA_RING15_TIMEOUT] = 0x68, 248 [DMA_RING16_TIMEOUT] = 0x6C, 249 [DMA_INDEX2RING_0] = 0x70, 250 [DMA_INDEX2RING_1] = 0x74, 251 [DMA_INDEX2RING_2] = 0x78, 252 [DMA_INDEX2RING_3] = 0x7C, 253 [DMA_INDEX2RING_4] = 0x80, 254 [DMA_INDEX2RING_5] = 0x84, 255 [DMA_INDEX2RING_6] = 0x88, 256 [DMA_INDEX2RING_7] = 0x8C, 257 }; 258 259 static const u8 bcmgenet_dma_regs_v2[] = { 260 [DMA_RING_CFG] = 0x00, 261 [DMA_CTRL] = 0x04, 262 [DMA_STATUS] = 0x08, 263 [DMA_SCB_BURST_SIZE] = 0x0C, 264 [DMA_ARB_CTRL] = 0x30, 265 [DMA_PRIORITY_0] = 0x34, 266 [DMA_PRIORITY_1] = 0x38, 267 [DMA_PRIORITY_2] = 0x3C, 268 [DMA_RING0_TIMEOUT] = 0x2C, 269 [DMA_RING1_TIMEOUT] = 0x30, 270 [DMA_RING2_TIMEOUT] = 0x34, 271 [DMA_RING3_TIMEOUT] = 0x38, 272 [DMA_RING4_TIMEOUT] = 0x3c, 273 [DMA_RING5_TIMEOUT] = 0x40, 274 [DMA_RING6_TIMEOUT] = 0x44, 275 [DMA_RING7_TIMEOUT] = 0x48, 276 [DMA_RING8_TIMEOUT] = 0x4c, 277 [DMA_RING9_TIMEOUT] = 0x50, 278 [DMA_RING10_TIMEOUT] = 0x54, 279 [DMA_RING11_TIMEOUT] = 0x58, 280 [DMA_RING12_TIMEOUT] = 0x5c, 281 [DMA_RING13_TIMEOUT] = 0x60, 282 [DMA_RING14_TIMEOUT] = 0x64, 283 [DMA_RING15_TIMEOUT] = 0x68, 284 [DMA_RING16_TIMEOUT] = 0x6C, 285 }; 286 287 static const u8 bcmgenet_dma_regs_v1[] = { 288 [DMA_CTRL] = 0x00, 289 [DMA_STATUS] = 0x04, 290 [DMA_SCB_BURST_SIZE] = 0x0C, 291 [DMA_ARB_CTRL] = 0x30, 292 [DMA_PRIORITY_0] = 0x34, 293 [DMA_PRIORITY_1] = 0x38, 294 [DMA_PRIORITY_2] = 0x3C, 295 [DMA_RING0_TIMEOUT] = 0x2C, 296 [DMA_RING1_TIMEOUT] = 0x30, 297 [DMA_RING2_TIMEOUT] = 0x34, 298 [DMA_RING3_TIMEOUT] = 0x38, 299 [DMA_RING4_TIMEOUT] = 0x3c, 300 [DMA_RING5_TIMEOUT] = 0x40, 301 [DMA_RING6_TIMEOUT] = 0x44, 302 [DMA_RING7_TIMEOUT] = 0x48, 303 [DMA_RING8_TIMEOUT] = 0x4c, 304 [DMA_RING9_TIMEOUT] = 0x50, 305 [DMA_RING10_TIMEOUT] = 0x54, 306 [DMA_RING11_TIMEOUT] = 0x58, 307 [DMA_RING12_TIMEOUT] = 0x5c, 308 [DMA_RING13_TIMEOUT] = 0x60, 309 [DMA_RING14_TIMEOUT] = 0x64, 310 [DMA_RING15_TIMEOUT] = 0x68, 311 [DMA_RING16_TIMEOUT] = 0x6C, 312 }; 313 314 /* Set at runtime once bcmgenet version is known */ 315 static const u8 *bcmgenet_dma_regs; 316 317 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 318 { 319 return netdev_priv(dev_get_drvdata(dev)); 320 } 321 322 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 323 enum dma_reg r) 324 { 325 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 326 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 327 } 328 329 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 330 u32 val, enum dma_reg r) 331 { 332 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 333 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 334 } 335 336 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 337 enum dma_reg r) 338 { 339 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 340 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 341 } 342 343 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 344 u32 val, enum dma_reg r) 345 { 346 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 347 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 348 } 349 350 /* RDMA/TDMA ring registers and accessors 351 * we merge the common fields and just prefix with T/D the registers 352 * having different meaning depending on the direction 353 */ 354 enum dma_ring_reg { 355 TDMA_READ_PTR = 0, 356 RDMA_WRITE_PTR = TDMA_READ_PTR, 357 TDMA_READ_PTR_HI, 358 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 359 TDMA_CONS_INDEX, 360 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 361 TDMA_PROD_INDEX, 362 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 363 DMA_RING_BUF_SIZE, 364 DMA_START_ADDR, 365 DMA_START_ADDR_HI, 366 DMA_END_ADDR, 367 DMA_END_ADDR_HI, 368 DMA_MBUF_DONE_THRESH, 369 TDMA_FLOW_PERIOD, 370 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 371 TDMA_WRITE_PTR, 372 RDMA_READ_PTR = TDMA_WRITE_PTR, 373 TDMA_WRITE_PTR_HI, 374 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 375 }; 376 377 /* GENET v4 supports 40-bits pointer addressing 378 * for obvious reasons the LO and HI word parts 379 * are contiguous, but this offsets the other 380 * registers. 381 */ 382 static const u8 genet_dma_ring_regs_v4[] = { 383 [TDMA_READ_PTR] = 0x00, 384 [TDMA_READ_PTR_HI] = 0x04, 385 [TDMA_CONS_INDEX] = 0x08, 386 [TDMA_PROD_INDEX] = 0x0C, 387 [DMA_RING_BUF_SIZE] = 0x10, 388 [DMA_START_ADDR] = 0x14, 389 [DMA_START_ADDR_HI] = 0x18, 390 [DMA_END_ADDR] = 0x1C, 391 [DMA_END_ADDR_HI] = 0x20, 392 [DMA_MBUF_DONE_THRESH] = 0x24, 393 [TDMA_FLOW_PERIOD] = 0x28, 394 [TDMA_WRITE_PTR] = 0x2C, 395 [TDMA_WRITE_PTR_HI] = 0x30, 396 }; 397 398 static const u8 genet_dma_ring_regs_v123[] = { 399 [TDMA_READ_PTR] = 0x00, 400 [TDMA_CONS_INDEX] = 0x04, 401 [TDMA_PROD_INDEX] = 0x08, 402 [DMA_RING_BUF_SIZE] = 0x0C, 403 [DMA_START_ADDR] = 0x10, 404 [DMA_END_ADDR] = 0x14, 405 [DMA_MBUF_DONE_THRESH] = 0x18, 406 [TDMA_FLOW_PERIOD] = 0x1C, 407 [TDMA_WRITE_PTR] = 0x20, 408 }; 409 410 /* Set at runtime once GENET version is known */ 411 static const u8 *genet_dma_ring_regs; 412 413 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 414 unsigned int ring, 415 enum dma_ring_reg r) 416 { 417 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 418 (DMA_RING_SIZE * ring) + 419 genet_dma_ring_regs[r]); 420 } 421 422 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 423 unsigned int ring, u32 val, 424 enum dma_ring_reg r) 425 { 426 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 427 (DMA_RING_SIZE * ring) + 428 genet_dma_ring_regs[r]); 429 } 430 431 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 432 unsigned int ring, 433 enum dma_ring_reg r) 434 { 435 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 436 (DMA_RING_SIZE * ring) + 437 genet_dma_ring_regs[r]); 438 } 439 440 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 441 unsigned int ring, u32 val, 442 enum dma_ring_reg r) 443 { 444 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 445 (DMA_RING_SIZE * ring) + 446 genet_dma_ring_regs[r]); 447 } 448 449 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 450 { 451 u32 offset; 452 u32 reg; 453 454 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 455 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 456 reg |= (1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)) | 457 RBUF_HFB_EN; 458 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 459 } else { 460 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 461 reg = bcmgenet_hfb_reg_readl(priv, offset); 462 reg |= (1 << (f_index % 32)); 463 bcmgenet_hfb_reg_writel(priv, reg, offset); 464 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 465 reg |= RBUF_HFB_EN; 466 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 467 } 468 } 469 470 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index) 471 { 472 u32 offset, reg, reg1; 473 474 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 475 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 476 reg &= ~(1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)); 477 if (!(reg & RBUF_HFB_FILTER_EN_MASK)) 478 reg &= ~RBUF_HFB_EN; 479 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 480 } else { 481 offset = HFB_FLT_ENABLE_V3PLUS; 482 reg = bcmgenet_hfb_reg_readl(priv, offset); 483 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 484 if (f_index < 32) { 485 reg1 &= ~(1 << (f_index % 32)); 486 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32)); 487 } else { 488 reg &= ~(1 << (f_index % 32)); 489 bcmgenet_hfb_reg_writel(priv, reg, offset); 490 } 491 if (!reg && !reg1) { 492 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 493 reg &= ~RBUF_HFB_EN; 494 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 495 } 496 } 497 } 498 499 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 500 u32 f_index, u32 rx_queue) 501 { 502 u32 offset; 503 u32 reg; 504 505 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 506 return; 507 508 offset = f_index / 8; 509 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 510 reg &= ~(0xF << (4 * (f_index % 8))); 511 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 512 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 513 } 514 515 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 516 u32 f_index, u32 f_length) 517 { 518 u32 offset; 519 u32 reg; 520 521 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 522 offset = HFB_FLT_LEN_V2; 523 else 524 offset = HFB_FLT_LEN_V3PLUS; 525 526 offset += sizeof(u32) * 527 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4); 528 reg = bcmgenet_hfb_reg_readl(priv, offset); 529 reg &= ~(0xFF << (8 * (f_index % 4))); 530 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 531 bcmgenet_hfb_reg_writel(priv, reg, offset); 532 } 533 534 static int bcmgenet_hfb_validate_mask(void *mask, size_t size) 535 { 536 while (size) { 537 switch (*(unsigned char *)mask++) { 538 case 0x00: 539 case 0x0f: 540 case 0xf0: 541 case 0xff: 542 size--; 543 continue; 544 default: 545 return -EINVAL; 546 } 547 } 548 549 return 0; 550 } 551 552 #define VALIDATE_MASK(x) \ 553 bcmgenet_hfb_validate_mask(&(x), sizeof(x)) 554 555 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index, 556 u32 offset, void *val, void *mask, 557 size_t size) 558 { 559 u32 index, tmp; 560 561 index = f_index * priv->hw_params->hfb_filter_size + offset / 2; 562 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32)); 563 564 while (size--) { 565 if (offset++ & 1) { 566 tmp &= ~0x300FF; 567 tmp |= (*(unsigned char *)val++); 568 switch ((*(unsigned char *)mask++)) { 569 case 0xFF: 570 tmp |= 0x30000; 571 break; 572 case 0xF0: 573 tmp |= 0x20000; 574 break; 575 case 0x0F: 576 tmp |= 0x10000; 577 break; 578 } 579 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32)); 580 if (size) 581 tmp = bcmgenet_hfb_readl(priv, 582 index * sizeof(u32)); 583 } else { 584 tmp &= ~0xCFF00; 585 tmp |= (*(unsigned char *)val++) << 8; 586 switch ((*(unsigned char *)mask++)) { 587 case 0xFF: 588 tmp |= 0xC0000; 589 break; 590 case 0xF0: 591 tmp |= 0x80000; 592 break; 593 case 0x0F: 594 tmp |= 0x40000; 595 break; 596 } 597 if (!size) 598 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32)); 599 } 600 } 601 602 return 0; 603 } 604 605 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv, 606 struct bcmgenet_rxnfc_rule *rule) 607 { 608 struct ethtool_rx_flow_spec *fs = &rule->fs; 609 u32 offset = 0, f_length = 0, f, q; 610 u8 val_8, mask_8; 611 __be16 val_16; 612 u16 mask_16; 613 size_t size; 614 615 f = fs->location + 1; 616 if (fs->flow_type & FLOW_MAC_EXT) { 617 bcmgenet_hfb_insert_data(priv, f, 0, 618 &fs->h_ext.h_dest, &fs->m_ext.h_dest, 619 sizeof(fs->h_ext.h_dest)); 620 } 621 622 if (fs->flow_type & FLOW_EXT) { 623 if (fs->m_ext.vlan_etype || 624 fs->m_ext.vlan_tci) { 625 bcmgenet_hfb_insert_data(priv, f, 12, 626 &fs->h_ext.vlan_etype, 627 &fs->m_ext.vlan_etype, 628 sizeof(fs->h_ext.vlan_etype)); 629 bcmgenet_hfb_insert_data(priv, f, 14, 630 &fs->h_ext.vlan_tci, 631 &fs->m_ext.vlan_tci, 632 sizeof(fs->h_ext.vlan_tci)); 633 offset += VLAN_HLEN; 634 f_length += DIV_ROUND_UP(VLAN_HLEN, 2); 635 } 636 } 637 638 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 639 case ETHER_FLOW: 640 f_length += DIV_ROUND_UP(ETH_HLEN, 2); 641 bcmgenet_hfb_insert_data(priv, f, 0, 642 &fs->h_u.ether_spec.h_dest, 643 &fs->m_u.ether_spec.h_dest, 644 sizeof(fs->h_u.ether_spec.h_dest)); 645 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN, 646 &fs->h_u.ether_spec.h_source, 647 &fs->m_u.ether_spec.h_source, 648 sizeof(fs->h_u.ether_spec.h_source)); 649 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 650 &fs->h_u.ether_spec.h_proto, 651 &fs->m_u.ether_spec.h_proto, 652 sizeof(fs->h_u.ether_spec.h_proto)); 653 break; 654 case IP_USER_FLOW: 655 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2); 656 /* Specify IP Ether Type */ 657 val_16 = htons(ETH_P_IP); 658 mask_16 = 0xFFFF; 659 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 660 &val_16, &mask_16, sizeof(val_16)); 661 bcmgenet_hfb_insert_data(priv, f, 15 + offset, 662 &fs->h_u.usr_ip4_spec.tos, 663 &fs->m_u.usr_ip4_spec.tos, 664 sizeof(fs->h_u.usr_ip4_spec.tos)); 665 bcmgenet_hfb_insert_data(priv, f, 23 + offset, 666 &fs->h_u.usr_ip4_spec.proto, 667 &fs->m_u.usr_ip4_spec.proto, 668 sizeof(fs->h_u.usr_ip4_spec.proto)); 669 bcmgenet_hfb_insert_data(priv, f, 26 + offset, 670 &fs->h_u.usr_ip4_spec.ip4src, 671 &fs->m_u.usr_ip4_spec.ip4src, 672 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 673 bcmgenet_hfb_insert_data(priv, f, 30 + offset, 674 &fs->h_u.usr_ip4_spec.ip4dst, 675 &fs->m_u.usr_ip4_spec.ip4dst, 676 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 677 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 678 break; 679 680 /* Only supports 20 byte IPv4 header */ 681 val_8 = 0x45; 682 mask_8 = 0xFF; 683 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset, 684 &val_8, &mask_8, 685 sizeof(val_8)); 686 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes); 687 bcmgenet_hfb_insert_data(priv, f, 688 ETH_HLEN + 20 + offset, 689 &fs->h_u.usr_ip4_spec.l4_4_bytes, 690 &fs->m_u.usr_ip4_spec.l4_4_bytes, 691 size); 692 f_length += DIV_ROUND_UP(size, 2); 693 break; 694 } 695 696 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length); 697 if (fs->ring_cookie == RX_CLS_FLOW_WAKE) 698 q = 0; 699 else if (fs->ring_cookie == RX_CLS_FLOW_DISC) 700 q = priv->hw_params->rx_queues + 1; 701 else 702 /* Other Rx rings are direct mapped here */ 703 q = fs->ring_cookie; 704 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, q); 705 bcmgenet_hfb_enable_filter(priv, f); 706 rule->state = BCMGENET_RXNFC_STATE_ENABLED; 707 } 708 709 /* bcmgenet_hfb_clear 710 * 711 * Clear Hardware Filter Block and disable all filtering. 712 */ 713 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index) 714 { 715 u32 base, i; 716 717 bcmgenet_hfb_set_filter_length(priv, f_index, 0); 718 base = f_index * priv->hw_params->hfb_filter_size; 719 for (i = 0; i < priv->hw_params->hfb_filter_size; i++) 720 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32)); 721 } 722 723 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 724 { 725 u32 i; 726 727 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 728 729 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) { 730 bcmgenet_hfb_reg_writel(priv, 0, 731 HFB_FLT_ENABLE_V3PLUS); 732 bcmgenet_hfb_reg_writel(priv, 0, 733 HFB_FLT_ENABLE_V3PLUS + 4); 734 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 735 bcmgenet_rdma_writel(priv, 0, i); 736 } 737 738 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++) 739 bcmgenet_hfb_clear_filter(priv, i); 740 741 /* Enable filter 0 to send default flow to ring 0 */ 742 bcmgenet_hfb_set_filter_length(priv, 0, 4); 743 bcmgenet_hfb_enable_filter(priv, 0); 744 } 745 746 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 747 { 748 int i; 749 750 INIT_LIST_HEAD(&priv->rxnfc_list); 751 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 752 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list); 753 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED; 754 } 755 } 756 757 static void bcmgenet_hfb_restore(struct bcmgenet_priv *priv) 758 { 759 struct bcmgenet_rxnfc_rule *rule; 760 761 bcmgenet_hfb_clear(priv); 762 763 list_for_each_entry(rule, &priv->rxnfc_list, list) 764 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) 765 bcmgenet_hfb_create_rxnfc_filter(priv, rule); 766 } 767 768 static int bcmgenet_begin(struct net_device *dev) 769 { 770 struct bcmgenet_priv *priv = netdev_priv(dev); 771 772 /* Turn on the clock */ 773 return clk_prepare_enable(priv->clk); 774 } 775 776 static void bcmgenet_complete(struct net_device *dev) 777 { 778 struct bcmgenet_priv *priv = netdev_priv(dev); 779 780 /* Turn off the clock */ 781 clk_disable_unprepare(priv->clk); 782 } 783 784 static int bcmgenet_get_link_ksettings(struct net_device *dev, 785 struct ethtool_link_ksettings *cmd) 786 { 787 if (!netif_running(dev)) 788 return -EINVAL; 789 790 if (!dev->phydev) 791 return -ENODEV; 792 793 phy_ethtool_ksettings_get(dev->phydev, cmd); 794 795 return 0; 796 } 797 798 static int bcmgenet_set_link_ksettings(struct net_device *dev, 799 const struct ethtool_link_ksettings *cmd) 800 { 801 if (!netif_running(dev)) 802 return -EINVAL; 803 804 if (!dev->phydev) 805 return -ENODEV; 806 807 return phy_ethtool_ksettings_set(dev->phydev, cmd); 808 } 809 810 static int bcmgenet_set_features(struct net_device *dev, 811 netdev_features_t features) 812 { 813 struct bcmgenet_priv *priv = netdev_priv(dev); 814 u32 reg; 815 int ret; 816 817 ret = clk_prepare_enable(priv->clk); 818 if (ret) 819 return ret; 820 821 /* Make sure we reflect the value of CRC_CMD_FWD */ 822 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 823 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 824 825 clk_disable_unprepare(priv->clk); 826 827 return ret; 828 } 829 830 static u32 bcmgenet_get_msglevel(struct net_device *dev) 831 { 832 struct bcmgenet_priv *priv = netdev_priv(dev); 833 834 return priv->msg_enable; 835 } 836 837 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 838 { 839 struct bcmgenet_priv *priv = netdev_priv(dev); 840 841 priv->msg_enable = level; 842 } 843 844 static int bcmgenet_get_coalesce(struct net_device *dev, 845 struct ethtool_coalesce *ec, 846 struct kernel_ethtool_coalesce *kernel_coal, 847 struct netlink_ext_ack *extack) 848 { 849 struct bcmgenet_priv *priv = netdev_priv(dev); 850 struct bcmgenet_rx_ring *ring; 851 unsigned int i; 852 853 ec->tx_max_coalesced_frames = 854 bcmgenet_tdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH); 855 ec->rx_max_coalesced_frames = 856 bcmgenet_rdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH); 857 ec->rx_coalesce_usecs = 858 (bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT) & 859 DMA_TIMEOUT_MASK) * 8192 / 1000; 860 861 for (i = 0; i <= priv->hw_params->rx_queues; i++) { 862 ring = &priv->rx_rings[i]; 863 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 864 } 865 866 return 0; 867 } 868 869 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 870 u32 usecs, u32 pkts) 871 { 872 struct bcmgenet_priv *priv = ring->priv; 873 unsigned int i = ring->index; 874 u32 reg; 875 876 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 877 878 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 879 reg &= ~DMA_TIMEOUT_MASK; 880 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 881 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 882 } 883 884 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 885 struct ethtool_coalesce *ec) 886 { 887 struct dim_cq_moder moder; 888 u32 usecs, pkts; 889 890 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 891 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 892 usecs = ring->rx_coalesce_usecs; 893 pkts = ring->rx_max_coalesced_frames; 894 895 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 896 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 897 usecs = moder.usec; 898 pkts = moder.pkts; 899 } 900 901 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 902 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 903 } 904 905 static int bcmgenet_set_coalesce(struct net_device *dev, 906 struct ethtool_coalesce *ec, 907 struct kernel_ethtool_coalesce *kernel_coal, 908 struct netlink_ext_ack *extack) 909 { 910 struct bcmgenet_priv *priv = netdev_priv(dev); 911 unsigned int i; 912 913 /* Base system clock is 125Mhz, DMA timeout is this reference clock 914 * divided by 1024, which yields roughly 8.192us, our maximum value 915 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 916 */ 917 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 918 ec->tx_max_coalesced_frames == 0 || 919 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 920 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 921 return -EINVAL; 922 923 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 924 return -EINVAL; 925 926 /* GENET TDMA hardware does not support a configurable timeout, but will 927 * always generate an interrupt either after MBDONE packets have been 928 * transmitted, or when the ring is empty. 929 */ 930 931 /* Program all TX queues with the same values, as there is no 932 * ethtool knob to do coalescing on a per-queue basis 933 */ 934 for (i = 0; i <= priv->hw_params->tx_queues; i++) 935 bcmgenet_tdma_ring_writel(priv, i, 936 ec->tx_max_coalesced_frames, 937 DMA_MBUF_DONE_THRESH); 938 939 for (i = 0; i <= priv->hw_params->rx_queues; i++) 940 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 941 942 return 0; 943 } 944 945 static void bcmgenet_get_pauseparam(struct net_device *dev, 946 struct ethtool_pauseparam *epause) 947 { 948 struct bcmgenet_priv *priv; 949 u32 umac_cmd; 950 951 priv = netdev_priv(dev); 952 953 epause->autoneg = priv->autoneg_pause; 954 955 if (netif_carrier_ok(dev)) { 956 /* report active state when link is up */ 957 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD); 958 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE); 959 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE); 960 } else { 961 /* otherwise report stored settings */ 962 epause->tx_pause = priv->tx_pause; 963 epause->rx_pause = priv->rx_pause; 964 } 965 } 966 967 static int bcmgenet_set_pauseparam(struct net_device *dev, 968 struct ethtool_pauseparam *epause) 969 { 970 struct bcmgenet_priv *priv = netdev_priv(dev); 971 972 if (!dev->phydev) 973 return -ENODEV; 974 975 if (!phy_validate_pause(dev->phydev, epause)) 976 return -EINVAL; 977 978 priv->autoneg_pause = !!epause->autoneg; 979 priv->tx_pause = !!epause->tx_pause; 980 priv->rx_pause = !!epause->rx_pause; 981 982 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 983 984 return 0; 985 } 986 987 /* standard ethtool support functions. */ 988 enum bcmgenet_stat_type { 989 BCMGENET_STAT_RTNL = -1, 990 BCMGENET_STAT_MIB_RX, 991 BCMGENET_STAT_MIB_TX, 992 BCMGENET_STAT_RUNT, 993 BCMGENET_STAT_MISC, 994 BCMGENET_STAT_SOFT, 995 BCMGENET_STAT_SOFT64, 996 }; 997 998 struct bcmgenet_stats { 999 char stat_string[ETH_GSTRING_LEN]; 1000 int stat_sizeof; 1001 int stat_offset; 1002 enum bcmgenet_stat_type type; 1003 /* reg offset from UMAC base for misc counters */ 1004 u16 reg_offset; 1005 /* sync for u64 stats counters */ 1006 int syncp_offset; 1007 }; 1008 1009 #define STAT_RTNL(m) { \ 1010 .stat_string = __stringify(m), \ 1011 .stat_sizeof = sizeof(((struct rtnl_link_stats64 *)0)->m), \ 1012 .stat_offset = offsetof(struct rtnl_link_stats64, m), \ 1013 .type = BCMGENET_STAT_RTNL, \ 1014 } 1015 1016 #define STAT_GENET_MIB(str, m, _type) { \ 1017 .stat_string = str, \ 1018 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1019 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1020 .type = _type, \ 1021 } 1022 1023 #define STAT_GENET_SOFT_MIB64(str, s, m) { \ 1024 .stat_string = str, \ 1025 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->s.m), \ 1026 .stat_offset = offsetof(struct bcmgenet_priv, s.m), \ 1027 .type = BCMGENET_STAT_SOFT64, \ 1028 .syncp_offset = offsetof(struct bcmgenet_priv, s.syncp), \ 1029 } 1030 1031 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 1032 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 1033 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 1034 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 1035 1036 #define STAT_GENET_MISC(str, m, offset) { \ 1037 .stat_string = str, \ 1038 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1039 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1040 .type = BCMGENET_STAT_MISC, \ 1041 .reg_offset = offset, \ 1042 } 1043 1044 #define STAT_GENET_Q(num) \ 1045 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_packets", \ 1046 tx_rings[num].stats64, packets), \ 1047 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_bytes", \ 1048 tx_rings[num].stats64, bytes), \ 1049 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_errors", \ 1050 tx_rings[num].stats64, errors), \ 1051 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_dropped", \ 1052 tx_rings[num].stats64, dropped), \ 1053 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_bytes", \ 1054 rx_rings[num].stats64, bytes), \ 1055 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_packets", \ 1056 rx_rings[num].stats64, packets), \ 1057 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_errors", \ 1058 rx_rings[num].stats64, errors), \ 1059 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_dropped", \ 1060 rx_rings[num].stats64, dropped), \ 1061 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_multicast", \ 1062 rx_rings[num].stats64, multicast), \ 1063 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_missed", \ 1064 rx_rings[num].stats64, missed), \ 1065 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_length_errors", \ 1066 rx_rings[num].stats64, length_errors), \ 1067 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_over_errors", \ 1068 rx_rings[num].stats64, over_errors), \ 1069 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_crc_errors", \ 1070 rx_rings[num].stats64, crc_errors), \ 1071 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_frame_errors", \ 1072 rx_rings[num].stats64, frame_errors), \ 1073 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_fragmented_errors", \ 1074 rx_rings[num].stats64, fragmented_errors), \ 1075 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_broadcast", \ 1076 rx_rings[num].stats64, broadcast) 1077 1078 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 1079 * between the end of TX stats and the beginning of the RX RUNT 1080 */ 1081 #define BCMGENET_STAT_OFFSET 0xc 1082 1083 /* Hardware counters must be kept in sync because the order/offset 1084 * is important here (order in structure declaration = order in hardware) 1085 */ 1086 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 1087 /* general stats */ 1088 STAT_RTNL(rx_packets), 1089 STAT_RTNL(tx_packets), 1090 STAT_RTNL(rx_bytes), 1091 STAT_RTNL(tx_bytes), 1092 STAT_RTNL(rx_errors), 1093 STAT_RTNL(tx_errors), 1094 STAT_RTNL(rx_dropped), 1095 STAT_RTNL(tx_dropped), 1096 STAT_RTNL(multicast), 1097 STAT_RTNL(rx_missed_errors), 1098 STAT_RTNL(rx_length_errors), 1099 STAT_RTNL(rx_over_errors), 1100 STAT_RTNL(rx_crc_errors), 1101 STAT_RTNL(rx_frame_errors), 1102 /* UniMAC RSV counters */ 1103 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 1104 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 1105 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 1106 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 1107 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 1108 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 1109 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 1110 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 1111 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 1112 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 1113 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 1114 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 1115 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 1116 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 1117 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 1118 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 1119 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 1120 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 1121 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 1122 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 1123 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 1124 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 1125 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 1126 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 1127 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 1128 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 1129 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 1130 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 1131 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 1132 /* UniMAC TSV counters */ 1133 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 1134 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 1135 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 1136 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 1137 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 1138 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 1139 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 1140 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 1141 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 1142 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 1143 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 1144 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 1145 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 1146 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 1147 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 1148 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 1149 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 1150 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 1151 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 1152 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 1153 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 1154 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 1155 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 1156 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 1157 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 1158 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 1159 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 1160 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 1161 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 1162 /* UniMAC RUNT counters */ 1163 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 1164 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 1165 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 1166 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 1167 /* Misc UniMAC counters */ 1168 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 1169 UMAC_RBUF_OVFL_CNT_V1), 1170 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 1171 UMAC_RBUF_ERR_CNT_V1), 1172 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 1173 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 1174 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 1175 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 1176 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 1177 mib.tx_realloc_tsb_failed), 1178 /* Per TX queues */ 1179 STAT_GENET_Q(0), 1180 STAT_GENET_Q(1), 1181 STAT_GENET_Q(2), 1182 STAT_GENET_Q(3), 1183 STAT_GENET_Q(4), 1184 }; 1185 1186 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 1187 1188 #define BCMGENET_STATS64_ADD(stats, m, v) \ 1189 do { \ 1190 u64_stats_update_begin(&stats->syncp); \ 1191 u64_stats_add(&stats->m, v); \ 1192 u64_stats_update_end(&stats->syncp); \ 1193 } while (0) 1194 1195 #define BCMGENET_STATS64_INC(stats, m) \ 1196 do { \ 1197 u64_stats_update_begin(&stats->syncp); \ 1198 u64_stats_inc(&stats->m); \ 1199 u64_stats_update_end(&stats->syncp); \ 1200 } while (0) 1201 1202 static void bcmgenet_get_drvinfo(struct net_device *dev, 1203 struct ethtool_drvinfo *info) 1204 { 1205 strscpy(info->driver, "bcmgenet", sizeof(info->driver)); 1206 } 1207 1208 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 1209 { 1210 switch (string_set) { 1211 case ETH_SS_STATS: 1212 return BCMGENET_STATS_LEN; 1213 default: 1214 return -EOPNOTSUPP; 1215 } 1216 } 1217 1218 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 1219 u8 *data) 1220 { 1221 const char *str; 1222 int i; 1223 1224 switch (stringset) { 1225 case ETH_SS_STATS: 1226 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1227 str = bcmgenet_gstrings_stats[i].stat_string; 1228 ethtool_puts(&data, str); 1229 } 1230 break; 1231 } 1232 } 1233 1234 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 1235 { 1236 u16 new_offset; 1237 u32 val; 1238 1239 switch (offset) { 1240 case UMAC_RBUF_OVFL_CNT_V1: 1241 if (GENET_IS_V2(priv)) 1242 new_offset = RBUF_OVFL_CNT_V2; 1243 else 1244 new_offset = RBUF_OVFL_CNT_V3PLUS; 1245 1246 val = bcmgenet_rbuf_readl(priv, new_offset); 1247 /* clear if overflowed */ 1248 if (val == ~0) 1249 bcmgenet_rbuf_writel(priv, 0, new_offset); 1250 break; 1251 case UMAC_RBUF_ERR_CNT_V1: 1252 if (GENET_IS_V2(priv)) 1253 new_offset = RBUF_ERR_CNT_V2; 1254 else 1255 new_offset = RBUF_ERR_CNT_V3PLUS; 1256 1257 val = bcmgenet_rbuf_readl(priv, new_offset); 1258 /* clear if overflowed */ 1259 if (val == ~0) 1260 bcmgenet_rbuf_writel(priv, 0, new_offset); 1261 break; 1262 default: 1263 val = bcmgenet_umac_readl(priv, offset); 1264 /* clear if overflowed */ 1265 if (val == ~0) 1266 bcmgenet_umac_writel(priv, 0, offset); 1267 break; 1268 } 1269 1270 return val; 1271 } 1272 1273 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 1274 { 1275 int i, j = 0; 1276 1277 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1278 const struct bcmgenet_stats *s; 1279 u8 offset = 0; 1280 u32 val = 0; 1281 char *p; 1282 1283 s = &bcmgenet_gstrings_stats[i]; 1284 switch (s->type) { 1285 case BCMGENET_STAT_RTNL: 1286 case BCMGENET_STAT_SOFT: 1287 case BCMGENET_STAT_SOFT64: 1288 continue; 1289 case BCMGENET_STAT_RUNT: 1290 offset += BCMGENET_STAT_OFFSET; 1291 fallthrough; 1292 case BCMGENET_STAT_MIB_TX: 1293 offset += BCMGENET_STAT_OFFSET; 1294 fallthrough; 1295 case BCMGENET_STAT_MIB_RX: 1296 val = bcmgenet_umac_readl(priv, 1297 UMAC_MIB_START + j + offset); 1298 offset = 0; /* Reset Offset */ 1299 break; 1300 case BCMGENET_STAT_MISC: 1301 if (GENET_IS_V1(priv)) { 1302 val = bcmgenet_umac_readl(priv, s->reg_offset); 1303 /* clear if overflowed */ 1304 if (val == ~0) 1305 bcmgenet_umac_writel(priv, 0, 1306 s->reg_offset); 1307 } else { 1308 val = bcmgenet_update_stat_misc(priv, 1309 s->reg_offset); 1310 } 1311 break; 1312 } 1313 1314 j += s->stat_sizeof; 1315 p = (char *)priv + s->stat_offset; 1316 *(u32 *)p = val; 1317 } 1318 } 1319 1320 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 1321 struct ethtool_stats *stats, 1322 u64 *data) 1323 { 1324 struct bcmgenet_priv *priv = netdev_priv(dev); 1325 struct rtnl_link_stats64 stats64; 1326 struct u64_stats_sync *syncp; 1327 unsigned int start; 1328 int i; 1329 1330 if (netif_running(dev)) 1331 bcmgenet_update_mib_counters(priv); 1332 1333 dev_get_stats(dev, &stats64); 1334 1335 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1336 const struct bcmgenet_stats *s; 1337 char *p; 1338 1339 s = &bcmgenet_gstrings_stats[i]; 1340 p = (char *)priv; 1341 1342 if (s->type == BCMGENET_STAT_SOFT64) { 1343 syncp = (struct u64_stats_sync *)(p + s->syncp_offset); 1344 do { 1345 start = u64_stats_fetch_begin(syncp); 1346 data[i] = u64_stats_read((u64_stats_t *)(p + s->stat_offset)); 1347 } while (u64_stats_fetch_retry(syncp, start)); 1348 } else { 1349 if (s->type == BCMGENET_STAT_RTNL) 1350 p = (char *)&stats64; 1351 1352 p += s->stat_offset; 1353 if (s->stat_sizeof == sizeof(u64)) 1354 data[i] = *(u64 *)p; 1355 else 1356 data[i] = *(u32 *)p; 1357 } 1358 } 1359 } 1360 1361 void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1362 { 1363 struct bcmgenet_priv *priv = netdev_priv(dev); 1364 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1365 u32 reg; 1366 1367 if (enable && !priv->clk_eee_enabled) { 1368 clk_prepare_enable(priv->clk_eee); 1369 priv->clk_eee_enabled = true; 1370 } 1371 1372 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1373 if (enable) 1374 reg |= EEE_EN; 1375 else 1376 reg &= ~EEE_EN; 1377 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1378 1379 /* Enable EEE and switch to a 27Mhz clock automatically */ 1380 reg = bcmgenet_readl(priv->base + off); 1381 if (enable) 1382 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1383 else 1384 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1385 bcmgenet_writel(reg, priv->base + off); 1386 1387 /* RBUF EEE/PM can break the RX path on GENET. Keep it disabled. */ 1388 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1389 if (reg & (RBUF_EEE_EN | RBUF_PM_EN)) { 1390 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1391 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1392 } 1393 1394 if (!enable && priv->clk_eee_enabled) { 1395 clk_disable_unprepare(priv->clk_eee); 1396 priv->clk_eee_enabled = false; 1397 } 1398 1399 } 1400 1401 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_keee *e) 1402 { 1403 struct bcmgenet_priv *priv = netdev_priv(dev); 1404 int ret; 1405 1406 if (GENET_IS_V1(priv)) 1407 return -EOPNOTSUPP; 1408 1409 if (!dev->phydev) 1410 return -ENODEV; 1411 1412 ret = phy_ethtool_get_eee(dev->phydev, e); 1413 if (ret) 1414 return ret; 1415 1416 /* tx_lpi_timer is maintained by the MAC hardware register; the 1417 * PHY-level eee_cfg timer is not set for GENET. 1418 */ 1419 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1420 1421 return 0; 1422 } 1423 1424 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_keee *e) 1425 { 1426 struct bcmgenet_priv *priv = netdev_priv(dev); 1427 1428 if (GENET_IS_V1(priv)) 1429 return -EOPNOTSUPP; 1430 1431 if (!dev->phydev) 1432 return -ENODEV; 1433 1434 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1435 1436 return phy_ethtool_set_eee(dev->phydev, e); 1437 } 1438 1439 static int bcmgenet_validate_flow(struct net_device *dev, 1440 struct ethtool_rxnfc *cmd) 1441 { 1442 struct ethtool_usrip4_spec *l4_mask; 1443 struct ethhdr *eth_mask; 1444 1445 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES && 1446 cmd->fs.location != RX_CLS_LOC_ANY) { 1447 netdev_err(dev, "rxnfc: Invalid location (%d)\n", 1448 cmd->fs.location); 1449 return -EINVAL; 1450 } 1451 1452 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1453 case IP_USER_FLOW: 1454 l4_mask = &cmd->fs.m_u.usr_ip4_spec; 1455 /* don't allow mask which isn't valid */ 1456 if (VALIDATE_MASK(l4_mask->ip4src) || 1457 VALIDATE_MASK(l4_mask->ip4dst) || 1458 VALIDATE_MASK(l4_mask->l4_4_bytes) || 1459 VALIDATE_MASK(l4_mask->proto) || 1460 VALIDATE_MASK(l4_mask->ip_ver) || 1461 VALIDATE_MASK(l4_mask->tos)) { 1462 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1463 return -EINVAL; 1464 } 1465 break; 1466 case ETHER_FLOW: 1467 eth_mask = &cmd->fs.m_u.ether_spec; 1468 /* don't allow mask which isn't valid */ 1469 if (VALIDATE_MASK(eth_mask->h_dest) || 1470 VALIDATE_MASK(eth_mask->h_source) || 1471 VALIDATE_MASK(eth_mask->h_proto)) { 1472 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1473 return -EINVAL; 1474 } 1475 break; 1476 default: 1477 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n", 1478 cmd->fs.flow_type); 1479 return -EINVAL; 1480 } 1481 1482 if ((cmd->fs.flow_type & FLOW_EXT)) { 1483 /* don't allow mask which isn't valid */ 1484 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) || 1485 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) { 1486 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1487 return -EINVAL; 1488 } 1489 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) { 1490 netdev_err(dev, "rxnfc: user-def not supported\n"); 1491 return -EINVAL; 1492 } 1493 } 1494 1495 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) { 1496 /* don't allow mask which isn't valid */ 1497 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) { 1498 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1499 return -EINVAL; 1500 } 1501 } 1502 1503 return 0; 1504 } 1505 1506 static int bcmgenet_insert_flow(struct net_device *dev, 1507 struct ethtool_rxnfc *cmd) 1508 { 1509 struct bcmgenet_priv *priv = netdev_priv(dev); 1510 struct bcmgenet_rxnfc_rule *loc_rule; 1511 int err, i; 1512 1513 if (priv->hw_params->hfb_filter_size < 128) { 1514 netdev_err(dev, "rxnfc: Not supported by this device\n"); 1515 return -EINVAL; 1516 } 1517 1518 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues && 1519 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE && 1520 cmd->fs.ring_cookie != RX_CLS_FLOW_DISC) { 1521 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n", 1522 cmd->fs.ring_cookie); 1523 return -EINVAL; 1524 } 1525 1526 err = bcmgenet_validate_flow(dev, cmd); 1527 if (err) 1528 return err; 1529 1530 if (cmd->fs.location == RX_CLS_LOC_ANY) { 1531 list_for_each_entry(loc_rule, &priv->rxnfc_list, list) { 1532 cmd->fs.location = loc_rule->fs.location; 1533 err = memcmp(&loc_rule->fs, &cmd->fs, 1534 sizeof(struct ethtool_rx_flow_spec)); 1535 if (!err) 1536 /* rule exists so return current location */ 1537 return 0; 1538 } 1539 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1540 loc_rule = &priv->rxnfc_rules[i]; 1541 if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1542 cmd->fs.location = i; 1543 break; 1544 } 1545 } 1546 if (i == MAX_NUM_OF_FS_RULES) { 1547 cmd->fs.location = RX_CLS_LOC_ANY; 1548 return -ENOSPC; 1549 } 1550 } else { 1551 loc_rule = &priv->rxnfc_rules[cmd->fs.location]; 1552 } 1553 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1554 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1); 1555 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1556 list_del(&loc_rule->list); 1557 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1); 1558 } 1559 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1560 memcpy(&loc_rule->fs, &cmd->fs, 1561 sizeof(struct ethtool_rx_flow_spec)); 1562 1563 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule); 1564 1565 list_add_tail(&loc_rule->list, &priv->rxnfc_list); 1566 1567 return 0; 1568 } 1569 1570 static int bcmgenet_delete_flow(struct net_device *dev, 1571 struct ethtool_rxnfc *cmd) 1572 { 1573 struct bcmgenet_priv *priv = netdev_priv(dev); 1574 struct bcmgenet_rxnfc_rule *rule; 1575 int err = 0; 1576 1577 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1578 return -EINVAL; 1579 1580 rule = &priv->rxnfc_rules[cmd->fs.location]; 1581 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1582 err = -ENOENT; 1583 goto out; 1584 } 1585 1586 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1587 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1); 1588 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1589 list_del(&rule->list); 1590 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1); 1591 } 1592 rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1593 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec)); 1594 1595 out: 1596 return err; 1597 } 1598 1599 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1600 { 1601 struct bcmgenet_priv *priv = netdev_priv(dev); 1602 int err = 0; 1603 1604 switch (cmd->cmd) { 1605 case ETHTOOL_SRXCLSRLINS: 1606 err = bcmgenet_insert_flow(dev, cmd); 1607 break; 1608 case ETHTOOL_SRXCLSRLDEL: 1609 err = bcmgenet_delete_flow(dev, cmd); 1610 break; 1611 default: 1612 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n", 1613 cmd->cmd); 1614 return -EINVAL; 1615 } 1616 1617 return err; 1618 } 1619 1620 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1621 int loc) 1622 { 1623 struct bcmgenet_priv *priv = netdev_priv(dev); 1624 struct bcmgenet_rxnfc_rule *rule; 1625 int err = 0; 1626 1627 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1628 return -EINVAL; 1629 1630 rule = &priv->rxnfc_rules[loc]; 1631 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) 1632 err = -ENOENT; 1633 else 1634 memcpy(&cmd->fs, &rule->fs, 1635 sizeof(struct ethtool_rx_flow_spec)); 1636 1637 return err; 1638 } 1639 1640 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv) 1641 { 1642 struct list_head *pos; 1643 int res = 0; 1644 1645 list_for_each(pos, &priv->rxnfc_list) 1646 res++; 1647 1648 return res; 1649 } 1650 1651 static u32 bcmgenet_get_rx_ring_count(struct net_device *dev) 1652 { 1653 struct bcmgenet_priv *priv = netdev_priv(dev); 1654 1655 return priv->hw_params->rx_queues ?: 1; 1656 } 1657 1658 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1659 u32 *rule_locs) 1660 { 1661 struct bcmgenet_priv *priv = netdev_priv(dev); 1662 struct bcmgenet_rxnfc_rule *rule; 1663 int err = 0; 1664 int i = 0; 1665 1666 switch (cmd->cmd) { 1667 case ETHTOOL_GRXCLSRLCNT: 1668 cmd->rule_cnt = bcmgenet_get_num_flows(priv); 1669 cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL; 1670 break; 1671 case ETHTOOL_GRXCLSRULE: 1672 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location); 1673 break; 1674 case ETHTOOL_GRXCLSRLALL: 1675 list_for_each_entry(rule, &priv->rxnfc_list, list) 1676 if (i < cmd->rule_cnt) 1677 rule_locs[i++] = rule->fs.location; 1678 cmd->rule_cnt = i; 1679 cmd->data = MAX_NUM_OF_FS_RULES; 1680 break; 1681 default: 1682 err = -EOPNOTSUPP; 1683 break; 1684 } 1685 1686 return err; 1687 } 1688 1689 /* standard ethtool support functions. */ 1690 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1691 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1692 ETHTOOL_COALESCE_MAX_FRAMES | 1693 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1694 .begin = bcmgenet_begin, 1695 .complete = bcmgenet_complete, 1696 .get_strings = bcmgenet_get_strings, 1697 .get_sset_count = bcmgenet_get_sset_count, 1698 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1699 .get_drvinfo = bcmgenet_get_drvinfo, 1700 .get_link = ethtool_op_get_link, 1701 .get_msglevel = bcmgenet_get_msglevel, 1702 .set_msglevel = bcmgenet_set_msglevel, 1703 .get_wol = bcmgenet_get_wol, 1704 .set_wol = bcmgenet_set_wol, 1705 .get_eee = bcmgenet_get_eee, 1706 .set_eee = bcmgenet_set_eee, 1707 .nway_reset = phy_ethtool_nway_reset, 1708 .get_coalesce = bcmgenet_get_coalesce, 1709 .set_coalesce = bcmgenet_set_coalesce, 1710 .get_link_ksettings = bcmgenet_get_link_ksettings, 1711 .set_link_ksettings = bcmgenet_set_link_ksettings, 1712 .get_ts_info = ethtool_op_get_ts_info, 1713 .get_rxnfc = bcmgenet_get_rxnfc, 1714 .set_rxnfc = bcmgenet_set_rxnfc, 1715 .get_rx_ring_count = bcmgenet_get_rx_ring_count, 1716 .get_pauseparam = bcmgenet_get_pauseparam, 1717 .set_pauseparam = bcmgenet_set_pauseparam, 1718 }; 1719 1720 /* Power down the unimac, based on mode. */ 1721 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1722 enum bcmgenet_power_mode mode) 1723 { 1724 int ret = 0; 1725 u32 reg; 1726 1727 switch (mode) { 1728 case GENET_POWER_CABLE_SENSE: 1729 phy_detach(priv->dev->phydev); 1730 break; 1731 1732 case GENET_POWER_WOL_MAGIC: 1733 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1734 break; 1735 1736 case GENET_POWER_PASSIVE: 1737 /* Power down LED */ 1738 if (bcmgenet_has_ext(priv)) { 1739 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1740 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) 1741 reg |= EXT_PWR_DOWN_PHY_EN | 1742 EXT_PWR_DOWN_PHY_RD | 1743 EXT_PWR_DOWN_PHY_SD | 1744 EXT_PWR_DOWN_PHY_RX | 1745 EXT_PWR_DOWN_PHY_TX | 1746 EXT_IDDQ_GLBL_PWR; 1747 else 1748 reg |= EXT_PWR_DOWN_PHY; 1749 1750 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1751 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1752 1753 bcmgenet_phy_power_set(priv->dev, false); 1754 } 1755 break; 1756 default: 1757 break; 1758 } 1759 1760 return ret; 1761 } 1762 1763 static int bcmgenet_power_up(struct bcmgenet_priv *priv, 1764 enum bcmgenet_power_mode mode) 1765 { 1766 int ret = 0; 1767 u32 reg; 1768 1769 switch (mode) { 1770 case GENET_POWER_PASSIVE: 1771 if (!bcmgenet_has_ext(priv)) 1772 break; 1773 1774 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1775 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS | 1776 EXT_ENERGY_DET_MASK); 1777 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) { 1778 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1779 EXT_PWR_DOWN_PHY_RD | 1780 EXT_PWR_DOWN_PHY_SD | 1781 EXT_PWR_DOWN_PHY_RX | 1782 EXT_PWR_DOWN_PHY_TX | 1783 EXT_IDDQ_GLBL_PWR); 1784 reg |= EXT_PHY_RESET; 1785 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1786 mdelay(1); 1787 1788 reg &= ~EXT_PHY_RESET; 1789 } else { 1790 reg &= ~EXT_PWR_DOWN_PHY; 1791 reg |= EXT_PWR_DN_EN_LD; 1792 } 1793 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1794 bcmgenet_phy_power_set(priv->dev, true); 1795 break; 1796 1797 case GENET_POWER_CABLE_SENSE: 1798 if (!bcmgenet_has_ext(priv)) 1799 break; 1800 1801 /* enable APD */ 1802 if (!GENET_IS_V5(priv)) { 1803 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1804 reg |= EXT_PWR_DN_EN_LD; 1805 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1806 } 1807 break; 1808 case GENET_POWER_WOL_MAGIC: 1809 ret = bcmgenet_wol_power_up_cfg(priv, mode); 1810 break; 1811 default: 1812 break; 1813 } 1814 1815 return ret; 1816 } 1817 1818 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1819 struct bcmgenet_tx_ring *ring) 1820 { 1821 struct enet_cb *tx_cb_ptr; 1822 1823 tx_cb_ptr = ring->cbs; 1824 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1825 1826 /* Advancing local write pointer */ 1827 if (ring->write_ptr == ring->end_ptr) 1828 ring->write_ptr = ring->cb_ptr; 1829 else 1830 ring->write_ptr++; 1831 1832 return tx_cb_ptr; 1833 } 1834 1835 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1836 struct bcmgenet_tx_ring *ring) 1837 { 1838 struct enet_cb *tx_cb_ptr; 1839 1840 /* Rewinding local write pointer */ 1841 if (ring->write_ptr == ring->cb_ptr) 1842 ring->write_ptr = ring->end_ptr; 1843 else 1844 ring->write_ptr--; 1845 1846 tx_cb_ptr = ring->cbs; 1847 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1848 1849 return tx_cb_ptr; 1850 } 1851 1852 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1853 { 1854 bcmgenet_intrl2_1_writel(ring->priv, 1855 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1856 INTRL2_CPU_MASK_SET); 1857 } 1858 1859 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1860 { 1861 bcmgenet_intrl2_1_writel(ring->priv, 1862 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1863 INTRL2_CPU_MASK_CLEAR); 1864 } 1865 1866 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1867 { 1868 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1869 INTRL2_CPU_MASK_CLEAR); 1870 } 1871 1872 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1873 { 1874 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1875 INTRL2_CPU_MASK_SET); 1876 } 1877 1878 /* Simple helper to free a transmit control block's resources 1879 * Returns an skb when the last transmit control block associated with the 1880 * skb is freed. The skb should be freed by the caller if necessary. 1881 */ 1882 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1883 struct enet_cb *cb) 1884 { 1885 struct sk_buff *skb; 1886 1887 skb = cb->skb; 1888 1889 if (skb) { 1890 cb->skb = NULL; 1891 if (cb == GENET_CB(skb)->first_cb) 1892 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1893 dma_unmap_len(cb, dma_len), 1894 DMA_TO_DEVICE); 1895 else 1896 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1897 dma_unmap_len(cb, dma_len), 1898 DMA_TO_DEVICE); 1899 dma_unmap_addr_set(cb, dma_addr, 0); 1900 1901 if (cb == GENET_CB(skb)->last_cb) 1902 return skb; 1903 1904 } else if (dma_unmap_addr(cb, dma_addr)) { 1905 dma_unmap_page(dev, 1906 dma_unmap_addr(cb, dma_addr), 1907 dma_unmap_len(cb, dma_len), 1908 DMA_TO_DEVICE); 1909 dma_unmap_addr_set(cb, dma_addr, 0); 1910 } 1911 1912 return NULL; 1913 } 1914 1915 /* Simple helper to free a receive control block's resources */ 1916 static void bcmgenet_free_rx_cb(struct enet_cb *cb, 1917 struct page_pool *pool) 1918 { 1919 if (cb->rx_page) { 1920 page_pool_put_full_page(pool, cb->rx_page, false); 1921 cb->rx_page = NULL; 1922 } 1923 } 1924 1925 /* Unlocked version of the reclaim routine */ 1926 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1927 struct bcmgenet_tx_ring *ring) 1928 { 1929 struct bcmgenet_tx_stats64 *stats = &ring->stats64; 1930 struct bcmgenet_priv *priv = netdev_priv(dev); 1931 unsigned int txbds_processed = 0; 1932 unsigned int bytes_compl = 0; 1933 unsigned int pkts_compl = 0; 1934 unsigned int txbds_ready; 1935 unsigned int c_index; 1936 struct sk_buff *skb; 1937 1938 /* Clear status before servicing to reduce spurious interrupts */ 1939 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), INTRL2_CPU_CLEAR); 1940 1941 /* Compute how many buffers are transmitted since last xmit call */ 1942 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1943 & DMA_C_INDEX_MASK; 1944 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1945 1946 netif_dbg(priv, tx_done, dev, 1947 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1948 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1949 1950 /* Reclaim transmitted buffers */ 1951 while (txbds_processed < txbds_ready) { 1952 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1953 &priv->tx_cbs[ring->clean_ptr]); 1954 if (skb) { 1955 pkts_compl++; 1956 bytes_compl += GENET_CB(skb)->bytes_sent; 1957 dev_consume_skb_any(skb); 1958 } 1959 1960 txbds_processed++; 1961 if (likely(ring->clean_ptr < ring->end_ptr)) 1962 ring->clean_ptr++; 1963 else 1964 ring->clean_ptr = ring->cb_ptr; 1965 } 1966 1967 ring->free_bds += txbds_processed; 1968 ring->c_index = c_index; 1969 1970 u64_stats_update_begin(&stats->syncp); 1971 u64_stats_add(&stats->packets, pkts_compl); 1972 u64_stats_add(&stats->bytes, bytes_compl); 1973 u64_stats_update_end(&stats->syncp); 1974 1975 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->index), 1976 pkts_compl, bytes_compl); 1977 1978 return txbds_processed; 1979 } 1980 1981 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1982 struct bcmgenet_tx_ring *ring, 1983 bool all) 1984 { 1985 struct bcmgenet_priv *priv = netdev_priv(dev); 1986 struct device *kdev = &priv->pdev->dev; 1987 unsigned int released, drop, wr_ptr; 1988 struct enet_cb *cb_ptr; 1989 struct sk_buff *skb; 1990 1991 spin_lock_bh(&ring->lock); 1992 released = __bcmgenet_tx_reclaim(dev, ring); 1993 if (all) { 1994 skb = NULL; 1995 drop = (ring->prod_index - ring->c_index) & DMA_C_INDEX_MASK; 1996 released += drop; 1997 ring->prod_index = ring->c_index & DMA_C_INDEX_MASK; 1998 ring->free_bds += drop; 1999 while (drop--) { 2000 cb_ptr = bcmgenet_put_txcb(priv, ring); 2001 skb = cb_ptr->skb; 2002 bcmgenet_free_tx_cb(kdev, cb_ptr); 2003 if (skb && cb_ptr == GENET_CB(skb)->first_cb) { 2004 dev_consume_skb_any(skb); 2005 skb = NULL; 2006 } 2007 } 2008 if (skb) 2009 dev_consume_skb_any(skb); 2010 netdev_tx_reset_queue(netdev_get_tx_queue(dev, ring->index)); 2011 bcmgenet_tdma_ring_writel(priv, ring->index, 2012 ring->prod_index, TDMA_PROD_INDEX); 2013 wr_ptr = ring->write_ptr * WORDS_PER_BD(priv); 2014 bcmgenet_tdma_ring_writel(priv, ring->index, wr_ptr, 2015 TDMA_WRITE_PTR); 2016 } 2017 spin_unlock_bh(&ring->lock); 2018 2019 return released; 2020 } 2021 2022 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 2023 { 2024 struct bcmgenet_tx_ring *ring = 2025 container_of(napi, struct bcmgenet_tx_ring, napi); 2026 unsigned int work_done = 0; 2027 struct netdev_queue *txq; 2028 2029 spin_lock(&ring->lock); 2030 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 2031 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 2032 txq = netdev_get_tx_queue(ring->priv->dev, ring->index); 2033 netif_tx_wake_queue(txq); 2034 } 2035 spin_unlock(&ring->lock); 2036 2037 if (work_done == 0) { 2038 napi_complete(napi); 2039 bcmgenet_tx_ring_int_enable(ring); 2040 2041 return 0; 2042 } 2043 2044 return budget; 2045 } 2046 2047 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 2048 { 2049 struct bcmgenet_priv *priv = netdev_priv(dev); 2050 int i = 0; 2051 2052 do { 2053 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i++], true); 2054 } while (i <= priv->hw_params->tx_queues && netif_is_multiqueue(dev)); 2055 } 2056 2057 /* Reallocate the SKB to put enough headroom in front of it and insert 2058 * the transmit checksum offsets in the descriptors 2059 */ 2060 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 2061 struct sk_buff *skb, 2062 struct bcmgenet_tx_ring *ring) 2063 { 2064 struct bcmgenet_tx_stats64 *stats = &ring->stats64; 2065 struct bcmgenet_priv *priv = netdev_priv(dev); 2066 struct status_64 *status = NULL; 2067 struct sk_buff *new_skb; 2068 u16 offset; 2069 u8 ip_proto; 2070 __be16 ip_ver; 2071 u32 tx_csum_info; 2072 2073 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 2074 /* If 64 byte status block enabled, must make sure skb has 2075 * enough headroom for us to insert 64B status block. 2076 */ 2077 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 2078 if (!new_skb) { 2079 dev_kfree_skb_any(skb); 2080 priv->mib.tx_realloc_tsb_failed++; 2081 BCMGENET_STATS64_INC(stats, dropped); 2082 return NULL; 2083 } 2084 dev_consume_skb_any(skb); 2085 skb = new_skb; 2086 priv->mib.tx_realloc_tsb++; 2087 } 2088 2089 skb_push(skb, sizeof(*status)); 2090 status = (struct status_64 *)skb->data; 2091 2092 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2093 ip_ver = skb->protocol; 2094 switch (ip_ver) { 2095 case htons(ETH_P_IP): 2096 ip_proto = ip_hdr(skb)->protocol; 2097 break; 2098 case htons(ETH_P_IPV6): 2099 ip_proto = ipv6_hdr(skb)->nexthdr; 2100 break; 2101 default: 2102 /* don't use UDP flag */ 2103 ip_proto = 0; 2104 break; 2105 } 2106 2107 offset = skb_checksum_start_offset(skb) - sizeof(*status); 2108 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 2109 (offset + skb->csum_offset) | 2110 STATUS_TX_CSUM_LV; 2111 2112 /* Set the special UDP flag for UDP */ 2113 if (ip_proto == IPPROTO_UDP) 2114 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 2115 2116 status->tx_csum_info = tx_csum_info; 2117 } 2118 2119 return skb; 2120 } 2121 2122 static void bcmgenet_hide_tsb(struct sk_buff *skb) 2123 { 2124 __skb_pull(skb, sizeof(struct status_64)); 2125 } 2126 2127 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 2128 { 2129 struct bcmgenet_priv *priv = netdev_priv(dev); 2130 struct device *kdev = &priv->pdev->dev; 2131 struct bcmgenet_tx_ring *ring = NULL; 2132 struct enet_cb *tx_cb_ptr; 2133 struct netdev_queue *txq; 2134 int nr_frags, index; 2135 dma_addr_t mapping; 2136 unsigned int size; 2137 skb_frag_t *frag; 2138 u32 len_stat; 2139 int ret; 2140 int i; 2141 2142 index = skb_get_queue_mapping(skb); 2143 ring = &priv->tx_rings[index]; 2144 txq = netdev_get_tx_queue(dev, index); 2145 2146 nr_frags = skb_shinfo(skb)->nr_frags; 2147 2148 spin_lock(&ring->lock); 2149 if (ring->free_bds <= (nr_frags + 1)) { 2150 if (!netif_tx_queue_stopped(txq)) 2151 netif_tx_stop_queue(txq); 2152 ret = NETDEV_TX_BUSY; 2153 goto out; 2154 } 2155 2156 /* Retain how many bytes will be sent on the wire, without TSB inserted 2157 * by transmit checksum offload 2158 */ 2159 GENET_CB(skb)->bytes_sent = skb->len; 2160 2161 /* add the Transmit Status Block */ 2162 skb = bcmgenet_add_tsb(dev, skb, ring); 2163 if (!skb) { 2164 ret = NETDEV_TX_OK; 2165 goto out; 2166 } 2167 2168 for (i = 0; i <= nr_frags; i++) { 2169 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 2170 2171 BUG_ON(!tx_cb_ptr); 2172 2173 if (!i) { 2174 /* Transmit single SKB or head of fragment list */ 2175 GENET_CB(skb)->first_cb = tx_cb_ptr; 2176 size = skb_headlen(skb); 2177 mapping = dma_map_single(kdev, skb->data, size, 2178 DMA_TO_DEVICE); 2179 } else { 2180 /* xmit fragment */ 2181 frag = &skb_shinfo(skb)->frags[i - 1]; 2182 size = skb_frag_size(frag); 2183 mapping = skb_frag_dma_map(kdev, frag, 0, size, 2184 DMA_TO_DEVICE); 2185 } 2186 2187 ret = dma_mapping_error(kdev, mapping); 2188 if (ret) { 2189 priv->mib.tx_dma_failed++; 2190 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 2191 ret = NETDEV_TX_OK; 2192 goto out_unmap_frags; 2193 } 2194 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 2195 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 2196 2197 tx_cb_ptr->skb = skb; 2198 2199 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 2200 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 2201 2202 /* Note: if we ever change from DMA_TX_APPEND_CRC below we 2203 * will need to restore software padding of "runt" packets 2204 */ 2205 len_stat |= DMA_TX_APPEND_CRC; 2206 2207 if (!i) { 2208 len_stat |= DMA_SOP; 2209 if (skb->ip_summed == CHECKSUM_PARTIAL) 2210 len_stat |= DMA_TX_DO_CSUM; 2211 } 2212 if (i == nr_frags) 2213 len_stat |= DMA_EOP; 2214 2215 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 2216 } 2217 2218 GENET_CB(skb)->last_cb = tx_cb_ptr; 2219 2220 bcmgenet_hide_tsb(skb); 2221 skb_tx_timestamp(skb); 2222 2223 /* Decrement total BD count and advance our write pointer */ 2224 ring->free_bds -= nr_frags + 1; 2225 ring->prod_index += nr_frags + 1; 2226 ring->prod_index &= DMA_P_INDEX_MASK; 2227 2228 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 2229 2230 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 2231 netif_tx_stop_queue(txq); 2232 2233 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 2234 /* Packets are ready, update producer index */ 2235 bcmgenet_tdma_ring_writel(priv, ring->index, 2236 ring->prod_index, TDMA_PROD_INDEX); 2237 out: 2238 spin_unlock(&ring->lock); 2239 2240 return ret; 2241 2242 out_unmap_frags: 2243 /* Back up for failed control block mapping */ 2244 bcmgenet_put_txcb(priv, ring); 2245 2246 /* Unmap successfully mapped control blocks */ 2247 while (i-- > 0) { 2248 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 2249 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 2250 } 2251 2252 dev_kfree_skb(skb); 2253 goto out; 2254 } 2255 2256 static int bcmgenet_rx_refill(struct bcmgenet_rx_ring *ring, 2257 struct enet_cb *cb) 2258 { 2259 struct bcmgenet_priv *priv = ring->priv; 2260 unsigned int size = GENET_RX_BUF_SIZE; 2261 unsigned int offset; 2262 dma_addr_t mapping; 2263 struct page *page; 2264 2265 page = page_pool_dev_alloc(ring->page_pool, &offset, &size); 2266 if (!page) { 2267 priv->mib.alloc_rx_buff_failed++; 2268 netif_err(priv, rx_err, priv->dev, 2269 "%s: Rx page allocation failed\n", __func__); 2270 return -ENOMEM; 2271 } 2272 2273 /* page_pool handles DMA mapping via PP_FLAG_DMA_MAP */ 2274 mapping = page_pool_get_dma_addr(page) + offset; 2275 dma_sync_single_for_device(&priv->pdev->dev, mapping, RX_BUF_LENGTH, 2276 DMA_FROM_DEVICE); 2277 2278 cb->rx_page = page; 2279 cb->rx_offset = offset; 2280 cb->rx_size = size; 2281 dmadesc_set_addr(priv, cb->bd_addr, mapping); 2282 2283 return 0; 2284 } 2285 2286 /* bcmgenet_desc_rx - descriptor based rx process. 2287 * this could be called from bottom half, or from NAPI polling method. 2288 */ 2289 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 2290 unsigned int budget) 2291 { 2292 struct bcmgenet_rx_stats64 *stats = &ring->stats64; 2293 struct bcmgenet_priv *priv = ring->priv; 2294 struct net_device *dev = priv->dev; 2295 struct enet_cb *cb; 2296 struct sk_buff *skb; 2297 u32 dma_length_status; 2298 unsigned long dma_flag; 2299 int len; 2300 unsigned int rxpktprocessed = 0, rxpkttoprocess; 2301 unsigned int bytes_processed = 0; 2302 unsigned int p_index, mask; 2303 unsigned int discards; 2304 2305 /* Clear status before servicing to reduce spurious interrupts */ 2306 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 2307 bcmgenet_intrl2_1_writel(priv, mask, INTRL2_CPU_CLEAR); 2308 2309 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 2310 2311 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 2312 DMA_P_INDEX_DISCARD_CNT_MASK; 2313 if (discards > ring->old_discards) { 2314 discards = discards - ring->old_discards; 2315 BCMGENET_STATS64_ADD(stats, missed, discards); 2316 ring->old_discards += discards; 2317 2318 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 2319 if (ring->old_discards >= 0xC000) { 2320 ring->old_discards = 0; 2321 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 2322 RDMA_PROD_INDEX); 2323 } 2324 } 2325 2326 p_index &= DMA_P_INDEX_MASK; 2327 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 2328 2329 netif_dbg(priv, rx_status, dev, 2330 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 2331 2332 while ((rxpktprocessed < rxpkttoprocess) && 2333 (rxpktprocessed < budget)) { 2334 unsigned int rx_offset, rx_size; 2335 struct status_64 *status; 2336 struct page *rx_page; 2337 void *hard_start; 2338 __be16 rx_csum; 2339 2340 cb = &priv->rx_cbs[ring->read_ptr]; 2341 2342 /* Save the received page before refilling */ 2343 rx_page = cb->rx_page; 2344 rx_offset = cb->rx_offset; 2345 rx_size = cb->rx_size; 2346 2347 if (bcmgenet_rx_refill(ring, cb)) { 2348 BCMGENET_STATS64_INC(stats, dropped); 2349 goto next; 2350 } 2351 2352 /* Sync the full buffer; the HW may have written anywhere 2353 * up to RX_BUF_LENGTH. 2354 */ 2355 page_pool_dma_sync_for_cpu(ring->page_pool, rx_page, rx_offset, 2356 RX_BUF_LENGTH); 2357 2358 hard_start = page_address(rx_page) + rx_offset; 2359 status = (struct status_64 *)hard_start; 2360 dma_length_status = status->length_status; 2361 2362 /* DMA flags and length are still valid no matter how 2363 * we got the Receive Status Vector (64B RSB or register) 2364 */ 2365 dma_flag = dma_length_status & 0xffff; 2366 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 2367 2368 netif_dbg(priv, rx_status, dev, 2369 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 2370 __func__, p_index, ring->c_index, 2371 ring->read_ptr, dma_length_status); 2372 2373 /* Reject lengths that would underflow the SKB build path. */ 2374 if (unlikely(len > RX_BUF_LENGTH || len < GENET_RSB_PAD)) { 2375 netif_err(priv, rx_status, dev, 2376 "invalid packet length %d\n", len); 2377 BCMGENET_STATS64_INC(stats, length_errors); 2378 page_pool_put_full_page(ring->page_pool, rx_page, 2379 true); 2380 goto next; 2381 } 2382 2383 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 2384 netif_err(priv, rx_status, dev, 2385 "dropping fragmented packet!\n"); 2386 BCMGENET_STATS64_INC(stats, fragmented_errors); 2387 page_pool_put_full_page(ring->page_pool, rx_page, 2388 true); 2389 goto next; 2390 } 2391 2392 /* report errors */ 2393 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 2394 DMA_RX_OV | 2395 DMA_RX_NO | 2396 DMA_RX_LG | 2397 DMA_RX_RXER))) { 2398 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 2399 (unsigned int)dma_flag); 2400 u64_stats_update_begin(&stats->syncp); 2401 if (dma_flag & DMA_RX_CRC_ERROR) 2402 u64_stats_inc(&stats->crc_errors); 2403 if (dma_flag & DMA_RX_OV) 2404 u64_stats_inc(&stats->over_errors); 2405 if (dma_flag & DMA_RX_NO) 2406 u64_stats_inc(&stats->frame_errors); 2407 if (dma_flag & DMA_RX_LG) 2408 u64_stats_inc(&stats->length_errors); 2409 if ((dma_flag & (DMA_RX_CRC_ERROR | 2410 DMA_RX_OV | 2411 DMA_RX_NO | 2412 DMA_RX_LG | 2413 DMA_RX_RXER)) == DMA_RX_RXER) 2414 u64_stats_inc(&stats->errors); 2415 u64_stats_update_end(&stats->syncp); 2416 page_pool_put_full_page(ring->page_pool, rx_page, 2417 true); 2418 goto next; 2419 } /* error packet */ 2420 2421 /* Build SKB from the page - data starts at hard_start, 2422 * frame begins after RSB(64) + pad(2) = 66 bytes. 2423 */ 2424 skb = napi_build_skb(hard_start, rx_size); 2425 if (unlikely(!skb)) { 2426 BCMGENET_STATS64_INC(stats, dropped); 2427 page_pool_put_full_page(ring->page_pool, rx_page, 2428 true); 2429 goto next; 2430 } 2431 2432 skb_mark_for_recycle(skb); 2433 2434 /* Reserve the RSB + pad, then set the data length */ 2435 skb_reserve(skb, GENET_RSB_PAD); 2436 __skb_put(skb, len - GENET_RSB_PAD); 2437 2438 if (priv->crc_fwd_en) { 2439 skb_trim(skb, skb->len - ETH_FCS_LEN); 2440 } 2441 2442 /* Set up checksum offload */ 2443 if (dev->features & NETIF_F_RXCSUM) { 2444 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 2445 if (rx_csum) { 2446 skb->csum = (__force __wsum)ntohs(rx_csum); 2447 skb->ip_summed = CHECKSUM_COMPLETE; 2448 } 2449 } 2450 2451 len = skb->len; 2452 bytes_processed += len; 2453 2454 /*Finish setting up the received SKB and send it to the kernel*/ 2455 skb->protocol = eth_type_trans(skb, priv->dev); 2456 2457 u64_stats_update_begin(&stats->syncp); 2458 u64_stats_inc(&stats->packets); 2459 u64_stats_add(&stats->bytes, len); 2460 if (dma_flag & DMA_RX_MULT) 2461 u64_stats_inc(&stats->multicast); 2462 else if (dma_flag & DMA_RX_BRDCAST) 2463 u64_stats_inc(&stats->broadcast); 2464 u64_stats_update_end(&stats->syncp); 2465 2466 /* Notify kernel */ 2467 napi_gro_receive(&ring->napi, skb); 2468 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 2469 2470 next: 2471 rxpktprocessed++; 2472 if (likely(ring->read_ptr < ring->end_ptr)) 2473 ring->read_ptr++; 2474 else 2475 ring->read_ptr = ring->cb_ptr; 2476 2477 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 2478 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 2479 } 2480 2481 ring->dim.bytes = bytes_processed; 2482 ring->dim.packets = rxpktprocessed; 2483 2484 return rxpktprocessed; 2485 } 2486 2487 /* Rx NAPI polling method */ 2488 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 2489 { 2490 struct bcmgenet_rx_ring *ring = container_of(napi, 2491 struct bcmgenet_rx_ring, napi); 2492 struct dim_sample dim_sample = {}; 2493 unsigned int work_done; 2494 2495 work_done = bcmgenet_desc_rx(ring, budget); 2496 2497 if (work_done < budget && napi_complete_done(napi, work_done)) 2498 bcmgenet_rx_ring_int_enable(ring); 2499 2500 if (ring->dim.use_dim) { 2501 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 2502 ring->dim.bytes, &dim_sample); 2503 net_dim(&ring->dim.dim, &dim_sample); 2504 } 2505 2506 return work_done; 2507 } 2508 2509 static void bcmgenet_dim_work(struct work_struct *work) 2510 { 2511 struct dim *dim = container_of(work, struct dim, work); 2512 struct bcmgenet_net_dim *ndim = 2513 container_of(dim, struct bcmgenet_net_dim, dim); 2514 struct bcmgenet_rx_ring *ring = 2515 container_of(ndim, struct bcmgenet_rx_ring, dim); 2516 struct dim_cq_moder cur_profile = 2517 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 2518 2519 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 2520 dim->state = DIM_START_MEASURE; 2521 } 2522 2523 /* Assign page_pool pages to RX DMA descriptors. */ 2524 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 2525 struct bcmgenet_rx_ring *ring) 2526 { 2527 struct enet_cb *cb; 2528 int i; 2529 2530 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2531 2532 /* loop here for each buffer needing assign */ 2533 for (i = 0; i < ring->size; i++) { 2534 cb = ring->cbs + i; 2535 if (bcmgenet_rx_refill(ring, cb)) 2536 return -ENOMEM; 2537 } 2538 2539 return 0; 2540 } 2541 2542 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 2543 { 2544 struct bcmgenet_rx_ring *ring; 2545 struct enet_cb *cb; 2546 int q, i; 2547 2548 for (q = 0; q <= priv->hw_params->rx_queues; q++) { 2549 ring = &priv->rx_rings[q]; 2550 if (!ring->page_pool) 2551 continue; 2552 for (i = 0; i < ring->size; i++) { 2553 cb = ring->cbs + i; 2554 bcmgenet_free_rx_cb(cb, ring->page_pool); 2555 } 2556 } 2557 } 2558 2559 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 2560 { 2561 u32 reg; 2562 2563 spin_lock_bh(&priv->reg_lock); 2564 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2565 if (reg & CMD_SW_RESET) { 2566 spin_unlock_bh(&priv->reg_lock); 2567 return; 2568 } 2569 if (enable) 2570 reg |= mask; 2571 else 2572 reg &= ~mask; 2573 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2574 spin_unlock_bh(&priv->reg_lock); 2575 2576 /* UniMAC stops on a packet boundary, wait for a full-size packet 2577 * to be processed 2578 */ 2579 if (enable == 0) 2580 usleep_range(1000, 2000); 2581 } 2582 2583 static void reset_umac(struct bcmgenet_priv *priv) 2584 { 2585 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 2586 bcmgenet_rbuf_ctrl_set(priv, 0); 2587 udelay(10); 2588 2589 /* issue soft reset and disable MAC while updating its registers */ 2590 spin_lock_bh(&priv->reg_lock); 2591 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 2592 udelay(2); 2593 spin_unlock_bh(&priv->reg_lock); 2594 } 2595 2596 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2597 { 2598 /* Mask all interrupts.*/ 2599 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2600 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2601 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2602 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2603 } 2604 2605 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2606 { 2607 u32 int0_enable = 0; 2608 2609 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2610 * and MoCA PHY 2611 */ 2612 if (priv->internal_phy) { 2613 int0_enable |= UMAC_IRQ_LINK_EVENT; 2614 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2615 int0_enable |= UMAC_IRQ_PHY_DET_R; 2616 } else if (priv->ext_phy) { 2617 int0_enable |= UMAC_IRQ_LINK_EVENT; 2618 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2619 if (bcmgenet_has_moca_link_det(priv)) 2620 int0_enable |= UMAC_IRQ_LINK_EVENT; 2621 } 2622 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2623 } 2624 2625 static void init_umac(struct bcmgenet_priv *priv) 2626 { 2627 struct device *kdev = &priv->pdev->dev; 2628 u32 reg; 2629 u32 int0_enable = 0; 2630 2631 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2632 2633 reset_umac(priv); 2634 2635 /* clear tx/rx counter */ 2636 bcmgenet_umac_writel(priv, 2637 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2638 UMAC_MIB_CTRL); 2639 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2640 2641 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2642 2643 /* init tx registers, enable TSB */ 2644 reg = bcmgenet_tbuf_ctrl_get(priv); 2645 reg |= TBUF_64B_EN; 2646 bcmgenet_tbuf_ctrl_set(priv, reg); 2647 2648 /* init rx registers, enable ip header optimization and RSB */ 2649 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2650 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 2651 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2652 2653 /* enable rx checksumming */ 2654 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 2655 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 2656 /* If UniMAC forwards CRC, we need to skip over it to get 2657 * a valid CHK bit to be set in the per-packet status word 2658 */ 2659 if (priv->crc_fwd_en) 2660 reg |= RBUF_SKIP_FCS; 2661 else 2662 reg &= ~RBUF_SKIP_FCS; 2663 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 2664 2665 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2666 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2667 2668 bcmgenet_intr_disable(priv); 2669 2670 /* Configure backpressure vectors for MoCA */ 2671 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2672 reg = bcmgenet_bp_mc_get(priv); 2673 reg |= BIT(priv->hw_params->bp_in_en_shift); 2674 2675 /* bp_mask: back pressure mask */ 2676 if (netif_is_multiqueue(priv->dev)) 2677 reg |= priv->hw_params->bp_in_mask; 2678 else 2679 reg &= ~priv->hw_params->bp_in_mask; 2680 bcmgenet_bp_mc_set(priv, reg); 2681 } 2682 2683 /* Enable MDIO interrupts on GENET v3+ */ 2684 if (bcmgenet_has_mdio_intr(priv)) 2685 int0_enable |= UMAC_IRQ_MDIO_EVENT; 2686 2687 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2688 2689 dev_dbg(kdev, "done init umac\n"); 2690 } 2691 2692 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2693 void (*cb)(struct work_struct *work)) 2694 { 2695 struct bcmgenet_net_dim *dim = &ring->dim; 2696 2697 INIT_WORK(&dim->dim.work, cb); 2698 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2699 dim->event_ctr = 0; 2700 dim->packets = 0; 2701 dim->bytes = 0; 2702 } 2703 2704 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2705 { 2706 struct bcmgenet_net_dim *dim = &ring->dim; 2707 struct dim_cq_moder moder; 2708 u32 usecs, pkts; 2709 2710 usecs = ring->rx_coalesce_usecs; 2711 pkts = ring->rx_max_coalesced_frames; 2712 2713 /* If DIM was enabled, re-apply default parameters */ 2714 if (dim->use_dim) { 2715 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2716 usecs = moder.usec; 2717 pkts = moder.pkts; 2718 } 2719 2720 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2721 } 2722 2723 /* Initialize a Tx ring along with corresponding hardware registers */ 2724 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2725 unsigned int index, unsigned int size, 2726 unsigned int start_ptr, unsigned int end_ptr) 2727 { 2728 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2729 u32 words_per_bd = WORDS_PER_BD(priv); 2730 u32 flow_period_val = 0; 2731 2732 spin_lock_init(&ring->lock); 2733 ring->priv = priv; 2734 ring->index = index; 2735 ring->cbs = priv->tx_cbs + start_ptr; 2736 ring->size = size; 2737 ring->clean_ptr = start_ptr; 2738 ring->c_index = 0; 2739 ring->free_bds = size; 2740 ring->write_ptr = start_ptr; 2741 ring->cb_ptr = start_ptr; 2742 ring->end_ptr = end_ptr - 1; 2743 ring->prod_index = 0; 2744 2745 /* Set flow period for ring != 0 */ 2746 if (index) 2747 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2748 2749 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2750 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2751 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2752 /* Disable rate control for now */ 2753 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2754 TDMA_FLOW_PERIOD); 2755 bcmgenet_tdma_ring_writel(priv, index, 2756 ((size << DMA_RING_SIZE_SHIFT) | 2757 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2758 2759 /* Set start and end address, read and write pointers */ 2760 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2761 DMA_START_ADDR); 2762 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2763 TDMA_READ_PTR); 2764 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2765 TDMA_WRITE_PTR); 2766 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2767 DMA_END_ADDR); 2768 2769 /* Initialize Tx NAPI */ 2770 netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll); 2771 } 2772 2773 static int bcmgenet_rx_ring_create_pool(struct bcmgenet_priv *priv, 2774 struct bcmgenet_rx_ring *ring) 2775 { 2776 /* Buffers share a page. bcmgenet_rx_refill() syncs each one for the 2777 * device, PP_FLAG_DMA_SYNC_DEV would sync the whole page. 2778 */ 2779 struct page_pool_params pp_params = { 2780 .order = 0, 2781 .flags = PP_FLAG_DMA_MAP, 2782 .pool_size = ring->size, 2783 .nid = NUMA_NO_NODE, 2784 .dev = &priv->pdev->dev, 2785 .dma_dir = DMA_FROM_DEVICE, 2786 }; 2787 int err; 2788 2789 ring->page_pool = page_pool_create(&pp_params); 2790 if (IS_ERR(ring->page_pool)) { 2791 err = PTR_ERR(ring->page_pool); 2792 ring->page_pool = NULL; 2793 return err; 2794 } 2795 2796 return 0; 2797 } 2798 2799 /* Initialize a RDMA ring */ 2800 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2801 unsigned int index, unsigned int size, 2802 unsigned int start_ptr, unsigned int end_ptr) 2803 { 2804 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2805 u32 words_per_bd = WORDS_PER_BD(priv); 2806 int ret, i; 2807 2808 ring->priv = priv; 2809 ring->index = index; 2810 ring->cbs = priv->rx_cbs + start_ptr; 2811 ring->size = size; 2812 ring->c_index = 0; 2813 ring->read_ptr = start_ptr; 2814 ring->cb_ptr = start_ptr; 2815 ring->end_ptr = end_ptr - 1; 2816 2817 ret = bcmgenet_rx_ring_create_pool(priv, ring); 2818 if (ret) 2819 return ret; 2820 2821 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2822 if (ret) { 2823 for (i = 0; i < ring->size; i++) 2824 bcmgenet_free_rx_cb(ring->cbs + i, ring->page_pool); 2825 page_pool_destroy(ring->page_pool); 2826 ring->page_pool = NULL; 2827 return ret; 2828 } 2829 2830 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2831 bcmgenet_init_rx_coalesce(ring); 2832 2833 /* Initialize Rx NAPI */ 2834 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll); 2835 2836 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2837 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2838 bcmgenet_rdma_ring_writel(priv, index, 2839 ((size << DMA_RING_SIZE_SHIFT) | 2840 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2841 bcmgenet_rdma_ring_writel(priv, index, 2842 (DMA_FC_THRESH_LO << 2843 DMA_XOFF_THRESHOLD_SHIFT) | 2844 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2845 2846 /* Set start and end address, read and write pointers */ 2847 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2848 DMA_START_ADDR); 2849 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2850 RDMA_READ_PTR); 2851 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2852 RDMA_WRITE_PTR); 2853 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2854 DMA_END_ADDR); 2855 2856 return ret; 2857 } 2858 2859 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2860 { 2861 unsigned int i; 2862 struct bcmgenet_tx_ring *ring; 2863 2864 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2865 ring = &priv->tx_rings[i]; 2866 napi_enable(&ring->napi); 2867 bcmgenet_tx_ring_int_enable(ring); 2868 } 2869 } 2870 2871 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2872 { 2873 unsigned int i; 2874 struct bcmgenet_tx_ring *ring; 2875 2876 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2877 ring = &priv->tx_rings[i]; 2878 napi_disable(&ring->napi); 2879 } 2880 } 2881 2882 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2883 { 2884 unsigned int i; 2885 struct bcmgenet_tx_ring *ring; 2886 2887 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2888 ring = &priv->tx_rings[i]; 2889 netif_napi_del(&ring->napi); 2890 } 2891 } 2892 2893 static int bcmgenet_tdma_disable(struct bcmgenet_priv *priv) 2894 { 2895 int timeout = 0; 2896 u32 reg, mask; 2897 2898 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2899 mask = (1 << (priv->hw_params->tx_queues + 1)) - 1; 2900 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2901 reg &= ~mask; 2902 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2903 2904 /* Check DMA status register to confirm DMA is disabled */ 2905 while (timeout++ < DMA_TIMEOUT_VAL) { 2906 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2907 if ((reg & mask) == mask) 2908 return 0; 2909 2910 udelay(1); 2911 } 2912 2913 return -ETIMEDOUT; 2914 } 2915 2916 static int bcmgenet_rdma_disable(struct bcmgenet_priv *priv) 2917 { 2918 int timeout = 0; 2919 u32 reg, mask; 2920 2921 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2922 mask = (1 << (priv->hw_params->rx_queues + 1)) - 1; 2923 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2924 reg &= ~mask; 2925 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2926 2927 /* Check DMA status register to confirm DMA is disabled */ 2928 while (timeout++ < DMA_TIMEOUT_VAL) { 2929 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2930 if ((reg & mask) == mask) 2931 return 0; 2932 2933 udelay(1); 2934 } 2935 2936 return -ETIMEDOUT; 2937 } 2938 2939 /* Initialize Tx queues 2940 * 2941 * Queues 1-4 are the priority queues, each one has 32 descriptors. 2942 * The weighted round-robin arbiter gives them a larger share of TX 2943 * bandwidth than the default queue 0. 2944 * 2945 * Queue 0 is the default Tx queue with 2946 * GENET_Q0_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2947 * 2948 * The transmit control block pool is then partitioned as follows: 2949 * - Tx queue 0 uses tx_cbs[0..127] 2950 * - Tx queue 1 uses tx_cbs[128..159] 2951 * - Tx queue 2 uses tx_cbs[160..191] 2952 * - Tx queue 3 uses tx_cbs[192..223] 2953 * - Tx queue 4 uses tx_cbs[224..255] 2954 */ 2955 static void bcmgenet_init_tx_queues(struct net_device *dev) 2956 { 2957 struct bcmgenet_priv *priv = netdev_priv(dev); 2958 unsigned int start = 0, end = GENET_Q0_TX_BD_CNT; 2959 u32 i, ring_mask, dma_priority[3] = {0, 0, 0}; 2960 2961 /* Enable Weighted Round-Robin arbiter mode */ 2962 bcmgenet_tdma_writel(priv, DMA_ARBITER_WRR, DMA_ARB_CTRL); 2963 2964 /* Initialize Tx priority queues */ 2965 for (i = 0; i <= priv->hw_params->tx_queues; i++) { 2966 bcmgenet_init_tx_ring(priv, i, end - start, start, end); 2967 start = end; 2968 end += priv->hw_params->tx_bds_per_q; 2969 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2970 (i ? GENET_Q1_WEIGHT : GENET_Q0_WEIGHT) 2971 << DMA_PRIO_REG_SHIFT(i); 2972 } 2973 2974 /* Set Tx queue priorities */ 2975 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2976 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2977 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2978 2979 /* Configure Tx queues as descriptor rings */ 2980 ring_mask = (1 << (priv->hw_params->tx_queues + 1)) - 1; 2981 bcmgenet_tdma_writel(priv, ring_mask, DMA_RING_CFG); 2982 2983 /* Enable Tx rings */ 2984 ring_mask <<= DMA_RING_BUF_EN_SHIFT; 2985 bcmgenet_tdma_writel(priv, ring_mask, DMA_CTRL); 2986 } 2987 2988 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2989 { 2990 unsigned int i; 2991 struct bcmgenet_rx_ring *ring; 2992 2993 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2994 ring = &priv->rx_rings[i]; 2995 napi_enable(&ring->napi); 2996 bcmgenet_rx_ring_int_enable(ring); 2997 } 2998 } 2999 3000 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 3001 { 3002 unsigned int i; 3003 struct bcmgenet_rx_ring *ring; 3004 3005 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 3006 ring = &priv->rx_rings[i]; 3007 napi_disable(&ring->napi); 3008 cancel_work_sync(&ring->dim.dim.work); 3009 } 3010 } 3011 3012 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 3013 { 3014 unsigned int i; 3015 struct bcmgenet_rx_ring *ring; 3016 3017 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 3018 ring = &priv->rx_rings[i]; 3019 netif_napi_del(&ring->napi); 3020 } 3021 } 3022 3023 static void bcmgenet_destroy_rx_page_pools(struct bcmgenet_priv *priv) 3024 { 3025 struct bcmgenet_rx_ring *ring; 3026 unsigned int i; 3027 3028 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 3029 ring = &priv->rx_rings[i]; 3030 if (ring->page_pool) { 3031 page_pool_destroy(ring->page_pool); 3032 ring->page_pool = NULL; 3033 } 3034 } 3035 } 3036 3037 /* Initialize Rx queues 3038 * 3039 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 3040 * used to direct traffic to these queues. 3041 * 3042 * Queue 0 is also the default Rx queue with GENET_Q0_RX_BD_CNT descriptors. 3043 */ 3044 static int bcmgenet_init_rx_queues(struct net_device *dev) 3045 { 3046 struct bcmgenet_priv *priv = netdev_priv(dev); 3047 unsigned int start = 0, end = GENET_Q0_RX_BD_CNT; 3048 u32 i, ring_mask; 3049 int ret; 3050 3051 /* Initialize Rx priority queues */ 3052 for (i = 0; i <= priv->hw_params->rx_queues; i++) { 3053 ret = bcmgenet_init_rx_ring(priv, i, end - start, start, end); 3054 if (ret) 3055 return ret; 3056 3057 start = end; 3058 end += priv->hw_params->rx_bds_per_q; 3059 } 3060 3061 /* Configure Rx queues as descriptor rings */ 3062 ring_mask = (1 << (priv->hw_params->rx_queues + 1)) - 1; 3063 bcmgenet_rdma_writel(priv, ring_mask, DMA_RING_CFG); 3064 3065 /* Enable Rx rings */ 3066 ring_mask <<= DMA_RING_BUF_EN_SHIFT; 3067 bcmgenet_rdma_writel(priv, ring_mask, DMA_CTRL); 3068 3069 return 0; 3070 } 3071 3072 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 3073 { 3074 int ret = 0; 3075 3076 /* Disable TDMA to stop add more frames in TX DMA */ 3077 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) { 3078 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 3079 ret = -ETIMEDOUT; 3080 } 3081 3082 /* Wait 10ms for packet drain in both tx and rx dma */ 3083 usleep_range(10000, 20000); 3084 3085 /* Disable RDMA */ 3086 if (-ETIMEDOUT == bcmgenet_rdma_disable(priv)) { 3087 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 3088 ret = -ETIMEDOUT; 3089 } 3090 3091 return ret; 3092 } 3093 3094 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 3095 { 3096 struct netdev_queue *txq; 3097 int i; 3098 3099 bcmgenet_fini_rx_napi(priv); 3100 bcmgenet_fini_tx_napi(priv); 3101 3102 for (i = 0; i <= priv->hw_params->tx_queues; i++) { 3103 txq = netdev_get_tx_queue(priv->dev, i); 3104 netdev_tx_reset_queue(txq); 3105 } 3106 3107 bcmgenet_free_rx_buffers(priv); 3108 bcmgenet_destroy_rx_page_pools(priv); 3109 kfree(priv->rx_cbs); 3110 kfree(priv->tx_cbs); 3111 } 3112 3113 /* init_edma: Initialize DMA control register */ 3114 static int bcmgenet_init_dma(struct bcmgenet_priv *priv, bool flush_rx) 3115 { 3116 struct enet_cb *cb; 3117 unsigned int i; 3118 int ret; 3119 u32 reg; 3120 3121 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 3122 3123 /* Disable TX DMA */ 3124 ret = bcmgenet_tdma_disable(priv); 3125 if (ret) { 3126 netdev_err(priv->dev, "failed to halt Tx DMA\n"); 3127 return ret; 3128 } 3129 3130 /* Disable RX DMA */ 3131 ret = bcmgenet_rdma_disable(priv); 3132 if (ret) { 3133 netdev_err(priv->dev, "failed to halt Rx DMA\n"); 3134 return ret; 3135 } 3136 3137 /* Flush TX queues */ 3138 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 3139 udelay(10); 3140 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 3141 3142 if (flush_rx) { 3143 reg = bcmgenet_rbuf_ctrl_get(priv); 3144 bcmgenet_rbuf_ctrl_set(priv, reg | BIT(0)); 3145 udelay(10); 3146 bcmgenet_rbuf_ctrl_set(priv, reg); 3147 udelay(10); 3148 } 3149 3150 /* Initialize common Rx ring structures */ 3151 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 3152 priv->num_rx_bds = TOTAL_DESC; 3153 priv->rx_cbs = kzalloc_objs(struct enet_cb, priv->num_rx_bds); 3154 if (!priv->rx_cbs) 3155 return -ENOMEM; 3156 3157 for (i = 0; i < priv->num_rx_bds; i++) { 3158 cb = priv->rx_cbs + i; 3159 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 3160 } 3161 3162 /* Initialize common TX ring structures */ 3163 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 3164 priv->num_tx_bds = TOTAL_DESC; 3165 priv->tx_cbs = kzalloc_objs(struct enet_cb, priv->num_tx_bds); 3166 if (!priv->tx_cbs) { 3167 kfree(priv->rx_cbs); 3168 return -ENOMEM; 3169 } 3170 3171 for (i = 0; i < priv->num_tx_bds; i++) { 3172 cb = priv->tx_cbs + i; 3173 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 3174 } 3175 3176 /* Init rDma */ 3177 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 3178 DMA_SCB_BURST_SIZE); 3179 3180 /* Initialize Rx queues */ 3181 ret = bcmgenet_init_rx_queues(priv->dev); 3182 if (ret) { 3183 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 3184 bcmgenet_free_rx_buffers(priv); 3185 bcmgenet_destroy_rx_page_pools(priv); 3186 kfree(priv->rx_cbs); 3187 kfree(priv->tx_cbs); 3188 return ret; 3189 } 3190 3191 /* Init tDma */ 3192 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 3193 DMA_SCB_BURST_SIZE); 3194 3195 /* Initialize Tx queues */ 3196 bcmgenet_init_tx_queues(priv->dev); 3197 3198 /* Enable RX/TX DMA */ 3199 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3200 reg |= DMA_EN; 3201 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3202 3203 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3204 reg |= DMA_EN; 3205 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3206 3207 return 0; 3208 } 3209 3210 /* Interrupt bottom half */ 3211 static void bcmgenet_irq_task(struct work_struct *work) 3212 { 3213 unsigned int status; 3214 struct bcmgenet_priv *priv = container_of( 3215 work, struct bcmgenet_priv, bcmgenet_irq_work); 3216 3217 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 3218 3219 spin_lock_irq(&priv->lock); 3220 status = priv->irq0_stat; 3221 priv->irq0_stat = 0; 3222 spin_unlock_irq(&priv->lock); 3223 3224 if (status & UMAC_IRQ_PHY_DET_R && 3225 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 3226 phy_init_hw(priv->dev->phydev); 3227 genphy_config_aneg(priv->dev->phydev); 3228 } 3229 3230 /* Link UP/DOWN event */ 3231 if (status & UMAC_IRQ_LINK_EVENT) 3232 phy_mac_interrupt(priv->dev->phydev); 3233 3234 } 3235 3236 /* bcmgenet_isr1: handle Rx and Tx queues */ 3237 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 3238 { 3239 struct bcmgenet_priv *priv = dev_id; 3240 struct bcmgenet_rx_ring *rx_ring; 3241 struct bcmgenet_tx_ring *tx_ring; 3242 unsigned int index, status; 3243 3244 /* Read irq status */ 3245 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 3246 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3247 3248 /* clear interrupts */ 3249 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 3250 3251 netif_dbg(priv, intr, priv->dev, 3252 "%s: IRQ=0x%x\n", __func__, status); 3253 3254 /* Check Rx priority queue interrupts */ 3255 for (index = 0; index <= priv->hw_params->rx_queues; index++) { 3256 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 3257 continue; 3258 3259 rx_ring = &priv->rx_rings[index]; 3260 rx_ring->dim.event_ctr++; 3261 3262 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3263 bcmgenet_rx_ring_int_disable(rx_ring); 3264 __napi_schedule_irqoff(&rx_ring->napi); 3265 } 3266 } 3267 3268 /* Check Tx priority queue interrupts */ 3269 for (index = 0; index <= priv->hw_params->tx_queues; index++) { 3270 if (!(status & BIT(index))) 3271 continue; 3272 3273 tx_ring = &priv->tx_rings[index]; 3274 3275 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3276 bcmgenet_tx_ring_int_disable(tx_ring); 3277 __napi_schedule_irqoff(&tx_ring->napi); 3278 } 3279 } 3280 3281 return IRQ_HANDLED; 3282 } 3283 3284 /* bcmgenet_isr0: handle other stuff */ 3285 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 3286 { 3287 struct bcmgenet_priv *priv = dev_id; 3288 unsigned int status; 3289 unsigned long flags; 3290 3291 /* Read irq status */ 3292 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 3293 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3294 3295 /* clear interrupts */ 3296 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 3297 3298 netif_dbg(priv, intr, priv->dev, 3299 "IRQ=0x%x\n", status); 3300 3301 if (bcmgenet_has_mdio_intr(priv) && status & UMAC_IRQ_MDIO_EVENT) 3302 wake_up(&priv->wq); 3303 3304 /* all other interested interrupts handled in bottom half */ 3305 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 3306 if (status) { 3307 /* Save irq status for bottom-half processing. */ 3308 spin_lock_irqsave(&priv->lock, flags); 3309 priv->irq0_stat |= status; 3310 spin_unlock_irqrestore(&priv->lock, flags); 3311 3312 schedule_work(&priv->bcmgenet_irq_work); 3313 } 3314 3315 return IRQ_HANDLED; 3316 } 3317 3318 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 3319 { 3320 /* Acknowledge the interrupt */ 3321 return IRQ_HANDLED; 3322 } 3323 3324 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 3325 { 3326 u32 reg; 3327 3328 reg = bcmgenet_rbuf_ctrl_get(priv); 3329 reg |= BIT(1); 3330 bcmgenet_rbuf_ctrl_set(priv, reg); 3331 udelay(10); 3332 3333 reg &= ~BIT(1); 3334 bcmgenet_rbuf_ctrl_set(priv, reg); 3335 udelay(10); 3336 } 3337 3338 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 3339 const unsigned char *addr) 3340 { 3341 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0); 3342 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1); 3343 } 3344 3345 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 3346 unsigned char *addr) 3347 { 3348 u32 addr_tmp; 3349 3350 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 3351 put_unaligned_be32(addr_tmp, &addr[0]); 3352 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 3353 put_unaligned_be16(addr_tmp, &addr[4]); 3354 } 3355 3356 static void bcmgenet_netif_start(struct net_device *dev) 3357 { 3358 struct bcmgenet_priv *priv = netdev_priv(dev); 3359 3360 /* Start the network engine */ 3361 netif_addr_lock_bh(dev); 3362 bcmgenet_set_rx_mode(dev); 3363 netif_addr_unlock_bh(dev); 3364 bcmgenet_enable_rx_napi(priv); 3365 3366 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 3367 3368 bcmgenet_enable_tx_napi(priv); 3369 3370 /* Monitor link interrupts now */ 3371 bcmgenet_link_intr_enable(priv); 3372 3373 phy_start(dev->phydev); 3374 } 3375 3376 static int bcmgenet_open(struct net_device *dev) 3377 { 3378 struct bcmgenet_priv *priv = netdev_priv(dev); 3379 int ret; 3380 3381 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 3382 3383 /* Turn on the clock */ 3384 clk_prepare_enable(priv->clk); 3385 3386 /* If this is an internal GPHY, power it back on now, before UniMAC is 3387 * brought out of reset as absolutely no UniMAC activity is allowed 3388 */ 3389 if (priv->internal_phy) 3390 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3391 3392 /* take MAC out of reset */ 3393 bcmgenet_umac_reset(priv); 3394 3395 init_umac(priv); 3396 3397 /* Apply features again in case we changed them while interface was 3398 * down 3399 */ 3400 bcmgenet_set_features(dev, dev->features); 3401 3402 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3403 3404 /* Restore the filters, the MAC was reset above */ 3405 bcmgenet_hfb_restore(priv); 3406 3407 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3408 ret = bcmgenet_init_dma(priv, true); 3409 if (ret) { 3410 netdev_err(dev, "failed to initialize DMA\n"); 3411 goto err_clk_disable; 3412 } 3413 3414 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 3415 dev->name, priv); 3416 if (ret < 0) { 3417 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 3418 goto err_fini_dma; 3419 } 3420 3421 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 3422 dev->name, priv); 3423 if (ret < 0) { 3424 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 3425 goto err_irq0; 3426 } 3427 3428 ret = bcmgenet_mii_probe(dev); 3429 if (ret) { 3430 netdev_err(dev, "failed to connect to PHY\n"); 3431 goto err_irq1; 3432 } 3433 3434 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 3435 3436 bcmgenet_netif_start(dev); 3437 3438 netif_tx_start_all_queues(dev); 3439 3440 return 0; 3441 3442 err_irq1: 3443 free_irq(priv->irq1, priv); 3444 err_irq0: 3445 free_irq(priv->irq0, priv); 3446 err_fini_dma: 3447 bcmgenet_dma_teardown(priv); 3448 bcmgenet_fini_dma(priv); 3449 err_clk_disable: 3450 if (priv->internal_phy) 3451 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3452 clk_disable_unprepare(priv->clk); 3453 return ret; 3454 } 3455 3456 static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy) 3457 { 3458 struct bcmgenet_priv *priv = netdev_priv(dev); 3459 3460 /* Stop completion polling before it can wake a stopped queue */ 3461 bcmgenet_disable_tx_napi(priv); 3462 netif_tx_disable(dev); 3463 3464 /* Disable MAC receive */ 3465 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 3466 umac_enable_set(priv, CMD_RX_EN, false); 3467 3468 if (stop_phy) 3469 phy_stop(dev->phydev); 3470 3471 bcmgenet_dma_teardown(priv); 3472 3473 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3474 umac_enable_set(priv, CMD_TX_EN, false); 3475 3476 bcmgenet_disable_rx_napi(priv); 3477 bcmgenet_intr_disable(priv); 3478 3479 /* Wait for pending work items to complete. Since interrupts are 3480 * disabled no new work will be scheduled. 3481 */ 3482 cancel_work_sync(&priv->bcmgenet_irq_work); 3483 3484 /* tx reclaim */ 3485 bcmgenet_tx_reclaim_all(dev); 3486 bcmgenet_fini_dma(priv); 3487 } 3488 3489 static int bcmgenet_close(struct net_device *dev) 3490 { 3491 struct bcmgenet_priv *priv = netdev_priv(dev); 3492 int ret = 0; 3493 3494 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3495 3496 bcmgenet_netif_stop(dev, false); 3497 3498 /* Really kill the PHY state machine and disconnect from it */ 3499 phy_disconnect(dev->phydev); 3500 3501 free_irq(priv->irq0, priv); 3502 free_irq(priv->irq1, priv); 3503 3504 if (priv->internal_phy) 3505 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3506 3507 clk_disable_unprepare(priv->clk); 3508 3509 return ret; 3510 } 3511 3512 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3513 { 3514 struct bcmgenet_priv *priv = ring->priv; 3515 u32 p_index, c_index, intsts, intmsk; 3516 struct netdev_queue *txq; 3517 unsigned int free_bds; 3518 bool txq_stopped; 3519 3520 if (!netif_msg_tx_err(priv)) 3521 return; 3522 3523 txq = netdev_get_tx_queue(priv->dev, ring->index); 3524 3525 spin_lock(&ring->lock); 3526 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3527 intmsk = 1 << ring->index; 3528 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3529 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3530 txq_stopped = netif_tx_queue_stopped(txq); 3531 free_bds = ring->free_bds; 3532 spin_unlock(&ring->lock); 3533 3534 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3535 "TX queue status: %s, interrupts: %s\n" 3536 "(sw)free_bds: %d (sw)size: %d\n" 3537 "(sw)p_index: %d (hw)p_index: %d\n" 3538 "(sw)c_index: %d (hw)c_index: %d\n" 3539 "(sw)clean_p: %d (sw)write_p: %d\n" 3540 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3541 ring->index, ring->index, 3542 txq_stopped ? "stopped" : "active", 3543 intsts & intmsk ? "enabled" : "disabled", 3544 free_bds, ring->size, 3545 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3546 ring->c_index, c_index & DMA_C_INDEX_MASK, 3547 ring->clean_ptr, ring->write_ptr, 3548 ring->cb_ptr, ring->end_ptr); 3549 } 3550 3551 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3552 { 3553 struct bcmgenet_priv *priv = netdev_priv(dev); 3554 struct bcmgenet_tx_ring *ring = &priv->tx_rings[txqueue]; 3555 struct netdev_queue *txq = netdev_get_tx_queue(dev, txqueue); 3556 3557 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3558 3559 bcmgenet_dump_tx_queue(ring); 3560 3561 bcmgenet_tx_reclaim(dev, ring, true); 3562 3563 /* Re-enable the TX interrupt for this ring */ 3564 bcmgenet_intrl2_1_writel(priv, 1 << txqueue, INTRL2_CPU_MASK_CLEAR); 3565 3566 txq_trans_cond_update(txq); 3567 3568 BCMGENET_STATS64_INC((&ring->stats64), errors); 3569 3570 netif_tx_wake_queue(txq); 3571 } 3572 3573 #define MAX_MDF_FILTER 17 3574 3575 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3576 const unsigned char *addr, 3577 int *i) 3578 { 3579 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3580 UMAC_MDF_ADDR + (*i * 4)); 3581 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3582 addr[4] << 8 | addr[5], 3583 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3584 *i += 2; 3585 } 3586 3587 static void bcmgenet_set_rx_mode(struct net_device *dev) 3588 { 3589 struct bcmgenet_priv *priv = netdev_priv(dev); 3590 struct netdev_hw_addr *ha; 3591 int i, nfilter; 3592 u32 reg; 3593 3594 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3595 3596 /* Number of filters needed */ 3597 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3598 3599 /* 3600 * Turn on promicuous mode for three scenarios 3601 * 1. IFF_PROMISC flag is set 3602 * 2. IFF_ALLMULTI flag is set 3603 * 3. The number of filters needed exceeds the number filters 3604 * supported by the hardware. 3605 */ 3606 spin_lock(&priv->reg_lock); 3607 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3608 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3609 (nfilter > MAX_MDF_FILTER)) { 3610 reg |= CMD_PROMISC; 3611 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3612 spin_unlock(&priv->reg_lock); 3613 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3614 return; 3615 } else { 3616 reg &= ~CMD_PROMISC; 3617 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3618 spin_unlock(&priv->reg_lock); 3619 } 3620 3621 /* update MDF filter */ 3622 i = 0; 3623 /* Broadcast */ 3624 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3625 /* my own address.*/ 3626 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3627 3628 /* Unicast */ 3629 netdev_for_each_uc_addr(ha, dev) 3630 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3631 3632 /* Multicast */ 3633 netdev_for_each_mc_addr(ha, dev) 3634 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3635 3636 /* Enable filters */ 3637 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3638 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3639 } 3640 3641 /* Set the hardware MAC address. */ 3642 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3643 { 3644 struct sockaddr *addr = p; 3645 3646 /* Setting the MAC address at the hardware level is not possible 3647 * without disabling the UniMAC RX/TX enable bits. 3648 */ 3649 if (netif_running(dev)) 3650 return -EBUSY; 3651 3652 if (!is_valid_ether_addr(addr->sa_data)) 3653 return -EADDRNOTAVAIL; 3654 3655 eth_hw_addr_set(dev, addr->sa_data); 3656 3657 return 0; 3658 } 3659 3660 static void bcmgenet_get_stats64(struct net_device *dev, 3661 struct rtnl_link_stats64 *stats) 3662 { 3663 struct bcmgenet_priv *priv = netdev_priv(dev); 3664 struct bcmgenet_tx_stats64 *tx_stats; 3665 struct bcmgenet_rx_stats64 *rx_stats; 3666 u64 rx_length_errors, rx_over_errors; 3667 u64 rx_missed, rx_fragmented_errors; 3668 u64 rx_crc_errors, rx_frame_errors; 3669 u64 tx_errors, tx_dropped; 3670 u64 rx_errors, rx_dropped; 3671 u64 tx_bytes, tx_packets; 3672 u64 rx_bytes, rx_packets; 3673 unsigned int start; 3674 unsigned int q; 3675 u64 multicast; 3676 3677 for (q = 0; q <= priv->hw_params->tx_queues; q++) { 3678 tx_stats = &priv->tx_rings[q].stats64; 3679 do { 3680 start = u64_stats_fetch_begin(&tx_stats->syncp); 3681 tx_bytes = u64_stats_read(&tx_stats->bytes); 3682 tx_packets = u64_stats_read(&tx_stats->packets); 3683 tx_errors = u64_stats_read(&tx_stats->errors); 3684 tx_dropped = u64_stats_read(&tx_stats->dropped); 3685 } while (u64_stats_fetch_retry(&tx_stats->syncp, start)); 3686 3687 stats->tx_bytes += tx_bytes; 3688 stats->tx_packets += tx_packets; 3689 stats->tx_errors += tx_errors; 3690 stats->tx_dropped += tx_dropped; 3691 } 3692 3693 for (q = 0; q <= priv->hw_params->rx_queues; q++) { 3694 rx_stats = &priv->rx_rings[q].stats64; 3695 do { 3696 start = u64_stats_fetch_begin(&rx_stats->syncp); 3697 rx_bytes = u64_stats_read(&rx_stats->bytes); 3698 rx_packets = u64_stats_read(&rx_stats->packets); 3699 rx_errors = u64_stats_read(&rx_stats->errors); 3700 rx_dropped = u64_stats_read(&rx_stats->dropped); 3701 rx_missed = u64_stats_read(&rx_stats->missed); 3702 rx_length_errors = u64_stats_read(&rx_stats->length_errors); 3703 rx_over_errors = u64_stats_read(&rx_stats->over_errors); 3704 rx_crc_errors = u64_stats_read(&rx_stats->crc_errors); 3705 rx_frame_errors = u64_stats_read(&rx_stats->frame_errors); 3706 rx_fragmented_errors = u64_stats_read(&rx_stats->fragmented_errors); 3707 multicast = u64_stats_read(&rx_stats->multicast); 3708 } while (u64_stats_fetch_retry(&rx_stats->syncp, start)); 3709 3710 rx_errors += rx_length_errors; 3711 rx_errors += rx_crc_errors; 3712 rx_errors += rx_frame_errors; 3713 rx_errors += rx_fragmented_errors; 3714 3715 stats->rx_bytes += rx_bytes; 3716 stats->rx_packets += rx_packets; 3717 stats->rx_errors += rx_errors; 3718 stats->rx_dropped += rx_dropped; 3719 stats->rx_missed_errors += rx_missed; 3720 stats->rx_length_errors += rx_length_errors; 3721 stats->rx_over_errors += rx_over_errors; 3722 stats->rx_crc_errors += rx_crc_errors; 3723 stats->rx_frame_errors += rx_frame_errors; 3724 stats->multicast += multicast; 3725 } 3726 } 3727 3728 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier) 3729 { 3730 struct bcmgenet_priv *priv = netdev_priv(dev); 3731 3732 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) || 3733 priv->phy_interface != PHY_INTERFACE_MODE_MOCA) 3734 return -EOPNOTSUPP; 3735 3736 if (new_carrier) 3737 netif_carrier_on(dev); 3738 else 3739 netif_carrier_off(dev); 3740 3741 return 0; 3742 } 3743 3744 static const struct net_device_ops bcmgenet_netdev_ops = { 3745 .ndo_open = bcmgenet_open, 3746 .ndo_stop = bcmgenet_close, 3747 .ndo_start_xmit = bcmgenet_xmit, 3748 .ndo_tx_timeout = bcmgenet_timeout, 3749 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3750 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3751 .ndo_eth_ioctl = phy_do_ioctl_running, 3752 .ndo_set_features = bcmgenet_set_features, 3753 .ndo_get_stats64 = bcmgenet_get_stats64, 3754 .ndo_change_carrier = bcmgenet_change_carrier, 3755 }; 3756 3757 /* GENET hardware parameters/characteristics */ 3758 static const struct bcmgenet_hw_params bcmgenet_hw_params_v1 = { 3759 .tx_queues = 0, 3760 .tx_bds_per_q = 0, 3761 .rx_queues = 0, 3762 .rx_bds_per_q = 0, 3763 .bp_in_en_shift = 16, 3764 .bp_in_mask = 0xffff, 3765 .hfb_filter_cnt = 16, 3766 .hfb_filter_size = 64, 3767 .qtag_mask = 0x1F, 3768 .hfb_offset = 0x1000, 3769 .hfb_reg_offset = GENET_RBUF_OFF + RBUF_HFB_CTRL_V1, 3770 .rdma_offset = 0x2000, 3771 .tdma_offset = 0x3000, 3772 .words_per_bd = 2, 3773 }; 3774 3775 static const struct bcmgenet_hw_params bcmgenet_hw_params_v2 = { 3776 .tx_queues = 4, 3777 .tx_bds_per_q = 32, 3778 .rx_queues = 0, 3779 .rx_bds_per_q = 0, 3780 .bp_in_en_shift = 16, 3781 .bp_in_mask = 0xffff, 3782 .hfb_filter_cnt = 16, 3783 .hfb_filter_size = 64, 3784 .qtag_mask = 0x1F, 3785 .tbuf_offset = 0x0600, 3786 .hfb_offset = 0x1000, 3787 .hfb_reg_offset = 0x2000, 3788 .rdma_offset = 0x3000, 3789 .tdma_offset = 0x4000, 3790 .words_per_bd = 2, 3791 }; 3792 3793 static const struct bcmgenet_hw_params bcmgenet_hw_params_v3 = { 3794 .tx_queues = 4, 3795 .tx_bds_per_q = 32, 3796 .rx_queues = 0, 3797 .rx_bds_per_q = 0, 3798 .bp_in_en_shift = 17, 3799 .bp_in_mask = 0x1ffff, 3800 .hfb_filter_cnt = 48, 3801 .hfb_filter_size = 128, 3802 .qtag_mask = 0x3F, 3803 .tbuf_offset = 0x0600, 3804 .hfb_offset = 0x8000, 3805 .hfb_reg_offset = 0xfc00, 3806 .rdma_offset = 0x10000, 3807 .tdma_offset = 0x11000, 3808 .words_per_bd = 2, 3809 }; 3810 3811 static const struct bcmgenet_hw_params bcmgenet_hw_params_v4 = { 3812 .tx_queues = 4, 3813 .tx_bds_per_q = 32, 3814 .rx_queues = 0, 3815 .rx_bds_per_q = 0, 3816 .bp_in_en_shift = 17, 3817 .bp_in_mask = 0x1ffff, 3818 .hfb_filter_cnt = 48, 3819 .hfb_filter_size = 128, 3820 .qtag_mask = 0x3F, 3821 .tbuf_offset = 0x0600, 3822 .hfb_offset = 0x8000, 3823 .hfb_reg_offset = 0xfc00, 3824 .rdma_offset = 0x2000, 3825 .tdma_offset = 0x4000, 3826 .words_per_bd = 3, 3827 }; 3828 3829 /* Infer hardware parameters from the detected GENET version */ 3830 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3831 { 3832 const struct bcmgenet_hw_params *params; 3833 u32 reg; 3834 u8 major; 3835 u16 gphy_rev; 3836 3837 /* default to latest values */ 3838 params = &bcmgenet_hw_params_v4; 3839 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3840 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3841 if (GENET_IS_V3(priv)) { 3842 params = &bcmgenet_hw_params_v3; 3843 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3844 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3845 } else if (GENET_IS_V2(priv)) { 3846 params = &bcmgenet_hw_params_v2; 3847 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3848 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3849 } else if (GENET_IS_V1(priv)) { 3850 params = &bcmgenet_hw_params_v1; 3851 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3852 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3853 } 3854 priv->hw_params = params; 3855 3856 /* Read GENET HW version */ 3857 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3858 major = (reg >> 24 & 0x0f); 3859 if (major == 6 || major == 7) 3860 major = 5; 3861 else if (major == 5) 3862 major = 4; 3863 else if (major == 0) 3864 major = 1; 3865 if (major != priv->version) { 3866 dev_err(&priv->pdev->dev, 3867 "GENET version mismatch, got: %d, configured for: %d\n", 3868 major, priv->version); 3869 } 3870 3871 /* Print the GENET core version */ 3872 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3873 major, (reg >> 16) & 0x0f, reg & 0xffff); 3874 3875 /* Store the integrated PHY revision for the MDIO probing function 3876 * to pass this information to the PHY driver. The PHY driver expects 3877 * to find the PHY major revision in bits 15:8 while the GENET register 3878 * stores that information in bits 7:0, account for that. 3879 * 3880 * On newer chips, starting with PHY revision G0, a new scheme is 3881 * deployed similar to the Starfighter 2 switch with GPHY major 3882 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3883 * is reserved as well as special value 0x01ff, we have a small 3884 * heuristic to check for the new GPHY revision and re-arrange things 3885 * so the GPHY driver is happy. 3886 */ 3887 gphy_rev = reg & 0xffff; 3888 3889 if (GENET_IS_V5(priv)) { 3890 /* The EPHY revision should come from the MDIO registers of 3891 * the PHY not from GENET. 3892 */ 3893 if (gphy_rev != 0) { 3894 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3895 gphy_rev); 3896 } 3897 /* This is reserved so should require special treatment */ 3898 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3899 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3900 return; 3901 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3902 } else if ((gphy_rev & 0xf0) != 0) { 3903 priv->gphy_rev = gphy_rev << 8; 3904 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3905 } else if ((gphy_rev & 0xff00) != 0) { 3906 priv->gphy_rev = gphy_rev; 3907 } 3908 3909 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3910 if (!bcmgenet_has_40bits(priv)) 3911 pr_warn("GENET does not support 40-bits PA\n"); 3912 #endif 3913 3914 pr_debug("Configuration for version: %d\n" 3915 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3916 "BP << en: %2d, BP msk: 0x%05x\n" 3917 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3918 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3919 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3920 "Words/BD: %d\n", 3921 priv->version, 3922 params->tx_queues, params->tx_bds_per_q, 3923 params->rx_queues, params->rx_bds_per_q, 3924 params->bp_in_en_shift, params->bp_in_mask, 3925 params->hfb_filter_cnt, params->qtag_mask, 3926 params->tbuf_offset, params->hfb_offset, 3927 params->hfb_reg_offset, 3928 params->rdma_offset, params->tdma_offset, 3929 params->words_per_bd); 3930 } 3931 3932 struct bcmgenet_plat_data { 3933 enum bcmgenet_version version; 3934 u32 dma_max_burst_length; 3935 u32 flags; 3936 }; 3937 3938 static const struct bcmgenet_plat_data v1_plat_data = { 3939 .version = GENET_V1, 3940 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3941 }; 3942 3943 static const struct bcmgenet_plat_data v2_plat_data = { 3944 .version = GENET_V2, 3945 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3946 .flags = GENET_HAS_EXT, 3947 }; 3948 3949 static const struct bcmgenet_plat_data v3_plat_data = { 3950 .version = GENET_V3, 3951 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3952 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3953 GENET_HAS_MOCA_LINK_DET, 3954 }; 3955 3956 static const struct bcmgenet_plat_data v4_plat_data = { 3957 .version = GENET_V4, 3958 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3959 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3960 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3961 }; 3962 3963 static const struct bcmgenet_plat_data v5_plat_data = { 3964 .version = GENET_V5, 3965 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3966 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3967 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3968 }; 3969 3970 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3971 .version = GENET_V5, 3972 .dma_max_burst_length = 0x08, 3973 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3974 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3975 }; 3976 3977 static const struct bcmgenet_plat_data bcm7712_plat_data = { 3978 .version = GENET_V5, 3979 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3980 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3981 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET | 3982 GENET_HAS_EPHY_16NM, 3983 }; 3984 3985 static const struct of_device_id bcmgenet_match[] = { 3986 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3987 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3988 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3989 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3990 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3991 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3992 { .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data }, 3993 { }, 3994 }; 3995 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3996 3997 static int bcmgenet_probe(struct platform_device *pdev) 3998 { 3999 const struct bcmgenet_plat_data *pdata; 4000 struct bcmgenet_priv *priv; 4001 struct net_device *dev; 4002 unsigned int i; 4003 int err = -EIO; 4004 4005 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 4006 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 4007 GENET_MAX_MQ_CNT + 1); 4008 if (!dev) { 4009 dev_err(&pdev->dev, "can't allocate net device\n"); 4010 return -ENOMEM; 4011 } 4012 4013 priv = netdev_priv(dev); 4014 priv->irq0 = platform_get_irq(pdev, 0); 4015 if (priv->irq0 < 0) { 4016 err = priv->irq0; 4017 goto err; 4018 } 4019 priv->irq1 = platform_get_irq(pdev, 1); 4020 if (priv->irq1 < 0) { 4021 err = priv->irq1; 4022 goto err; 4023 } 4024 priv->wol_irq = platform_get_irq_optional(pdev, 2); 4025 if (priv->wol_irq == -EPROBE_DEFER) { 4026 err = priv->wol_irq; 4027 goto err; 4028 } 4029 4030 priv->base = devm_platform_ioremap_resource(pdev, 0); 4031 if (IS_ERR(priv->base)) { 4032 err = PTR_ERR(priv->base); 4033 goto err; 4034 } 4035 4036 spin_lock_init(&priv->reg_lock); 4037 spin_lock_init(&priv->lock); 4038 4039 /* Set default pause parameters */ 4040 priv->autoneg_pause = 1; 4041 priv->tx_pause = 1; 4042 priv->rx_pause = 1; 4043 4044 SET_NETDEV_DEV(dev, &pdev->dev); 4045 dev_set_drvdata(&pdev->dev, dev); 4046 dev->watchdog_timeo = 2 * HZ; 4047 dev->ethtool_ops = &bcmgenet_ethtool_ops; 4048 dev->netdev_ops = &bcmgenet_netdev_ops; 4049 4050 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 4051 4052 /* Set default features */ 4053 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 4054 NETIF_F_RXCSUM; 4055 dev->hw_features |= dev->features; 4056 dev->vlan_features |= dev->features; 4057 4058 netdev_sw_irq_coalesce_default_on(dev); 4059 4060 /* Request the WOL interrupt and advertise suspend if available */ 4061 priv->wol_irq_disabled = true; 4062 if (priv->wol_irq > 0) { 4063 err = devm_request_irq(&pdev->dev, priv->wol_irq, 4064 bcmgenet_wol_isr, 0, dev->name, priv); 4065 if (!err) 4066 device_set_wakeup_capable(&pdev->dev, 1); 4067 } 4068 4069 /* Set the needed headroom to account for any possible 4070 * features enabling/disabling at runtime 4071 */ 4072 dev->needed_headroom += 64; 4073 4074 priv->dev = dev; 4075 priv->pdev = pdev; 4076 4077 pdata = device_get_match_data(&pdev->dev); 4078 if (pdata) { 4079 priv->version = pdata->version; 4080 priv->dma_max_burst_length = pdata->dma_max_burst_length; 4081 priv->flags = pdata->flags; 4082 } 4083 4084 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet"); 4085 if (IS_ERR(priv->clk)) { 4086 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 4087 err = PTR_ERR(priv->clk); 4088 goto err; 4089 } 4090 4091 err = clk_prepare_enable(priv->clk); 4092 if (err) 4093 goto err; 4094 4095 bcmgenet_set_hw_params(priv); 4096 4097 err = -EIO; 4098 if (bcmgenet_has_40bits(priv)) 4099 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 4100 if (err) 4101 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 4102 if (err) 4103 goto err_clk_disable; 4104 4105 /* Mii wait queue */ 4106 init_waitqueue_head(&priv->wq); 4107 bcmgenet_hfb_init(priv); 4108 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 4109 4110 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol"); 4111 if (IS_ERR(priv->clk_wol)) { 4112 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 4113 err = PTR_ERR(priv->clk_wol); 4114 goto err_clk_disable; 4115 } 4116 4117 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee"); 4118 if (IS_ERR(priv->clk_eee)) { 4119 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 4120 err = PTR_ERR(priv->clk_eee); 4121 goto err_clk_disable; 4122 } 4123 4124 /* If this is an internal GPHY, power it on now, before UniMAC is 4125 * brought out of reset as absolutely no UniMAC activity is allowed 4126 */ 4127 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 4128 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4129 4130 if (device_get_ethdev_address(&pdev->dev, dev)) 4131 if (has_acpi_companion(&pdev->dev)) { 4132 u8 addr[ETH_ALEN]; 4133 4134 bcmgenet_get_hw_addr(priv, addr); 4135 eth_hw_addr_set(dev, addr); 4136 } 4137 4138 if (!is_valid_ether_addr(dev->dev_addr)) { 4139 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 4140 eth_hw_addr_random(dev); 4141 } 4142 4143 reset_umac(priv); 4144 4145 err = bcmgenet_mii_init(dev); 4146 if (err) 4147 goto err_clk_disable; 4148 4149 /* setup number of real queues + 1 */ 4150 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 4151 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 4152 4153 /* Set default coalescing parameters */ 4154 for (i = 0; i <= priv->hw_params->rx_queues; i++) { 4155 priv->rx_rings[i].priv = priv; 4156 priv->rx_rings[i].index = i; 4157 priv->rx_rings[i].rx_max_coalesced_frames = 1; 4158 } 4159 4160 /* Initialize u64 stats seq counter for 32bit machines */ 4161 for (i = 0; i <= GENET_MAX_MQ_CNT; i++) { 4162 u64_stats_init(&priv->rx_rings[i].stats64.syncp); 4163 u64_stats_init(&priv->tx_rings[i].stats64.syncp); 4164 } 4165 4166 /* libphy will determine the link state */ 4167 netif_carrier_off(dev); 4168 4169 /* Turn off the main clock, WOL clock is handled separately */ 4170 clk_disable_unprepare(priv->clk); 4171 4172 err = register_netdev(dev); 4173 if (err) { 4174 bcmgenet_mii_exit(dev); 4175 goto err; 4176 } 4177 4178 return err; 4179 4180 err_clk_disable: 4181 clk_disable_unprepare(priv->clk); 4182 err: 4183 free_netdev(dev); 4184 return err; 4185 } 4186 4187 static void bcmgenet_remove(struct platform_device *pdev) 4188 { 4189 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 4190 4191 dev_set_drvdata(&pdev->dev, NULL); 4192 unregister_netdev(priv->dev); 4193 bcmgenet_mii_exit(priv->dev); 4194 free_netdev(priv->dev); 4195 } 4196 4197 static void bcmgenet_shutdown(struct platform_device *pdev) 4198 { 4199 bcmgenet_remove(pdev); 4200 } 4201 4202 #ifdef CONFIG_PM_SLEEP 4203 static int bcmgenet_resume_noirq(struct device *d) 4204 { 4205 struct net_device *dev = dev_get_drvdata(d); 4206 struct bcmgenet_priv *priv = netdev_priv(dev); 4207 int ret; 4208 u32 reg; 4209 4210 if (!netif_running(dev)) 4211 return 0; 4212 4213 /* Turn on the clock */ 4214 ret = clk_prepare_enable(priv->clk); 4215 if (ret) 4216 return ret; 4217 4218 if (device_may_wakeup(d) && priv->wolopts) { 4219 /* Account for Wake-on-LAN events and clear those events 4220 * (Some devices need more time between enabling the clocks 4221 * and the interrupt register reflecting the wake event so 4222 * read the register twice) 4223 */ 4224 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4225 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4226 if (reg & UMAC_IRQ_WAKE_EVENT) 4227 pm_wakeup_event(&priv->pdev->dev, 0); 4228 4229 /* From WOL-enabled suspend, switch to regular clock */ 4230 if (!bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC)) 4231 return 0; 4232 4233 /* Failed so fall through to reset MAC */ 4234 } 4235 4236 /* If this is an internal GPHY, power it back on now, before UniMAC is 4237 * brought out of reset as absolutely no UniMAC activity is allowed 4238 */ 4239 if (priv->internal_phy) 4240 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4241 4242 /* take MAC out of reset */ 4243 bcmgenet_umac_reset(priv); 4244 4245 return 0; 4246 } 4247 4248 static int bcmgenet_resume(struct device *d) 4249 { 4250 struct net_device *dev = dev_get_drvdata(d); 4251 struct bcmgenet_priv *priv = netdev_priv(dev); 4252 struct bcmgenet_rxnfc_rule *rule; 4253 int ret; 4254 u32 reg; 4255 4256 if (!netif_running(dev)) 4257 return 0; 4258 4259 if (device_may_wakeup(d) && priv->wolopts) { 4260 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 4261 if (reg & CMD_RX_EN) { 4262 /* Successfully exited WoL, just resume data flows */ 4263 list_for_each_entry(rule, &priv->rxnfc_list, list) 4264 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 4265 bcmgenet_hfb_enable_filter(priv, 4266 rule->fs.location + 1); 4267 bcmgenet_hfb_enable_filter(priv, 0); 4268 bcmgenet_set_rx_mode(dev); 4269 bcmgenet_enable_rx_napi(priv); 4270 4271 /* Reinitialize Tx flows */ 4272 bcmgenet_tdma_disable(priv); 4273 bcmgenet_init_tx_queues(priv->dev); 4274 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 4275 reg |= DMA_EN; 4276 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 4277 bcmgenet_enable_tx_napi(priv); 4278 4279 bcmgenet_link_intr_enable(priv); 4280 phy_start_machine(dev->phydev); 4281 4282 netif_device_attach(dev); 4283 enable_irq(priv->irq1); 4284 return 0; 4285 } 4286 /* MAC was reset so complete bcmgenet_netif_stop() */ 4287 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, false); 4288 bcmgenet_rdma_disable(priv); 4289 bcmgenet_intr_disable(priv); 4290 bcmgenet_fini_dma(priv); 4291 enable_irq(priv->irq1); 4292 } 4293 4294 init_umac(priv); 4295 4296 phy_init_hw(dev->phydev); 4297 4298 /* Speed settings must be restored */ 4299 genphy_config_aneg(dev->phydev); 4300 bcmgenet_mii_config(priv->dev, false); 4301 4302 /* Restore enabled features */ 4303 bcmgenet_set_features(dev, dev->features); 4304 4305 bcmgenet_set_hw_addr(priv, dev->dev_addr); 4306 4307 /* Restore hardware filters */ 4308 bcmgenet_hfb_restore(priv); 4309 4310 /* Reinitialize TDMA and RDMA and SW housekeeping */ 4311 ret = bcmgenet_init_dma(priv, false); 4312 if (ret) { 4313 netdev_err(dev, "failed to initialize DMA\n"); 4314 goto out_clk_disable; 4315 } 4316 4317 if (!device_may_wakeup(d)) 4318 phy_resume(dev->phydev); 4319 4320 bcmgenet_netif_start(dev); 4321 4322 netif_device_attach(dev); 4323 4324 return 0; 4325 4326 out_clk_disable: 4327 if (priv->internal_phy) 4328 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4329 clk_disable_unprepare(priv->clk); 4330 return ret; 4331 } 4332 4333 static int bcmgenet_suspend(struct device *d) 4334 { 4335 struct net_device *dev = dev_get_drvdata(d); 4336 struct bcmgenet_priv *priv = netdev_priv(dev); 4337 struct bcmgenet_rxnfc_rule *rule; 4338 u32 reg, hfb_enable = 0; 4339 4340 if (!netif_running(dev)) 4341 return 0; 4342 4343 netif_device_detach(dev); 4344 4345 if (device_may_wakeup(d) && priv->wolopts) { 4346 /* Stop completion polling before it can wake a stopped queue */ 4347 bcmgenet_disable_tx_napi(priv); 4348 netif_tx_disable(dev); 4349 4350 /* Suspend non-wake Rx data flows */ 4351 if (priv->wolopts & WAKE_FILTER) 4352 list_for_each_entry(rule, &priv->rxnfc_list, list) 4353 if (rule->fs.ring_cookie == RX_CLS_FLOW_WAKE && 4354 rule->state == BCMGENET_RXNFC_STATE_ENABLED) 4355 hfb_enable |= 1 << rule->fs.location; 4356 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 4357 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 4358 reg &= ~RBUF_HFB_FILTER_EN_MASK; 4359 reg |= hfb_enable << (RBUF_HFB_FILTER_EN_SHIFT + 1); 4360 } else { 4361 bcmgenet_hfb_reg_writel(priv, hfb_enable << 1, 4362 HFB_FLT_ENABLE_V3PLUS + 4); 4363 } 4364 if (!hfb_enable) 4365 reg &= ~RBUF_HFB_EN; 4366 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 4367 4368 /* Clear any old filter matches so only new matches wake */ 4369 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 4370 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 4371 4372 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) 4373 netdev_warn(priv->dev, 4374 "Timed out while disabling TX DMA\n"); 4375 4376 bcmgenet_disable_rx_napi(priv); 4377 disable_irq(priv->irq1); 4378 bcmgenet_tx_reclaim_all(dev); 4379 bcmgenet_fini_tx_napi(priv); 4380 } else { 4381 /* Teardown the interface */ 4382 bcmgenet_netif_stop(dev, true); 4383 } 4384 4385 return 0; 4386 } 4387 4388 static int bcmgenet_suspend_noirq(struct device *d) 4389 { 4390 struct net_device *dev = dev_get_drvdata(d); 4391 struct bcmgenet_priv *priv = netdev_priv(dev); 4392 int ret = 0; 4393 4394 if (!netif_running(dev)) 4395 return 0; 4396 4397 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 4398 if (device_may_wakeup(d) && priv->wolopts) 4399 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 4400 else if (priv->internal_phy) 4401 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4402 4403 /* Let the framework handle resumption and leave the clocks on */ 4404 if (ret) 4405 return ret; 4406 4407 /* Turn off the clocks */ 4408 clk_disable_unprepare(priv->clk); 4409 4410 return 0; 4411 } 4412 #else 4413 #define bcmgenet_suspend NULL 4414 #define bcmgenet_suspend_noirq NULL 4415 #define bcmgenet_resume NULL 4416 #define bcmgenet_resume_noirq NULL 4417 #endif /* CONFIG_PM_SLEEP */ 4418 4419 static const struct dev_pm_ops bcmgenet_pm_ops = { 4420 .suspend = bcmgenet_suspend, 4421 .suspend_noirq = bcmgenet_suspend_noirq, 4422 .resume = bcmgenet_resume, 4423 .resume_noirq = bcmgenet_resume_noirq, 4424 }; 4425 4426 static const struct acpi_device_id genet_acpi_match[] = { 4427 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 4428 { }, 4429 }; 4430 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 4431 4432 static struct platform_driver bcmgenet_driver = { 4433 .probe = bcmgenet_probe, 4434 .remove = bcmgenet_remove, 4435 .shutdown = bcmgenet_shutdown, 4436 .driver = { 4437 .name = "bcmgenet", 4438 .of_match_table = bcmgenet_match, 4439 .pm = &bcmgenet_pm_ops, 4440 .acpi_match_table = genet_acpi_match, 4441 }, 4442 }; 4443 module_platform_driver(bcmgenet_driver); 4444 4445 MODULE_AUTHOR("Broadcom Corporation"); 4446 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 4447 MODULE_ALIAS("platform:bcmgenet"); 4448 MODULE_LICENSE("GPL"); 4449 MODULE_SOFTDEP("pre: mdio-bcm-unimac"); 4450