1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2025 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <net/arp.h> 27 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/netdevice.h> 31 #include <linux/inetdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/in.h> 35 #include <linux/ip.h> 36 #include <linux/ipv6.h> 37 #include <linux/phy.h> 38 39 #include <linux/unaligned.h> 40 41 #include "bcmgenet.h" 42 43 #define GENET_Q0_WEIGHT 1 44 #define GENET_Q1_WEIGHT 4 45 46 #define GENET_Q0_RX_BD_CNT \ 47 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 48 #define GENET_Q0_TX_BD_CNT \ 49 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 50 51 #define RX_BUF_LENGTH 2048 52 #define SKB_ALIGNMENT 32 53 54 /* Page pool RX buffer layout: 55 * RSB(64) + pad(2) | frame data | skb_shared_info 56 * The HW writes the 64B RSB + 2B alignment padding before the frame. 57 */ 58 #define GENET_RSB_PAD (sizeof(struct status_64) + 2) 59 60 /* Tx/Rx DMA register offset, skip 256 descriptors */ 61 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 62 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 63 64 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 65 TOTAL_DESC * DMA_DESC_SIZE) 66 67 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 68 TOTAL_DESC * DMA_DESC_SIZE) 69 70 /* Forward declarations */ 71 static void bcmgenet_set_rx_mode(struct net_device *dev); 72 73 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 74 { 75 /* MIPS chips strapped for BE will automagically configure the 76 * peripheral registers for CPU-native byte order. 77 */ 78 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 79 __raw_writel(value, offset); 80 else 81 writel_relaxed(value, offset); 82 } 83 84 static inline u32 bcmgenet_readl(void __iomem *offset) 85 { 86 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 87 return __raw_readl(offset); 88 else 89 return readl_relaxed(offset); 90 } 91 92 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 93 void __iomem *d, u32 value) 94 { 95 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 96 } 97 98 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 99 void __iomem *d, 100 dma_addr_t addr) 101 { 102 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 103 104 /* Register writes to GISB bus can take couple hundred nanoseconds 105 * and are done for each packet, save these expensive writes unless 106 * the platform is explicitly configured for 64-bits/LPAE. 107 */ 108 #ifdef CONFIG_PHYS_ADDR_T_64BIT 109 if (bcmgenet_has_40bits(priv)) 110 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 111 #endif 112 } 113 114 /* Combined address + length/status setter */ 115 static inline void dmadesc_set(struct bcmgenet_priv *priv, 116 void __iomem *d, dma_addr_t addr, u32 val) 117 { 118 dmadesc_set_addr(priv, d, addr); 119 dmadesc_set_length_status(priv, d, val); 120 } 121 122 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 123 124 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 125 NETIF_MSG_LINK) 126 127 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 128 { 129 if (GENET_IS_V1(priv)) 130 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 131 else 132 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 133 } 134 135 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 136 { 137 if (GENET_IS_V1(priv)) 138 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 139 else 140 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 141 } 142 143 /* These macros are defined to deal with register map change 144 * between GENET1.1 and GENET2. Only those currently being used 145 * by driver are defined. 146 */ 147 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 148 { 149 if (GENET_IS_V1(priv)) 150 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 151 else 152 return bcmgenet_readl(priv->base + 153 priv->hw_params->tbuf_offset + TBUF_CTRL); 154 } 155 156 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 157 { 158 if (GENET_IS_V1(priv)) 159 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 160 else 161 bcmgenet_writel(val, priv->base + 162 priv->hw_params->tbuf_offset + TBUF_CTRL); 163 } 164 165 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 166 { 167 if (GENET_IS_V1(priv)) 168 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 169 else 170 return bcmgenet_readl(priv->base + 171 priv->hw_params->tbuf_offset + TBUF_BP_MC); 172 } 173 174 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 175 { 176 if (GENET_IS_V1(priv)) 177 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 178 else 179 bcmgenet_writel(val, priv->base + 180 priv->hw_params->tbuf_offset + TBUF_BP_MC); 181 } 182 183 /* RX/TX DMA register accessors */ 184 enum dma_reg { 185 DMA_RING_CFG = 0, 186 DMA_CTRL, 187 DMA_STATUS, 188 DMA_SCB_BURST_SIZE, 189 DMA_ARB_CTRL, 190 DMA_PRIORITY_0, 191 DMA_PRIORITY_1, 192 DMA_PRIORITY_2, 193 DMA_INDEX2RING_0, 194 DMA_INDEX2RING_1, 195 DMA_INDEX2RING_2, 196 DMA_INDEX2RING_3, 197 DMA_INDEX2RING_4, 198 DMA_INDEX2RING_5, 199 DMA_INDEX2RING_6, 200 DMA_INDEX2RING_7, 201 DMA_RING0_TIMEOUT, 202 DMA_RING1_TIMEOUT, 203 DMA_RING2_TIMEOUT, 204 DMA_RING3_TIMEOUT, 205 DMA_RING4_TIMEOUT, 206 DMA_RING5_TIMEOUT, 207 DMA_RING6_TIMEOUT, 208 DMA_RING7_TIMEOUT, 209 DMA_RING8_TIMEOUT, 210 DMA_RING9_TIMEOUT, 211 DMA_RING10_TIMEOUT, 212 DMA_RING11_TIMEOUT, 213 DMA_RING12_TIMEOUT, 214 DMA_RING13_TIMEOUT, 215 DMA_RING14_TIMEOUT, 216 DMA_RING15_TIMEOUT, 217 DMA_RING16_TIMEOUT, 218 }; 219 220 static const u8 bcmgenet_dma_regs_v3plus[] = { 221 [DMA_RING_CFG] = 0x00, 222 [DMA_CTRL] = 0x04, 223 [DMA_STATUS] = 0x08, 224 [DMA_SCB_BURST_SIZE] = 0x0C, 225 [DMA_ARB_CTRL] = 0x2C, 226 [DMA_PRIORITY_0] = 0x30, 227 [DMA_PRIORITY_1] = 0x34, 228 [DMA_PRIORITY_2] = 0x38, 229 [DMA_RING0_TIMEOUT] = 0x2C, 230 [DMA_RING1_TIMEOUT] = 0x30, 231 [DMA_RING2_TIMEOUT] = 0x34, 232 [DMA_RING3_TIMEOUT] = 0x38, 233 [DMA_RING4_TIMEOUT] = 0x3c, 234 [DMA_RING5_TIMEOUT] = 0x40, 235 [DMA_RING6_TIMEOUT] = 0x44, 236 [DMA_RING7_TIMEOUT] = 0x48, 237 [DMA_RING8_TIMEOUT] = 0x4c, 238 [DMA_RING9_TIMEOUT] = 0x50, 239 [DMA_RING10_TIMEOUT] = 0x54, 240 [DMA_RING11_TIMEOUT] = 0x58, 241 [DMA_RING12_TIMEOUT] = 0x5c, 242 [DMA_RING13_TIMEOUT] = 0x60, 243 [DMA_RING14_TIMEOUT] = 0x64, 244 [DMA_RING15_TIMEOUT] = 0x68, 245 [DMA_RING16_TIMEOUT] = 0x6C, 246 [DMA_INDEX2RING_0] = 0x70, 247 [DMA_INDEX2RING_1] = 0x74, 248 [DMA_INDEX2RING_2] = 0x78, 249 [DMA_INDEX2RING_3] = 0x7C, 250 [DMA_INDEX2RING_4] = 0x80, 251 [DMA_INDEX2RING_5] = 0x84, 252 [DMA_INDEX2RING_6] = 0x88, 253 [DMA_INDEX2RING_7] = 0x8C, 254 }; 255 256 static const u8 bcmgenet_dma_regs_v2[] = { 257 [DMA_RING_CFG] = 0x00, 258 [DMA_CTRL] = 0x04, 259 [DMA_STATUS] = 0x08, 260 [DMA_SCB_BURST_SIZE] = 0x0C, 261 [DMA_ARB_CTRL] = 0x30, 262 [DMA_PRIORITY_0] = 0x34, 263 [DMA_PRIORITY_1] = 0x38, 264 [DMA_PRIORITY_2] = 0x3C, 265 [DMA_RING0_TIMEOUT] = 0x2C, 266 [DMA_RING1_TIMEOUT] = 0x30, 267 [DMA_RING2_TIMEOUT] = 0x34, 268 [DMA_RING3_TIMEOUT] = 0x38, 269 [DMA_RING4_TIMEOUT] = 0x3c, 270 [DMA_RING5_TIMEOUT] = 0x40, 271 [DMA_RING6_TIMEOUT] = 0x44, 272 [DMA_RING7_TIMEOUT] = 0x48, 273 [DMA_RING8_TIMEOUT] = 0x4c, 274 [DMA_RING9_TIMEOUT] = 0x50, 275 [DMA_RING10_TIMEOUT] = 0x54, 276 [DMA_RING11_TIMEOUT] = 0x58, 277 [DMA_RING12_TIMEOUT] = 0x5c, 278 [DMA_RING13_TIMEOUT] = 0x60, 279 [DMA_RING14_TIMEOUT] = 0x64, 280 [DMA_RING15_TIMEOUT] = 0x68, 281 [DMA_RING16_TIMEOUT] = 0x6C, 282 }; 283 284 static const u8 bcmgenet_dma_regs_v1[] = { 285 [DMA_CTRL] = 0x00, 286 [DMA_STATUS] = 0x04, 287 [DMA_SCB_BURST_SIZE] = 0x0C, 288 [DMA_ARB_CTRL] = 0x30, 289 [DMA_PRIORITY_0] = 0x34, 290 [DMA_PRIORITY_1] = 0x38, 291 [DMA_PRIORITY_2] = 0x3C, 292 [DMA_RING0_TIMEOUT] = 0x2C, 293 [DMA_RING1_TIMEOUT] = 0x30, 294 [DMA_RING2_TIMEOUT] = 0x34, 295 [DMA_RING3_TIMEOUT] = 0x38, 296 [DMA_RING4_TIMEOUT] = 0x3c, 297 [DMA_RING5_TIMEOUT] = 0x40, 298 [DMA_RING6_TIMEOUT] = 0x44, 299 [DMA_RING7_TIMEOUT] = 0x48, 300 [DMA_RING8_TIMEOUT] = 0x4c, 301 [DMA_RING9_TIMEOUT] = 0x50, 302 [DMA_RING10_TIMEOUT] = 0x54, 303 [DMA_RING11_TIMEOUT] = 0x58, 304 [DMA_RING12_TIMEOUT] = 0x5c, 305 [DMA_RING13_TIMEOUT] = 0x60, 306 [DMA_RING14_TIMEOUT] = 0x64, 307 [DMA_RING15_TIMEOUT] = 0x68, 308 [DMA_RING16_TIMEOUT] = 0x6C, 309 }; 310 311 /* Set at runtime once bcmgenet version is known */ 312 static const u8 *bcmgenet_dma_regs; 313 314 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 315 { 316 return netdev_priv(dev_get_drvdata(dev)); 317 } 318 319 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 320 enum dma_reg r) 321 { 322 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 323 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 324 } 325 326 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 327 u32 val, enum dma_reg r) 328 { 329 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 330 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 331 } 332 333 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 334 enum dma_reg r) 335 { 336 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 337 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 338 } 339 340 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 341 u32 val, enum dma_reg r) 342 { 343 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 344 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 345 } 346 347 /* RDMA/TDMA ring registers and accessors 348 * we merge the common fields and just prefix with T/D the registers 349 * having different meaning depending on the direction 350 */ 351 enum dma_ring_reg { 352 TDMA_READ_PTR = 0, 353 RDMA_WRITE_PTR = TDMA_READ_PTR, 354 TDMA_READ_PTR_HI, 355 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 356 TDMA_CONS_INDEX, 357 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 358 TDMA_PROD_INDEX, 359 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 360 DMA_RING_BUF_SIZE, 361 DMA_START_ADDR, 362 DMA_START_ADDR_HI, 363 DMA_END_ADDR, 364 DMA_END_ADDR_HI, 365 DMA_MBUF_DONE_THRESH, 366 TDMA_FLOW_PERIOD, 367 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 368 TDMA_WRITE_PTR, 369 RDMA_READ_PTR = TDMA_WRITE_PTR, 370 TDMA_WRITE_PTR_HI, 371 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 372 }; 373 374 /* GENET v4 supports 40-bits pointer addressing 375 * for obvious reasons the LO and HI word parts 376 * are contiguous, but this offsets the other 377 * registers. 378 */ 379 static const u8 genet_dma_ring_regs_v4[] = { 380 [TDMA_READ_PTR] = 0x00, 381 [TDMA_READ_PTR_HI] = 0x04, 382 [TDMA_CONS_INDEX] = 0x08, 383 [TDMA_PROD_INDEX] = 0x0C, 384 [DMA_RING_BUF_SIZE] = 0x10, 385 [DMA_START_ADDR] = 0x14, 386 [DMA_START_ADDR_HI] = 0x18, 387 [DMA_END_ADDR] = 0x1C, 388 [DMA_END_ADDR_HI] = 0x20, 389 [DMA_MBUF_DONE_THRESH] = 0x24, 390 [TDMA_FLOW_PERIOD] = 0x28, 391 [TDMA_WRITE_PTR] = 0x2C, 392 [TDMA_WRITE_PTR_HI] = 0x30, 393 }; 394 395 static const u8 genet_dma_ring_regs_v123[] = { 396 [TDMA_READ_PTR] = 0x00, 397 [TDMA_CONS_INDEX] = 0x04, 398 [TDMA_PROD_INDEX] = 0x08, 399 [DMA_RING_BUF_SIZE] = 0x0C, 400 [DMA_START_ADDR] = 0x10, 401 [DMA_END_ADDR] = 0x14, 402 [DMA_MBUF_DONE_THRESH] = 0x18, 403 [TDMA_FLOW_PERIOD] = 0x1C, 404 [TDMA_WRITE_PTR] = 0x20, 405 }; 406 407 /* Set at runtime once GENET version is known */ 408 static const u8 *genet_dma_ring_regs; 409 410 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 411 unsigned int ring, 412 enum dma_ring_reg r) 413 { 414 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 415 (DMA_RING_SIZE * ring) + 416 genet_dma_ring_regs[r]); 417 } 418 419 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 420 unsigned int ring, u32 val, 421 enum dma_ring_reg r) 422 { 423 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 424 (DMA_RING_SIZE * ring) + 425 genet_dma_ring_regs[r]); 426 } 427 428 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 429 unsigned int ring, 430 enum dma_ring_reg r) 431 { 432 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 433 (DMA_RING_SIZE * ring) + 434 genet_dma_ring_regs[r]); 435 } 436 437 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 438 unsigned int ring, u32 val, 439 enum dma_ring_reg r) 440 { 441 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 442 (DMA_RING_SIZE * ring) + 443 genet_dma_ring_regs[r]); 444 } 445 446 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 447 { 448 u32 offset; 449 u32 reg; 450 451 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 452 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 453 reg |= (1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)) | 454 RBUF_HFB_EN; 455 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 456 } else { 457 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 458 reg = bcmgenet_hfb_reg_readl(priv, offset); 459 reg |= (1 << (f_index % 32)); 460 bcmgenet_hfb_reg_writel(priv, reg, offset); 461 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 462 reg |= RBUF_HFB_EN; 463 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 464 } 465 } 466 467 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index) 468 { 469 u32 offset, reg, reg1; 470 471 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 472 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 473 reg &= ~(1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)); 474 if (!(reg & RBUF_HFB_FILTER_EN_MASK)) 475 reg &= ~RBUF_HFB_EN; 476 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 477 } else { 478 offset = HFB_FLT_ENABLE_V3PLUS; 479 reg = bcmgenet_hfb_reg_readl(priv, offset); 480 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 481 if (f_index < 32) { 482 reg1 &= ~(1 << (f_index % 32)); 483 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32)); 484 } else { 485 reg &= ~(1 << (f_index % 32)); 486 bcmgenet_hfb_reg_writel(priv, reg, offset); 487 } 488 if (!reg && !reg1) { 489 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 490 reg &= ~RBUF_HFB_EN; 491 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 492 } 493 } 494 } 495 496 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 497 u32 f_index, u32 rx_queue) 498 { 499 u32 offset; 500 u32 reg; 501 502 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 503 return; 504 505 offset = f_index / 8; 506 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 507 reg &= ~(0xF << (4 * (f_index % 8))); 508 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 509 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 510 } 511 512 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 513 u32 f_index, u32 f_length) 514 { 515 u32 offset; 516 u32 reg; 517 518 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 519 offset = HFB_FLT_LEN_V2; 520 else 521 offset = HFB_FLT_LEN_V3PLUS; 522 523 offset += sizeof(u32) * 524 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4); 525 reg = bcmgenet_hfb_reg_readl(priv, offset); 526 reg &= ~(0xFF << (8 * (f_index % 4))); 527 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 528 bcmgenet_hfb_reg_writel(priv, reg, offset); 529 } 530 531 static int bcmgenet_hfb_validate_mask(void *mask, size_t size) 532 { 533 while (size) { 534 switch (*(unsigned char *)mask++) { 535 case 0x00: 536 case 0x0f: 537 case 0xf0: 538 case 0xff: 539 size--; 540 continue; 541 default: 542 return -EINVAL; 543 } 544 } 545 546 return 0; 547 } 548 549 #define VALIDATE_MASK(x) \ 550 bcmgenet_hfb_validate_mask(&(x), sizeof(x)) 551 552 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index, 553 u32 offset, void *val, void *mask, 554 size_t size) 555 { 556 u32 index, tmp; 557 558 index = f_index * priv->hw_params->hfb_filter_size + offset / 2; 559 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32)); 560 561 while (size--) { 562 if (offset++ & 1) { 563 tmp &= ~0x300FF; 564 tmp |= (*(unsigned char *)val++); 565 switch ((*(unsigned char *)mask++)) { 566 case 0xFF: 567 tmp |= 0x30000; 568 break; 569 case 0xF0: 570 tmp |= 0x20000; 571 break; 572 case 0x0F: 573 tmp |= 0x10000; 574 break; 575 } 576 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32)); 577 if (size) 578 tmp = bcmgenet_hfb_readl(priv, 579 index * sizeof(u32)); 580 } else { 581 tmp &= ~0xCFF00; 582 tmp |= (*(unsigned char *)val++) << 8; 583 switch ((*(unsigned char *)mask++)) { 584 case 0xFF: 585 tmp |= 0xC0000; 586 break; 587 case 0xF0: 588 tmp |= 0x80000; 589 break; 590 case 0x0F: 591 tmp |= 0x40000; 592 break; 593 } 594 if (!size) 595 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32)); 596 } 597 } 598 599 return 0; 600 } 601 602 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv, 603 struct bcmgenet_rxnfc_rule *rule) 604 { 605 struct ethtool_rx_flow_spec *fs = &rule->fs; 606 u32 offset = 0, f_length = 0, f, q; 607 u8 val_8, mask_8; 608 __be16 val_16; 609 u16 mask_16; 610 size_t size; 611 612 f = fs->location + 1; 613 if (fs->flow_type & FLOW_MAC_EXT) { 614 bcmgenet_hfb_insert_data(priv, f, 0, 615 &fs->h_ext.h_dest, &fs->m_ext.h_dest, 616 sizeof(fs->h_ext.h_dest)); 617 } 618 619 if (fs->flow_type & FLOW_EXT) { 620 if (fs->m_ext.vlan_etype || 621 fs->m_ext.vlan_tci) { 622 bcmgenet_hfb_insert_data(priv, f, 12, 623 &fs->h_ext.vlan_etype, 624 &fs->m_ext.vlan_etype, 625 sizeof(fs->h_ext.vlan_etype)); 626 bcmgenet_hfb_insert_data(priv, f, 14, 627 &fs->h_ext.vlan_tci, 628 &fs->m_ext.vlan_tci, 629 sizeof(fs->h_ext.vlan_tci)); 630 offset += VLAN_HLEN; 631 f_length += DIV_ROUND_UP(VLAN_HLEN, 2); 632 } 633 } 634 635 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 636 case ETHER_FLOW: 637 f_length += DIV_ROUND_UP(ETH_HLEN, 2); 638 bcmgenet_hfb_insert_data(priv, f, 0, 639 &fs->h_u.ether_spec.h_dest, 640 &fs->m_u.ether_spec.h_dest, 641 sizeof(fs->h_u.ether_spec.h_dest)); 642 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN, 643 &fs->h_u.ether_spec.h_source, 644 &fs->m_u.ether_spec.h_source, 645 sizeof(fs->h_u.ether_spec.h_source)); 646 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 647 &fs->h_u.ether_spec.h_proto, 648 &fs->m_u.ether_spec.h_proto, 649 sizeof(fs->h_u.ether_spec.h_proto)); 650 break; 651 case IP_USER_FLOW: 652 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2); 653 /* Specify IP Ether Type */ 654 val_16 = htons(ETH_P_IP); 655 mask_16 = 0xFFFF; 656 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 657 &val_16, &mask_16, sizeof(val_16)); 658 bcmgenet_hfb_insert_data(priv, f, 15 + offset, 659 &fs->h_u.usr_ip4_spec.tos, 660 &fs->m_u.usr_ip4_spec.tos, 661 sizeof(fs->h_u.usr_ip4_spec.tos)); 662 bcmgenet_hfb_insert_data(priv, f, 23 + offset, 663 &fs->h_u.usr_ip4_spec.proto, 664 &fs->m_u.usr_ip4_spec.proto, 665 sizeof(fs->h_u.usr_ip4_spec.proto)); 666 bcmgenet_hfb_insert_data(priv, f, 26 + offset, 667 &fs->h_u.usr_ip4_spec.ip4src, 668 &fs->m_u.usr_ip4_spec.ip4src, 669 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 670 bcmgenet_hfb_insert_data(priv, f, 30 + offset, 671 &fs->h_u.usr_ip4_spec.ip4dst, 672 &fs->m_u.usr_ip4_spec.ip4dst, 673 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 674 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 675 break; 676 677 /* Only supports 20 byte IPv4 header */ 678 val_8 = 0x45; 679 mask_8 = 0xFF; 680 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset, 681 &val_8, &mask_8, 682 sizeof(val_8)); 683 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes); 684 bcmgenet_hfb_insert_data(priv, f, 685 ETH_HLEN + 20 + offset, 686 &fs->h_u.usr_ip4_spec.l4_4_bytes, 687 &fs->m_u.usr_ip4_spec.l4_4_bytes, 688 size); 689 f_length += DIV_ROUND_UP(size, 2); 690 break; 691 } 692 693 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length); 694 if (fs->ring_cookie == RX_CLS_FLOW_WAKE) 695 q = 0; 696 else if (fs->ring_cookie == RX_CLS_FLOW_DISC) 697 q = priv->hw_params->rx_queues + 1; 698 else 699 /* Other Rx rings are direct mapped here */ 700 q = fs->ring_cookie; 701 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, q); 702 bcmgenet_hfb_enable_filter(priv, f); 703 rule->state = BCMGENET_RXNFC_STATE_ENABLED; 704 } 705 706 /* bcmgenet_hfb_clear 707 * 708 * Clear Hardware Filter Block and disable all filtering. 709 */ 710 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index) 711 { 712 u32 base, i; 713 714 bcmgenet_hfb_set_filter_length(priv, f_index, 0); 715 base = f_index * priv->hw_params->hfb_filter_size; 716 for (i = 0; i < priv->hw_params->hfb_filter_size; i++) 717 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32)); 718 } 719 720 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 721 { 722 u32 i; 723 724 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 725 726 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) { 727 bcmgenet_hfb_reg_writel(priv, 0, 728 HFB_FLT_ENABLE_V3PLUS); 729 bcmgenet_hfb_reg_writel(priv, 0, 730 HFB_FLT_ENABLE_V3PLUS + 4); 731 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 732 bcmgenet_rdma_writel(priv, 0, i); 733 } 734 735 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++) 736 bcmgenet_hfb_clear_filter(priv, i); 737 738 /* Enable filter 0 to send default flow to ring 0 */ 739 bcmgenet_hfb_set_filter_length(priv, 0, 4); 740 bcmgenet_hfb_enable_filter(priv, 0); 741 } 742 743 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 744 { 745 int i; 746 747 INIT_LIST_HEAD(&priv->rxnfc_list); 748 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 749 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list); 750 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED; 751 } 752 753 bcmgenet_hfb_clear(priv); 754 } 755 756 static int bcmgenet_begin(struct net_device *dev) 757 { 758 struct bcmgenet_priv *priv = netdev_priv(dev); 759 760 /* Turn on the clock */ 761 return clk_prepare_enable(priv->clk); 762 } 763 764 static void bcmgenet_complete(struct net_device *dev) 765 { 766 struct bcmgenet_priv *priv = netdev_priv(dev); 767 768 /* Turn off the clock */ 769 clk_disable_unprepare(priv->clk); 770 } 771 772 static int bcmgenet_get_link_ksettings(struct net_device *dev, 773 struct ethtool_link_ksettings *cmd) 774 { 775 if (!netif_running(dev)) 776 return -EINVAL; 777 778 if (!dev->phydev) 779 return -ENODEV; 780 781 phy_ethtool_ksettings_get(dev->phydev, cmd); 782 783 return 0; 784 } 785 786 static int bcmgenet_set_link_ksettings(struct net_device *dev, 787 const struct ethtool_link_ksettings *cmd) 788 { 789 if (!netif_running(dev)) 790 return -EINVAL; 791 792 if (!dev->phydev) 793 return -ENODEV; 794 795 return phy_ethtool_ksettings_set(dev->phydev, cmd); 796 } 797 798 static int bcmgenet_set_features(struct net_device *dev, 799 netdev_features_t features) 800 { 801 struct bcmgenet_priv *priv = netdev_priv(dev); 802 u32 reg; 803 int ret; 804 805 ret = clk_prepare_enable(priv->clk); 806 if (ret) 807 return ret; 808 809 /* Make sure we reflect the value of CRC_CMD_FWD */ 810 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 811 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 812 813 clk_disable_unprepare(priv->clk); 814 815 return ret; 816 } 817 818 static u32 bcmgenet_get_msglevel(struct net_device *dev) 819 { 820 struct bcmgenet_priv *priv = netdev_priv(dev); 821 822 return priv->msg_enable; 823 } 824 825 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 826 { 827 struct bcmgenet_priv *priv = netdev_priv(dev); 828 829 priv->msg_enable = level; 830 } 831 832 static int bcmgenet_get_coalesce(struct net_device *dev, 833 struct ethtool_coalesce *ec, 834 struct kernel_ethtool_coalesce *kernel_coal, 835 struct netlink_ext_ack *extack) 836 { 837 struct bcmgenet_priv *priv = netdev_priv(dev); 838 struct bcmgenet_rx_ring *ring; 839 unsigned int i; 840 841 ec->tx_max_coalesced_frames = 842 bcmgenet_tdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH); 843 ec->rx_max_coalesced_frames = 844 bcmgenet_rdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH); 845 ec->rx_coalesce_usecs = 846 bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT) * 8192 / 1000; 847 848 for (i = 0; i <= priv->hw_params->rx_queues; i++) { 849 ring = &priv->rx_rings[i]; 850 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 851 } 852 853 return 0; 854 } 855 856 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 857 u32 usecs, u32 pkts) 858 { 859 struct bcmgenet_priv *priv = ring->priv; 860 unsigned int i = ring->index; 861 u32 reg; 862 863 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 864 865 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 866 reg &= ~DMA_TIMEOUT_MASK; 867 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 868 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 869 } 870 871 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 872 struct ethtool_coalesce *ec) 873 { 874 struct dim_cq_moder moder; 875 u32 usecs, pkts; 876 877 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 878 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 879 usecs = ring->rx_coalesce_usecs; 880 pkts = ring->rx_max_coalesced_frames; 881 882 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 883 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 884 usecs = moder.usec; 885 pkts = moder.pkts; 886 } 887 888 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 889 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 890 } 891 892 static int bcmgenet_set_coalesce(struct net_device *dev, 893 struct ethtool_coalesce *ec, 894 struct kernel_ethtool_coalesce *kernel_coal, 895 struct netlink_ext_ack *extack) 896 { 897 struct bcmgenet_priv *priv = netdev_priv(dev); 898 unsigned int i; 899 900 /* Base system clock is 125Mhz, DMA timeout is this reference clock 901 * divided by 1024, which yields roughly 8.192us, our maximum value 902 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 903 */ 904 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 905 ec->tx_max_coalesced_frames == 0 || 906 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 907 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 908 return -EINVAL; 909 910 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 911 return -EINVAL; 912 913 /* GENET TDMA hardware does not support a configurable timeout, but will 914 * always generate an interrupt either after MBDONE packets have been 915 * transmitted, or when the ring is empty. 916 */ 917 918 /* Program all TX queues with the same values, as there is no 919 * ethtool knob to do coalescing on a per-queue basis 920 */ 921 for (i = 0; i <= priv->hw_params->tx_queues; i++) 922 bcmgenet_tdma_ring_writel(priv, i, 923 ec->tx_max_coalesced_frames, 924 DMA_MBUF_DONE_THRESH); 925 926 for (i = 0; i <= priv->hw_params->rx_queues; i++) 927 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 928 929 return 0; 930 } 931 932 static void bcmgenet_get_pauseparam(struct net_device *dev, 933 struct ethtool_pauseparam *epause) 934 { 935 struct bcmgenet_priv *priv; 936 u32 umac_cmd; 937 938 priv = netdev_priv(dev); 939 940 epause->autoneg = priv->autoneg_pause; 941 942 if (netif_carrier_ok(dev)) { 943 /* report active state when link is up */ 944 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD); 945 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE); 946 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE); 947 } else { 948 /* otherwise report stored settings */ 949 epause->tx_pause = priv->tx_pause; 950 epause->rx_pause = priv->rx_pause; 951 } 952 } 953 954 static int bcmgenet_set_pauseparam(struct net_device *dev, 955 struct ethtool_pauseparam *epause) 956 { 957 struct bcmgenet_priv *priv = netdev_priv(dev); 958 959 if (!dev->phydev) 960 return -ENODEV; 961 962 if (!phy_validate_pause(dev->phydev, epause)) 963 return -EINVAL; 964 965 priv->autoneg_pause = !!epause->autoneg; 966 priv->tx_pause = !!epause->tx_pause; 967 priv->rx_pause = !!epause->rx_pause; 968 969 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 970 971 return 0; 972 } 973 974 /* standard ethtool support functions. */ 975 enum bcmgenet_stat_type { 976 BCMGENET_STAT_RTNL = -1, 977 BCMGENET_STAT_MIB_RX, 978 BCMGENET_STAT_MIB_TX, 979 BCMGENET_STAT_RUNT, 980 BCMGENET_STAT_MISC, 981 BCMGENET_STAT_SOFT, 982 BCMGENET_STAT_SOFT64, 983 }; 984 985 struct bcmgenet_stats { 986 char stat_string[ETH_GSTRING_LEN]; 987 int stat_sizeof; 988 int stat_offset; 989 enum bcmgenet_stat_type type; 990 /* reg offset from UMAC base for misc counters */ 991 u16 reg_offset; 992 /* sync for u64 stats counters */ 993 int syncp_offset; 994 }; 995 996 #define STAT_RTNL(m) { \ 997 .stat_string = __stringify(m), \ 998 .stat_sizeof = sizeof(((struct rtnl_link_stats64 *)0)->m), \ 999 .stat_offset = offsetof(struct rtnl_link_stats64, m), \ 1000 .type = BCMGENET_STAT_RTNL, \ 1001 } 1002 1003 #define STAT_GENET_MIB(str, m, _type) { \ 1004 .stat_string = str, \ 1005 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1006 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1007 .type = _type, \ 1008 } 1009 1010 #define STAT_GENET_SOFT_MIB64(str, s, m) { \ 1011 .stat_string = str, \ 1012 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->s.m), \ 1013 .stat_offset = offsetof(struct bcmgenet_priv, s.m), \ 1014 .type = BCMGENET_STAT_SOFT64, \ 1015 .syncp_offset = offsetof(struct bcmgenet_priv, s.syncp), \ 1016 } 1017 1018 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 1019 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 1020 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 1021 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 1022 1023 #define STAT_GENET_MISC(str, m, offset) { \ 1024 .stat_string = str, \ 1025 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1026 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1027 .type = BCMGENET_STAT_MISC, \ 1028 .reg_offset = offset, \ 1029 } 1030 1031 #define STAT_GENET_Q(num) \ 1032 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_packets", \ 1033 tx_rings[num].stats64, packets), \ 1034 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_bytes", \ 1035 tx_rings[num].stats64, bytes), \ 1036 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_errors", \ 1037 tx_rings[num].stats64, errors), \ 1038 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_dropped", \ 1039 tx_rings[num].stats64, dropped), \ 1040 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_bytes", \ 1041 rx_rings[num].stats64, bytes), \ 1042 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_packets", \ 1043 rx_rings[num].stats64, packets), \ 1044 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_errors", \ 1045 rx_rings[num].stats64, errors), \ 1046 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_dropped", \ 1047 rx_rings[num].stats64, dropped), \ 1048 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_multicast", \ 1049 rx_rings[num].stats64, multicast), \ 1050 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_missed", \ 1051 rx_rings[num].stats64, missed), \ 1052 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_length_errors", \ 1053 rx_rings[num].stats64, length_errors), \ 1054 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_over_errors", \ 1055 rx_rings[num].stats64, over_errors), \ 1056 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_crc_errors", \ 1057 rx_rings[num].stats64, crc_errors), \ 1058 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_frame_errors", \ 1059 rx_rings[num].stats64, frame_errors), \ 1060 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_fragmented_errors", \ 1061 rx_rings[num].stats64, fragmented_errors), \ 1062 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_broadcast", \ 1063 rx_rings[num].stats64, broadcast) 1064 1065 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 1066 * between the end of TX stats and the beginning of the RX RUNT 1067 */ 1068 #define BCMGENET_STAT_OFFSET 0xc 1069 1070 /* Hardware counters must be kept in sync because the order/offset 1071 * is important here (order in structure declaration = order in hardware) 1072 */ 1073 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 1074 /* general stats */ 1075 STAT_RTNL(rx_packets), 1076 STAT_RTNL(tx_packets), 1077 STAT_RTNL(rx_bytes), 1078 STAT_RTNL(tx_bytes), 1079 STAT_RTNL(rx_errors), 1080 STAT_RTNL(tx_errors), 1081 STAT_RTNL(rx_dropped), 1082 STAT_RTNL(tx_dropped), 1083 STAT_RTNL(multicast), 1084 STAT_RTNL(rx_missed_errors), 1085 STAT_RTNL(rx_length_errors), 1086 STAT_RTNL(rx_over_errors), 1087 STAT_RTNL(rx_crc_errors), 1088 STAT_RTNL(rx_frame_errors), 1089 /* UniMAC RSV counters */ 1090 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 1091 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 1092 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 1093 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 1094 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 1095 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 1096 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 1097 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 1098 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 1099 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 1100 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 1101 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 1102 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 1103 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 1104 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 1105 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 1106 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 1107 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 1108 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 1109 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 1110 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 1111 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 1112 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 1113 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 1114 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 1115 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 1116 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 1117 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 1118 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 1119 /* UniMAC TSV counters */ 1120 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 1121 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 1122 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 1123 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 1124 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 1125 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 1126 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 1127 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 1128 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 1129 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 1130 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 1131 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 1132 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 1133 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 1134 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 1135 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 1136 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 1137 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 1138 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 1139 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 1140 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 1141 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 1142 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 1143 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 1144 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 1145 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 1146 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 1147 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 1148 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 1149 /* UniMAC RUNT counters */ 1150 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 1151 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 1152 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 1153 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 1154 /* Misc UniMAC counters */ 1155 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 1156 UMAC_RBUF_OVFL_CNT_V1), 1157 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 1158 UMAC_RBUF_ERR_CNT_V1), 1159 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 1160 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 1161 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 1162 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 1163 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 1164 mib.tx_realloc_tsb_failed), 1165 /* Per TX queues */ 1166 STAT_GENET_Q(0), 1167 STAT_GENET_Q(1), 1168 STAT_GENET_Q(2), 1169 STAT_GENET_Q(3), 1170 STAT_GENET_Q(4), 1171 }; 1172 1173 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 1174 1175 #define BCMGENET_STATS64_ADD(stats, m, v) \ 1176 do { \ 1177 u64_stats_update_begin(&stats->syncp); \ 1178 u64_stats_add(&stats->m, v); \ 1179 u64_stats_update_end(&stats->syncp); \ 1180 } while (0) 1181 1182 #define BCMGENET_STATS64_INC(stats, m) \ 1183 do { \ 1184 u64_stats_update_begin(&stats->syncp); \ 1185 u64_stats_inc(&stats->m); \ 1186 u64_stats_update_end(&stats->syncp); \ 1187 } while (0) 1188 1189 static void bcmgenet_get_drvinfo(struct net_device *dev, 1190 struct ethtool_drvinfo *info) 1191 { 1192 strscpy(info->driver, "bcmgenet", sizeof(info->driver)); 1193 } 1194 1195 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 1196 { 1197 switch (string_set) { 1198 case ETH_SS_STATS: 1199 return BCMGENET_STATS_LEN; 1200 default: 1201 return -EOPNOTSUPP; 1202 } 1203 } 1204 1205 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 1206 u8 *data) 1207 { 1208 const char *str; 1209 int i; 1210 1211 switch (stringset) { 1212 case ETH_SS_STATS: 1213 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1214 str = bcmgenet_gstrings_stats[i].stat_string; 1215 ethtool_puts(&data, str); 1216 } 1217 break; 1218 } 1219 } 1220 1221 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 1222 { 1223 u16 new_offset; 1224 u32 val; 1225 1226 switch (offset) { 1227 case UMAC_RBUF_OVFL_CNT_V1: 1228 if (GENET_IS_V2(priv)) 1229 new_offset = RBUF_OVFL_CNT_V2; 1230 else 1231 new_offset = RBUF_OVFL_CNT_V3PLUS; 1232 1233 val = bcmgenet_rbuf_readl(priv, new_offset); 1234 /* clear if overflowed */ 1235 if (val == ~0) 1236 bcmgenet_rbuf_writel(priv, 0, new_offset); 1237 break; 1238 case UMAC_RBUF_ERR_CNT_V1: 1239 if (GENET_IS_V2(priv)) 1240 new_offset = RBUF_ERR_CNT_V2; 1241 else 1242 new_offset = RBUF_ERR_CNT_V3PLUS; 1243 1244 val = bcmgenet_rbuf_readl(priv, new_offset); 1245 /* clear if overflowed */ 1246 if (val == ~0) 1247 bcmgenet_rbuf_writel(priv, 0, new_offset); 1248 break; 1249 default: 1250 val = bcmgenet_umac_readl(priv, offset); 1251 /* clear if overflowed */ 1252 if (val == ~0) 1253 bcmgenet_umac_writel(priv, 0, offset); 1254 break; 1255 } 1256 1257 return val; 1258 } 1259 1260 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 1261 { 1262 int i, j = 0; 1263 1264 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1265 const struct bcmgenet_stats *s; 1266 u8 offset = 0; 1267 u32 val = 0; 1268 char *p; 1269 1270 s = &bcmgenet_gstrings_stats[i]; 1271 switch (s->type) { 1272 case BCMGENET_STAT_RTNL: 1273 case BCMGENET_STAT_SOFT: 1274 case BCMGENET_STAT_SOFT64: 1275 continue; 1276 case BCMGENET_STAT_RUNT: 1277 offset += BCMGENET_STAT_OFFSET; 1278 fallthrough; 1279 case BCMGENET_STAT_MIB_TX: 1280 offset += BCMGENET_STAT_OFFSET; 1281 fallthrough; 1282 case BCMGENET_STAT_MIB_RX: 1283 val = bcmgenet_umac_readl(priv, 1284 UMAC_MIB_START + j + offset); 1285 offset = 0; /* Reset Offset */ 1286 break; 1287 case BCMGENET_STAT_MISC: 1288 if (GENET_IS_V1(priv)) { 1289 val = bcmgenet_umac_readl(priv, s->reg_offset); 1290 /* clear if overflowed */ 1291 if (val == ~0) 1292 bcmgenet_umac_writel(priv, 0, 1293 s->reg_offset); 1294 } else { 1295 val = bcmgenet_update_stat_misc(priv, 1296 s->reg_offset); 1297 } 1298 break; 1299 } 1300 1301 j += s->stat_sizeof; 1302 p = (char *)priv + s->stat_offset; 1303 *(u32 *)p = val; 1304 } 1305 } 1306 1307 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 1308 struct ethtool_stats *stats, 1309 u64 *data) 1310 { 1311 struct bcmgenet_priv *priv = netdev_priv(dev); 1312 struct rtnl_link_stats64 stats64; 1313 struct u64_stats_sync *syncp; 1314 unsigned int start; 1315 int i; 1316 1317 if (netif_running(dev)) 1318 bcmgenet_update_mib_counters(priv); 1319 1320 dev_get_stats(dev, &stats64); 1321 1322 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1323 const struct bcmgenet_stats *s; 1324 char *p; 1325 1326 s = &bcmgenet_gstrings_stats[i]; 1327 p = (char *)priv; 1328 1329 if (s->type == BCMGENET_STAT_SOFT64) { 1330 syncp = (struct u64_stats_sync *)(p + s->syncp_offset); 1331 do { 1332 start = u64_stats_fetch_begin(syncp); 1333 data[i] = u64_stats_read((u64_stats_t *)(p + s->stat_offset)); 1334 } while (u64_stats_fetch_retry(syncp, start)); 1335 } else { 1336 if (s->type == BCMGENET_STAT_RTNL) 1337 p = (char *)&stats64; 1338 1339 p += s->stat_offset; 1340 if (sizeof(unsigned long) != sizeof(u32) && 1341 s->stat_sizeof == sizeof(unsigned long)) 1342 data[i] = *(unsigned long *)p; 1343 else 1344 data[i] = *(u32 *)p; 1345 } 1346 } 1347 } 1348 1349 void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1350 { 1351 struct bcmgenet_priv *priv = netdev_priv(dev); 1352 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1353 u32 reg; 1354 1355 if (enable && !priv->clk_eee_enabled) { 1356 clk_prepare_enable(priv->clk_eee); 1357 priv->clk_eee_enabled = true; 1358 } 1359 1360 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1361 if (enable) 1362 reg |= EEE_EN; 1363 else 1364 reg &= ~EEE_EN; 1365 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1366 1367 /* Enable EEE and switch to a 27Mhz clock automatically */ 1368 reg = bcmgenet_readl(priv->base + off); 1369 if (enable) 1370 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1371 else 1372 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1373 bcmgenet_writel(reg, priv->base + off); 1374 1375 /* RBUF EEE/PM can break the RX path on GENET. Keep it disabled. */ 1376 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1377 if (reg & (RBUF_EEE_EN | RBUF_PM_EN)) { 1378 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1379 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1380 } 1381 1382 if (!enable && priv->clk_eee_enabled) { 1383 clk_disable_unprepare(priv->clk_eee); 1384 priv->clk_eee_enabled = false; 1385 } 1386 1387 } 1388 1389 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_keee *e) 1390 { 1391 struct bcmgenet_priv *priv = netdev_priv(dev); 1392 int ret; 1393 1394 if (GENET_IS_V1(priv)) 1395 return -EOPNOTSUPP; 1396 1397 if (!dev->phydev) 1398 return -ENODEV; 1399 1400 ret = phy_ethtool_get_eee(dev->phydev, e); 1401 if (ret) 1402 return ret; 1403 1404 /* tx_lpi_timer is maintained by the MAC hardware register; the 1405 * PHY-level eee_cfg timer is not set for GENET. 1406 */ 1407 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1408 1409 return 0; 1410 } 1411 1412 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_keee *e) 1413 { 1414 struct bcmgenet_priv *priv = netdev_priv(dev); 1415 1416 if (GENET_IS_V1(priv)) 1417 return -EOPNOTSUPP; 1418 1419 if (!dev->phydev) 1420 return -ENODEV; 1421 1422 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1423 1424 return phy_ethtool_set_eee(dev->phydev, e); 1425 } 1426 1427 static int bcmgenet_validate_flow(struct net_device *dev, 1428 struct ethtool_rxnfc *cmd) 1429 { 1430 struct ethtool_usrip4_spec *l4_mask; 1431 struct ethhdr *eth_mask; 1432 1433 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES && 1434 cmd->fs.location != RX_CLS_LOC_ANY) { 1435 netdev_err(dev, "rxnfc: Invalid location (%d)\n", 1436 cmd->fs.location); 1437 return -EINVAL; 1438 } 1439 1440 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1441 case IP_USER_FLOW: 1442 l4_mask = &cmd->fs.m_u.usr_ip4_spec; 1443 /* don't allow mask which isn't valid */ 1444 if (VALIDATE_MASK(l4_mask->ip4src) || 1445 VALIDATE_MASK(l4_mask->ip4dst) || 1446 VALIDATE_MASK(l4_mask->l4_4_bytes) || 1447 VALIDATE_MASK(l4_mask->proto) || 1448 VALIDATE_MASK(l4_mask->ip_ver) || 1449 VALIDATE_MASK(l4_mask->tos)) { 1450 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1451 return -EINVAL; 1452 } 1453 break; 1454 case ETHER_FLOW: 1455 eth_mask = &cmd->fs.m_u.ether_spec; 1456 /* don't allow mask which isn't valid */ 1457 if (VALIDATE_MASK(eth_mask->h_dest) || 1458 VALIDATE_MASK(eth_mask->h_source) || 1459 VALIDATE_MASK(eth_mask->h_proto)) { 1460 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1461 return -EINVAL; 1462 } 1463 break; 1464 default: 1465 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n", 1466 cmd->fs.flow_type); 1467 return -EINVAL; 1468 } 1469 1470 if ((cmd->fs.flow_type & FLOW_EXT)) { 1471 /* don't allow mask which isn't valid */ 1472 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) || 1473 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) { 1474 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1475 return -EINVAL; 1476 } 1477 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) { 1478 netdev_err(dev, "rxnfc: user-def not supported\n"); 1479 return -EINVAL; 1480 } 1481 } 1482 1483 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) { 1484 /* don't allow mask which isn't valid */ 1485 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) { 1486 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1487 return -EINVAL; 1488 } 1489 } 1490 1491 return 0; 1492 } 1493 1494 static int bcmgenet_insert_flow(struct net_device *dev, 1495 struct ethtool_rxnfc *cmd) 1496 { 1497 struct bcmgenet_priv *priv = netdev_priv(dev); 1498 struct bcmgenet_rxnfc_rule *loc_rule; 1499 int err, i; 1500 1501 if (priv->hw_params->hfb_filter_size < 128) { 1502 netdev_err(dev, "rxnfc: Not supported by this device\n"); 1503 return -EINVAL; 1504 } 1505 1506 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues && 1507 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE && 1508 cmd->fs.ring_cookie != RX_CLS_FLOW_DISC) { 1509 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n", 1510 cmd->fs.ring_cookie); 1511 return -EINVAL; 1512 } 1513 1514 err = bcmgenet_validate_flow(dev, cmd); 1515 if (err) 1516 return err; 1517 1518 if (cmd->fs.location == RX_CLS_LOC_ANY) { 1519 list_for_each_entry(loc_rule, &priv->rxnfc_list, list) { 1520 cmd->fs.location = loc_rule->fs.location; 1521 err = memcmp(&loc_rule->fs, &cmd->fs, 1522 sizeof(struct ethtool_rx_flow_spec)); 1523 if (!err) 1524 /* rule exists so return current location */ 1525 return 0; 1526 } 1527 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1528 loc_rule = &priv->rxnfc_rules[i]; 1529 if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1530 cmd->fs.location = i; 1531 break; 1532 } 1533 } 1534 if (i == MAX_NUM_OF_FS_RULES) { 1535 cmd->fs.location = RX_CLS_LOC_ANY; 1536 return -ENOSPC; 1537 } 1538 } else { 1539 loc_rule = &priv->rxnfc_rules[cmd->fs.location]; 1540 } 1541 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1542 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1); 1543 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1544 list_del(&loc_rule->list); 1545 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1); 1546 } 1547 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1548 memcpy(&loc_rule->fs, &cmd->fs, 1549 sizeof(struct ethtool_rx_flow_spec)); 1550 1551 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule); 1552 1553 list_add_tail(&loc_rule->list, &priv->rxnfc_list); 1554 1555 return 0; 1556 } 1557 1558 static int bcmgenet_delete_flow(struct net_device *dev, 1559 struct ethtool_rxnfc *cmd) 1560 { 1561 struct bcmgenet_priv *priv = netdev_priv(dev); 1562 struct bcmgenet_rxnfc_rule *rule; 1563 int err = 0; 1564 1565 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1566 return -EINVAL; 1567 1568 rule = &priv->rxnfc_rules[cmd->fs.location]; 1569 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1570 err = -ENOENT; 1571 goto out; 1572 } 1573 1574 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1575 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1); 1576 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1577 list_del(&rule->list); 1578 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1); 1579 } 1580 rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1581 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec)); 1582 1583 out: 1584 return err; 1585 } 1586 1587 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1588 { 1589 struct bcmgenet_priv *priv = netdev_priv(dev); 1590 int err = 0; 1591 1592 switch (cmd->cmd) { 1593 case ETHTOOL_SRXCLSRLINS: 1594 err = bcmgenet_insert_flow(dev, cmd); 1595 break; 1596 case ETHTOOL_SRXCLSRLDEL: 1597 err = bcmgenet_delete_flow(dev, cmd); 1598 break; 1599 default: 1600 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n", 1601 cmd->cmd); 1602 return -EINVAL; 1603 } 1604 1605 return err; 1606 } 1607 1608 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1609 int loc) 1610 { 1611 struct bcmgenet_priv *priv = netdev_priv(dev); 1612 struct bcmgenet_rxnfc_rule *rule; 1613 int err = 0; 1614 1615 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1616 return -EINVAL; 1617 1618 rule = &priv->rxnfc_rules[loc]; 1619 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) 1620 err = -ENOENT; 1621 else 1622 memcpy(&cmd->fs, &rule->fs, 1623 sizeof(struct ethtool_rx_flow_spec)); 1624 1625 return err; 1626 } 1627 1628 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv) 1629 { 1630 struct list_head *pos; 1631 int res = 0; 1632 1633 list_for_each(pos, &priv->rxnfc_list) 1634 res++; 1635 1636 return res; 1637 } 1638 1639 static u32 bcmgenet_get_rx_ring_count(struct net_device *dev) 1640 { 1641 struct bcmgenet_priv *priv = netdev_priv(dev); 1642 1643 return priv->hw_params->rx_queues ?: 1; 1644 } 1645 1646 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1647 u32 *rule_locs) 1648 { 1649 struct bcmgenet_priv *priv = netdev_priv(dev); 1650 struct bcmgenet_rxnfc_rule *rule; 1651 int err = 0; 1652 int i = 0; 1653 1654 switch (cmd->cmd) { 1655 case ETHTOOL_GRXCLSRLCNT: 1656 cmd->rule_cnt = bcmgenet_get_num_flows(priv); 1657 cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL; 1658 break; 1659 case ETHTOOL_GRXCLSRULE: 1660 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location); 1661 break; 1662 case ETHTOOL_GRXCLSRLALL: 1663 list_for_each_entry(rule, &priv->rxnfc_list, list) 1664 if (i < cmd->rule_cnt) 1665 rule_locs[i++] = rule->fs.location; 1666 cmd->rule_cnt = i; 1667 cmd->data = MAX_NUM_OF_FS_RULES; 1668 break; 1669 default: 1670 err = -EOPNOTSUPP; 1671 break; 1672 } 1673 1674 return err; 1675 } 1676 1677 /* standard ethtool support functions. */ 1678 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1679 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1680 ETHTOOL_COALESCE_MAX_FRAMES | 1681 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1682 .begin = bcmgenet_begin, 1683 .complete = bcmgenet_complete, 1684 .get_strings = bcmgenet_get_strings, 1685 .get_sset_count = bcmgenet_get_sset_count, 1686 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1687 .get_drvinfo = bcmgenet_get_drvinfo, 1688 .get_link = ethtool_op_get_link, 1689 .get_msglevel = bcmgenet_get_msglevel, 1690 .set_msglevel = bcmgenet_set_msglevel, 1691 .get_wol = bcmgenet_get_wol, 1692 .set_wol = bcmgenet_set_wol, 1693 .get_eee = bcmgenet_get_eee, 1694 .set_eee = bcmgenet_set_eee, 1695 .nway_reset = phy_ethtool_nway_reset, 1696 .get_coalesce = bcmgenet_get_coalesce, 1697 .set_coalesce = bcmgenet_set_coalesce, 1698 .get_link_ksettings = bcmgenet_get_link_ksettings, 1699 .set_link_ksettings = bcmgenet_set_link_ksettings, 1700 .get_ts_info = ethtool_op_get_ts_info, 1701 .get_rxnfc = bcmgenet_get_rxnfc, 1702 .set_rxnfc = bcmgenet_set_rxnfc, 1703 .get_rx_ring_count = bcmgenet_get_rx_ring_count, 1704 .get_pauseparam = bcmgenet_get_pauseparam, 1705 .set_pauseparam = bcmgenet_set_pauseparam, 1706 }; 1707 1708 /* Power down the unimac, based on mode. */ 1709 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1710 enum bcmgenet_power_mode mode) 1711 { 1712 int ret = 0; 1713 u32 reg; 1714 1715 switch (mode) { 1716 case GENET_POWER_CABLE_SENSE: 1717 phy_detach(priv->dev->phydev); 1718 break; 1719 1720 case GENET_POWER_WOL_MAGIC: 1721 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1722 break; 1723 1724 case GENET_POWER_PASSIVE: 1725 /* Power down LED */ 1726 if (bcmgenet_has_ext(priv)) { 1727 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1728 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) 1729 reg |= EXT_PWR_DOWN_PHY_EN | 1730 EXT_PWR_DOWN_PHY_RD | 1731 EXT_PWR_DOWN_PHY_SD | 1732 EXT_PWR_DOWN_PHY_RX | 1733 EXT_PWR_DOWN_PHY_TX | 1734 EXT_IDDQ_GLBL_PWR; 1735 else 1736 reg |= EXT_PWR_DOWN_PHY; 1737 1738 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1739 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1740 1741 bcmgenet_phy_power_set(priv->dev, false); 1742 } 1743 break; 1744 default: 1745 break; 1746 } 1747 1748 return ret; 1749 } 1750 1751 static int bcmgenet_power_up(struct bcmgenet_priv *priv, 1752 enum bcmgenet_power_mode mode) 1753 { 1754 int ret = 0; 1755 u32 reg; 1756 1757 if (!bcmgenet_has_ext(priv)) 1758 return ret; 1759 1760 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1761 1762 switch (mode) { 1763 case GENET_POWER_PASSIVE: 1764 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS | 1765 EXT_ENERGY_DET_MASK); 1766 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) { 1767 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1768 EXT_PWR_DOWN_PHY_RD | 1769 EXT_PWR_DOWN_PHY_SD | 1770 EXT_PWR_DOWN_PHY_RX | 1771 EXT_PWR_DOWN_PHY_TX | 1772 EXT_IDDQ_GLBL_PWR); 1773 reg |= EXT_PHY_RESET; 1774 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1775 mdelay(1); 1776 1777 reg &= ~EXT_PHY_RESET; 1778 } else { 1779 reg &= ~EXT_PWR_DOWN_PHY; 1780 reg |= EXT_PWR_DN_EN_LD; 1781 } 1782 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1783 bcmgenet_phy_power_set(priv->dev, true); 1784 break; 1785 1786 case GENET_POWER_CABLE_SENSE: 1787 /* enable APD */ 1788 if (!GENET_IS_V5(priv)) { 1789 reg |= EXT_PWR_DN_EN_LD; 1790 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1791 } 1792 break; 1793 case GENET_POWER_WOL_MAGIC: 1794 ret = bcmgenet_wol_power_up_cfg(priv, mode); 1795 break; 1796 default: 1797 break; 1798 } 1799 1800 return ret; 1801 } 1802 1803 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1804 struct bcmgenet_tx_ring *ring) 1805 { 1806 struct enet_cb *tx_cb_ptr; 1807 1808 tx_cb_ptr = ring->cbs; 1809 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1810 1811 /* Advancing local write pointer */ 1812 if (ring->write_ptr == ring->end_ptr) 1813 ring->write_ptr = ring->cb_ptr; 1814 else 1815 ring->write_ptr++; 1816 1817 return tx_cb_ptr; 1818 } 1819 1820 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1821 struct bcmgenet_tx_ring *ring) 1822 { 1823 struct enet_cb *tx_cb_ptr; 1824 1825 /* Rewinding local write pointer */ 1826 if (ring->write_ptr == ring->cb_ptr) 1827 ring->write_ptr = ring->end_ptr; 1828 else 1829 ring->write_ptr--; 1830 1831 tx_cb_ptr = ring->cbs; 1832 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1833 1834 return tx_cb_ptr; 1835 } 1836 1837 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1838 { 1839 bcmgenet_intrl2_1_writel(ring->priv, 1840 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1841 INTRL2_CPU_MASK_SET); 1842 } 1843 1844 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1845 { 1846 bcmgenet_intrl2_1_writel(ring->priv, 1847 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1848 INTRL2_CPU_MASK_CLEAR); 1849 } 1850 1851 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1852 { 1853 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1854 INTRL2_CPU_MASK_CLEAR); 1855 } 1856 1857 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1858 { 1859 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1860 INTRL2_CPU_MASK_SET); 1861 } 1862 1863 /* Simple helper to free a transmit control block's resources 1864 * Returns an skb when the last transmit control block associated with the 1865 * skb is freed. The skb should be freed by the caller if necessary. 1866 */ 1867 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1868 struct enet_cb *cb) 1869 { 1870 struct sk_buff *skb; 1871 1872 skb = cb->skb; 1873 1874 if (skb) { 1875 cb->skb = NULL; 1876 if (cb == GENET_CB(skb)->first_cb) 1877 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1878 dma_unmap_len(cb, dma_len), 1879 DMA_TO_DEVICE); 1880 else 1881 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1882 dma_unmap_len(cb, dma_len), 1883 DMA_TO_DEVICE); 1884 dma_unmap_addr_set(cb, dma_addr, 0); 1885 1886 if (cb == GENET_CB(skb)->last_cb) 1887 return skb; 1888 1889 } else if (dma_unmap_addr(cb, dma_addr)) { 1890 dma_unmap_page(dev, 1891 dma_unmap_addr(cb, dma_addr), 1892 dma_unmap_len(cb, dma_len), 1893 DMA_TO_DEVICE); 1894 dma_unmap_addr_set(cb, dma_addr, 0); 1895 } 1896 1897 return NULL; 1898 } 1899 1900 /* Simple helper to free a receive control block's resources */ 1901 static void bcmgenet_free_rx_cb(struct enet_cb *cb, 1902 struct page_pool *pool) 1903 { 1904 if (cb->rx_page) { 1905 page_pool_put_full_page(pool, cb->rx_page, false); 1906 cb->rx_page = NULL; 1907 } 1908 } 1909 1910 /* Unlocked version of the reclaim routine */ 1911 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1912 struct bcmgenet_tx_ring *ring) 1913 { 1914 struct bcmgenet_tx_stats64 *stats = &ring->stats64; 1915 struct bcmgenet_priv *priv = netdev_priv(dev); 1916 unsigned int txbds_processed = 0; 1917 unsigned int bytes_compl = 0; 1918 unsigned int pkts_compl = 0; 1919 unsigned int txbds_ready; 1920 unsigned int c_index; 1921 struct sk_buff *skb; 1922 1923 /* Clear status before servicing to reduce spurious interrupts */ 1924 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), INTRL2_CPU_CLEAR); 1925 1926 /* Compute how many buffers are transmitted since last xmit call */ 1927 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1928 & DMA_C_INDEX_MASK; 1929 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1930 1931 netif_dbg(priv, tx_done, dev, 1932 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1933 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1934 1935 /* Reclaim transmitted buffers */ 1936 while (txbds_processed < txbds_ready) { 1937 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1938 &priv->tx_cbs[ring->clean_ptr]); 1939 if (skb) { 1940 pkts_compl++; 1941 bytes_compl += GENET_CB(skb)->bytes_sent; 1942 dev_consume_skb_any(skb); 1943 } 1944 1945 txbds_processed++; 1946 if (likely(ring->clean_ptr < ring->end_ptr)) 1947 ring->clean_ptr++; 1948 else 1949 ring->clean_ptr = ring->cb_ptr; 1950 } 1951 1952 ring->free_bds += txbds_processed; 1953 ring->c_index = c_index; 1954 1955 u64_stats_update_begin(&stats->syncp); 1956 u64_stats_add(&stats->packets, pkts_compl); 1957 u64_stats_add(&stats->bytes, bytes_compl); 1958 u64_stats_update_end(&stats->syncp); 1959 1960 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->index), 1961 pkts_compl, bytes_compl); 1962 1963 return txbds_processed; 1964 } 1965 1966 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1967 struct bcmgenet_tx_ring *ring, 1968 bool all) 1969 { 1970 struct bcmgenet_priv *priv = netdev_priv(dev); 1971 struct device *kdev = &priv->pdev->dev; 1972 unsigned int released, drop, wr_ptr; 1973 struct enet_cb *cb_ptr; 1974 struct sk_buff *skb; 1975 1976 spin_lock_bh(&ring->lock); 1977 released = __bcmgenet_tx_reclaim(dev, ring); 1978 if (all) { 1979 skb = NULL; 1980 drop = (ring->prod_index - ring->c_index) & DMA_C_INDEX_MASK; 1981 released += drop; 1982 ring->prod_index = ring->c_index & DMA_C_INDEX_MASK; 1983 ring->free_bds += drop; 1984 while (drop--) { 1985 cb_ptr = bcmgenet_put_txcb(priv, ring); 1986 skb = cb_ptr->skb; 1987 bcmgenet_free_tx_cb(kdev, cb_ptr); 1988 if (skb && cb_ptr == GENET_CB(skb)->first_cb) { 1989 dev_consume_skb_any(skb); 1990 skb = NULL; 1991 } 1992 } 1993 if (skb) 1994 dev_consume_skb_any(skb); 1995 netdev_tx_reset_queue(netdev_get_tx_queue(dev, ring->index)); 1996 bcmgenet_tdma_ring_writel(priv, ring->index, 1997 ring->prod_index, TDMA_PROD_INDEX); 1998 wr_ptr = ring->write_ptr * WORDS_PER_BD(priv); 1999 bcmgenet_tdma_ring_writel(priv, ring->index, wr_ptr, 2000 TDMA_WRITE_PTR); 2001 } 2002 spin_unlock_bh(&ring->lock); 2003 2004 return released; 2005 } 2006 2007 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 2008 { 2009 struct bcmgenet_tx_ring *ring = 2010 container_of(napi, struct bcmgenet_tx_ring, napi); 2011 unsigned int work_done = 0; 2012 struct netdev_queue *txq; 2013 2014 spin_lock(&ring->lock); 2015 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 2016 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 2017 txq = netdev_get_tx_queue(ring->priv->dev, ring->index); 2018 netif_tx_wake_queue(txq); 2019 } 2020 spin_unlock(&ring->lock); 2021 2022 if (work_done == 0) { 2023 napi_complete(napi); 2024 bcmgenet_tx_ring_int_enable(ring); 2025 2026 return 0; 2027 } 2028 2029 return budget; 2030 } 2031 2032 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 2033 { 2034 struct bcmgenet_priv *priv = netdev_priv(dev); 2035 int i = 0; 2036 2037 do { 2038 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i++], true); 2039 } while (i <= priv->hw_params->tx_queues && netif_is_multiqueue(dev)); 2040 } 2041 2042 /* Reallocate the SKB to put enough headroom in front of it and insert 2043 * the transmit checksum offsets in the descriptors 2044 */ 2045 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 2046 struct sk_buff *skb, 2047 struct bcmgenet_tx_ring *ring) 2048 { 2049 struct bcmgenet_tx_stats64 *stats = &ring->stats64; 2050 struct bcmgenet_priv *priv = netdev_priv(dev); 2051 struct status_64 *status = NULL; 2052 struct sk_buff *new_skb; 2053 u16 offset; 2054 u8 ip_proto; 2055 __be16 ip_ver; 2056 u32 tx_csum_info; 2057 2058 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 2059 /* If 64 byte status block enabled, must make sure skb has 2060 * enough headroom for us to insert 64B status block. 2061 */ 2062 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 2063 if (!new_skb) { 2064 dev_kfree_skb_any(skb); 2065 priv->mib.tx_realloc_tsb_failed++; 2066 BCMGENET_STATS64_INC(stats, dropped); 2067 return NULL; 2068 } 2069 dev_consume_skb_any(skb); 2070 skb = new_skb; 2071 priv->mib.tx_realloc_tsb++; 2072 } 2073 2074 skb_push(skb, sizeof(*status)); 2075 status = (struct status_64 *)skb->data; 2076 2077 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2078 ip_ver = skb->protocol; 2079 switch (ip_ver) { 2080 case htons(ETH_P_IP): 2081 ip_proto = ip_hdr(skb)->protocol; 2082 break; 2083 case htons(ETH_P_IPV6): 2084 ip_proto = ipv6_hdr(skb)->nexthdr; 2085 break; 2086 default: 2087 /* don't use UDP flag */ 2088 ip_proto = 0; 2089 break; 2090 } 2091 2092 offset = skb_checksum_start_offset(skb) - sizeof(*status); 2093 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 2094 (offset + skb->csum_offset) | 2095 STATUS_TX_CSUM_LV; 2096 2097 /* Set the special UDP flag for UDP */ 2098 if (ip_proto == IPPROTO_UDP) 2099 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 2100 2101 status->tx_csum_info = tx_csum_info; 2102 } 2103 2104 return skb; 2105 } 2106 2107 static void bcmgenet_hide_tsb(struct sk_buff *skb) 2108 { 2109 __skb_pull(skb, sizeof(struct status_64)); 2110 } 2111 2112 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 2113 { 2114 struct bcmgenet_priv *priv = netdev_priv(dev); 2115 struct device *kdev = &priv->pdev->dev; 2116 struct bcmgenet_tx_ring *ring = NULL; 2117 struct enet_cb *tx_cb_ptr; 2118 struct netdev_queue *txq; 2119 int nr_frags, index; 2120 dma_addr_t mapping; 2121 unsigned int size; 2122 skb_frag_t *frag; 2123 u32 len_stat; 2124 int ret; 2125 int i; 2126 2127 index = skb_get_queue_mapping(skb); 2128 ring = &priv->tx_rings[index]; 2129 txq = netdev_get_tx_queue(dev, index); 2130 2131 nr_frags = skb_shinfo(skb)->nr_frags; 2132 2133 spin_lock(&ring->lock); 2134 if (ring->free_bds <= (nr_frags + 1)) { 2135 if (!netif_tx_queue_stopped(txq)) 2136 netif_tx_stop_queue(txq); 2137 ret = NETDEV_TX_BUSY; 2138 goto out; 2139 } 2140 2141 /* Retain how many bytes will be sent on the wire, without TSB inserted 2142 * by transmit checksum offload 2143 */ 2144 GENET_CB(skb)->bytes_sent = skb->len; 2145 2146 /* add the Transmit Status Block */ 2147 skb = bcmgenet_add_tsb(dev, skb, ring); 2148 if (!skb) { 2149 ret = NETDEV_TX_OK; 2150 goto out; 2151 } 2152 2153 for (i = 0; i <= nr_frags; i++) { 2154 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 2155 2156 BUG_ON(!tx_cb_ptr); 2157 2158 if (!i) { 2159 /* Transmit single SKB or head of fragment list */ 2160 GENET_CB(skb)->first_cb = tx_cb_ptr; 2161 size = skb_headlen(skb); 2162 mapping = dma_map_single(kdev, skb->data, size, 2163 DMA_TO_DEVICE); 2164 } else { 2165 /* xmit fragment */ 2166 frag = &skb_shinfo(skb)->frags[i - 1]; 2167 size = skb_frag_size(frag); 2168 mapping = skb_frag_dma_map(kdev, frag, 0, size, 2169 DMA_TO_DEVICE); 2170 } 2171 2172 ret = dma_mapping_error(kdev, mapping); 2173 if (ret) { 2174 priv->mib.tx_dma_failed++; 2175 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 2176 ret = NETDEV_TX_OK; 2177 goto out_unmap_frags; 2178 } 2179 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 2180 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 2181 2182 tx_cb_ptr->skb = skb; 2183 2184 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 2185 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 2186 2187 /* Note: if we ever change from DMA_TX_APPEND_CRC below we 2188 * will need to restore software padding of "runt" packets 2189 */ 2190 len_stat |= DMA_TX_APPEND_CRC; 2191 2192 if (!i) { 2193 len_stat |= DMA_SOP; 2194 if (skb->ip_summed == CHECKSUM_PARTIAL) 2195 len_stat |= DMA_TX_DO_CSUM; 2196 } 2197 if (i == nr_frags) 2198 len_stat |= DMA_EOP; 2199 2200 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 2201 } 2202 2203 GENET_CB(skb)->last_cb = tx_cb_ptr; 2204 2205 bcmgenet_hide_tsb(skb); 2206 skb_tx_timestamp(skb); 2207 2208 /* Decrement total BD count and advance our write pointer */ 2209 ring->free_bds -= nr_frags + 1; 2210 ring->prod_index += nr_frags + 1; 2211 ring->prod_index &= DMA_P_INDEX_MASK; 2212 2213 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 2214 2215 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 2216 netif_tx_stop_queue(txq); 2217 2218 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 2219 /* Packets are ready, update producer index */ 2220 bcmgenet_tdma_ring_writel(priv, ring->index, 2221 ring->prod_index, TDMA_PROD_INDEX); 2222 out: 2223 spin_unlock(&ring->lock); 2224 2225 return ret; 2226 2227 out_unmap_frags: 2228 /* Back up for failed control block mapping */ 2229 bcmgenet_put_txcb(priv, ring); 2230 2231 /* Unmap successfully mapped control blocks */ 2232 while (i-- > 0) { 2233 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 2234 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 2235 } 2236 2237 dev_kfree_skb(skb); 2238 goto out; 2239 } 2240 2241 static int bcmgenet_rx_refill(struct bcmgenet_rx_ring *ring, 2242 struct enet_cb *cb) 2243 { 2244 struct bcmgenet_priv *priv = ring->priv; 2245 dma_addr_t mapping; 2246 struct page *page; 2247 2248 page = page_pool_alloc_pages(ring->page_pool, 2249 GFP_ATOMIC); 2250 if (!page) { 2251 priv->mib.alloc_rx_buff_failed++; 2252 netif_err(priv, rx_err, priv->dev, 2253 "%s: Rx page allocation failed\n", __func__); 2254 return -ENOMEM; 2255 } 2256 2257 /* page_pool handles DMA mapping via PP_FLAG_DMA_MAP */ 2258 mapping = page_pool_get_dma_addr(page); 2259 2260 cb->rx_page = page; 2261 dmadesc_set_addr(priv, cb->bd_addr, mapping); 2262 2263 return 0; 2264 } 2265 2266 /* bcmgenet_desc_rx - descriptor based rx process. 2267 * this could be called from bottom half, or from NAPI polling method. 2268 */ 2269 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 2270 unsigned int budget) 2271 { 2272 struct bcmgenet_rx_stats64 *stats = &ring->stats64; 2273 struct bcmgenet_priv *priv = ring->priv; 2274 struct net_device *dev = priv->dev; 2275 struct enet_cb *cb; 2276 struct sk_buff *skb; 2277 u32 dma_length_status; 2278 unsigned long dma_flag; 2279 int len; 2280 unsigned int rxpktprocessed = 0, rxpkttoprocess; 2281 unsigned int bytes_processed = 0; 2282 unsigned int p_index, mask; 2283 unsigned int discards; 2284 2285 /* Clear status before servicing to reduce spurious interrupts */ 2286 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 2287 bcmgenet_intrl2_1_writel(priv, mask, INTRL2_CPU_CLEAR); 2288 2289 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 2290 2291 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 2292 DMA_P_INDEX_DISCARD_CNT_MASK; 2293 if (discards > ring->old_discards) { 2294 discards = discards - ring->old_discards; 2295 BCMGENET_STATS64_ADD(stats, missed, discards); 2296 ring->old_discards += discards; 2297 2298 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 2299 if (ring->old_discards >= 0xC000) { 2300 ring->old_discards = 0; 2301 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 2302 RDMA_PROD_INDEX); 2303 } 2304 } 2305 2306 p_index &= DMA_P_INDEX_MASK; 2307 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 2308 2309 netif_dbg(priv, rx_status, dev, 2310 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 2311 2312 while ((rxpktprocessed < rxpkttoprocess) && 2313 (rxpktprocessed < budget)) { 2314 struct status_64 *status; 2315 struct page *rx_page; 2316 void *hard_start; 2317 __be16 rx_csum; 2318 2319 cb = &priv->rx_cbs[ring->read_ptr]; 2320 2321 /* Save the received page before refilling */ 2322 rx_page = cb->rx_page; 2323 2324 if (bcmgenet_rx_refill(ring, cb)) { 2325 BCMGENET_STATS64_INC(stats, dropped); 2326 goto next; 2327 } 2328 2329 /* Sync the full buffer; the HW may have written anywhere 2330 * up to RX_BUF_LENGTH. 2331 */ 2332 page_pool_dma_sync_for_cpu(ring->page_pool, rx_page, 0, 2333 RX_BUF_LENGTH); 2334 2335 hard_start = page_address(rx_page); 2336 status = (struct status_64 *)hard_start; 2337 dma_length_status = status->length_status; 2338 2339 /* DMA flags and length are still valid no matter how 2340 * we got the Receive Status Vector (64B RSB or register) 2341 */ 2342 dma_flag = dma_length_status & 0xffff; 2343 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 2344 2345 netif_dbg(priv, rx_status, dev, 2346 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 2347 __func__, p_index, ring->c_index, 2348 ring->read_ptr, dma_length_status); 2349 2350 /* Reject lengths that would underflow the SKB build path. */ 2351 if (unlikely(len > RX_BUF_LENGTH || len < GENET_RSB_PAD)) { 2352 netif_err(priv, rx_status, dev, 2353 "invalid packet length %d\n", len); 2354 BCMGENET_STATS64_INC(stats, length_errors); 2355 page_pool_put_full_page(ring->page_pool, rx_page, 2356 true); 2357 goto next; 2358 } 2359 2360 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 2361 netif_err(priv, rx_status, dev, 2362 "dropping fragmented packet!\n"); 2363 BCMGENET_STATS64_INC(stats, fragmented_errors); 2364 page_pool_put_full_page(ring->page_pool, rx_page, 2365 true); 2366 goto next; 2367 } 2368 2369 /* report errors */ 2370 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 2371 DMA_RX_OV | 2372 DMA_RX_NO | 2373 DMA_RX_LG | 2374 DMA_RX_RXER))) { 2375 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 2376 (unsigned int)dma_flag); 2377 u64_stats_update_begin(&stats->syncp); 2378 if (dma_flag & DMA_RX_CRC_ERROR) 2379 u64_stats_inc(&stats->crc_errors); 2380 if (dma_flag & DMA_RX_OV) 2381 u64_stats_inc(&stats->over_errors); 2382 if (dma_flag & DMA_RX_NO) 2383 u64_stats_inc(&stats->frame_errors); 2384 if (dma_flag & DMA_RX_LG) 2385 u64_stats_inc(&stats->length_errors); 2386 if ((dma_flag & (DMA_RX_CRC_ERROR | 2387 DMA_RX_OV | 2388 DMA_RX_NO | 2389 DMA_RX_LG | 2390 DMA_RX_RXER)) == DMA_RX_RXER) 2391 u64_stats_inc(&stats->errors); 2392 u64_stats_update_end(&stats->syncp); 2393 page_pool_put_full_page(ring->page_pool, rx_page, 2394 true); 2395 goto next; 2396 } /* error packet */ 2397 2398 /* Build SKB from the page - data starts at hard_start, 2399 * frame begins after RSB(64) + pad(2) = 66 bytes. 2400 */ 2401 skb = napi_build_skb(hard_start, PAGE_SIZE); 2402 if (unlikely(!skb)) { 2403 BCMGENET_STATS64_INC(stats, dropped); 2404 page_pool_put_full_page(ring->page_pool, rx_page, 2405 true); 2406 goto next; 2407 } 2408 2409 skb_mark_for_recycle(skb); 2410 2411 /* Reserve the RSB + pad, then set the data length */ 2412 skb_reserve(skb, GENET_RSB_PAD); 2413 __skb_put(skb, len - GENET_RSB_PAD); 2414 2415 if (priv->crc_fwd_en) { 2416 skb_trim(skb, skb->len - ETH_FCS_LEN); 2417 } 2418 2419 /* Set up checksum offload */ 2420 if (dev->features & NETIF_F_RXCSUM) { 2421 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 2422 if (rx_csum) { 2423 skb->csum = (__force __wsum)ntohs(rx_csum); 2424 skb->ip_summed = CHECKSUM_COMPLETE; 2425 } 2426 } 2427 2428 len = skb->len; 2429 bytes_processed += len; 2430 2431 /*Finish setting up the received SKB and send it to the kernel*/ 2432 skb->protocol = eth_type_trans(skb, priv->dev); 2433 2434 u64_stats_update_begin(&stats->syncp); 2435 u64_stats_inc(&stats->packets); 2436 u64_stats_add(&stats->bytes, len); 2437 if (dma_flag & DMA_RX_MULT) 2438 u64_stats_inc(&stats->multicast); 2439 else if (dma_flag & DMA_RX_BRDCAST) 2440 u64_stats_inc(&stats->broadcast); 2441 u64_stats_update_end(&stats->syncp); 2442 2443 /* Notify kernel */ 2444 napi_gro_receive(&ring->napi, skb); 2445 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 2446 2447 next: 2448 rxpktprocessed++; 2449 if (likely(ring->read_ptr < ring->end_ptr)) 2450 ring->read_ptr++; 2451 else 2452 ring->read_ptr = ring->cb_ptr; 2453 2454 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 2455 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 2456 } 2457 2458 ring->dim.bytes = bytes_processed; 2459 ring->dim.packets = rxpktprocessed; 2460 2461 return rxpktprocessed; 2462 } 2463 2464 /* Rx NAPI polling method */ 2465 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 2466 { 2467 struct bcmgenet_rx_ring *ring = container_of(napi, 2468 struct bcmgenet_rx_ring, napi); 2469 struct dim_sample dim_sample = {}; 2470 unsigned int work_done; 2471 2472 work_done = bcmgenet_desc_rx(ring, budget); 2473 2474 if (work_done < budget && napi_complete_done(napi, work_done)) 2475 bcmgenet_rx_ring_int_enable(ring); 2476 2477 if (ring->dim.use_dim) { 2478 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 2479 ring->dim.bytes, &dim_sample); 2480 net_dim(&ring->dim.dim, &dim_sample); 2481 } 2482 2483 return work_done; 2484 } 2485 2486 static void bcmgenet_dim_work(struct work_struct *work) 2487 { 2488 struct dim *dim = container_of(work, struct dim, work); 2489 struct bcmgenet_net_dim *ndim = 2490 container_of(dim, struct bcmgenet_net_dim, dim); 2491 struct bcmgenet_rx_ring *ring = 2492 container_of(ndim, struct bcmgenet_rx_ring, dim); 2493 struct dim_cq_moder cur_profile = 2494 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 2495 2496 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 2497 dim->state = DIM_START_MEASURE; 2498 } 2499 2500 /* Assign page_pool pages to RX DMA descriptors. */ 2501 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 2502 struct bcmgenet_rx_ring *ring) 2503 { 2504 struct enet_cb *cb; 2505 int i; 2506 2507 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2508 2509 /* loop here for each buffer needing assign */ 2510 for (i = 0; i < ring->size; i++) { 2511 cb = ring->cbs + i; 2512 if (bcmgenet_rx_refill(ring, cb)) 2513 return -ENOMEM; 2514 } 2515 2516 return 0; 2517 } 2518 2519 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 2520 { 2521 struct bcmgenet_rx_ring *ring; 2522 struct enet_cb *cb; 2523 int q, i; 2524 2525 for (q = 0; q <= priv->hw_params->rx_queues; q++) { 2526 ring = &priv->rx_rings[q]; 2527 if (!ring->page_pool) 2528 continue; 2529 for (i = 0; i < ring->size; i++) { 2530 cb = ring->cbs + i; 2531 bcmgenet_free_rx_cb(cb, ring->page_pool); 2532 } 2533 } 2534 } 2535 2536 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 2537 { 2538 u32 reg; 2539 2540 spin_lock_bh(&priv->reg_lock); 2541 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2542 if (reg & CMD_SW_RESET) { 2543 spin_unlock_bh(&priv->reg_lock); 2544 return; 2545 } 2546 if (enable) 2547 reg |= mask; 2548 else 2549 reg &= ~mask; 2550 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2551 spin_unlock_bh(&priv->reg_lock); 2552 2553 /* UniMAC stops on a packet boundary, wait for a full-size packet 2554 * to be processed 2555 */ 2556 if (enable == 0) 2557 usleep_range(1000, 2000); 2558 } 2559 2560 static void reset_umac(struct bcmgenet_priv *priv) 2561 { 2562 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 2563 bcmgenet_rbuf_ctrl_set(priv, 0); 2564 udelay(10); 2565 2566 /* issue soft reset and disable MAC while updating its registers */ 2567 spin_lock_bh(&priv->reg_lock); 2568 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 2569 udelay(2); 2570 spin_unlock_bh(&priv->reg_lock); 2571 } 2572 2573 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2574 { 2575 /* Mask all interrupts.*/ 2576 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2577 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2578 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2579 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2580 } 2581 2582 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2583 { 2584 u32 int0_enable = 0; 2585 2586 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2587 * and MoCA PHY 2588 */ 2589 if (priv->internal_phy) { 2590 int0_enable |= UMAC_IRQ_LINK_EVENT; 2591 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2592 int0_enable |= UMAC_IRQ_PHY_DET_R; 2593 } else if (priv->ext_phy) { 2594 int0_enable |= UMAC_IRQ_LINK_EVENT; 2595 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2596 if (bcmgenet_has_moca_link_det(priv)) 2597 int0_enable |= UMAC_IRQ_LINK_EVENT; 2598 } 2599 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2600 } 2601 2602 static void init_umac(struct bcmgenet_priv *priv) 2603 { 2604 struct device *kdev = &priv->pdev->dev; 2605 u32 reg; 2606 u32 int0_enable = 0; 2607 2608 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2609 2610 reset_umac(priv); 2611 2612 /* clear tx/rx counter */ 2613 bcmgenet_umac_writel(priv, 2614 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2615 UMAC_MIB_CTRL); 2616 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2617 2618 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2619 2620 /* init tx registers, enable TSB */ 2621 reg = bcmgenet_tbuf_ctrl_get(priv); 2622 reg |= TBUF_64B_EN; 2623 bcmgenet_tbuf_ctrl_set(priv, reg); 2624 2625 /* init rx registers, enable ip header optimization and RSB */ 2626 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2627 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 2628 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2629 2630 /* enable rx checksumming */ 2631 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 2632 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 2633 /* If UniMAC forwards CRC, we need to skip over it to get 2634 * a valid CHK bit to be set in the per-packet status word 2635 */ 2636 if (priv->crc_fwd_en) 2637 reg |= RBUF_SKIP_FCS; 2638 else 2639 reg &= ~RBUF_SKIP_FCS; 2640 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 2641 2642 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2643 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2644 2645 bcmgenet_intr_disable(priv); 2646 2647 /* Configure backpressure vectors for MoCA */ 2648 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2649 reg = bcmgenet_bp_mc_get(priv); 2650 reg |= BIT(priv->hw_params->bp_in_en_shift); 2651 2652 /* bp_mask: back pressure mask */ 2653 if (netif_is_multiqueue(priv->dev)) 2654 reg |= priv->hw_params->bp_in_mask; 2655 else 2656 reg &= ~priv->hw_params->bp_in_mask; 2657 bcmgenet_bp_mc_set(priv, reg); 2658 } 2659 2660 /* Enable MDIO interrupts on GENET v3+ */ 2661 if (bcmgenet_has_mdio_intr(priv)) 2662 int0_enable |= UMAC_IRQ_MDIO_EVENT; 2663 2664 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2665 2666 dev_dbg(kdev, "done init umac\n"); 2667 } 2668 2669 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2670 void (*cb)(struct work_struct *work)) 2671 { 2672 struct bcmgenet_net_dim *dim = &ring->dim; 2673 2674 INIT_WORK(&dim->dim.work, cb); 2675 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2676 dim->event_ctr = 0; 2677 dim->packets = 0; 2678 dim->bytes = 0; 2679 } 2680 2681 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2682 { 2683 struct bcmgenet_net_dim *dim = &ring->dim; 2684 struct dim_cq_moder moder; 2685 u32 usecs, pkts; 2686 2687 usecs = ring->rx_coalesce_usecs; 2688 pkts = ring->rx_max_coalesced_frames; 2689 2690 /* If DIM was enabled, re-apply default parameters */ 2691 if (dim->use_dim) { 2692 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2693 usecs = moder.usec; 2694 pkts = moder.pkts; 2695 } 2696 2697 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2698 } 2699 2700 /* Initialize a Tx ring along with corresponding hardware registers */ 2701 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2702 unsigned int index, unsigned int size, 2703 unsigned int start_ptr, unsigned int end_ptr) 2704 { 2705 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2706 u32 words_per_bd = WORDS_PER_BD(priv); 2707 u32 flow_period_val = 0; 2708 2709 spin_lock_init(&ring->lock); 2710 ring->priv = priv; 2711 ring->index = index; 2712 ring->cbs = priv->tx_cbs + start_ptr; 2713 ring->size = size; 2714 ring->clean_ptr = start_ptr; 2715 ring->c_index = 0; 2716 ring->free_bds = size; 2717 ring->write_ptr = start_ptr; 2718 ring->cb_ptr = start_ptr; 2719 ring->end_ptr = end_ptr - 1; 2720 ring->prod_index = 0; 2721 2722 /* Set flow period for ring != 0 */ 2723 if (index) 2724 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2725 2726 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2727 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2728 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2729 /* Disable rate control for now */ 2730 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2731 TDMA_FLOW_PERIOD); 2732 bcmgenet_tdma_ring_writel(priv, index, 2733 ((size << DMA_RING_SIZE_SHIFT) | 2734 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2735 2736 /* Set start and end address, read and write pointers */ 2737 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2738 DMA_START_ADDR); 2739 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2740 TDMA_READ_PTR); 2741 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2742 TDMA_WRITE_PTR); 2743 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2744 DMA_END_ADDR); 2745 2746 /* Initialize Tx NAPI */ 2747 netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll); 2748 } 2749 2750 static int bcmgenet_rx_ring_create_pool(struct bcmgenet_priv *priv, 2751 struct bcmgenet_rx_ring *ring) 2752 { 2753 struct page_pool_params pp_params = { 2754 .order = 0, 2755 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 2756 .pool_size = ring->size, 2757 .nid = NUMA_NO_NODE, 2758 .dev = &priv->pdev->dev, 2759 .dma_dir = DMA_FROM_DEVICE, 2760 .max_len = RX_BUF_LENGTH, 2761 }; 2762 int err; 2763 2764 ring->page_pool = page_pool_create(&pp_params); 2765 if (IS_ERR(ring->page_pool)) { 2766 err = PTR_ERR(ring->page_pool); 2767 ring->page_pool = NULL; 2768 return err; 2769 } 2770 2771 return 0; 2772 } 2773 2774 /* Initialize a RDMA ring */ 2775 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2776 unsigned int index, unsigned int size, 2777 unsigned int start_ptr, unsigned int end_ptr) 2778 { 2779 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2780 u32 words_per_bd = WORDS_PER_BD(priv); 2781 int ret, i; 2782 2783 ring->priv = priv; 2784 ring->index = index; 2785 ring->cbs = priv->rx_cbs + start_ptr; 2786 ring->size = size; 2787 ring->c_index = 0; 2788 ring->read_ptr = start_ptr; 2789 ring->cb_ptr = start_ptr; 2790 ring->end_ptr = end_ptr - 1; 2791 2792 ret = bcmgenet_rx_ring_create_pool(priv, ring); 2793 if (ret) 2794 return ret; 2795 2796 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2797 if (ret) { 2798 for (i = 0; i < ring->size; i++) 2799 bcmgenet_free_rx_cb(ring->cbs + i, ring->page_pool); 2800 page_pool_destroy(ring->page_pool); 2801 ring->page_pool = NULL; 2802 return ret; 2803 } 2804 2805 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2806 bcmgenet_init_rx_coalesce(ring); 2807 2808 /* Initialize Rx NAPI */ 2809 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll); 2810 2811 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2812 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2813 bcmgenet_rdma_ring_writel(priv, index, 2814 ((size << DMA_RING_SIZE_SHIFT) | 2815 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2816 bcmgenet_rdma_ring_writel(priv, index, 2817 (DMA_FC_THRESH_LO << 2818 DMA_XOFF_THRESHOLD_SHIFT) | 2819 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2820 2821 /* Set start and end address, read and write pointers */ 2822 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2823 DMA_START_ADDR); 2824 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2825 RDMA_READ_PTR); 2826 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2827 RDMA_WRITE_PTR); 2828 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2829 DMA_END_ADDR); 2830 2831 return ret; 2832 } 2833 2834 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2835 { 2836 unsigned int i; 2837 struct bcmgenet_tx_ring *ring; 2838 2839 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2840 ring = &priv->tx_rings[i]; 2841 napi_enable(&ring->napi); 2842 bcmgenet_tx_ring_int_enable(ring); 2843 } 2844 } 2845 2846 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2847 { 2848 unsigned int i; 2849 struct bcmgenet_tx_ring *ring; 2850 2851 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2852 ring = &priv->tx_rings[i]; 2853 napi_disable(&ring->napi); 2854 } 2855 } 2856 2857 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2858 { 2859 unsigned int i; 2860 struct bcmgenet_tx_ring *ring; 2861 2862 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2863 ring = &priv->tx_rings[i]; 2864 netif_napi_del(&ring->napi); 2865 } 2866 } 2867 2868 static int bcmgenet_tdma_disable(struct bcmgenet_priv *priv) 2869 { 2870 int timeout = 0; 2871 u32 reg, mask; 2872 2873 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2874 mask = (1 << (priv->hw_params->tx_queues + 1)) - 1; 2875 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2876 reg &= ~mask; 2877 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2878 2879 /* Check DMA status register to confirm DMA is disabled */ 2880 while (timeout++ < DMA_TIMEOUT_VAL) { 2881 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2882 if ((reg & mask) == mask) 2883 return 0; 2884 2885 udelay(1); 2886 } 2887 2888 return -ETIMEDOUT; 2889 } 2890 2891 static int bcmgenet_rdma_disable(struct bcmgenet_priv *priv) 2892 { 2893 int timeout = 0; 2894 u32 reg, mask; 2895 2896 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2897 mask = (1 << (priv->hw_params->rx_queues + 1)) - 1; 2898 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2899 reg &= ~mask; 2900 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2901 2902 /* Check DMA status register to confirm DMA is disabled */ 2903 while (timeout++ < DMA_TIMEOUT_VAL) { 2904 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2905 if ((reg & mask) == mask) 2906 return 0; 2907 2908 udelay(1); 2909 } 2910 2911 return -ETIMEDOUT; 2912 } 2913 2914 /* Initialize Tx queues 2915 * 2916 * Queues 1-4 are the priority queues, each one has 32 descriptors. 2917 * The weighted round-robin arbiter gives them a larger share of TX 2918 * bandwidth than the default queue 0. 2919 * 2920 * Queue 0 is the default Tx queue with 2921 * GENET_Q0_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2922 * 2923 * The transmit control block pool is then partitioned as follows: 2924 * - Tx queue 0 uses tx_cbs[0..127] 2925 * - Tx queue 1 uses tx_cbs[128..159] 2926 * - Tx queue 2 uses tx_cbs[160..191] 2927 * - Tx queue 3 uses tx_cbs[192..223] 2928 * - Tx queue 4 uses tx_cbs[224..255] 2929 */ 2930 static void bcmgenet_init_tx_queues(struct net_device *dev) 2931 { 2932 struct bcmgenet_priv *priv = netdev_priv(dev); 2933 unsigned int start = 0, end = GENET_Q0_TX_BD_CNT; 2934 u32 i, ring_mask, dma_priority[3] = {0, 0, 0}; 2935 2936 /* Enable Weighted Round-Robin arbiter mode */ 2937 bcmgenet_tdma_writel(priv, DMA_ARBITER_WRR, DMA_ARB_CTRL); 2938 2939 /* Initialize Tx priority queues */ 2940 for (i = 0; i <= priv->hw_params->tx_queues; i++) { 2941 bcmgenet_init_tx_ring(priv, i, end - start, start, end); 2942 start = end; 2943 end += priv->hw_params->tx_bds_per_q; 2944 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2945 (i ? GENET_Q1_WEIGHT : GENET_Q0_WEIGHT) 2946 << DMA_PRIO_REG_SHIFT(i); 2947 } 2948 2949 /* Set Tx queue priorities */ 2950 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2951 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2952 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2953 2954 /* Configure Tx queues as descriptor rings */ 2955 ring_mask = (1 << (priv->hw_params->tx_queues + 1)) - 1; 2956 bcmgenet_tdma_writel(priv, ring_mask, DMA_RING_CFG); 2957 2958 /* Enable Tx rings */ 2959 ring_mask <<= DMA_RING_BUF_EN_SHIFT; 2960 bcmgenet_tdma_writel(priv, ring_mask, DMA_CTRL); 2961 } 2962 2963 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2964 { 2965 unsigned int i; 2966 struct bcmgenet_rx_ring *ring; 2967 2968 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2969 ring = &priv->rx_rings[i]; 2970 napi_enable(&ring->napi); 2971 bcmgenet_rx_ring_int_enable(ring); 2972 } 2973 } 2974 2975 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2976 { 2977 unsigned int i; 2978 struct bcmgenet_rx_ring *ring; 2979 2980 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2981 ring = &priv->rx_rings[i]; 2982 napi_disable(&ring->napi); 2983 cancel_work_sync(&ring->dim.dim.work); 2984 } 2985 } 2986 2987 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2988 { 2989 unsigned int i; 2990 struct bcmgenet_rx_ring *ring; 2991 2992 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2993 ring = &priv->rx_rings[i]; 2994 netif_napi_del(&ring->napi); 2995 } 2996 } 2997 2998 static void bcmgenet_destroy_rx_page_pools(struct bcmgenet_priv *priv) 2999 { 3000 struct bcmgenet_rx_ring *ring; 3001 unsigned int i; 3002 3003 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 3004 ring = &priv->rx_rings[i]; 3005 if (ring->page_pool) { 3006 page_pool_destroy(ring->page_pool); 3007 ring->page_pool = NULL; 3008 } 3009 } 3010 } 3011 3012 /* Initialize Rx queues 3013 * 3014 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 3015 * used to direct traffic to these queues. 3016 * 3017 * Queue 0 is also the default Rx queue with GENET_Q0_RX_BD_CNT descriptors. 3018 */ 3019 static int bcmgenet_init_rx_queues(struct net_device *dev) 3020 { 3021 struct bcmgenet_priv *priv = netdev_priv(dev); 3022 unsigned int start = 0, end = GENET_Q0_RX_BD_CNT; 3023 u32 i, ring_mask; 3024 int ret; 3025 3026 /* Initialize Rx priority queues */ 3027 for (i = 0; i <= priv->hw_params->rx_queues; i++) { 3028 ret = bcmgenet_init_rx_ring(priv, i, end - start, start, end); 3029 if (ret) 3030 return ret; 3031 3032 start = end; 3033 end += priv->hw_params->rx_bds_per_q; 3034 } 3035 3036 /* Configure Rx queues as descriptor rings */ 3037 ring_mask = (1 << (priv->hw_params->rx_queues + 1)) - 1; 3038 bcmgenet_rdma_writel(priv, ring_mask, DMA_RING_CFG); 3039 3040 /* Enable Rx rings */ 3041 ring_mask <<= DMA_RING_BUF_EN_SHIFT; 3042 bcmgenet_rdma_writel(priv, ring_mask, DMA_CTRL); 3043 3044 return 0; 3045 } 3046 3047 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 3048 { 3049 int ret = 0; 3050 3051 /* Disable TDMA to stop add more frames in TX DMA */ 3052 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) { 3053 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 3054 ret = -ETIMEDOUT; 3055 } 3056 3057 /* Wait 10ms for packet drain in both tx and rx dma */ 3058 usleep_range(10000, 20000); 3059 3060 /* Disable RDMA */ 3061 if (-ETIMEDOUT == bcmgenet_rdma_disable(priv)) { 3062 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 3063 ret = -ETIMEDOUT; 3064 } 3065 3066 return ret; 3067 } 3068 3069 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 3070 { 3071 struct netdev_queue *txq; 3072 int i; 3073 3074 bcmgenet_fini_rx_napi(priv); 3075 bcmgenet_fini_tx_napi(priv); 3076 3077 for (i = 0; i <= priv->hw_params->tx_queues; i++) { 3078 txq = netdev_get_tx_queue(priv->dev, i); 3079 netdev_tx_reset_queue(txq); 3080 } 3081 3082 bcmgenet_free_rx_buffers(priv); 3083 bcmgenet_destroy_rx_page_pools(priv); 3084 kfree(priv->rx_cbs); 3085 kfree(priv->tx_cbs); 3086 } 3087 3088 /* init_edma: Initialize DMA control register */ 3089 static int bcmgenet_init_dma(struct bcmgenet_priv *priv, bool flush_rx) 3090 { 3091 struct enet_cb *cb; 3092 unsigned int i; 3093 int ret; 3094 u32 reg; 3095 3096 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 3097 3098 /* Disable TX DMA */ 3099 ret = bcmgenet_tdma_disable(priv); 3100 if (ret) { 3101 netdev_err(priv->dev, "failed to halt Tx DMA\n"); 3102 return ret; 3103 } 3104 3105 /* Disable RX DMA */ 3106 ret = bcmgenet_rdma_disable(priv); 3107 if (ret) { 3108 netdev_err(priv->dev, "failed to halt Rx DMA\n"); 3109 return ret; 3110 } 3111 3112 /* Flush TX queues */ 3113 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 3114 udelay(10); 3115 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 3116 3117 if (flush_rx) { 3118 reg = bcmgenet_rbuf_ctrl_get(priv); 3119 bcmgenet_rbuf_ctrl_set(priv, reg | BIT(0)); 3120 udelay(10); 3121 bcmgenet_rbuf_ctrl_set(priv, reg); 3122 udelay(10); 3123 } 3124 3125 /* Initialize common Rx ring structures */ 3126 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 3127 priv->num_rx_bds = TOTAL_DESC; 3128 priv->rx_cbs = kzalloc_objs(struct enet_cb, priv->num_rx_bds); 3129 if (!priv->rx_cbs) 3130 return -ENOMEM; 3131 3132 for (i = 0; i < priv->num_rx_bds; i++) { 3133 cb = priv->rx_cbs + i; 3134 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 3135 } 3136 3137 /* Initialize common TX ring structures */ 3138 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 3139 priv->num_tx_bds = TOTAL_DESC; 3140 priv->tx_cbs = kzalloc_objs(struct enet_cb, priv->num_tx_bds); 3141 if (!priv->tx_cbs) { 3142 kfree(priv->rx_cbs); 3143 return -ENOMEM; 3144 } 3145 3146 for (i = 0; i < priv->num_tx_bds; i++) { 3147 cb = priv->tx_cbs + i; 3148 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 3149 } 3150 3151 /* Init rDma */ 3152 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 3153 DMA_SCB_BURST_SIZE); 3154 3155 /* Initialize Rx queues */ 3156 ret = bcmgenet_init_rx_queues(priv->dev); 3157 if (ret) { 3158 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 3159 bcmgenet_free_rx_buffers(priv); 3160 bcmgenet_destroy_rx_page_pools(priv); 3161 kfree(priv->rx_cbs); 3162 kfree(priv->tx_cbs); 3163 return ret; 3164 } 3165 3166 /* Init tDma */ 3167 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 3168 DMA_SCB_BURST_SIZE); 3169 3170 /* Initialize Tx queues */ 3171 bcmgenet_init_tx_queues(priv->dev); 3172 3173 /* Enable RX/TX DMA */ 3174 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3175 reg |= DMA_EN; 3176 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3177 3178 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3179 reg |= DMA_EN; 3180 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3181 3182 return 0; 3183 } 3184 3185 /* Interrupt bottom half */ 3186 static void bcmgenet_irq_task(struct work_struct *work) 3187 { 3188 unsigned int status; 3189 struct bcmgenet_priv *priv = container_of( 3190 work, struct bcmgenet_priv, bcmgenet_irq_work); 3191 3192 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 3193 3194 spin_lock_irq(&priv->lock); 3195 status = priv->irq0_stat; 3196 priv->irq0_stat = 0; 3197 spin_unlock_irq(&priv->lock); 3198 3199 if (status & UMAC_IRQ_PHY_DET_R && 3200 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 3201 phy_init_hw(priv->dev->phydev); 3202 genphy_config_aneg(priv->dev->phydev); 3203 } 3204 3205 /* Link UP/DOWN event */ 3206 if (status & UMAC_IRQ_LINK_EVENT) 3207 phy_mac_interrupt(priv->dev->phydev); 3208 3209 } 3210 3211 /* bcmgenet_isr1: handle Rx and Tx queues */ 3212 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 3213 { 3214 struct bcmgenet_priv *priv = dev_id; 3215 struct bcmgenet_rx_ring *rx_ring; 3216 struct bcmgenet_tx_ring *tx_ring; 3217 unsigned int index, status; 3218 3219 /* Read irq status */ 3220 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 3221 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3222 3223 /* clear interrupts */ 3224 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 3225 3226 netif_dbg(priv, intr, priv->dev, 3227 "%s: IRQ=0x%x\n", __func__, status); 3228 3229 /* Check Rx priority queue interrupts */ 3230 for (index = 0; index <= priv->hw_params->rx_queues; index++) { 3231 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 3232 continue; 3233 3234 rx_ring = &priv->rx_rings[index]; 3235 rx_ring->dim.event_ctr++; 3236 3237 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3238 bcmgenet_rx_ring_int_disable(rx_ring); 3239 __napi_schedule_irqoff(&rx_ring->napi); 3240 } 3241 } 3242 3243 /* Check Tx priority queue interrupts */ 3244 for (index = 0; index <= priv->hw_params->tx_queues; index++) { 3245 if (!(status & BIT(index))) 3246 continue; 3247 3248 tx_ring = &priv->tx_rings[index]; 3249 3250 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3251 bcmgenet_tx_ring_int_disable(tx_ring); 3252 __napi_schedule_irqoff(&tx_ring->napi); 3253 } 3254 } 3255 3256 return IRQ_HANDLED; 3257 } 3258 3259 /* bcmgenet_isr0: handle other stuff */ 3260 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 3261 { 3262 struct bcmgenet_priv *priv = dev_id; 3263 unsigned int status; 3264 unsigned long flags; 3265 3266 /* Read irq status */ 3267 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 3268 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3269 3270 /* clear interrupts */ 3271 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 3272 3273 netif_dbg(priv, intr, priv->dev, 3274 "IRQ=0x%x\n", status); 3275 3276 if (bcmgenet_has_mdio_intr(priv) && status & UMAC_IRQ_MDIO_EVENT) 3277 wake_up(&priv->wq); 3278 3279 /* all other interested interrupts handled in bottom half */ 3280 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 3281 if (status) { 3282 /* Save irq status for bottom-half processing. */ 3283 spin_lock_irqsave(&priv->lock, flags); 3284 priv->irq0_stat |= status; 3285 spin_unlock_irqrestore(&priv->lock, flags); 3286 3287 schedule_work(&priv->bcmgenet_irq_work); 3288 } 3289 3290 return IRQ_HANDLED; 3291 } 3292 3293 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 3294 { 3295 /* Acknowledge the interrupt */ 3296 return IRQ_HANDLED; 3297 } 3298 3299 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 3300 { 3301 u32 reg; 3302 3303 reg = bcmgenet_rbuf_ctrl_get(priv); 3304 reg |= BIT(1); 3305 bcmgenet_rbuf_ctrl_set(priv, reg); 3306 udelay(10); 3307 3308 reg &= ~BIT(1); 3309 bcmgenet_rbuf_ctrl_set(priv, reg); 3310 udelay(10); 3311 } 3312 3313 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 3314 const unsigned char *addr) 3315 { 3316 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0); 3317 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1); 3318 } 3319 3320 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 3321 unsigned char *addr) 3322 { 3323 u32 addr_tmp; 3324 3325 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 3326 put_unaligned_be32(addr_tmp, &addr[0]); 3327 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 3328 put_unaligned_be16(addr_tmp, &addr[4]); 3329 } 3330 3331 static void bcmgenet_netif_start(struct net_device *dev) 3332 { 3333 struct bcmgenet_priv *priv = netdev_priv(dev); 3334 3335 /* Start the network engine */ 3336 netif_addr_lock_bh(dev); 3337 bcmgenet_set_rx_mode(dev); 3338 netif_addr_unlock_bh(dev); 3339 bcmgenet_enable_rx_napi(priv); 3340 3341 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 3342 3343 bcmgenet_enable_tx_napi(priv); 3344 3345 /* Monitor link interrupts now */ 3346 bcmgenet_link_intr_enable(priv); 3347 3348 phy_start(dev->phydev); 3349 } 3350 3351 static int bcmgenet_open(struct net_device *dev) 3352 { 3353 struct bcmgenet_priv *priv = netdev_priv(dev); 3354 int ret; 3355 3356 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 3357 3358 /* Turn on the clock */ 3359 clk_prepare_enable(priv->clk); 3360 3361 /* If this is an internal GPHY, power it back on now, before UniMAC is 3362 * brought out of reset as absolutely no UniMAC activity is allowed 3363 */ 3364 if (priv->internal_phy) 3365 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3366 3367 /* take MAC out of reset */ 3368 bcmgenet_umac_reset(priv); 3369 3370 init_umac(priv); 3371 3372 /* Apply features again in case we changed them while interface was 3373 * down 3374 */ 3375 bcmgenet_set_features(dev, dev->features); 3376 3377 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3378 3379 /* HFB init */ 3380 bcmgenet_hfb_init(priv); 3381 3382 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3383 ret = bcmgenet_init_dma(priv, true); 3384 if (ret) { 3385 netdev_err(dev, "failed to initialize DMA\n"); 3386 goto err_clk_disable; 3387 } 3388 3389 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 3390 dev->name, priv); 3391 if (ret < 0) { 3392 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 3393 goto err_fini_dma; 3394 } 3395 3396 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 3397 dev->name, priv); 3398 if (ret < 0) { 3399 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 3400 goto err_irq0; 3401 } 3402 3403 ret = bcmgenet_mii_probe(dev); 3404 if (ret) { 3405 netdev_err(dev, "failed to connect to PHY\n"); 3406 goto err_irq1; 3407 } 3408 3409 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 3410 3411 bcmgenet_netif_start(dev); 3412 3413 netif_tx_start_all_queues(dev); 3414 3415 return 0; 3416 3417 err_irq1: 3418 free_irq(priv->irq1, priv); 3419 err_irq0: 3420 free_irq(priv->irq0, priv); 3421 err_fini_dma: 3422 bcmgenet_dma_teardown(priv); 3423 bcmgenet_fini_dma(priv); 3424 err_clk_disable: 3425 if (priv->internal_phy) 3426 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3427 clk_disable_unprepare(priv->clk); 3428 return ret; 3429 } 3430 3431 static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy) 3432 { 3433 struct bcmgenet_priv *priv = netdev_priv(dev); 3434 3435 netif_tx_disable(dev); 3436 3437 /* Disable MAC receive */ 3438 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 3439 umac_enable_set(priv, CMD_RX_EN, false); 3440 3441 if (stop_phy) 3442 phy_stop(dev->phydev); 3443 3444 bcmgenet_dma_teardown(priv); 3445 3446 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3447 umac_enable_set(priv, CMD_TX_EN, false); 3448 3449 bcmgenet_disable_tx_napi(priv); 3450 bcmgenet_disable_rx_napi(priv); 3451 bcmgenet_intr_disable(priv); 3452 3453 /* Wait for pending work items to complete. Since interrupts are 3454 * disabled no new work will be scheduled. 3455 */ 3456 cancel_work_sync(&priv->bcmgenet_irq_work); 3457 3458 /* tx reclaim */ 3459 bcmgenet_tx_reclaim_all(dev); 3460 bcmgenet_fini_dma(priv); 3461 } 3462 3463 static int bcmgenet_close(struct net_device *dev) 3464 { 3465 struct bcmgenet_priv *priv = netdev_priv(dev); 3466 int ret = 0; 3467 3468 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3469 3470 bcmgenet_netif_stop(dev, false); 3471 3472 /* Really kill the PHY state machine and disconnect from it */ 3473 phy_disconnect(dev->phydev); 3474 3475 free_irq(priv->irq0, priv); 3476 free_irq(priv->irq1, priv); 3477 3478 if (priv->internal_phy) 3479 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3480 3481 clk_disable_unprepare(priv->clk); 3482 3483 return ret; 3484 } 3485 3486 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3487 { 3488 struct bcmgenet_priv *priv = ring->priv; 3489 u32 p_index, c_index, intsts, intmsk; 3490 struct netdev_queue *txq; 3491 unsigned int free_bds; 3492 bool txq_stopped; 3493 3494 if (!netif_msg_tx_err(priv)) 3495 return; 3496 3497 txq = netdev_get_tx_queue(priv->dev, ring->index); 3498 3499 spin_lock(&ring->lock); 3500 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3501 intmsk = 1 << ring->index; 3502 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3503 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3504 txq_stopped = netif_tx_queue_stopped(txq); 3505 free_bds = ring->free_bds; 3506 spin_unlock(&ring->lock); 3507 3508 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3509 "TX queue status: %s, interrupts: %s\n" 3510 "(sw)free_bds: %d (sw)size: %d\n" 3511 "(sw)p_index: %d (hw)p_index: %d\n" 3512 "(sw)c_index: %d (hw)c_index: %d\n" 3513 "(sw)clean_p: %d (sw)write_p: %d\n" 3514 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3515 ring->index, ring->index, 3516 txq_stopped ? "stopped" : "active", 3517 intsts & intmsk ? "enabled" : "disabled", 3518 free_bds, ring->size, 3519 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3520 ring->c_index, c_index & DMA_C_INDEX_MASK, 3521 ring->clean_ptr, ring->write_ptr, 3522 ring->cb_ptr, ring->end_ptr); 3523 } 3524 3525 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3526 { 3527 struct bcmgenet_priv *priv = netdev_priv(dev); 3528 struct bcmgenet_tx_ring *ring = &priv->tx_rings[txqueue]; 3529 struct netdev_queue *txq = netdev_get_tx_queue(dev, txqueue); 3530 3531 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3532 3533 bcmgenet_dump_tx_queue(ring); 3534 3535 bcmgenet_tx_reclaim(dev, ring, true); 3536 3537 /* Re-enable the TX interrupt for this ring */ 3538 bcmgenet_intrl2_1_writel(priv, 1 << txqueue, INTRL2_CPU_MASK_CLEAR); 3539 3540 txq_trans_cond_update(txq); 3541 3542 BCMGENET_STATS64_INC((&ring->stats64), errors); 3543 3544 netif_tx_wake_queue(txq); 3545 } 3546 3547 #define MAX_MDF_FILTER 17 3548 3549 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3550 const unsigned char *addr, 3551 int *i) 3552 { 3553 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3554 UMAC_MDF_ADDR + (*i * 4)); 3555 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3556 addr[4] << 8 | addr[5], 3557 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3558 *i += 2; 3559 } 3560 3561 static void bcmgenet_set_rx_mode(struct net_device *dev) 3562 { 3563 struct bcmgenet_priv *priv = netdev_priv(dev); 3564 struct netdev_hw_addr *ha; 3565 int i, nfilter; 3566 u32 reg; 3567 3568 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3569 3570 /* Number of filters needed */ 3571 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3572 3573 /* 3574 * Turn on promicuous mode for three scenarios 3575 * 1. IFF_PROMISC flag is set 3576 * 2. IFF_ALLMULTI flag is set 3577 * 3. The number of filters needed exceeds the number filters 3578 * supported by the hardware. 3579 */ 3580 spin_lock(&priv->reg_lock); 3581 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3582 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3583 (nfilter > MAX_MDF_FILTER)) { 3584 reg |= CMD_PROMISC; 3585 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3586 spin_unlock(&priv->reg_lock); 3587 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3588 return; 3589 } else { 3590 reg &= ~CMD_PROMISC; 3591 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3592 spin_unlock(&priv->reg_lock); 3593 } 3594 3595 /* update MDF filter */ 3596 i = 0; 3597 /* Broadcast */ 3598 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3599 /* my own address.*/ 3600 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3601 3602 /* Unicast */ 3603 netdev_for_each_uc_addr(ha, dev) 3604 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3605 3606 /* Multicast */ 3607 netdev_for_each_mc_addr(ha, dev) 3608 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3609 3610 /* Enable filters */ 3611 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3612 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3613 } 3614 3615 /* Set the hardware MAC address. */ 3616 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3617 { 3618 struct sockaddr *addr = p; 3619 3620 /* Setting the MAC address at the hardware level is not possible 3621 * without disabling the UniMAC RX/TX enable bits. 3622 */ 3623 if (netif_running(dev)) 3624 return -EBUSY; 3625 3626 eth_hw_addr_set(dev, addr->sa_data); 3627 3628 return 0; 3629 } 3630 3631 static void bcmgenet_get_stats64(struct net_device *dev, 3632 struct rtnl_link_stats64 *stats) 3633 { 3634 struct bcmgenet_priv *priv = netdev_priv(dev); 3635 struct bcmgenet_tx_stats64 *tx_stats; 3636 struct bcmgenet_rx_stats64 *rx_stats; 3637 u64 rx_length_errors, rx_over_errors; 3638 u64 rx_missed, rx_fragmented_errors; 3639 u64 rx_crc_errors, rx_frame_errors; 3640 u64 tx_errors, tx_dropped; 3641 u64 rx_errors, rx_dropped; 3642 u64 tx_bytes, tx_packets; 3643 u64 rx_bytes, rx_packets; 3644 unsigned int start; 3645 unsigned int q; 3646 u64 multicast; 3647 3648 for (q = 0; q <= priv->hw_params->tx_queues; q++) { 3649 tx_stats = &priv->tx_rings[q].stats64; 3650 do { 3651 start = u64_stats_fetch_begin(&tx_stats->syncp); 3652 tx_bytes = u64_stats_read(&tx_stats->bytes); 3653 tx_packets = u64_stats_read(&tx_stats->packets); 3654 tx_errors = u64_stats_read(&tx_stats->errors); 3655 tx_dropped = u64_stats_read(&tx_stats->dropped); 3656 } while (u64_stats_fetch_retry(&tx_stats->syncp, start)); 3657 3658 stats->tx_bytes += tx_bytes; 3659 stats->tx_packets += tx_packets; 3660 stats->tx_errors += tx_errors; 3661 stats->tx_dropped += tx_dropped; 3662 } 3663 3664 for (q = 0; q <= priv->hw_params->rx_queues; q++) { 3665 rx_stats = &priv->rx_rings[q].stats64; 3666 do { 3667 start = u64_stats_fetch_begin(&rx_stats->syncp); 3668 rx_bytes = u64_stats_read(&rx_stats->bytes); 3669 rx_packets = u64_stats_read(&rx_stats->packets); 3670 rx_errors = u64_stats_read(&rx_stats->errors); 3671 rx_dropped = u64_stats_read(&rx_stats->dropped); 3672 rx_missed = u64_stats_read(&rx_stats->missed); 3673 rx_length_errors = u64_stats_read(&rx_stats->length_errors); 3674 rx_over_errors = u64_stats_read(&rx_stats->over_errors); 3675 rx_crc_errors = u64_stats_read(&rx_stats->crc_errors); 3676 rx_frame_errors = u64_stats_read(&rx_stats->frame_errors); 3677 rx_fragmented_errors = u64_stats_read(&rx_stats->fragmented_errors); 3678 multicast = u64_stats_read(&rx_stats->multicast); 3679 } while (u64_stats_fetch_retry(&rx_stats->syncp, start)); 3680 3681 rx_errors += rx_length_errors; 3682 rx_errors += rx_crc_errors; 3683 rx_errors += rx_frame_errors; 3684 rx_errors += rx_fragmented_errors; 3685 3686 stats->rx_bytes += rx_bytes; 3687 stats->rx_packets += rx_packets; 3688 stats->rx_errors += rx_errors; 3689 stats->rx_dropped += rx_dropped; 3690 stats->rx_missed_errors += rx_missed; 3691 stats->rx_length_errors += rx_length_errors; 3692 stats->rx_over_errors += rx_over_errors; 3693 stats->rx_crc_errors += rx_crc_errors; 3694 stats->rx_frame_errors += rx_frame_errors; 3695 stats->multicast += multicast; 3696 } 3697 } 3698 3699 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier) 3700 { 3701 struct bcmgenet_priv *priv = netdev_priv(dev); 3702 3703 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) || 3704 priv->phy_interface != PHY_INTERFACE_MODE_MOCA) 3705 return -EOPNOTSUPP; 3706 3707 if (new_carrier) 3708 netif_carrier_on(dev); 3709 else 3710 netif_carrier_off(dev); 3711 3712 return 0; 3713 } 3714 3715 static const struct net_device_ops bcmgenet_netdev_ops = { 3716 .ndo_open = bcmgenet_open, 3717 .ndo_stop = bcmgenet_close, 3718 .ndo_start_xmit = bcmgenet_xmit, 3719 .ndo_tx_timeout = bcmgenet_timeout, 3720 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3721 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3722 .ndo_eth_ioctl = phy_do_ioctl_running, 3723 .ndo_set_features = bcmgenet_set_features, 3724 .ndo_get_stats64 = bcmgenet_get_stats64, 3725 .ndo_change_carrier = bcmgenet_change_carrier, 3726 }; 3727 3728 /* GENET hardware parameters/characteristics */ 3729 static const struct bcmgenet_hw_params bcmgenet_hw_params_v1 = { 3730 .tx_queues = 0, 3731 .tx_bds_per_q = 0, 3732 .rx_queues = 0, 3733 .rx_bds_per_q = 0, 3734 .bp_in_en_shift = 16, 3735 .bp_in_mask = 0xffff, 3736 .hfb_filter_cnt = 16, 3737 .hfb_filter_size = 64, 3738 .qtag_mask = 0x1F, 3739 .hfb_offset = 0x1000, 3740 .hfb_reg_offset = GENET_RBUF_OFF + RBUF_HFB_CTRL_V1, 3741 .rdma_offset = 0x2000, 3742 .tdma_offset = 0x3000, 3743 .words_per_bd = 2, 3744 }; 3745 3746 static const struct bcmgenet_hw_params bcmgenet_hw_params_v2 = { 3747 .tx_queues = 4, 3748 .tx_bds_per_q = 32, 3749 .rx_queues = 0, 3750 .rx_bds_per_q = 0, 3751 .bp_in_en_shift = 16, 3752 .bp_in_mask = 0xffff, 3753 .hfb_filter_cnt = 16, 3754 .hfb_filter_size = 64, 3755 .qtag_mask = 0x1F, 3756 .tbuf_offset = 0x0600, 3757 .hfb_offset = 0x1000, 3758 .hfb_reg_offset = 0x2000, 3759 .rdma_offset = 0x3000, 3760 .tdma_offset = 0x4000, 3761 .words_per_bd = 2, 3762 }; 3763 3764 static const struct bcmgenet_hw_params bcmgenet_hw_params_v3 = { 3765 .tx_queues = 4, 3766 .tx_bds_per_q = 32, 3767 .rx_queues = 0, 3768 .rx_bds_per_q = 0, 3769 .bp_in_en_shift = 17, 3770 .bp_in_mask = 0x1ffff, 3771 .hfb_filter_cnt = 48, 3772 .hfb_filter_size = 128, 3773 .qtag_mask = 0x3F, 3774 .tbuf_offset = 0x0600, 3775 .hfb_offset = 0x8000, 3776 .hfb_reg_offset = 0xfc00, 3777 .rdma_offset = 0x10000, 3778 .tdma_offset = 0x11000, 3779 .words_per_bd = 2, 3780 }; 3781 3782 static const struct bcmgenet_hw_params bcmgenet_hw_params_v4 = { 3783 .tx_queues = 4, 3784 .tx_bds_per_q = 32, 3785 .rx_queues = 0, 3786 .rx_bds_per_q = 0, 3787 .bp_in_en_shift = 17, 3788 .bp_in_mask = 0x1ffff, 3789 .hfb_filter_cnt = 48, 3790 .hfb_filter_size = 128, 3791 .qtag_mask = 0x3F, 3792 .tbuf_offset = 0x0600, 3793 .hfb_offset = 0x8000, 3794 .hfb_reg_offset = 0xfc00, 3795 .rdma_offset = 0x2000, 3796 .tdma_offset = 0x4000, 3797 .words_per_bd = 3, 3798 }; 3799 3800 /* Infer hardware parameters from the detected GENET version */ 3801 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3802 { 3803 const struct bcmgenet_hw_params *params; 3804 u32 reg; 3805 u8 major; 3806 u16 gphy_rev; 3807 3808 /* default to latest values */ 3809 params = &bcmgenet_hw_params_v4; 3810 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3811 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3812 if (GENET_IS_V3(priv)) { 3813 params = &bcmgenet_hw_params_v3; 3814 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3815 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3816 } else if (GENET_IS_V2(priv)) { 3817 params = &bcmgenet_hw_params_v2; 3818 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3819 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3820 } else if (GENET_IS_V1(priv)) { 3821 params = &bcmgenet_hw_params_v1; 3822 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3823 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3824 } 3825 priv->hw_params = params; 3826 3827 /* Read GENET HW version */ 3828 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3829 major = (reg >> 24 & 0x0f); 3830 if (major == 6 || major == 7) 3831 major = 5; 3832 else if (major == 5) 3833 major = 4; 3834 else if (major == 0) 3835 major = 1; 3836 if (major != priv->version) { 3837 dev_err(&priv->pdev->dev, 3838 "GENET version mismatch, got: %d, configured for: %d\n", 3839 major, priv->version); 3840 } 3841 3842 /* Print the GENET core version */ 3843 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3844 major, (reg >> 16) & 0x0f, reg & 0xffff); 3845 3846 /* Store the integrated PHY revision for the MDIO probing function 3847 * to pass this information to the PHY driver. The PHY driver expects 3848 * to find the PHY major revision in bits 15:8 while the GENET register 3849 * stores that information in bits 7:0, account for that. 3850 * 3851 * On newer chips, starting with PHY revision G0, a new scheme is 3852 * deployed similar to the Starfighter 2 switch with GPHY major 3853 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3854 * is reserved as well as special value 0x01ff, we have a small 3855 * heuristic to check for the new GPHY revision and re-arrange things 3856 * so the GPHY driver is happy. 3857 */ 3858 gphy_rev = reg & 0xffff; 3859 3860 if (GENET_IS_V5(priv)) { 3861 /* The EPHY revision should come from the MDIO registers of 3862 * the PHY not from GENET. 3863 */ 3864 if (gphy_rev != 0) { 3865 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3866 gphy_rev); 3867 } 3868 /* This is reserved so should require special treatment */ 3869 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3870 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3871 return; 3872 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3873 } else if ((gphy_rev & 0xf0) != 0) { 3874 priv->gphy_rev = gphy_rev << 8; 3875 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3876 } else if ((gphy_rev & 0xff00) != 0) { 3877 priv->gphy_rev = gphy_rev; 3878 } 3879 3880 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3881 if (!bcmgenet_has_40bits(priv)) 3882 pr_warn("GENET does not support 40-bits PA\n"); 3883 #endif 3884 3885 pr_debug("Configuration for version: %d\n" 3886 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3887 "BP << en: %2d, BP msk: 0x%05x\n" 3888 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3889 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3890 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3891 "Words/BD: %d\n", 3892 priv->version, 3893 params->tx_queues, params->tx_bds_per_q, 3894 params->rx_queues, params->rx_bds_per_q, 3895 params->bp_in_en_shift, params->bp_in_mask, 3896 params->hfb_filter_cnt, params->qtag_mask, 3897 params->tbuf_offset, params->hfb_offset, 3898 params->hfb_reg_offset, 3899 params->rdma_offset, params->tdma_offset, 3900 params->words_per_bd); 3901 } 3902 3903 struct bcmgenet_plat_data { 3904 enum bcmgenet_version version; 3905 u32 dma_max_burst_length; 3906 u32 flags; 3907 }; 3908 3909 static const struct bcmgenet_plat_data v1_plat_data = { 3910 .version = GENET_V1, 3911 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3912 }; 3913 3914 static const struct bcmgenet_plat_data v2_plat_data = { 3915 .version = GENET_V2, 3916 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3917 .flags = GENET_HAS_EXT, 3918 }; 3919 3920 static const struct bcmgenet_plat_data v3_plat_data = { 3921 .version = GENET_V3, 3922 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3923 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3924 GENET_HAS_MOCA_LINK_DET, 3925 }; 3926 3927 static const struct bcmgenet_plat_data v4_plat_data = { 3928 .version = GENET_V4, 3929 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3930 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3931 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3932 }; 3933 3934 static const struct bcmgenet_plat_data v5_plat_data = { 3935 .version = GENET_V5, 3936 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3937 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3938 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3939 }; 3940 3941 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3942 .version = GENET_V5, 3943 .dma_max_burst_length = 0x08, 3944 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3945 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3946 }; 3947 3948 static const struct bcmgenet_plat_data bcm7712_plat_data = { 3949 .version = GENET_V5, 3950 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3951 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3952 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET | 3953 GENET_HAS_EPHY_16NM, 3954 }; 3955 3956 static const struct of_device_id bcmgenet_match[] = { 3957 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3958 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3959 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3960 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3961 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3962 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3963 { .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data }, 3964 { }, 3965 }; 3966 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3967 3968 static int bcmgenet_probe(struct platform_device *pdev) 3969 { 3970 const struct bcmgenet_plat_data *pdata; 3971 struct bcmgenet_priv *priv; 3972 struct net_device *dev; 3973 unsigned int i; 3974 int err = -EIO; 3975 3976 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3977 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3978 GENET_MAX_MQ_CNT + 1); 3979 if (!dev) { 3980 dev_err(&pdev->dev, "can't allocate net device\n"); 3981 return -ENOMEM; 3982 } 3983 3984 priv = netdev_priv(dev); 3985 priv->irq0 = platform_get_irq(pdev, 0); 3986 if (priv->irq0 < 0) { 3987 err = priv->irq0; 3988 goto err; 3989 } 3990 priv->irq1 = platform_get_irq(pdev, 1); 3991 if (priv->irq1 < 0) { 3992 err = priv->irq1; 3993 goto err; 3994 } 3995 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3996 if (priv->wol_irq == -EPROBE_DEFER) { 3997 err = priv->wol_irq; 3998 goto err; 3999 } 4000 4001 priv->base = devm_platform_ioremap_resource(pdev, 0); 4002 if (IS_ERR(priv->base)) { 4003 err = PTR_ERR(priv->base); 4004 goto err; 4005 } 4006 4007 spin_lock_init(&priv->reg_lock); 4008 spin_lock_init(&priv->lock); 4009 4010 /* Set default pause parameters */ 4011 priv->autoneg_pause = 1; 4012 priv->tx_pause = 1; 4013 priv->rx_pause = 1; 4014 4015 SET_NETDEV_DEV(dev, &pdev->dev); 4016 dev_set_drvdata(&pdev->dev, dev); 4017 dev->watchdog_timeo = 2 * HZ; 4018 dev->ethtool_ops = &bcmgenet_ethtool_ops; 4019 dev->netdev_ops = &bcmgenet_netdev_ops; 4020 4021 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 4022 4023 /* Set default features */ 4024 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 4025 NETIF_F_RXCSUM; 4026 dev->hw_features |= dev->features; 4027 dev->vlan_features |= dev->features; 4028 4029 netdev_sw_irq_coalesce_default_on(dev); 4030 4031 /* Request the WOL interrupt and advertise suspend if available */ 4032 priv->wol_irq_disabled = true; 4033 if (priv->wol_irq > 0) { 4034 err = devm_request_irq(&pdev->dev, priv->wol_irq, 4035 bcmgenet_wol_isr, 0, dev->name, priv); 4036 if (!err) 4037 device_set_wakeup_capable(&pdev->dev, 1); 4038 } 4039 4040 /* Set the needed headroom to account for any possible 4041 * features enabling/disabling at runtime 4042 */ 4043 dev->needed_headroom += 64; 4044 4045 priv->dev = dev; 4046 priv->pdev = pdev; 4047 4048 pdata = device_get_match_data(&pdev->dev); 4049 if (pdata) { 4050 priv->version = pdata->version; 4051 priv->dma_max_burst_length = pdata->dma_max_burst_length; 4052 priv->flags = pdata->flags; 4053 } 4054 4055 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet"); 4056 if (IS_ERR(priv->clk)) { 4057 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 4058 err = PTR_ERR(priv->clk); 4059 goto err; 4060 } 4061 4062 err = clk_prepare_enable(priv->clk); 4063 if (err) 4064 goto err; 4065 4066 bcmgenet_set_hw_params(priv); 4067 4068 err = -EIO; 4069 if (bcmgenet_has_40bits(priv)) 4070 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 4071 if (err) 4072 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 4073 if (err) 4074 goto err_clk_disable; 4075 4076 /* Mii wait queue */ 4077 init_waitqueue_head(&priv->wq); 4078 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 4079 4080 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol"); 4081 if (IS_ERR(priv->clk_wol)) { 4082 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 4083 err = PTR_ERR(priv->clk_wol); 4084 goto err_clk_disable; 4085 } 4086 4087 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee"); 4088 if (IS_ERR(priv->clk_eee)) { 4089 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 4090 err = PTR_ERR(priv->clk_eee); 4091 goto err_clk_disable; 4092 } 4093 4094 /* If this is an internal GPHY, power it on now, before UniMAC is 4095 * brought out of reset as absolutely no UniMAC activity is allowed 4096 */ 4097 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 4098 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4099 4100 if (device_get_ethdev_address(&pdev->dev, dev)) 4101 if (has_acpi_companion(&pdev->dev)) { 4102 u8 addr[ETH_ALEN]; 4103 4104 bcmgenet_get_hw_addr(priv, addr); 4105 eth_hw_addr_set(dev, addr); 4106 } 4107 4108 if (!is_valid_ether_addr(dev->dev_addr)) { 4109 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 4110 eth_hw_addr_random(dev); 4111 } 4112 4113 reset_umac(priv); 4114 4115 err = bcmgenet_mii_init(dev); 4116 if (err) 4117 goto err_clk_disable; 4118 4119 /* setup number of real queues + 1 */ 4120 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 4121 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 4122 4123 /* Set default coalescing parameters */ 4124 for (i = 0; i <= priv->hw_params->rx_queues; i++) 4125 priv->rx_rings[i].rx_max_coalesced_frames = 1; 4126 4127 /* Initialize u64 stats seq counter for 32bit machines */ 4128 for (i = 0; i <= priv->hw_params->rx_queues; i++) 4129 u64_stats_init(&priv->rx_rings[i].stats64.syncp); 4130 for (i = 0; i <= priv->hw_params->tx_queues; i++) 4131 u64_stats_init(&priv->tx_rings[i].stats64.syncp); 4132 4133 /* libphy will determine the link state */ 4134 netif_carrier_off(dev); 4135 4136 /* Turn off the main clock, WOL clock is handled separately */ 4137 clk_disable_unprepare(priv->clk); 4138 4139 err = register_netdev(dev); 4140 if (err) { 4141 bcmgenet_mii_exit(dev); 4142 goto err; 4143 } 4144 4145 return err; 4146 4147 err_clk_disable: 4148 clk_disable_unprepare(priv->clk); 4149 err: 4150 free_netdev(dev); 4151 return err; 4152 } 4153 4154 static void bcmgenet_remove(struct platform_device *pdev) 4155 { 4156 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 4157 4158 dev_set_drvdata(&pdev->dev, NULL); 4159 unregister_netdev(priv->dev); 4160 bcmgenet_mii_exit(priv->dev); 4161 free_netdev(priv->dev); 4162 } 4163 4164 static void bcmgenet_shutdown(struct platform_device *pdev) 4165 { 4166 bcmgenet_remove(pdev); 4167 } 4168 4169 #ifdef CONFIG_PM_SLEEP 4170 static int bcmgenet_resume_noirq(struct device *d) 4171 { 4172 struct net_device *dev = dev_get_drvdata(d); 4173 struct bcmgenet_priv *priv = netdev_priv(dev); 4174 int ret; 4175 u32 reg; 4176 4177 if (!netif_running(dev)) 4178 return 0; 4179 4180 /* Turn on the clock */ 4181 ret = clk_prepare_enable(priv->clk); 4182 if (ret) 4183 return ret; 4184 4185 if (device_may_wakeup(d) && priv->wolopts) { 4186 /* Account for Wake-on-LAN events and clear those events 4187 * (Some devices need more time between enabling the clocks 4188 * and the interrupt register reflecting the wake event so 4189 * read the register twice) 4190 */ 4191 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4192 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4193 if (reg & UMAC_IRQ_WAKE_EVENT) 4194 pm_wakeup_event(&priv->pdev->dev, 0); 4195 4196 /* From WOL-enabled suspend, switch to regular clock */ 4197 if (!bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC)) 4198 return 0; 4199 4200 /* Failed so fall through to reset MAC */ 4201 } 4202 4203 /* If this is an internal GPHY, power it back on now, before UniMAC is 4204 * brought out of reset as absolutely no UniMAC activity is allowed 4205 */ 4206 if (priv->internal_phy) 4207 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4208 4209 /* take MAC out of reset */ 4210 bcmgenet_umac_reset(priv); 4211 4212 return 0; 4213 } 4214 4215 static int bcmgenet_resume(struct device *d) 4216 { 4217 struct net_device *dev = dev_get_drvdata(d); 4218 struct bcmgenet_priv *priv = netdev_priv(dev); 4219 struct bcmgenet_rxnfc_rule *rule; 4220 int ret; 4221 u32 reg; 4222 4223 if (!netif_running(dev)) 4224 return 0; 4225 4226 if (device_may_wakeup(d) && priv->wolopts) { 4227 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 4228 if (reg & CMD_RX_EN) { 4229 /* Successfully exited WoL, just resume data flows */ 4230 list_for_each_entry(rule, &priv->rxnfc_list, list) 4231 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 4232 bcmgenet_hfb_enable_filter(priv, 4233 rule->fs.location + 1); 4234 bcmgenet_hfb_enable_filter(priv, 0); 4235 bcmgenet_set_rx_mode(dev); 4236 bcmgenet_enable_rx_napi(priv); 4237 4238 /* Reinitialize Tx flows */ 4239 bcmgenet_tdma_disable(priv); 4240 bcmgenet_init_tx_queues(priv->dev); 4241 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 4242 reg |= DMA_EN; 4243 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 4244 bcmgenet_enable_tx_napi(priv); 4245 4246 bcmgenet_link_intr_enable(priv); 4247 phy_start_machine(dev->phydev); 4248 4249 netif_device_attach(dev); 4250 enable_irq(priv->irq1); 4251 return 0; 4252 } 4253 /* MAC was reset so complete bcmgenet_netif_stop() */ 4254 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, false); 4255 bcmgenet_rdma_disable(priv); 4256 bcmgenet_intr_disable(priv); 4257 bcmgenet_fini_dma(priv); 4258 enable_irq(priv->irq1); 4259 } 4260 4261 init_umac(priv); 4262 4263 phy_init_hw(dev->phydev); 4264 4265 /* Speed settings must be restored */ 4266 genphy_config_aneg(dev->phydev); 4267 bcmgenet_mii_config(priv->dev, false); 4268 4269 /* Restore enabled features */ 4270 bcmgenet_set_features(dev, dev->features); 4271 4272 bcmgenet_set_hw_addr(priv, dev->dev_addr); 4273 4274 /* Restore hardware filters */ 4275 bcmgenet_hfb_clear(priv); 4276 list_for_each_entry(rule, &priv->rxnfc_list, list) 4277 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) 4278 bcmgenet_hfb_create_rxnfc_filter(priv, rule); 4279 4280 /* Reinitialize TDMA and RDMA and SW housekeeping */ 4281 ret = bcmgenet_init_dma(priv, false); 4282 if (ret) { 4283 netdev_err(dev, "failed to initialize DMA\n"); 4284 goto out_clk_disable; 4285 } 4286 4287 if (!device_may_wakeup(d)) 4288 phy_resume(dev->phydev); 4289 4290 bcmgenet_netif_start(dev); 4291 4292 netif_device_attach(dev); 4293 4294 return 0; 4295 4296 out_clk_disable: 4297 if (priv->internal_phy) 4298 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4299 clk_disable_unprepare(priv->clk); 4300 return ret; 4301 } 4302 4303 static int bcmgenet_suspend(struct device *d) 4304 { 4305 struct net_device *dev = dev_get_drvdata(d); 4306 struct bcmgenet_priv *priv = netdev_priv(dev); 4307 struct bcmgenet_rxnfc_rule *rule; 4308 u32 reg, hfb_enable = 0; 4309 4310 if (!netif_running(dev)) 4311 return 0; 4312 4313 netif_device_detach(dev); 4314 4315 if (device_may_wakeup(d) && priv->wolopts) { 4316 netif_tx_disable(dev); 4317 4318 /* Suspend non-wake Rx data flows */ 4319 if (priv->wolopts & WAKE_FILTER) 4320 list_for_each_entry(rule, &priv->rxnfc_list, list) 4321 if (rule->fs.ring_cookie == RX_CLS_FLOW_WAKE && 4322 rule->state == BCMGENET_RXNFC_STATE_ENABLED) 4323 hfb_enable |= 1 << rule->fs.location; 4324 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 4325 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 4326 reg &= ~RBUF_HFB_FILTER_EN_MASK; 4327 reg |= hfb_enable << (RBUF_HFB_FILTER_EN_SHIFT + 1); 4328 } else { 4329 bcmgenet_hfb_reg_writel(priv, hfb_enable << 1, 4330 HFB_FLT_ENABLE_V3PLUS + 4); 4331 } 4332 if (!hfb_enable) 4333 reg &= ~RBUF_HFB_EN; 4334 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 4335 4336 /* Clear any old filter matches so only new matches wake */ 4337 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 4338 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 4339 4340 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) 4341 netdev_warn(priv->dev, 4342 "Timed out while disabling TX DMA\n"); 4343 4344 bcmgenet_disable_tx_napi(priv); 4345 bcmgenet_disable_rx_napi(priv); 4346 disable_irq(priv->irq1); 4347 bcmgenet_tx_reclaim_all(dev); 4348 bcmgenet_fini_tx_napi(priv); 4349 } else { 4350 /* Teardown the interface */ 4351 bcmgenet_netif_stop(dev, true); 4352 } 4353 4354 return 0; 4355 } 4356 4357 static int bcmgenet_suspend_noirq(struct device *d) 4358 { 4359 struct net_device *dev = dev_get_drvdata(d); 4360 struct bcmgenet_priv *priv = netdev_priv(dev); 4361 int ret = 0; 4362 4363 if (!netif_running(dev)) 4364 return 0; 4365 4366 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 4367 if (device_may_wakeup(d) && priv->wolopts) 4368 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 4369 else if (priv->internal_phy) 4370 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4371 4372 /* Let the framework handle resumption and leave the clocks on */ 4373 if (ret) 4374 return ret; 4375 4376 /* Turn off the clocks */ 4377 clk_disable_unprepare(priv->clk); 4378 4379 return 0; 4380 } 4381 #else 4382 #define bcmgenet_suspend NULL 4383 #define bcmgenet_suspend_noirq NULL 4384 #define bcmgenet_resume NULL 4385 #define bcmgenet_resume_noirq NULL 4386 #endif /* CONFIG_PM_SLEEP */ 4387 4388 static const struct dev_pm_ops bcmgenet_pm_ops = { 4389 .suspend = bcmgenet_suspend, 4390 .suspend_noirq = bcmgenet_suspend_noirq, 4391 .resume = bcmgenet_resume, 4392 .resume_noirq = bcmgenet_resume_noirq, 4393 }; 4394 4395 static const struct acpi_device_id genet_acpi_match[] = { 4396 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 4397 { }, 4398 }; 4399 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 4400 4401 static struct platform_driver bcmgenet_driver = { 4402 .probe = bcmgenet_probe, 4403 .remove = bcmgenet_remove, 4404 .shutdown = bcmgenet_shutdown, 4405 .driver = { 4406 .name = "bcmgenet", 4407 .of_match_table = bcmgenet_match, 4408 .pm = &bcmgenet_pm_ops, 4409 .acpi_match_table = genet_acpi_match, 4410 }, 4411 }; 4412 module_platform_driver(bcmgenet_driver); 4413 4414 MODULE_AUTHOR("Broadcom Corporation"); 4415 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 4416 MODULE_ALIAS("platform:bcmgenet"); 4417 MODULE_LICENSE("GPL"); 4418 MODULE_SOFTDEP("pre: mdio-bcm-unimac"); 4419