1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Defines for using and allocating DMA channels on the Alchemy
4 * Au1x00 MIPS processors.
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 */
30 #ifndef __ASM_AU1000_DMA_H
31 #define __ASM_AU1000_DMA_H
32
33 #include <linux/io.h> /* need byte IO */
34 #include <linux/spinlock.h> /* And spinlocks */
35 #include <linux/delay.h>
36
37 #define NUM_AU1000_DMA_CHANNELS 8
38
39 /* DMA Channel Register Offsets */
40 #define DMA_MODE_SET 0x00000000
41 #define DMA_MODE_READ DMA_MODE_SET
42 #define DMA_MODE_CLEAR 0x00000004
43 /* DMA Mode register bits follow */
44 #define DMA_DAH_MASK (0x0f << 20)
45 #define DMA_DID_BIT 16
46 #define DMA_DID_MASK (0x0f << DMA_DID_BIT)
47 #define DMA_DS (1 << 15)
48 #define DMA_BE (1 << 13)
49 #define DMA_DR (1 << 12)
50 #define DMA_TS8 (1 << 11)
51 #define DMA_DW_BIT 9
52 #define DMA_DW_MASK (0x03 << DMA_DW_BIT)
53 #define DMA_DW8 (0 << DMA_DW_BIT)
54 #define DMA_DW16 (1 << DMA_DW_BIT)
55 #define DMA_DW32 (2 << DMA_DW_BIT)
56 #define DMA_NC (1 << 8)
57 #define DMA_IE (1 << 7)
58 #define DMA_HALT (1 << 6)
59 #define DMA_GO (1 << 5)
60 #define DMA_AB (1 << 4)
61 #define DMA_D1 (1 << 3)
62 #define DMA_BE1 (1 << 2)
63 #define DMA_D0 (1 << 1)
64 #define DMA_BE0 (1 << 0)
65
66 #define DMA_PERIPHERAL_ADDR 0x00000008
67 #define DMA_BUFFER0_START 0x0000000C
68 #define DMA_BUFFER1_START 0x00000014
69 #define DMA_BUFFER0_COUNT 0x00000010
70 #define DMA_BUFFER1_COUNT 0x00000018
71 #define DMA_BAH_BIT 16
72 #define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
73 #define DMA_COUNT_BIT 0
74 #define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
75
76 /* DMA Device IDs follow */
77 enum {
78 DMA_ID_UART0_TX = 0,
79 DMA_ID_UART0_RX,
80 DMA_ID_GP04,
81 DMA_ID_GP05,
82 DMA_ID_AC97C_TX,
83 DMA_ID_AC97C_RX,
84 DMA_ID_UART3_TX,
85 DMA_ID_UART3_RX,
86 DMA_ID_USBDEV_EP0_RX,
87 DMA_ID_USBDEV_EP0_TX,
88 DMA_ID_USBDEV_EP2_TX,
89 DMA_ID_USBDEV_EP3_TX,
90 DMA_ID_USBDEV_EP4_RX,
91 DMA_ID_USBDEV_EP5_RX,
92 DMA_ID_I2S_TX,
93 DMA_ID_I2S_RX,
94 DMA_NUM_DEV
95 };
96
97 /* DMA Device ID's for 2nd bank (AU1100) follow */
98 enum {
99 DMA_ID_SD0_TX = 0,
100 DMA_ID_SD0_RX,
101 DMA_ID_SD1_TX,
102 DMA_ID_SD1_RX,
103 DMA_NUM_DEV_BANK2
104 };
105
106 struct dma_chan {
107 int dev_id; /* this channel is allocated if >= 0, */
108 /* free otherwise */
109 void __iomem *io;
110 const char *dev_str;
111 int irq;
112 void *irq_dev;
113 unsigned int fifo_addr;
114 unsigned int mode;
115 };
116
117 /* These are in arch/mips/au1000/common/dma.c */
118 extern struct dma_chan au1000_dma_table[];
119 extern int request_au1000_dma(int dev_id,
120 const char *dev_str,
121 irq_handler_t irqhandler,
122 unsigned long irqflags,
123 void *irq_dev_id);
124 extern void free_au1000_dma(unsigned int dmanr);
125 extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
126 int length, int *eof, void *data);
127 extern spinlock_t au1000_dma_spin_lock;
128
get_dma_chan(unsigned int dmanr)129 static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
130 {
131 if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
132 au1000_dma_table[dmanr].dev_id < 0)
133 return NULL;
134 return &au1000_dma_table[dmanr];
135 }
136
claim_dma_lock(void)137 static inline unsigned long claim_dma_lock(void)
138 {
139 unsigned long flags;
140
141 spin_lock_irqsave(&au1000_dma_spin_lock, flags);
142 return flags;
143 }
144
release_dma_lock(unsigned long flags)145 static inline void release_dma_lock(unsigned long flags)
146 {
147 spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
148 }
149
150 /*
151 * Set the DMA buffer enable bits in the mode register.
152 */
enable_dma_buffer0(unsigned int dmanr)153 static inline void enable_dma_buffer0(unsigned int dmanr)
154 {
155 struct dma_chan *chan = get_dma_chan(dmanr);
156
157 if (!chan)
158 return;
159 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);
160 }
161
enable_dma_buffer1(unsigned int dmanr)162 static inline void enable_dma_buffer1(unsigned int dmanr)
163 {
164 struct dma_chan *chan = get_dma_chan(dmanr);
165
166 if (!chan)
167 return;
168 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);
169 }
enable_dma_buffers(unsigned int dmanr)170 static inline void enable_dma_buffers(unsigned int dmanr)
171 {
172 struct dma_chan *chan = get_dma_chan(dmanr);
173
174 if (!chan)
175 return;
176 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
177 }
178
start_dma(unsigned int dmanr)179 static inline void start_dma(unsigned int dmanr)
180 {
181 struct dma_chan *chan = get_dma_chan(dmanr);
182
183 if (!chan)
184 return;
185 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET);
186 }
187
188 #define DMA_HALT_POLL 0x5000
189
halt_dma(unsigned int dmanr)190 static inline void halt_dma(unsigned int dmanr)
191 {
192 struct dma_chan *chan = get_dma_chan(dmanr);
193 int i;
194
195 if (!chan)
196 return;
197 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
198
199 /* Poll the halt bit */
200 for (i = 0; i < DMA_HALT_POLL; i++)
201 if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
202 break;
203 if (i == DMA_HALT_POLL)
204 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
205 }
206
disable_dma(unsigned int dmanr)207 static inline void disable_dma(unsigned int dmanr)
208 {
209 struct dma_chan *chan = get_dma_chan(dmanr);
210
211 if (!chan)
212 return;
213
214 halt_dma(dmanr);
215
216 /* Now we can disable the buffers */
217 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
218 }
219
dma_halted(unsigned int dmanr)220 static inline int dma_halted(unsigned int dmanr)
221 {
222 struct dma_chan *chan = get_dma_chan(dmanr);
223
224 if (!chan)
225 return 1;
226 return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
227 }
228
229 /* Initialize a DMA channel. */
init_dma(unsigned int dmanr)230 static inline void init_dma(unsigned int dmanr)
231 {
232 struct dma_chan *chan = get_dma_chan(dmanr);
233 u32 mode;
234
235 if (!chan)
236 return;
237
238 disable_dma(dmanr);
239
240 /* Set device FIFO address */
241 __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
242
243 mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
244 if (chan->irq)
245 mode |= DMA_IE;
246
247 __raw_writel(~mode, chan->io + DMA_MODE_CLEAR);
248 __raw_writel(mode, chan->io + DMA_MODE_SET);
249 }
250
251 /*
252 * Set mode for a specific DMA channel
253 */
set_dma_mode(unsigned int dmanr,unsigned int mode)254 static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
255 {
256 struct dma_chan *chan = get_dma_chan(dmanr);
257
258 if (!chan)
259 return;
260 /*
261 * set_dma_mode is only allowed to change endianness, direction,
262 * transfer size, device FIFO width, and coherency settings.
263 * Make sure anything else is masked off.
264 */
265 mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
266 chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
267 chan->mode |= mode;
268 }
269
get_dma_mode(unsigned int dmanr)270 static inline unsigned int get_dma_mode(unsigned int dmanr)
271 {
272 struct dma_chan *chan = get_dma_chan(dmanr);
273
274 if (!chan)
275 return 0;
276 return chan->mode;
277 }
278
get_dma_active_buffer(unsigned int dmanr)279 static inline int get_dma_active_buffer(unsigned int dmanr)
280 {
281 struct dma_chan *chan = get_dma_chan(dmanr);
282
283 if (!chan)
284 return -1;
285 return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
286 }
287
288 /*
289 * Set the device FIFO address for a specific DMA channel - only
290 * applicable to GPO4 and GPO5. All the other devices have fixed
291 * FIFO addresses.
292 */
set_dma_fifo_addr(unsigned int dmanr,unsigned int a)293 static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
294 {
295 struct dma_chan *chan = get_dma_chan(dmanr);
296
297 if (!chan)
298 return;
299
300 if (chan->mode & DMA_DS) /* second bank of device IDs */
301 return;
302
303 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
304 return;
305
306 __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
307 }
308
309 /*
310 * Clear the DMA buffer done bits in the mode register.
311 */
clear_dma_done0(unsigned int dmanr)312 static inline void clear_dma_done0(unsigned int dmanr)
313 {
314 struct dma_chan *chan = get_dma_chan(dmanr);
315
316 if (!chan)
317 return;
318 __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
319 }
320
clear_dma_done1(unsigned int dmanr)321 static inline void clear_dma_done1(unsigned int dmanr)
322 {
323 struct dma_chan *chan = get_dma_chan(dmanr);
324
325 if (!chan)
326 return;
327 __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
328 }
329
330 /*
331 * This does nothing - not applicable to Au1000 DMA.
332 */
set_dma_page(unsigned int dmanr,char pagenr)333 static inline void set_dma_page(unsigned int dmanr, char pagenr)
334 {
335 }
336
337 /*
338 * Set Buffer 0 transfer address for specific DMA channel.
339 */
set_dma_addr0(unsigned int dmanr,unsigned int a)340 static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
341 {
342 struct dma_chan *chan = get_dma_chan(dmanr);
343
344 if (!chan)
345 return;
346 __raw_writel(a, chan->io + DMA_BUFFER0_START);
347 }
348
349 /*
350 * Set Buffer 1 transfer address for specific DMA channel.
351 */
set_dma_addr1(unsigned int dmanr,unsigned int a)352 static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
353 {
354 struct dma_chan *chan = get_dma_chan(dmanr);
355
356 if (!chan)
357 return;
358 __raw_writel(a, chan->io + DMA_BUFFER1_START);
359 }
360
361
362 /*
363 * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
364 */
set_dma_count0(unsigned int dmanr,unsigned int count)365 static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
366 {
367 struct dma_chan *chan = get_dma_chan(dmanr);
368
369 if (!chan)
370 return;
371 count &= DMA_COUNT_MASK;
372 __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
373 }
374
375 /*
376 * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
377 */
set_dma_count1(unsigned int dmanr,unsigned int count)378 static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
379 {
380 struct dma_chan *chan = get_dma_chan(dmanr);
381
382 if (!chan)
383 return;
384 count &= DMA_COUNT_MASK;
385 __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
386 }
387
388 /*
389 * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
390 */
set_dma_count(unsigned int dmanr,unsigned int count)391 static inline void set_dma_count(unsigned int dmanr, unsigned int count)
392 {
393 struct dma_chan *chan = get_dma_chan(dmanr);
394
395 if (!chan)
396 return;
397 count &= DMA_COUNT_MASK;
398 __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
399 __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
400 }
401
402 /*
403 * Returns which buffer has its done bit set in the mode register.
404 * Returns -1 if neither or both done bits set.
405 */
get_dma_buffer_done(unsigned int dmanr)406 static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
407 {
408 struct dma_chan *chan = get_dma_chan(dmanr);
409
410 if (!chan)
411 return 0;
412 return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
413 }
414
415
416 /*
417 * Returns the DMA channel's Buffer Done IRQ number.
418 */
get_dma_done_irq(unsigned int dmanr)419 static inline int get_dma_done_irq(unsigned int dmanr)
420 {
421 struct dma_chan *chan = get_dma_chan(dmanr);
422
423 if (!chan)
424 return -1;
425 return chan->irq;
426 }
427
428 /*
429 * Get DMA residue count. Returns the number of _bytes_ left to transfer.
430 */
get_dma_residue(unsigned int dmanr)431 static inline int get_dma_residue(unsigned int dmanr)
432 {
433 int curBufCntReg, count;
434 struct dma_chan *chan = get_dma_chan(dmanr);
435
436 if (!chan)
437 return 0;
438
439 curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
440 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
441
442 count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
443
444 if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
445 count <<= 1;
446 else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
447 count <<= 2;
448
449 return count;
450 }
451
452 #endif /* __ASM_AU1000_DMA_H */
453