1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DWMAC4 DMA Header file. 4 * 5 * Copyright (C) 2007-2015 STMicroelectronics Ltd 6 * 7 * Author: Alexandre Torgue <alexandre.torgue@st.com> 8 */ 9 10 #ifndef __DWMAC4_DMA_H__ 11 #define __DWMAC4_DMA_H__ 12 13 /* Define the max channel number used for tx (also rx). 14 * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX 15 */ 16 #define DMA_CHANNEL_NB_MAX 1 17 18 #define DMA_BUS_MODE 0x00001000 19 #define DMA_SYS_BUS_MODE 0x00001004 20 #define DMA_STATUS 0x00001008 21 #define DMA_DEBUG_STATUS_0 0x0000100c 22 #define DMA_DEBUG_STATUS_1 0x00001010 23 #define DMA_DEBUG_STATUS_2 0x00001014 24 #define DMA_AXI_BUS_MODE 0x00001028 25 #define DMA_TBS_CTRL 0x00001050 26 27 /* DMA Bus Mode bitmap */ 28 #define DMA_BUS_MODE_DCHE BIT(19) 29 #define DMA_BUS_MODE_INTM_MASK GENMASK(17, 16) 30 #define DMA_BUS_MODE_INTM_SHIFT 16 31 #define DMA_BUS_MODE_INTM_MODE1 0x1 32 #define DMA_BUS_MODE_SFT_RESET BIT(0) 33 34 /* DMA SYS Bus Mode bitmap */ 35 #define DMA_BUS_MODE_SPH BIT(24) 36 #define DMA_BUS_MODE_PBL BIT(16) 37 #define DMA_BUS_MODE_PBL_SHIFT 16 38 #define DMA_BUS_MODE_RPBL_SHIFT 16 39 #define DMA_BUS_MODE_MB BIT(14) 40 #define DMA_BUS_MODE_FB BIT(0) 41 42 /* DMA Interrupt top status */ 43 #define DMA_STATUS_MAC BIT(17) 44 #define DMA_STATUS_MTL BIT(16) 45 #define DMA_STATUS_CHAN7 BIT(7) 46 #define DMA_STATUS_CHAN6 BIT(6) 47 #define DMA_STATUS_CHAN5 BIT(5) 48 #define DMA_STATUS_CHAN4 BIT(4) 49 #define DMA_STATUS_CHAN3 BIT(3) 50 #define DMA_STATUS_CHAN2 BIT(2) 51 #define DMA_STATUS_CHAN1 BIT(1) 52 #define DMA_STATUS_CHAN0 BIT(0) 53 54 /* DMA debug status bitmap */ 55 #define DMA_DEBUG_STATUS_TS_MASK 0xf 56 #define DMA_DEBUG_STATUS_RS_MASK 0xf 57 58 /* DMA AXI bitmap */ 59 #define DMA_AXI_EN_LPI BIT(31) 60 #define DMA_AXI_LPI_XIT_FRM BIT(30) 61 #define DMA_AXI_WR_OSR_LMT GENMASK(27, 24) 62 #define DMA_AXI_WR_OSR_LMT_SHIFT 24 63 #define DMA_AXI_RD_OSR_LMT GENMASK(19, 16) 64 #define DMA_AXI_RD_OSR_LMT_SHIFT 16 65 66 #define DMA_AXI_OSR_MAX 0xf 67 #define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \ 68 (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT)) 69 70 #define DMA_SYS_BUS_MB BIT(14) 71 #define DMA_AXI_1KBBE BIT(13) 72 #define DMA_SYS_BUS_AAL DMA_AXI_AAL 73 #define DMA_SYS_BUS_EAME BIT(11) 74 #define DMA_SYS_BUS_FB BIT(0) 75 76 #define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \ 77 DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \ 78 DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \ 79 DMA_AXI_BLEN4) 80 81 /* DMA TBS Control */ 82 #define DMA_TBS_FTOS GENMASK(31, 8) 83 #define DMA_TBS_FTOV BIT(0) 84 #define DMA_TBS_DEF_FTOS (DMA_TBS_FTOS | DMA_TBS_FTOV) 85 86 /* Following DMA defines are channel-oriented */ 87 #define DMA_CHAN_BASE_ADDR 0x00001100 88 #define DMA_CHAN_BASE_OFFSET 0x80 89 90 static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs, 91 const u32 x) 92 { 93 u32 addr; 94 95 if (addrs) 96 addr = addrs->dma_chan + (x * addrs->dma_chan_offset); 97 else 98 addr = DMA_CHAN_BASE_ADDR + (x * DMA_CHAN_BASE_OFFSET); 99 100 return addr; 101 } 102 103 #define DMA_CHAN_REG_NUMBER 17 104 105 #define DMA_CHAN_CONTROL(addrs, x) dma_chanx_base_addr(addrs, x) 106 #define DMA_CHAN_TX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4) 107 #define DMA_CHAN_RX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x8) 108 #define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x10) 109 #define DMA_CHAN_TX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x14) 110 #define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x18) 111 #define DMA_CHAN_RX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x1c) 112 #define DMA_CHAN_TX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x20) 113 #define DMA_CHAN_RX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x28) 114 #define DMA_CHAN_TX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x2c) 115 #define DMA_CHAN_RX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x30) 116 #define DMA_CHAN_INTR_ENA(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x34) 117 #define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38) 118 #define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x3c) 119 #define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x44) 120 #define DMA_CHAN_CUR_RX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4c) 121 #define DMA_CHAN_CUR_TX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x50) 122 #define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x54) 123 #define DMA_CHAN_CUR_RX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x58) 124 #define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x5c) 125 #define DMA_CHAN_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x60) 126 127 /* DMA Control X */ 128 #define DMA_CONTROL_SPH BIT(24) 129 #define DMA_CONTROL_MSS_MASK GENMASK(13, 0) 130 131 /* DMA Tx Channel X Control register defines */ 132 #define DMA_CONTROL_EDSE BIT(28) 133 #define DMA_CONTROL_TSE BIT(12) 134 #define DMA_CONTROL_OSP BIT(4) 135 #define DMA_CONTROL_ST BIT(0) 136 137 /* DMA Rx Channel X Control register defines */ 138 #define DMA_CONTROL_SR BIT(0) 139 #define DMA_RBSZ_MASK GENMASK(14, 1) 140 #define DMA_RBSZ_SHIFT 1 141 142 /* Interrupt status per channel */ 143 #define DMA_CHAN_STATUS_REB GENMASK(21, 19) 144 #define DMA_CHAN_STATUS_REB_SHIFT 19 145 #define DMA_CHAN_STATUS_TEB GENMASK(18, 16) 146 #define DMA_CHAN_STATUS_TEB_SHIFT 16 147 #define DMA_CHAN_STATUS_NIS BIT(15) 148 #define DMA_CHAN_STATUS_AIS BIT(14) 149 #define DMA_CHAN_STATUS_CDE BIT(13) 150 #define DMA_CHAN_STATUS_FBE BIT(12) 151 #define DMA_CHAN_STATUS_ERI BIT(11) 152 #define DMA_CHAN_STATUS_ETI BIT(10) 153 #define DMA_CHAN_STATUS_RWT BIT(9) 154 #define DMA_CHAN_STATUS_RPS BIT(8) 155 #define DMA_CHAN_STATUS_RBU BIT(7) 156 #define DMA_CHAN_STATUS_RI BIT(6) 157 #define DMA_CHAN_STATUS_TBU BIT(2) 158 #define DMA_CHAN_STATUS_TPS BIT(1) 159 #define DMA_CHAN_STATUS_TI BIT(0) 160 161 #define DMA_CHAN_STATUS_MSK_COMMON (DMA_CHAN_STATUS_NIS | \ 162 DMA_CHAN_STATUS_AIS | \ 163 DMA_CHAN_STATUS_CDE | \ 164 DMA_CHAN_STATUS_FBE) 165 166 #define DMA_CHAN_STATUS_MSK_RX (DMA_CHAN_STATUS_REB | \ 167 DMA_CHAN_STATUS_ERI | \ 168 DMA_CHAN_STATUS_RWT | \ 169 DMA_CHAN_STATUS_RPS | \ 170 DMA_CHAN_STATUS_RBU | \ 171 DMA_CHAN_STATUS_RI | \ 172 DMA_CHAN_STATUS_MSK_COMMON) 173 174 #define DMA_CHAN_STATUS_MSK_TX (DMA_CHAN_STATUS_ETI | \ 175 DMA_CHAN_STATUS_TBU | \ 176 DMA_CHAN_STATUS_TPS | \ 177 DMA_CHAN_STATUS_TI | \ 178 DMA_CHAN_STATUS_MSK_COMMON) 179 180 /* Interrupt enable bits per channel */ 181 #define DMA_CHAN_INTR_ENA_NIE BIT(16) 182 #define DMA_CHAN_INTR_ENA_AIE BIT(15) 183 #define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15) 184 #define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14) 185 #define DMA_CHAN_INTR_ENA_CDE BIT(13) 186 #define DMA_CHAN_INTR_ENA_FBE BIT(12) 187 #define DMA_CHAN_INTR_ENA_ERE BIT(11) 188 #define DMA_CHAN_INTR_ENA_ETE BIT(10) 189 #define DMA_CHAN_INTR_ENA_RWE BIT(9) 190 #define DMA_CHAN_INTR_ENA_RSE BIT(8) 191 #define DMA_CHAN_INTR_ENA_RBUE BIT(7) 192 #define DMA_CHAN_INTR_ENA_RIE BIT(6) 193 #define DMA_CHAN_INTR_ENA_TBUE BIT(2) 194 #define DMA_CHAN_INTR_ENA_TSE BIT(1) 195 #define DMA_CHAN_INTR_ENA_TIE BIT(0) 196 197 #define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \ 198 DMA_CHAN_INTR_ENA_RIE | \ 199 DMA_CHAN_INTR_ENA_TIE) 200 201 #define DMA_CHAN_INTR_ABNORMAL (DMA_CHAN_INTR_ENA_AIE | \ 202 DMA_CHAN_INTR_ENA_FBE) 203 /* DMA default interrupt mask for 4.00 */ 204 #define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \ 205 DMA_CHAN_INTR_ABNORMAL) 206 #define DMA_CHAN_INTR_DEFAULT_RX (DMA_CHAN_INTR_ENA_RIE) 207 #define DMA_CHAN_INTR_DEFAULT_TX (DMA_CHAN_INTR_ENA_TIE) 208 209 #define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \ 210 DMA_CHAN_INTR_ENA_RIE | \ 211 DMA_CHAN_INTR_ENA_TIE) 212 213 #define DMA_CHAN_INTR_ABNORMAL_4_10 (DMA_CHAN_INTR_ENA_AIE_4_10 | \ 214 DMA_CHAN_INTR_ENA_FBE) 215 /* DMA default interrupt mask for 4.10a */ 216 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \ 217 DMA_CHAN_INTR_ABNORMAL_4_10) 218 #define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE) 219 #define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE) 220 221 /* channel 0 specific fields */ 222 #define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12) 223 #define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12 224 #define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8) 225 #define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8 226 227 int dwmac4_dma_reset(void __iomem *ioaddr); 228 void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 229 u32 chan, bool rx, bool tx); 230 void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 231 u32 chan, bool rx, bool tx); 232 void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 233 u32 chan, bool rx, bool tx); 234 void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, 235 u32 chan, bool rx, bool tx); 236 void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, 237 u32 chan); 238 void dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, 239 u32 chan); 240 void dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, 241 u32 chan); 242 void dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, 243 u32 chan); 244 int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, 245 struct stmmac_extra_stats *x, u32 chan, u32 dir); 246 void dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, 247 u32 len, u32 chan); 248 void dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, 249 u32 len, u32 chan); 250 void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, 251 u32 tail_ptr, u32 chan); 252 void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, 253 u32 tail_ptr, u32 chan); 254 255 #endif /* __DWMAC4_DMA_H__ */ 256