1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DMA0_CORE_MASKS_H_ 14 #define ASIC_REG_DMA0_CORE_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DMA0_CORE (Prototype: DMA_CORE) 19 ***************************************** 20 */ 21 22 /* DMA0_CORE_CFG_0 */ 23 #define DMA0_CORE_CFG_0_EN_SHIFT 0 24 #define DMA0_CORE_CFG_0_EN_MASK 0x1 25 26 /* DMA0_CORE_CFG_1 */ 27 #define DMA0_CORE_CFG_1_HALT_SHIFT 0 28 #define DMA0_CORE_CFG_1_HALT_MASK 0x1 29 #define DMA0_CORE_CFG_1_FLUSH_SHIFT 1 30 #define DMA0_CORE_CFG_1_FLUSH_MASK 0x2 31 #define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT 2 32 #define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK 0x4 33 34 /* DMA0_CORE_LBW_MAX_OUTSTAND */ 35 #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT 0 36 #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK 0x1F 37 38 /* DMA0_CORE_SRC_BASE_LO */ 39 #define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT 0 40 #define DMA0_CORE_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF 41 42 /* DMA0_CORE_SRC_BASE_HI */ 43 #define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT 0 44 #define DMA0_CORE_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF 45 46 /* DMA0_CORE_DST_BASE_LO */ 47 #define DMA0_CORE_DST_BASE_LO_VAL_SHIFT 0 48 #define DMA0_CORE_DST_BASE_LO_VAL_MASK 0xFFFFFFFF 49 50 /* DMA0_CORE_DST_BASE_HI */ 51 #define DMA0_CORE_DST_BASE_HI_VAL_SHIFT 0 52 #define DMA0_CORE_DST_BASE_HI_VAL_MASK 0xFFFFFF 53 #define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT 24 54 #define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK 0xFF000000 55 56 /* DMA0_CORE_SRC_TSIZE_1 */ 57 #define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT 0 58 #define DMA0_CORE_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF 59 60 /* DMA0_CORE_SRC_STRIDE_1 */ 61 #define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT 0 62 #define DMA0_CORE_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF 63 64 /* DMA0_CORE_SRC_TSIZE_2 */ 65 #define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT 0 66 #define DMA0_CORE_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF 67 68 /* DMA0_CORE_SRC_STRIDE_2 */ 69 #define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT 0 70 #define DMA0_CORE_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF 71 72 /* DMA0_CORE_SRC_TSIZE_3 */ 73 #define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT 0 74 #define DMA0_CORE_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF 75 76 /* DMA0_CORE_SRC_STRIDE_3 */ 77 #define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT 0 78 #define DMA0_CORE_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF 79 80 /* DMA0_CORE_SRC_TSIZE_4 */ 81 #define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT 0 82 #define DMA0_CORE_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF 83 84 /* DMA0_CORE_SRC_STRIDE_4 */ 85 #define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT 0 86 #define DMA0_CORE_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF 87 88 /* DMA0_CORE_SRC_TSIZE_0 */ 89 #define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT 0 90 #define DMA0_CORE_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF 91 92 /* DMA0_CORE_DST_TSIZE_1 */ 93 #define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT 0 94 #define DMA0_CORE_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF 95 96 /* DMA0_CORE_DST_STRIDE_1 */ 97 #define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT 0 98 #define DMA0_CORE_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF 99 100 /* DMA0_CORE_DST_TSIZE_2 */ 101 #define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT 0 102 #define DMA0_CORE_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF 103 104 /* DMA0_CORE_DST_STRIDE_2 */ 105 #define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT 0 106 #define DMA0_CORE_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF 107 108 /* DMA0_CORE_DST_TSIZE_3 */ 109 #define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT 0 110 #define DMA0_CORE_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF 111 112 /* DMA0_CORE_DST_STRIDE_3 */ 113 #define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT 0 114 #define DMA0_CORE_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF 115 116 /* DMA0_CORE_DST_TSIZE_4 */ 117 #define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT 0 118 #define DMA0_CORE_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF 119 120 /* DMA0_CORE_DST_STRIDE_4 */ 121 #define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT 0 122 #define DMA0_CORE_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF 123 124 /* DMA0_CORE_DST_TSIZE_0 */ 125 #define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT 0 126 #define DMA0_CORE_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF 127 128 /* DMA0_CORE_COMMIT */ 129 #define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT 0 130 #define DMA0_CORE_COMMIT_WR_COMP_EN_MASK 0x1 131 #define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT 1 132 #define DMA0_CORE_COMMIT_TRANSPOSE_MASK 0x2 133 #define DMA0_CORE_COMMIT_DTYPE_SHIFT 2 134 #define DMA0_CORE_COMMIT_DTYPE_MASK 0x4 135 #define DMA0_CORE_COMMIT_LIN_SHIFT 3 136 #define DMA0_CORE_COMMIT_LIN_MASK 0x8 137 #define DMA0_CORE_COMMIT_MEM_SET_SHIFT 4 138 #define DMA0_CORE_COMMIT_MEM_SET_MASK 0x10 139 #define DMA0_CORE_COMMIT_COMPRESS_SHIFT 5 140 #define DMA0_CORE_COMMIT_COMPRESS_MASK 0x20 141 #define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT 6 142 #define DMA0_CORE_COMMIT_DECOMPRESS_MASK 0x40 143 #define DMA0_CORE_COMMIT_CTX_ID_SHIFT 16 144 #define DMA0_CORE_COMMIT_CTX_ID_MASK 0xFF0000 145 146 /* DMA0_CORE_WR_COMP_WDATA */ 147 #define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT 0 148 #define DMA0_CORE_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF 149 150 /* DMA0_CORE_WR_COMP_ADDR_LO */ 151 #define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT 0 152 #define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF 153 154 /* DMA0_CORE_WR_COMP_ADDR_HI */ 155 #define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT 0 156 #define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF 157 158 /* DMA0_CORE_WR_COMP_AWUSER_31_11 */ 159 #define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT 0 160 #define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK 0x1FFFFF 161 162 /* DMA0_CORE_TE_NUMROWS */ 163 #define DMA0_CORE_TE_NUMROWS_VAL_SHIFT 0 164 #define DMA0_CORE_TE_NUMROWS_VAL_MASK 0xFFFFFFFF 165 166 /* DMA0_CORE_PROT */ 167 #define DMA0_CORE_PROT_VAL_SHIFT 0 168 #define DMA0_CORE_PROT_VAL_MASK 0x1 169 #define DMA0_CORE_PROT_ERR_VAL_SHIFT 1 170 #define DMA0_CORE_PROT_ERR_VAL_MASK 0x2 171 172 /* DMA0_CORE_SECURE_PROPS */ 173 #define DMA0_CORE_SECURE_PROPS_ASID_SHIFT 0 174 #define DMA0_CORE_SECURE_PROPS_ASID_MASK 0x3FF 175 #define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT 10 176 #define DMA0_CORE_SECURE_PROPS_MMBP_MASK 0x400 177 178 /* DMA0_CORE_NON_SECURE_PROPS */ 179 #define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT 0 180 #define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK 0x3FF 181 #define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT 10 182 #define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK 0x400 183 184 /* DMA0_CORE_RD_MAX_OUTSTAND */ 185 #define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT 0 186 #define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK 0xFFF 187 188 /* DMA0_CORE_RD_MAX_SIZE */ 189 #define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT 0 190 #define DMA0_CORE_RD_MAX_SIZE_DATA_MASK 0x7FF 191 #define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT 16 192 #define DMA0_CORE_RD_MAX_SIZE_MD_MASK 0x7FF0000 193 194 /* DMA0_CORE_RD_ARCACHE */ 195 #define DMA0_CORE_RD_ARCACHE_VAL_SHIFT 0 196 #define DMA0_CORE_RD_ARCACHE_VAL_MASK 0xF 197 198 /* DMA0_CORE_RD_ARUSER_31_11 */ 199 #define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT 0 200 #define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK 0x1FFFFF 201 202 /* DMA0_CORE_RD_INFLIGHTS */ 203 #define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT 0 204 #define DMA0_CORE_RD_INFLIGHTS_VAL_MASK 0xFFFFFFFF 205 206 /* DMA0_CORE_WR_MAX_OUTSTAND */ 207 #define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT 0 208 #define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK 0xFFF 209 210 /* DMA0_CORE_WR_MAX_AWID */ 211 #define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT 0 212 #define DMA0_CORE_WR_MAX_AWID_VAL_MASK 0xFFFF 213 214 /* DMA0_CORE_WR_AWCACHE */ 215 #define DMA0_CORE_WR_AWCACHE_VAL_SHIFT 0 216 #define DMA0_CORE_WR_AWCACHE_VAL_MASK 0xF 217 218 /* DMA0_CORE_WR_AWUSER_31_11 */ 219 #define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT 0 220 #define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK 0x1FFFFF 221 222 /* DMA0_CORE_WR_INFLIGHTS */ 223 #define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT 0 224 #define DMA0_CORE_WR_INFLIGHTS_VAL_MASK 0xFFFF 225 226 /* DMA0_CORE_RD_RATE_LIM_CFG_0 */ 227 #define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 228 #define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 229 #define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 230 #define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 231 232 /* DMA0_CORE_RD_RATE_LIM_CFG_1 */ 233 #define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 234 #define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF 235 #define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT 31 236 #define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 237 238 /* DMA0_CORE_WR_RATE_LIM_CFG_0 */ 239 #define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 240 #define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 241 #define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 242 #define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 243 244 /* DMA0_CORE_WR_RATE_LIM_CFG_1 */ 245 #define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 246 #define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF 247 #define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT 31 248 #define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 249 250 /* DMA0_CORE_ERR_CFG */ 251 #define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 252 #define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 253 #define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 254 #define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 255 256 /* DMA0_CORE_ERR_CAUSE */ 257 #define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 258 #define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 259 #define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 260 #define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 261 #define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 2 262 #define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x4 263 #define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 264 #define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 265 266 /* DMA0_CORE_ERRMSG_ADDR_LO */ 267 #define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 268 #define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF 269 270 /* DMA0_CORE_ERRMSG_ADDR_HI */ 271 #define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 272 #define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF 273 274 /* DMA0_CORE_ERRMSG_WDATA */ 275 #define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 276 #define DMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF 277 278 /* DMA0_CORE_STS0 */ 279 #define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 280 #define DMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF 281 #define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 282 #define DMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 283 #define DMA0_CORE_STS0_BUSY_SHIFT 31 284 #define DMA0_CORE_STS0_BUSY_MASK 0x80000000 285 286 /* DMA0_CORE_STS1 */ 287 #define DMA0_CORE_STS1_IS_HALT_SHIFT 0 288 #define DMA0_CORE_STS1_IS_HALT_MASK 0x1 289 290 /* DMA0_CORE_RD_DBGMEM_ADD */ 291 #define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT 0 292 #define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK 0xFFFFFFFF 293 294 /* DMA0_CORE_RD_DBGMEM_DATA_WR */ 295 #define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT 0 296 #define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK 0xFFFFFFFF 297 298 /* DMA0_CORE_RD_DBGMEM_DATA_RD */ 299 #define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT 0 300 #define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK 0xFFFFFFFF 301 302 /* DMA0_CORE_RD_DBGMEM_CTRL */ 303 #define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT 0 304 #define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK 0x1 305 306 /* DMA0_CORE_RD_DBGMEM_RC */ 307 #define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT 0 308 #define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK 0x1 309 310 /* DMA0_CORE_DBG_HBW_AXI_AR_CNT */ 311 312 /* DMA0_CORE_DBG_HBW_AXI_AW_CNT */ 313 314 /* DMA0_CORE_DBG_LBW_AXI_AW_CNT */ 315 316 /* DMA0_CORE_DBG_DESC_CNT */ 317 #define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT 0 318 #define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK 0xFFFFFFFF 319 320 /* DMA0_CORE_DBG_STS */ 321 #define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 322 #define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 323 #define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 324 #define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 325 #define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 326 #define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 327 #define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 328 #define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 329 #define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 330 #define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 331 #define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 332 #define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 333 #define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 334 #define DMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 335 #define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 336 #define DMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 337 #define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 338 #define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 339 #define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 340 #define DMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 341 #define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT 20 342 #define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK 0x7FF00000 343 344 /* DMA0_CORE_DBG_RD_DESC_ID */ 345 346 /* DMA0_CORE_DBG_WR_DESC_ID */ 347 348 #endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */ 349