1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MTK_MMSYS_H 4 #define __SOC_MEDIATEK_MTK_MMSYS_H 5 6 #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 7 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 8 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 9 #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c 10 #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 11 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 12 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 13 #define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 14 #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 15 #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac 16 #define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 17 #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 18 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 19 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 20 21 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 22 #define DISP_REG_CONFIG_OUT_SEL 0x04c 23 #define DISP_REG_CONFIG_DSI_SEL 0x050 24 #define DISP_REG_CONFIG_DPI_SEL 0x064 25 26 #define OVL0_MOUT_EN_COLOR0 0x1 27 #define OD_MOUT_EN_RDMA0 0x1 28 #define OD1_MOUT_EN_RDMA1 BIT(16) 29 #define UFOE_MOUT_EN_DSI0 0x1 30 #define COLOR0_SEL_IN_OVL0 0x1 31 #define OVL1_MOUT_EN_COLOR1 0x1 32 #define GAMMA_MOUT_EN_RDMA1 0x1 33 #define RDMA0_SOUT_DPI0 0x2 34 #define RDMA0_SOUT_DPI1 0x3 35 #define RDMA0_SOUT_DSI1 0x1 36 #define RDMA0_SOUT_DSI2 0x4 37 #define RDMA0_SOUT_DSI3 0x5 38 #define RDMA0_SOUT_MASK 0x7 39 #define RDMA1_SOUT_DPI0 0x2 40 #define RDMA1_SOUT_DPI1 0x3 41 #define RDMA1_SOUT_DSI1 0x1 42 #define RDMA1_SOUT_DSI2 0x4 43 #define RDMA1_SOUT_DSI3 0x5 44 #define RDMA1_SOUT_MASK 0x7 45 #define RDMA2_SOUT_DPI0 0x2 46 #define RDMA2_SOUT_DPI1 0x3 47 #define RDMA2_SOUT_DSI1 0x1 48 #define RDMA2_SOUT_DSI2 0x4 49 #define RDMA2_SOUT_DSI3 0x5 50 #define RDMA2_SOUT_MASK 0x7 51 #define DPI0_SEL_IN_RDMA1 0x1 52 #define DPI0_SEL_IN_RDMA2 0x3 53 #define DPI0_SEL_IN_MASK 0x3 54 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) 55 #define DPI1_SEL_IN_RDMA2 (0x3 << 8) 56 #define DPI1_SEL_IN_MASK (0x3 << 8) 57 #define DSI0_SEL_IN_RDMA1 0x1 58 #define DSI0_SEL_IN_RDMA2 0x4 59 #define DSI0_SEL_IN_MASK 0x7 60 #define DSI1_SEL_IN_RDMA1 0x1 61 #define DSI1_SEL_IN_RDMA2 0x4 62 #define DSI1_SEL_IN_MASK 0x7 63 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) 64 #define DSI2_SEL_IN_RDMA2 (0x4 << 16) 65 #define DSI2_SEL_IN_MASK (0x7 << 16) 66 #define DSI3_SEL_IN_RDMA1 (0x1 << 16) 67 #define DSI3_SEL_IN_RDMA2 (0x4 << 16) 68 #define DSI3_SEL_IN_MASK (0x7 << 16) 69 #define COLOR1_SEL_IN_OVL1 0x1 70 71 #define OVL_MOUT_EN_RDMA 0x1 72 #define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 73 #define BLS_TO_DPI_RDMA1_TO_DSI 0x2 74 #define BLS_RDMA1_DSI_DPI_MASK 0xf 75 #define DSI_SEL_IN_BLS 0x0 76 #define DPI_SEL_IN_BLS 0x0 77 #define DPI_SEL_IN_MASK 0x1 78 #define DSI_SEL_IN_RDMA 0x1 79 #define DSI_SEL_IN_MASK 0x1 80 81 #define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit)) 82 83 /* 84 * This macro adds a compile time check to make sure that the in/out 85 * selection bit(s) fit in the register mask, similar to bitfield 86 * macros, but this does not transform the value. 87 */ 88 #define MMSYS_ROUTE(from, to, reg_addr, reg_mask, selection) \ 89 { DDP_COMPONENT_##from, DDP_COMPONENT_##to, reg_addr, reg_mask, \ 90 (__BUILD_BUG_ON_ZERO_MSG((reg_mask) == 0, "Invalid mask") + \ 91 __BUILD_BUG_ON_ZERO_MSG(~(reg_mask) & (selection), \ 92 #selection " does not fit in " \ 93 #reg_mask) + \ 94 (selection)) \ 95 } 96 97 struct mtk_mmsys_routes { 98 u32 from_comp; 99 u32 to_comp; 100 u32 addr; 101 u32 mask; 102 u32 val; 103 }; 104 105 /** 106 * struct mtk_mmsys_driver_data - Settings of the mmsys 107 * @clk_driver: Clock driver name that the mmsys is using 108 * (defined in drivers/clk/mediatek/clk-*.c). 109 * @routes: Routing table of the mmsys. 110 * It provides mux settings from one module to another. 111 * @num_routes: Array size of the routes. 112 * @sw0_rst_offset: Register offset for the reset control. 113 * @num_resets: Number of reset bits that are defined 114 * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe) 115 * or VDOSYS (Video). Only VDOSYS needs to be added to drm driver. 116 * @vsync_len: VSYNC length of the MIXER. 117 * VSYNC is usually triggered by the connector, so its length is a 118 * fixed value when the frame rate is decided, but ETHDR and 119 * MIXER generate their own VSYNC due to hardware design, therefore 120 * MIXER has to sync with ETHDR by adjusting VSYNC length. 121 * On MT8195, there is no such setting so we use the gap between 122 * falling edge and rising edge of SOF (Start of Frame) signal to 123 * do the job, but since MT8188, VSYNC_LEN setting is introduced to 124 * solve the problem and is given 0x40 (ticks) as the default value. 125 * Please notice that this value has to be set to 1 (minimum) if 126 * ETHDR is bypassed, otherwise MIXER could wait too long and causing 127 * underflow. 128 * 129 * Each MMSYS (multi-media system) may have different settings, they may use 130 * different clock sources, mux settings, reset control ...etc., and these 131 * differences are all stored here. 132 */ 133 struct mtk_mmsys_driver_data { 134 const char *clk_driver; 135 const struct mtk_mmsys_routes *routes; 136 const unsigned int num_routes; 137 const u16 sw0_rst_offset; 138 const u8 *rst_tb; 139 const u32 num_resets; 140 const bool is_vppsys; 141 const u8 vsync_len; 142 }; 143 144 /* 145 * Routes in mt2701 and mt2712 are different. That means 146 * in the same register address, it controls different input/output 147 * selection for each SoC. But, right now, they use the same table as 148 * default routes meet their requirements. But we don't have the complete 149 * route information for these three SoC, so just keep them in the same 150 * table. After we've more information, we could separate mt2701, mt2712 151 * to an independent table. 152 */ 153 static const struct mtk_mmsys_routes mmsys_default_routing_table[] = { 154 { 155 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, 156 DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK, 157 BLS_TO_DSI_RDMA1_TO_DPI1 158 }, { 159 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, 160 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK, 161 DSI_SEL_IN_BLS 162 }, { 163 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 164 DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK, 165 BLS_TO_DPI_RDMA1_TO_DSI 166 }, { 167 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 168 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK, 169 DSI_SEL_IN_RDMA 170 }, { 171 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 172 DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK, 173 DPI_SEL_IN_BLS 174 }, { 175 DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1, 176 DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1, 177 GAMMA_MOUT_EN_RDMA1 178 }, { 179 DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, 180 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0, 181 OD_MOUT_EN_RDMA0 182 }, { 183 DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1, 184 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1, 185 OD1_MOUT_EN_RDMA1 186 }, { 187 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, 188 DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, 189 OVL0_MOUT_EN_COLOR0 190 }, { 191 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, 192 DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0, 193 COLOR0_SEL_IN_OVL0 194 }, { 195 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 196 DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA, 197 OVL_MOUT_EN_RDMA 198 }, { 199 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, 200 DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1, 201 OVL1_MOUT_EN_COLOR1 202 }, { 203 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, 204 DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1, 205 COLOR1_SEL_IN_OVL1 206 }, { 207 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0, 208 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 209 RDMA0_SOUT_DPI0 210 }, { 211 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1, 212 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 213 RDMA0_SOUT_DPI1 214 }, { 215 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1, 216 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 217 RDMA0_SOUT_DSI1 218 }, { 219 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2, 220 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 221 RDMA0_SOUT_DSI2 222 }, { 223 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3, 224 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 225 RDMA0_SOUT_DSI3 226 }, { 227 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 228 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 229 RDMA1_SOUT_DPI0 230 }, { 231 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 232 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK, 233 DPI0_SEL_IN_RDMA1 234 }, { 235 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, 236 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 237 RDMA1_SOUT_DPI1 238 }, { 239 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, 240 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK, 241 DPI1_SEL_IN_RDMA1 242 }, { 243 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0, 244 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK, 245 DSI0_SEL_IN_RDMA1 246 }, { 247 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, 248 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 249 RDMA1_SOUT_DSI1 250 }, { 251 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, 252 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK, 253 DSI1_SEL_IN_RDMA1 254 }, { 255 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, 256 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 257 RDMA1_SOUT_DSI2 258 }, { 259 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, 260 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK, 261 DSI2_SEL_IN_RDMA1 262 }, { 263 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, 264 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 265 RDMA1_SOUT_DSI3 266 }, { 267 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, 268 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, 269 DSI3_SEL_IN_RDMA1 270 }, { 271 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, 272 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 273 RDMA2_SOUT_DPI0 274 }, { 275 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, 276 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK, 277 DPI0_SEL_IN_RDMA2 278 }, { 279 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, 280 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 281 RDMA2_SOUT_DPI1 282 }, { 283 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, 284 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK, 285 DPI1_SEL_IN_RDMA2 286 }, { 287 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0, 288 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK, 289 DSI0_SEL_IN_RDMA2 290 }, { 291 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, 292 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 293 RDMA2_SOUT_DSI1 294 }, { 295 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, 296 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK, 297 DSI1_SEL_IN_RDMA2 298 }, { 299 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, 300 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 301 RDMA2_SOUT_DSI2 302 }, { 303 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, 304 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK, 305 DSI2_SEL_IN_RDMA2 306 }, { 307 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, 308 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 309 RDMA2_SOUT_DSI3 310 }, { 311 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, 312 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, 313 DSI3_SEL_IN_RDMA2 314 }, { 315 DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, 316 DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0, 317 UFOE_MOUT_EN_DSI0 318 } 319 }; 320 321 #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */ 322