1 // SPDX-License-Identifier: GPL-2.0
2 #define KMSG_COMPONENT "zpci"
3 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
4
5 #include <linux/kernel.h>
6 #include <linux/irq.h>
7 #include <linux/kernel_stat.h>
8 #include <linux/pci.h>
9 #include <linux/msi.h>
10 #include <linux/smp.h>
11
12 #include <asm/isc.h>
13 #include <asm/airq.h>
14 #include <asm/tpi.h>
15
16 static enum {FLOATING, DIRECTED} irq_delivery;
17
18 /*
19 * summary bit vector
20 * FLOATING - summary bit per function
21 * DIRECTED - summary bit per cpu (only used in fallback path)
22 */
23 static struct airq_iv *zpci_sbv;
24
25 /*
26 * interrupt bit vectors
27 * FLOATING - interrupt bit vector per function
28 * DIRECTED - interrupt bit vector per cpu
29 */
30 static struct airq_iv **zpci_ibv;
31
32 /* Modify PCI: Register floating adapter interruptions */
zpci_set_airq(struct zpci_dev * zdev)33 static int zpci_set_airq(struct zpci_dev *zdev)
34 {
35 u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT);
36 struct zpci_fib fib = {0};
37 u8 status;
38
39 fib.fmt0.isc = PCI_ISC;
40 fib.fmt0.sum = 1; /* enable summary notifications */
41 fib.fmt0.noi = airq_iv_end(zdev->aibv);
42 fib.fmt0.aibv = virt_to_phys(zdev->aibv->vector);
43 fib.fmt0.aibvo = 0; /* each zdev has its own interrupt vector */
44 fib.fmt0.aisb = virt_to_phys(zpci_sbv->vector) + (zdev->aisb / 64) * 8;
45 fib.fmt0.aisbo = zdev->aisb & 63;
46 fib.gd = zdev->gisa;
47
48 return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
49 }
50
51 /* Modify PCI: Unregister floating adapter interruptions */
zpci_clear_airq(struct zpci_dev * zdev)52 static int zpci_clear_airq(struct zpci_dev *zdev)
53 {
54 u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT);
55 struct zpci_fib fib = {0};
56 u8 cc, status;
57
58 fib.gd = zdev->gisa;
59
60 cc = zpci_mod_fc(req, &fib, &status);
61 if (cc == 3 || (cc == 1 && status == 24))
62 /* Function already gone or IRQs already deregistered. */
63 cc = 0;
64
65 return cc ? -EIO : 0;
66 }
67
68 /* Modify PCI: Register CPU directed interruptions */
zpci_set_directed_irq(struct zpci_dev * zdev)69 static int zpci_set_directed_irq(struct zpci_dev *zdev)
70 {
71 u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT_D);
72 struct zpci_fib fib = {0};
73 u8 status;
74
75 fib.fmt = 1;
76 fib.fmt1.noi = zdev->msi_nr_irqs;
77 fib.fmt1.dibvo = zdev->msi_first_bit;
78 fib.gd = zdev->gisa;
79
80 return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
81 }
82
83 /* Modify PCI: Unregister CPU directed interruptions */
zpci_clear_directed_irq(struct zpci_dev * zdev)84 static int zpci_clear_directed_irq(struct zpci_dev *zdev)
85 {
86 u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT_D);
87 struct zpci_fib fib = {0};
88 u8 cc, status;
89
90 fib.fmt = 1;
91 fib.gd = zdev->gisa;
92 cc = zpci_mod_fc(req, &fib, &status);
93 if (cc == 3 || (cc == 1 && status == 24))
94 /* Function already gone or IRQs already deregistered. */
95 cc = 0;
96
97 return cc ? -EIO : 0;
98 }
99
100 /* Register adapter interruptions */
zpci_set_irq(struct zpci_dev * zdev)101 static int zpci_set_irq(struct zpci_dev *zdev)
102 {
103 int rc;
104
105 if (irq_delivery == DIRECTED)
106 rc = zpci_set_directed_irq(zdev);
107 else
108 rc = zpci_set_airq(zdev);
109
110 return rc;
111 }
112
113 /* Clear adapter interruptions */
zpci_clear_irq(struct zpci_dev * zdev)114 static int zpci_clear_irq(struct zpci_dev *zdev)
115 {
116 int rc;
117
118 if (irq_delivery == DIRECTED)
119 rc = zpci_clear_directed_irq(zdev);
120 else
121 rc = zpci_clear_airq(zdev);
122
123 return rc;
124 }
125
zpci_set_irq_affinity(struct irq_data * data,const struct cpumask * dest,bool force)126 static int zpci_set_irq_affinity(struct irq_data *data, const struct cpumask *dest,
127 bool force)
128 {
129 struct msi_desc *entry = irq_data_get_msi_desc(data);
130 struct msi_msg msg = entry->msg;
131 int cpu_addr = smp_cpu_get_cpu_address(cpumask_first(dest));
132
133 msg.address_lo &= 0xff0000ff;
134 msg.address_lo |= (cpu_addr << 8);
135 pci_write_msi_msg(data->irq, &msg);
136
137 return IRQ_SET_MASK_OK;
138 }
139
140 static struct irq_chip zpci_irq_chip = {
141 .name = "PCI-MSI",
142 .irq_unmask = pci_msi_unmask_irq,
143 .irq_mask = pci_msi_mask_irq,
144 };
145
zpci_handle_cpu_local_irq(bool rescan)146 static void zpci_handle_cpu_local_irq(bool rescan)
147 {
148 struct airq_iv *dibv = zpci_ibv[smp_processor_id()];
149 union zpci_sic_iib iib = {{0}};
150 unsigned long bit;
151 int irqs_on = 0;
152
153 for (bit = 0;;) {
154 /* Scan the directed IRQ bit vector */
155 bit = airq_iv_scan(dibv, bit, airq_iv_end(dibv));
156 if (bit == -1UL) {
157 if (!rescan || irqs_on++)
158 /* End of second scan with interrupts on. */
159 break;
160 /* First scan complete, re-enable interrupts. */
161 if (zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC, &iib))
162 break;
163 bit = 0;
164 continue;
165 }
166 inc_irq_stat(IRQIO_MSI);
167 generic_handle_irq(airq_iv_get_data(dibv, bit));
168 }
169 }
170
171 struct cpu_irq_data {
172 call_single_data_t csd;
173 atomic_t scheduled;
174 };
175 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_irq_data, irq_data);
176
zpci_handle_remote_irq(void * data)177 static void zpci_handle_remote_irq(void *data)
178 {
179 atomic_t *scheduled = data;
180
181 do {
182 zpci_handle_cpu_local_irq(false);
183 } while (atomic_dec_return(scheduled));
184 }
185
zpci_handle_fallback_irq(void)186 static void zpci_handle_fallback_irq(void)
187 {
188 struct cpu_irq_data *cpu_data;
189 union zpci_sic_iib iib = {{0}};
190 unsigned long cpu;
191 int irqs_on = 0;
192
193 for (cpu = 0;;) {
194 cpu = airq_iv_scan(zpci_sbv, cpu, airq_iv_end(zpci_sbv));
195 if (cpu == -1UL) {
196 if (irqs_on++)
197 /* End of second scan with interrupts on. */
198 break;
199 /* First scan complete, re-enable interrupts. */
200 if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC, &iib))
201 break;
202 cpu = 0;
203 continue;
204 }
205 cpu_data = &per_cpu(irq_data, cpu);
206 if (atomic_inc_return(&cpu_data->scheduled) > 1)
207 continue;
208
209 INIT_CSD(&cpu_data->csd, zpci_handle_remote_irq, &cpu_data->scheduled);
210 smp_call_function_single_async(cpu, &cpu_data->csd);
211 }
212 }
213
zpci_directed_irq_handler(struct airq_struct * airq,struct tpi_info * tpi_info)214 static void zpci_directed_irq_handler(struct airq_struct *airq,
215 struct tpi_info *tpi_info)
216 {
217 bool floating = !tpi_info->directed_irq;
218
219 if (floating) {
220 inc_irq_stat(IRQIO_PCF);
221 zpci_handle_fallback_irq();
222 } else {
223 inc_irq_stat(IRQIO_PCD);
224 zpci_handle_cpu_local_irq(true);
225 }
226 }
227
zpci_floating_irq_handler(struct airq_struct * airq,struct tpi_info * tpi_info)228 static void zpci_floating_irq_handler(struct airq_struct *airq,
229 struct tpi_info *tpi_info)
230 {
231 union zpci_sic_iib iib = {{0}};
232 unsigned long si, ai;
233 struct airq_iv *aibv;
234 int irqs_on = 0;
235
236 inc_irq_stat(IRQIO_PCF);
237 for (si = 0;;) {
238 /* Scan adapter summary indicator bit vector */
239 si = airq_iv_scan(zpci_sbv, si, airq_iv_end(zpci_sbv));
240 if (si == -1UL) {
241 if (irqs_on++)
242 /* End of second scan with interrupts on. */
243 break;
244 /* First scan complete, re-enable interrupts. */
245 if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC, &iib))
246 break;
247 si = 0;
248 continue;
249 }
250
251 /* Scan the adapter interrupt vector for this device. */
252 aibv = zpci_ibv[si];
253 for (ai = 0;;) {
254 ai = airq_iv_scan(aibv, ai, airq_iv_end(aibv));
255 if (ai == -1UL)
256 break;
257 inc_irq_stat(IRQIO_MSI);
258 airq_iv_lock(aibv, ai);
259 generic_handle_irq(airq_iv_get_data(aibv, ai));
260 airq_iv_unlock(aibv, ai);
261 }
262 }
263 }
264
__alloc_airq(struct zpci_dev * zdev,int msi_vecs,unsigned long * bit)265 static int __alloc_airq(struct zpci_dev *zdev, int msi_vecs,
266 unsigned long *bit)
267 {
268 if (irq_delivery == DIRECTED) {
269 /* Allocate cpu vector bits */
270 *bit = airq_iv_alloc(zpci_ibv[0], msi_vecs);
271 if (*bit == -1UL)
272 return -EIO;
273 } else {
274 /* Allocate adapter summary indicator bit */
275 *bit = airq_iv_alloc_bit(zpci_sbv);
276 if (*bit == -1UL)
277 return -EIO;
278 zdev->aisb = *bit;
279
280 /* Create adapter interrupt vector */
281 zdev->aibv = airq_iv_create(msi_vecs, AIRQ_IV_DATA | AIRQ_IV_BITLOCK, NULL);
282 if (!zdev->aibv)
283 return -ENOMEM;
284
285 /* Wire up shortcut pointer */
286 zpci_ibv[*bit] = zdev->aibv;
287 /* Each function has its own interrupt vector */
288 *bit = 0;
289 }
290 return 0;
291 }
292
arch_setup_msi_irqs(struct pci_dev * pdev,int nvec,int type)293 int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
294 {
295 unsigned int hwirq, msi_vecs, irqs_per_msi, i, cpu;
296 struct zpci_dev *zdev = to_zpci(pdev);
297 struct msi_desc *msi;
298 struct msi_msg msg;
299 unsigned long bit;
300 int cpu_addr;
301 int rc, irq;
302
303 zdev->aisb = -1UL;
304 zdev->msi_first_bit = -1U;
305
306 msi_vecs = min_t(unsigned int, nvec, zdev->max_msi);
307 if (msi_vecs < nvec) {
308 pr_info("%s requested %d irqs, allocate system limit of %d",
309 pci_name(pdev), nvec, zdev->max_msi);
310 }
311
312 rc = __alloc_airq(zdev, msi_vecs, &bit);
313 if (rc < 0)
314 return rc;
315
316 /*
317 * Request MSI interrupts:
318 * When using MSI, nvec_used interrupt sources and their irq
319 * descriptors are controlled through one msi descriptor.
320 * Thus the outer loop over msi descriptors shall run only once,
321 * while two inner loops iterate over the interrupt vectors.
322 * When using MSI-X, each interrupt vector/irq descriptor
323 * is bound to exactly one msi descriptor (nvec_used is one).
324 * So the inner loops are executed once, while the outer iterates
325 * over the MSI-X descriptors.
326 */
327 hwirq = bit;
328 msi_for_each_desc(msi, &pdev->dev, MSI_DESC_NOTASSOCIATED) {
329 if (hwirq - bit >= msi_vecs)
330 break;
331 irqs_per_msi = min_t(unsigned int, msi_vecs, msi->nvec_used);
332 irq = __irq_alloc_descs(-1, 0, irqs_per_msi, 0, THIS_MODULE,
333 (irq_delivery == DIRECTED) ?
334 msi->affinity : NULL);
335 if (irq < 0)
336 return -ENOMEM;
337
338 for (i = 0; i < irqs_per_msi; i++) {
339 rc = irq_set_msi_desc_off(irq, i, msi);
340 if (rc)
341 return rc;
342 irq_set_chip_and_handler(irq + i, &zpci_irq_chip,
343 handle_percpu_irq);
344 }
345
346 msg.data = hwirq - bit;
347 if (irq_delivery == DIRECTED) {
348 if (msi->affinity)
349 cpu = cpumask_first(&msi->affinity->mask);
350 else
351 cpu = 0;
352 cpu_addr = smp_cpu_get_cpu_address(cpu);
353
354 msg.address_lo = zdev->msi_addr & 0xff0000ff;
355 msg.address_lo |= (cpu_addr << 8);
356
357 for_each_possible_cpu(cpu) {
358 for (i = 0; i < irqs_per_msi; i++)
359 airq_iv_set_data(zpci_ibv[cpu],
360 hwirq + i, irq + i);
361 }
362 } else {
363 msg.address_lo = zdev->msi_addr & 0xffffffff;
364 for (i = 0; i < irqs_per_msi; i++)
365 airq_iv_set_data(zdev->aibv, hwirq + i, irq + i);
366 }
367 msg.address_hi = zdev->msi_addr >> 32;
368 pci_write_msi_msg(irq, &msg);
369 hwirq += irqs_per_msi;
370 }
371
372 zdev->msi_first_bit = bit;
373 zdev->msi_nr_irqs = hwirq - bit;
374
375 rc = zpci_set_irq(zdev);
376 if (rc)
377 return rc;
378
379 return (zdev->msi_nr_irqs == nvec) ? 0 : zdev->msi_nr_irqs;
380 }
381
arch_teardown_msi_irqs(struct pci_dev * pdev)382 void arch_teardown_msi_irqs(struct pci_dev *pdev)
383 {
384 struct zpci_dev *zdev = to_zpci(pdev);
385 struct msi_desc *msi;
386 unsigned int i;
387 int rc;
388
389 /* Disable interrupts */
390 rc = zpci_clear_irq(zdev);
391 if (rc)
392 return;
393
394 /* Release MSI interrupts */
395 msi_for_each_desc(msi, &pdev->dev, MSI_DESC_ASSOCIATED) {
396 for (i = 0; i < msi->nvec_used; i++) {
397 irq_set_msi_desc(msi->irq + i, NULL);
398 irq_free_desc(msi->irq + i);
399 }
400 msi->msg.address_lo = 0;
401 msi->msg.address_hi = 0;
402 msi->msg.data = 0;
403 msi->irq = 0;
404 }
405
406 if (zdev->aisb != -1UL) {
407 zpci_ibv[zdev->aisb] = NULL;
408 airq_iv_free_bit(zpci_sbv, zdev->aisb);
409 zdev->aisb = -1UL;
410 }
411 if (zdev->aibv) {
412 airq_iv_release(zdev->aibv);
413 zdev->aibv = NULL;
414 }
415
416 if ((irq_delivery == DIRECTED) && zdev->msi_first_bit != -1U)
417 airq_iv_free(zpci_ibv[0], zdev->msi_first_bit, zdev->msi_nr_irqs);
418 }
419
arch_restore_msi_irqs(struct pci_dev * pdev)420 bool arch_restore_msi_irqs(struct pci_dev *pdev)
421 {
422 struct zpci_dev *zdev = to_zpci(pdev);
423
424 zpci_set_irq(zdev);
425 return true;
426 }
427
428 static struct airq_struct zpci_airq = {
429 .handler = zpci_floating_irq_handler,
430 .isc = PCI_ISC,
431 };
432
cpu_enable_directed_irq(void * unused)433 static void __init cpu_enable_directed_irq(void *unused)
434 {
435 union zpci_sic_iib iib = {{0}};
436 union zpci_sic_iib ziib = {{0}};
437
438 iib.cdiib.dibv_addr = virt_to_phys(zpci_ibv[smp_processor_id()]->vector);
439
440 zpci_set_irq_ctrl(SIC_IRQ_MODE_SET_CPU, 0, &iib);
441 zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC, &ziib);
442 }
443
zpci_directed_irq_init(void)444 static int __init zpci_directed_irq_init(void)
445 {
446 union zpci_sic_iib iib = {{0}};
447 unsigned int cpu;
448
449 zpci_sbv = airq_iv_create(num_possible_cpus(), 0, NULL);
450 if (!zpci_sbv)
451 return -ENOMEM;
452
453 iib.diib.isc = PCI_ISC;
454 iib.diib.nr_cpus = num_possible_cpus();
455 iib.diib.disb_addr = virt_to_phys(zpci_sbv->vector);
456 zpci_set_irq_ctrl(SIC_IRQ_MODE_DIRECT, 0, &iib);
457
458 zpci_ibv = kcalloc(num_possible_cpus(), sizeof(*zpci_ibv),
459 GFP_KERNEL);
460 if (!zpci_ibv)
461 return -ENOMEM;
462
463 for_each_possible_cpu(cpu) {
464 /*
465 * Per CPU IRQ vectors look the same but bit-allocation
466 * is only done on the first vector.
467 */
468 zpci_ibv[cpu] = airq_iv_create(cache_line_size() * BITS_PER_BYTE,
469 AIRQ_IV_DATA |
470 AIRQ_IV_CACHELINE |
471 (!cpu ? AIRQ_IV_ALLOC : 0), NULL);
472 if (!zpci_ibv[cpu])
473 return -ENOMEM;
474 }
475 on_each_cpu(cpu_enable_directed_irq, NULL, 1);
476
477 zpci_irq_chip.irq_set_affinity = zpci_set_irq_affinity;
478
479 return 0;
480 }
481
zpci_floating_irq_init(void)482 static int __init zpci_floating_irq_init(void)
483 {
484 zpci_ibv = kcalloc(ZPCI_NR_DEVICES, sizeof(*zpci_ibv), GFP_KERNEL);
485 if (!zpci_ibv)
486 return -ENOMEM;
487
488 zpci_sbv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC, NULL);
489 if (!zpci_sbv)
490 goto out_free;
491
492 return 0;
493
494 out_free:
495 kfree(zpci_ibv);
496 return -ENOMEM;
497 }
498
zpci_irq_init(void)499 int __init zpci_irq_init(void)
500 {
501 union zpci_sic_iib iib = {{0}};
502 int rc;
503
504 irq_delivery = sclp.has_dirq ? DIRECTED : FLOATING;
505 if (s390_pci_force_floating)
506 irq_delivery = FLOATING;
507
508 if (irq_delivery == DIRECTED)
509 zpci_airq.handler = zpci_directed_irq_handler;
510
511 rc = register_adapter_interrupt(&zpci_airq);
512 if (rc)
513 goto out;
514 /* Set summary to 1 to be called every time for the ISC. */
515 *zpci_airq.lsi_ptr = 1;
516
517 switch (irq_delivery) {
518 case FLOATING:
519 rc = zpci_floating_irq_init();
520 break;
521 case DIRECTED:
522 rc = zpci_directed_irq_init();
523 break;
524 }
525
526 if (rc)
527 goto out_airq;
528
529 /*
530 * Enable floating IRQs (with suppression after one IRQ). When using
531 * directed IRQs this enables the fallback path.
532 */
533 zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC, &iib);
534
535 return 0;
536 out_airq:
537 unregister_adapter_interrupt(&zpci_airq);
538 out:
539 return rc;
540 }
541
zpci_irq_exit(void)542 void __init zpci_irq_exit(void)
543 {
544 unsigned int cpu;
545
546 if (irq_delivery == DIRECTED) {
547 for_each_possible_cpu(cpu) {
548 airq_iv_release(zpci_ibv[cpu]);
549 }
550 }
551 kfree(zpci_ibv);
552 if (zpci_sbv)
553 airq_iv_release(zpci_sbv);
554 unregister_adapter_interrupt(&zpci_airq);
555 }
556