xref: /linux/drivers/hwmon/peci/dimmtemp.c (revision 8287dfc2915368092e98ef0caef9c03e8e0f7aa9)
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2021 Intel Corporation
3 
4 #include <linux/auxiliary_bus.h>
5 #include <linux/bitfield.h>
6 #include <linux/bitops.h>
7 #include <linux/devm-helpers.h>
8 #include <linux/hwmon.h>
9 #include <linux/jiffies.h>
10 #include <linux/module.h>
11 #include <linux/peci.h>
12 #include <linux/peci-cpu.h>
13 #include <linux/units.h>
14 #include <linux/workqueue.h>
15 
16 #include "common.h"
17 
18 #define DIMM_MASK_CHECK_DELAY_JIFFIES	msecs_to_jiffies(5000)
19 
20 /* Max number of channel ranks and DIMM index per channel */
21 #define CHAN_RANK_MAX_ON_HSX	8
22 #define DIMM_IDX_MAX_ON_HSX	3
23 #define CHAN_RANK_MAX_ON_BDX	4
24 #define DIMM_IDX_MAX_ON_BDX	3
25 #define CHAN_RANK_MAX_ON_BDXD	2
26 #define DIMM_IDX_MAX_ON_BDXD	2
27 #define CHAN_RANK_MAX_ON_SKX	6
28 #define DIMM_IDX_MAX_ON_SKX	2
29 #define CHAN_RANK_MAX_ON_ICX	8
30 #define DIMM_IDX_MAX_ON_ICX	2
31 #define CHAN_RANK_MAX_ON_ICXD	4
32 #define DIMM_IDX_MAX_ON_ICXD	2
33 #define CHAN_RANK_MAX_ON_SPR	8
34 #define DIMM_IDX_MAX_ON_SPR	2
35 
36 #define CHAN_RANK_MAX		CHAN_RANK_MAX_ON_HSX
37 #define DIMM_IDX_MAX		DIMM_IDX_MAX_ON_HSX
38 #define DIMM_NUMS_MAX		(CHAN_RANK_MAX * DIMM_IDX_MAX)
39 
40 #define CPU_SEG_MASK		GENMASK(23, 16)
41 #define GET_CPU_SEG(x)		(((x) & CPU_SEG_MASK) >> 16)
42 #define CPU_BUS_MASK		GENMASK(7, 0)
43 #define GET_CPU_BUS(x)		((x) & CPU_BUS_MASK)
44 
45 #define DIMM_TEMP_MAX		GENMASK(15, 8)
46 #define DIMM_TEMP_CRIT		GENMASK(23, 16)
47 #define GET_TEMP_MAX(x)		(((x) & DIMM_TEMP_MAX) >> 8)
48 #define GET_TEMP_CRIT(x)	(((x) & DIMM_TEMP_CRIT) >> 16)
49 
50 #define NO_DIMM_RETRY_COUNT_MAX	120
51 
52 struct peci_dimmtemp;
53 
54 struct dimm_info {
55 	int chan_rank_max;
56 	int dimm_idx_max;
57 	u8 min_peci_revision;
58 	int (*read_thresholds)(struct peci_dimmtemp *priv, int dimm_order,
59 			       int chan_rank, u32 *data);
60 };
61 
62 struct peci_dimm_thresholds {
63 	long temp_max;
64 	long temp_crit;
65 	struct peci_sensor_state state;
66 };
67 
68 enum peci_dimm_threshold_type {
69 	temp_max_type,
70 	temp_crit_type,
71 };
72 
73 struct peci_dimmtemp {
74 	struct peci_device *peci_dev;
75 	struct device *dev;
76 	const char *name;
77 	const struct dimm_info *gen_info;
78 	struct delayed_work detect_work;
79 	struct {
80 		struct peci_sensor_data temp;
81 		struct peci_dimm_thresholds thresholds;
82 	} dimm[DIMM_NUMS_MAX];
83 	char **dimmtemp_label;
84 	DECLARE_BITMAP(dimm_mask, DIMM_NUMS_MAX);
85 	u8 no_dimm_retry_count;
86 };
87 
__dimm_temp(u32 reg,int dimm_order)88 static u8 __dimm_temp(u32 reg, int dimm_order)
89 {
90 	return (reg >> (dimm_order * 8)) & 0xff;
91 }
92 
get_dimm_temp(struct peci_dimmtemp * priv,int dimm_no,long * val)93 static int get_dimm_temp(struct peci_dimmtemp *priv, int dimm_no, long *val)
94 {
95 	int dimm_order = dimm_no % priv->gen_info->dimm_idx_max;
96 	int chan_rank = dimm_no / priv->gen_info->dimm_idx_max;
97 	int ret = 0;
98 	u32 data;
99 
100 	mutex_lock(&priv->dimm[dimm_no].temp.state.lock);
101 	if (!peci_sensor_need_update(&priv->dimm[dimm_no].temp.state))
102 		goto skip_update;
103 
104 	ret = peci_pcs_read(priv->peci_dev, PECI_PCS_DDR_DIMM_TEMP, chan_rank, &data);
105 	if (ret)
106 		goto unlock;
107 
108 	priv->dimm[dimm_no].temp.value = __dimm_temp(data, dimm_order) * MILLIDEGREE_PER_DEGREE;
109 
110 	peci_sensor_mark_updated(&priv->dimm[dimm_no].temp.state);
111 
112 skip_update:
113 	*val = priv->dimm[dimm_no].temp.value;
114 unlock:
115 	mutex_unlock(&priv->dimm[dimm_no].temp.state.lock);
116 	return ret;
117 }
118 
update_thresholds(struct peci_dimmtemp * priv,int dimm_no)119 static int update_thresholds(struct peci_dimmtemp *priv, int dimm_no)
120 {
121 	int dimm_order = dimm_no % priv->gen_info->dimm_idx_max;
122 	int chan_rank = dimm_no / priv->gen_info->dimm_idx_max;
123 	u32 data;
124 	int ret;
125 
126 	if (!peci_sensor_need_update(&priv->dimm[dimm_no].thresholds.state))
127 		return 0;
128 
129 	ret = priv->gen_info->read_thresholds(priv, dimm_order, chan_rank, &data);
130 	if (ret)
131 		return ret;
132 
133 	priv->dimm[dimm_no].thresholds.temp_max = GET_TEMP_MAX(data) * MILLIDEGREE_PER_DEGREE;
134 	priv->dimm[dimm_no].thresholds.temp_crit = GET_TEMP_CRIT(data) * MILLIDEGREE_PER_DEGREE;
135 
136 	peci_sensor_mark_updated(&priv->dimm[dimm_no].thresholds.state);
137 
138 	return 0;
139 }
140 
get_dimm_thresholds(struct peci_dimmtemp * priv,enum peci_dimm_threshold_type type,int dimm_no,long * val)141 static int get_dimm_thresholds(struct peci_dimmtemp *priv, enum peci_dimm_threshold_type type,
142 			       int dimm_no, long *val)
143 {
144 	int ret;
145 
146 	mutex_lock(&priv->dimm[dimm_no].thresholds.state.lock);
147 	ret = update_thresholds(priv, dimm_no);
148 	if (ret)
149 		goto unlock;
150 
151 	switch (type) {
152 	case temp_max_type:
153 		*val = priv->dimm[dimm_no].thresholds.temp_max;
154 		break;
155 	case temp_crit_type:
156 		*val = priv->dimm[dimm_no].thresholds.temp_crit;
157 		break;
158 	default:
159 		ret = -EOPNOTSUPP;
160 		break;
161 	}
162 unlock:
163 	mutex_unlock(&priv->dimm[dimm_no].thresholds.state.lock);
164 
165 	return ret;
166 }
167 
dimmtemp_read_string(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)168 static int dimmtemp_read_string(struct device *dev,
169 				enum hwmon_sensor_types type,
170 				u32 attr, int channel, const char **str)
171 {
172 	struct peci_dimmtemp *priv = dev_get_drvdata(dev);
173 
174 	if (attr != hwmon_temp_label)
175 		return -EOPNOTSUPP;
176 
177 	*str = (const char *)priv->dimmtemp_label[channel];
178 
179 	return 0;
180 }
181 
dimmtemp_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)182 static int dimmtemp_read(struct device *dev, enum hwmon_sensor_types type,
183 			 u32 attr, int channel, long *val)
184 {
185 	struct peci_dimmtemp *priv = dev_get_drvdata(dev);
186 
187 	switch (attr) {
188 	case hwmon_temp_input:
189 		return get_dimm_temp(priv, channel, val);
190 	case hwmon_temp_max:
191 		return get_dimm_thresholds(priv, temp_max_type, channel, val);
192 	case hwmon_temp_crit:
193 		return get_dimm_thresholds(priv, temp_crit_type, channel, val);
194 	default:
195 		break;
196 	}
197 
198 	return -EOPNOTSUPP;
199 }
200 
dimmtemp_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)201 static umode_t dimmtemp_is_visible(const void *data, enum hwmon_sensor_types type,
202 				   u32 attr, int channel)
203 {
204 	const struct peci_dimmtemp *priv = data;
205 
206 	if (test_bit(channel, priv->dimm_mask))
207 		return 0444;
208 
209 	return 0;
210 }
211 
212 static const struct hwmon_ops peci_dimmtemp_ops = {
213 	.is_visible = dimmtemp_is_visible,
214 	.read_string = dimmtemp_read_string,
215 	.read = dimmtemp_read,
216 };
217 
check_populated_dimms(struct peci_dimmtemp * priv)218 static int check_populated_dimms(struct peci_dimmtemp *priv)
219 {
220 	int chan_rank_max = priv->gen_info->chan_rank_max;
221 	int dimm_idx_max = priv->gen_info->dimm_idx_max;
222 	DECLARE_BITMAP(dimm_mask, DIMM_NUMS_MAX);
223 	DECLARE_BITMAP(chan_rank_empty, CHAN_RANK_MAX);
224 
225 	int chan_rank, dimm_idx, ret, i;
226 	u32 pcs;
227 
228 	if (chan_rank_max * dimm_idx_max > DIMM_NUMS_MAX) {
229 		WARN_ONCE(1, "Unsupported number of DIMMs - chan_rank_max: %d, dimm_idx_max: %d",
230 			  chan_rank_max, dimm_idx_max);
231 		return -EINVAL;
232 	}
233 
234 	bitmap_zero(dimm_mask, DIMM_NUMS_MAX);
235 	bitmap_zero(chan_rank_empty, CHAN_RANK_MAX);
236 
237 	for (chan_rank = 0; chan_rank < chan_rank_max; chan_rank++) {
238 		ret = peci_pcs_read(priv->peci_dev, PECI_PCS_DDR_DIMM_TEMP, chan_rank, &pcs);
239 		if (ret) {
240 			/*
241 			 * Overall, we expect either success or -EINVAL in
242 			 * order to determine whether DIMM is populated or not.
243 			 * For anything else we fall back to deferring the
244 			 * detection to be performed at a later point in time.
245 			 */
246 			if (ret == -EINVAL) {
247 				bitmap_set(chan_rank_empty, chan_rank, 1);
248 				continue;
249 			}
250 
251 			return -EAGAIN;
252 		}
253 
254 		for (dimm_idx = 0; dimm_idx < dimm_idx_max; dimm_idx++)
255 			if (__dimm_temp(pcs, dimm_idx))
256 				bitmap_set(dimm_mask, chan_rank * dimm_idx_max + dimm_idx, 1);
257 	}
258 
259 	/*
260 	 * If we got all -EINVALs, it means that the CPU doesn't have any
261 	 * DIMMs. Unfortunately, it may also happen at the very start of
262 	 * host platform boot. Retrying a couple of times lets us make sure
263 	 * that the state is persistent.
264 	 */
265 	if (bitmap_full(chan_rank_empty, chan_rank_max)) {
266 		if (priv->no_dimm_retry_count < NO_DIMM_RETRY_COUNT_MAX) {
267 			priv->no_dimm_retry_count++;
268 
269 			return -EAGAIN;
270 		}
271 
272 		return -ENODEV;
273 	}
274 
275 	/*
276 	 * It's possible that memory training is not done yet. In this case we
277 	 * defer the detection to be performed at a later point in time.
278 	 */
279 	if (bitmap_empty(dimm_mask, DIMM_NUMS_MAX)) {
280 		priv->no_dimm_retry_count = 0;
281 		return -EAGAIN;
282 	}
283 
284 	for_each_set_bit(i, dimm_mask, DIMM_NUMS_MAX) {
285 		dev_dbg(priv->dev, "Found DIMM%#x\n", i);
286 	}
287 
288 	bitmap_copy(priv->dimm_mask, dimm_mask, DIMM_NUMS_MAX);
289 
290 	return 0;
291 }
292 
create_dimm_temp_label(struct peci_dimmtemp * priv,int chan)293 static int create_dimm_temp_label(struct peci_dimmtemp *priv, int chan)
294 {
295 	int rank = chan / priv->gen_info->dimm_idx_max;
296 	int idx = chan % priv->gen_info->dimm_idx_max;
297 
298 	priv->dimmtemp_label[chan] = devm_kasprintf(priv->dev, GFP_KERNEL,
299 						    "DIMM %c%d", 'A' + rank,
300 						    idx + 1);
301 	if (!priv->dimmtemp_label[chan])
302 		return -ENOMEM;
303 
304 	return 0;
305 }
306 
307 static const struct hwmon_channel_info * const peci_dimmtemp_temp_info[] = {
308 	HWMON_CHANNEL_INFO(temp,
309 			   [0 ... DIMM_NUMS_MAX - 1] = HWMON_T_LABEL |
310 				HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT),
311 	NULL
312 };
313 
314 static const struct hwmon_chip_info peci_dimmtemp_chip_info = {
315 	.ops = &peci_dimmtemp_ops,
316 	.info = peci_dimmtemp_temp_info,
317 };
318 
create_dimm_temp_info(struct peci_dimmtemp * priv)319 static int create_dimm_temp_info(struct peci_dimmtemp *priv)
320 {
321 	int ret, i, channels;
322 	struct device *dev;
323 
324 	/*
325 	 * We expect to either find populated DIMMs and carry on with creating
326 	 * sensors, or find out that there are no DIMMs populated.
327 	 * All other states mean that the platform never reached the state that
328 	 * allows to check DIMM state - causing us to retry later on.
329 	 */
330 	ret = check_populated_dimms(priv);
331 	if (ret == -ENODEV) {
332 		dev_dbg(priv->dev, "No DIMMs found\n");
333 		return 0;
334 	} else if (ret) {
335 		schedule_delayed_work(&priv->detect_work, DIMM_MASK_CHECK_DELAY_JIFFIES);
336 		dev_dbg(priv->dev, "Deferred populating DIMM temp info\n");
337 		return ret;
338 	}
339 
340 	channels = priv->gen_info->chan_rank_max * priv->gen_info->dimm_idx_max;
341 
342 	priv->dimmtemp_label = devm_kzalloc(priv->dev, channels * sizeof(char *), GFP_KERNEL);
343 	if (!priv->dimmtemp_label)
344 		return -ENOMEM;
345 
346 	for_each_set_bit(i, priv->dimm_mask, DIMM_NUMS_MAX) {
347 		ret = create_dimm_temp_label(priv, i);
348 		if (ret)
349 			return ret;
350 		mutex_init(&priv->dimm[i].thresholds.state.lock);
351 		mutex_init(&priv->dimm[i].temp.state.lock);
352 	}
353 
354 	dev = devm_hwmon_device_register_with_info(priv->dev, priv->name, priv,
355 						   &peci_dimmtemp_chip_info, NULL);
356 	if (IS_ERR(dev)) {
357 		dev_err(priv->dev, "Failed to register hwmon device\n");
358 		return PTR_ERR(dev);
359 	}
360 
361 	dev_dbg(priv->dev, "%s: sensor '%s'\n", dev_name(dev), priv->name);
362 
363 	return 0;
364 }
365 
create_dimm_temp_info_delayed(struct work_struct * work)366 static void create_dimm_temp_info_delayed(struct work_struct *work)
367 {
368 	struct peci_dimmtemp *priv = container_of(to_delayed_work(work),
369 						  struct peci_dimmtemp,
370 						  detect_work);
371 	int ret;
372 
373 	ret = create_dimm_temp_info(priv);
374 	if (ret && ret != -EAGAIN)
375 		dev_err(priv->dev, "Failed to populate DIMM temp info\n");
376 }
377 
peci_dimmtemp_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)378 static int peci_dimmtemp_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id)
379 {
380 	struct device *dev = &adev->dev;
381 	struct peci_device *peci_dev = to_peci_device(dev->parent);
382 	struct peci_dimmtemp *priv;
383 	int ret;
384 
385 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
386 	if (!priv)
387 		return -ENOMEM;
388 
389 	priv->name = devm_kasprintf(dev, GFP_KERNEL, "peci_dimmtemp.cpu%d",
390 				    peci_dev->info.socket_id);
391 	if (!priv->name)
392 		return -ENOMEM;
393 
394 	priv->dev = dev;
395 	priv->peci_dev = peci_dev;
396 	priv->gen_info = (const struct dimm_info *)id->driver_data;
397 
398 	/*
399 	 * This is just a sanity check. Since we're using commands that are
400 	 * guaranteed to be supported on a given platform, we should never see
401 	 * revision lower than expected.
402 	 */
403 	if (peci_dev->info.peci_revision < priv->gen_info->min_peci_revision)
404 		dev_warn(priv->dev,
405 			 "Unexpected PECI revision %#x, some features may be unavailable\n",
406 			 peci_dev->info.peci_revision);
407 
408 	ret = devm_delayed_work_autocancel(priv->dev, &priv->detect_work,
409 					   create_dimm_temp_info_delayed);
410 	if (ret)
411 		return ret;
412 
413 	ret = create_dimm_temp_info(priv);
414 	if (ret && ret != -EAGAIN) {
415 		dev_err(dev, "Failed to populate DIMM temp info\n");
416 		return ret;
417 	}
418 
419 	return 0;
420 }
421 
422 static int
read_thresholds_hsx(struct peci_dimmtemp * priv,int dimm_order,int chan_rank,u32 * data)423 read_thresholds_hsx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
424 {
425 	u8 dev, func;
426 	u16 reg;
427 	int ret;
428 
429 	/*
430 	 * Device 20, Function 0: IMC 0 channel 0 -> rank 0
431 	 * Device 20, Function 1: IMC 0 channel 1 -> rank 1
432 	 * Device 21, Function 0: IMC 0 channel 2 -> rank 2
433 	 * Device 21, Function 1: IMC 0 channel 3 -> rank 3
434 	 * Device 23, Function 0: IMC 1 channel 0 -> rank 4
435 	 * Device 23, Function 1: IMC 1 channel 1 -> rank 5
436 	 * Device 24, Function 0: IMC 1 channel 2 -> rank 6
437 	 * Device 24, Function 1: IMC 1 channel 3 -> rank 7
438 	 */
439 	dev = 20 + chan_rank / 2 + chan_rank / 4;
440 	func = chan_rank % 2;
441 	reg = 0x120 + dimm_order * 4;
442 
443 	ret = peci_pci_local_read(priv->peci_dev, 1, dev, func, reg, data);
444 	if (ret)
445 		return ret;
446 
447 	return 0;
448 }
449 
450 static int
read_thresholds_bdxd(struct peci_dimmtemp * priv,int dimm_order,int chan_rank,u32 * data)451 read_thresholds_bdxd(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
452 {
453 	u8 dev, func;
454 	u16 reg;
455 	int ret;
456 
457 	/*
458 	 * Device 10, Function 2: IMC 0 channel 0 -> rank 0
459 	 * Device 10, Function 6: IMC 0 channel 1 -> rank 1
460 	 * Device 12, Function 2: IMC 1 channel 0 -> rank 2
461 	 * Device 12, Function 6: IMC 1 channel 1 -> rank 3
462 	 */
463 	dev = 10 + chan_rank / 2 * 2;
464 	func = (chan_rank % 2) ? 6 : 2;
465 	reg = 0x120 + dimm_order * 4;
466 
467 	ret = peci_pci_local_read(priv->peci_dev, 2, dev, func, reg, data);
468 	if (ret)
469 		return ret;
470 
471 	return 0;
472 }
473 
474 static int
read_thresholds_skx(struct peci_dimmtemp * priv,int dimm_order,int chan_rank,u32 * data)475 read_thresholds_skx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
476 {
477 	u8 dev, func;
478 	u16 reg;
479 	int ret;
480 
481 	/*
482 	 * Device 10, Function 2: IMC 0 channel 0 -> rank 0
483 	 * Device 10, Function 6: IMC 0 channel 1 -> rank 1
484 	 * Device 11, Function 2: IMC 0 channel 2 -> rank 2
485 	 * Device 12, Function 2: IMC 1 channel 0 -> rank 3
486 	 * Device 12, Function 6: IMC 1 channel 1 -> rank 4
487 	 * Device 13, Function 2: IMC 1 channel 2 -> rank 5
488 	 */
489 	dev = 10 + chan_rank / 3 * 2 + (chan_rank % 3 == 2 ? 1 : 0);
490 	func = chan_rank % 3 == 1 ? 6 : 2;
491 	reg = 0x120 + dimm_order * 4;
492 
493 	ret = peci_pci_local_read(priv->peci_dev, 2, dev, func, reg, data);
494 	if (ret)
495 		return ret;
496 
497 	return 0;
498 }
499 
500 static int
read_thresholds_icx(struct peci_dimmtemp * priv,int dimm_order,int chan_rank,u32 * data)501 read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
502 {
503 	u32 reg_val;
504 	u64 offset;
505 	int ret;
506 	u8 dev;
507 
508 	ret = peci_ep_pci_local_read(priv->peci_dev, 0, 13, 0, 2, 0xd4, &reg_val);
509 	if (ret || !(reg_val & BIT(31)))
510 		return -ENODATA;
511 
512 	ret = peci_ep_pci_local_read(priv->peci_dev, 0, 13, 0, 2, 0xd0, &reg_val);
513 	if (ret)
514 		return -ENODATA;
515 
516 	/*
517 	 * Device 26, Offset 224e0: IMC 0 channel 0 -> rank 0
518 	 * Device 26, Offset 264e0: IMC 0 channel 1 -> rank 1
519 	 * Device 27, Offset 224e0: IMC 1 channel 0 -> rank 2
520 	 * Device 27, Offset 264e0: IMC 1 channel 1 -> rank 3
521 	 * Device 28, Offset 224e0: IMC 2 channel 0 -> rank 4
522 	 * Device 28, Offset 264e0: IMC 2 channel 1 -> rank 5
523 	 * Device 29, Offset 224e0: IMC 3 channel 0 -> rank 6
524 	 * Device 29, Offset 264e0: IMC 3 channel 1 -> rank 7
525 	 */
526 	dev = 26 + chan_rank / 2;
527 	offset = 0x224e0 + dimm_order * 4 + (chan_rank % 2) * 0x4000;
528 
529 	ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val),
530 			     dev, 0, offset, data);
531 	if (ret)
532 		return ret;
533 
534 	return 0;
535 }
536 
537 static int
read_thresholds_spr(struct peci_dimmtemp * priv,int dimm_order,int chan_rank,u32 * data)538 read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
539 {
540 	u32 reg_val;
541 	u64 offset;
542 	int ret;
543 	u8 dev;
544 
545 	ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4, &reg_val);
546 	if (ret || !(reg_val & BIT(31)))
547 		return -ENODATA;
548 
549 	ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0, &reg_val);
550 	if (ret)
551 		return -ENODATA;
552 
553 	/*
554 	 * Device 26, Offset 219a8: IMC 0 channel 0 -> rank 0
555 	 * Device 26, Offset 299a8: IMC 0 channel 1 -> rank 1
556 	 * Device 27, Offset 219a8: IMC 1 channel 0 -> rank 2
557 	 * Device 27, Offset 299a8: IMC 1 channel 1 -> rank 3
558 	 * Device 28, Offset 219a8: IMC 2 channel 0 -> rank 4
559 	 * Device 28, Offset 299a8: IMC 2 channel 1 -> rank 5
560 	 * Device 29, Offset 219a8: IMC 3 channel 0 -> rank 6
561 	 * Device 29, Offset 299a8: IMC 3 channel 1 -> rank 7
562 	 */
563 	dev = 26 + chan_rank / 2;
564 	offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000;
565 
566 	ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val),
567 			     dev, 0, offset, data);
568 	if (ret)
569 		return ret;
570 
571 	return 0;
572 }
573 
574 static const struct dimm_info dimm_hsx = {
575 	.chan_rank_max	= CHAN_RANK_MAX_ON_HSX,
576 	.dimm_idx_max	= DIMM_IDX_MAX_ON_HSX,
577 	.min_peci_revision = 0x33,
578 	.read_thresholds = &read_thresholds_hsx,
579 };
580 
581 static const struct dimm_info dimm_bdx = {
582 	.chan_rank_max	= CHAN_RANK_MAX_ON_BDX,
583 	.dimm_idx_max	= DIMM_IDX_MAX_ON_BDX,
584 	.min_peci_revision = 0x33,
585 	.read_thresholds = &read_thresholds_hsx,
586 };
587 
588 static const struct dimm_info dimm_bdxd = {
589 	.chan_rank_max	= CHAN_RANK_MAX_ON_BDXD,
590 	.dimm_idx_max	= DIMM_IDX_MAX_ON_BDXD,
591 	.min_peci_revision = 0x33,
592 	.read_thresholds = &read_thresholds_bdxd,
593 };
594 
595 static const struct dimm_info dimm_skx = {
596 	.chan_rank_max	= CHAN_RANK_MAX_ON_SKX,
597 	.dimm_idx_max	= DIMM_IDX_MAX_ON_SKX,
598 	.min_peci_revision = 0x33,
599 	.read_thresholds = &read_thresholds_skx,
600 };
601 
602 static const struct dimm_info dimm_icx = {
603 	.chan_rank_max	= CHAN_RANK_MAX_ON_ICX,
604 	.dimm_idx_max	= DIMM_IDX_MAX_ON_ICX,
605 	.min_peci_revision = 0x40,
606 	.read_thresholds = &read_thresholds_icx,
607 };
608 
609 static const struct dimm_info dimm_icxd = {
610 	.chan_rank_max	= CHAN_RANK_MAX_ON_ICXD,
611 	.dimm_idx_max	= DIMM_IDX_MAX_ON_ICXD,
612 	.min_peci_revision = 0x40,
613 	.read_thresholds = &read_thresholds_icx,
614 };
615 
616 static const struct dimm_info dimm_spr = {
617 	.chan_rank_max	= CHAN_RANK_MAX_ON_SPR,
618 	.dimm_idx_max	= DIMM_IDX_MAX_ON_SPR,
619 	.min_peci_revision = 0x40,
620 	.read_thresholds = &read_thresholds_spr,
621 };
622 
623 static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
624 	{
625 		.name = "peci_cpu.dimmtemp.hsx",
626 		.driver_data = (kernel_ulong_t)&dimm_hsx,
627 	},
628 	{
629 		.name = "peci_cpu.dimmtemp.bdx",
630 		.driver_data = (kernel_ulong_t)&dimm_bdx,
631 	},
632 	{
633 		.name = "peci_cpu.dimmtemp.bdxd",
634 		.driver_data = (kernel_ulong_t)&dimm_bdxd,
635 	},
636 	{
637 		.name = "peci_cpu.dimmtemp.skx",
638 		.driver_data = (kernel_ulong_t)&dimm_skx,
639 	},
640 	{
641 		.name = "peci_cpu.dimmtemp.icx",
642 		.driver_data = (kernel_ulong_t)&dimm_icx,
643 	},
644 	{
645 		.name = "peci_cpu.dimmtemp.icxd",
646 		.driver_data = (kernel_ulong_t)&dimm_icxd,
647 	},
648 	{
649 		.name = "peci_cpu.dimmtemp.spr",
650 		.driver_data = (kernel_ulong_t)&dimm_spr,
651 	},
652 	{ }
653 };
654 MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
655 
656 static struct auxiliary_driver peci_dimmtemp_driver = {
657 	.probe		= peci_dimmtemp_probe,
658 	.id_table	= peci_dimmtemp_ids,
659 };
660 
661 module_auxiliary_driver(peci_dimmtemp_driver);
662 
663 MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>");
664 MODULE_AUTHOR("Iwona Winiarska <iwona.winiarska@intel.com>");
665 MODULE_DESCRIPTION("PECI dimmtemp driver");
666 MODULE_LICENSE("GPL");
667 MODULE_IMPORT_NS("PECI_CPU");
668