xref: /linux/drivers/ras/amd/atl/reg_fields.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * AMD Address Translation Library
4  *
5  * reg_fields.h : Register field definitions
6  *
7  * Copyright (c) 2023, Advanced Micro Devices, Inc.
8  * All Rights Reserved.
9  *
10  * Author: Yazen Ghannam <Yazen.Ghannam@amd.com>
11  */
12 
13 /*
14  * Notes on naming:
15  * 1) Use "DF_" prefix for fields that are the same for all revisions.
16  * 2) Use "DFx_" prefix for fields that differ between revisions.
17  *	a) "x" is the first major revision where the new field appears.
18  *	b) E.g., if DF2 and DF3 have the same field, then call it DF2.
19  *	c) E.g., if DF3p5 and DF4 have the same field, then call it DF4.
20  */
21 
22 /*
23  * Coherent Station Fabric ID
24  *
25  * Access type: Instance
26  *
27  * Register
28  *	Rev	Fieldname	Bits
29  *
30  *	D18F0x50 [Fabric Block Instance Information 3]
31  *	DF2	BlockFabricId	[19:8]
32  *	DF3	BlockFabricId	[19:8]
33  *	DF3p5	BlockFabricId	[19:8]
34  *	DF4	BlockFabricId	[19:8]
35  *	DF4p5	BlockFabricId	[15:8]
36  */
37 #define DF2_COH_ST_FABRIC_ID	GENMASK(19, 8)
38 #define DF4p5_COH_ST_FABRIC_ID	GENMASK(15, 8)
39 
40 /*
41  * Component ID Mask
42  *
43  * Access type: Broadcast
44  *
45  * Register
46  *	Rev	Fieldname	Bits
47  *
48  *	DF2	N/A
49  *
50  *	D18F1x208 [System Fabric ID Mask 0]
51  *	DF3	ComponentIdMask	[9:0]
52  *
53  *	D18F1x150 [System Fabric ID Mask 0]
54  *	DF3p5	ComponentIdMask	[15:0]
55  *
56  *	D18F4x1B0 [System Fabric ID Mask 0]
57  *	DF4	ComponentIdMask	[15:0]
58  *	DF4p5	ComponentIdMask	[15:0]
59  */
60 #define DF3_COMPONENT_ID_MASK	GENMASK(9, 0)
61 #define DF4_COMPONENT_ID_MASK	GENMASK(15, 0)
62 
63 /*
64  * Destination Fabric ID
65  *
66  * Access type: Instance
67  *
68  * Register
69  *	Rev	Fieldname	Bits
70  *
71  *	D18F0x114 [DRAM Limit Address]
72  *	DF2	DstFabricID	[7:0]
73  *	DF3	DstFabricID	[9:0]
74  *	DF3	DstFabricID	[11:0]
75  *
76  *	D18F7xE08 [DRAM Address Control]
77  *	DF4	DstFabricID	[27:16]
78  *
79  *	D18F7x208 [DRAM Address Control]
80  *	DF4p5	DstFabricID	[23:16]
81  */
82 #define DF2_DST_FABRIC_ID	GENMASK(7, 0)
83 #define DF3_DST_FABRIC_ID	GENMASK(9, 0)
84 #define DF3p5_DST_FABRIC_ID	GENMASK(11, 0)
85 #define DF4_DST_FABRIC_ID	GENMASK(27, 16)
86 #define DF4p5_DST_FABRIC_ID	GENMASK(23, 16)
87 
88 /*
89  * Die ID Mask
90  *
91  * Access type: Broadcast
92  *
93  * Register
94  *	Rev	Fieldname	Bits
95  *
96  *	D18F1x208 [System Fabric ID Mask]
97  *	DF2	DieIdMask	[15:8]
98  *
99  *	D18F1x20C [System Fabric ID Mask 1]
100  *	DF3	DieIdMask	[18:16]
101  *
102  *	D18F1x158 [System Fabric ID Mask 2]
103  *	DF3p5	DieIdMask	[15:0]
104  *
105  *	D18F4x1B8 [System Fabric ID Mask 2]
106  *	DF4	DieIdMask	[15:0]
107  *	DF4p5	DieIdMask	[15:0]
108  */
109 #define DF2_DIE_ID_MASK		GENMASK(15, 8)
110 #define DF3_DIE_ID_MASK		GENMASK(18, 16)
111 #define DF4_DIE_ID_MASK		GENMASK(15, 0)
112 
113 /*
114  * Die ID Shift
115  *
116  * Access type: Broadcast
117  *
118  * Register
119  *	Rev	Fieldname	Bits
120  *
121  *	D18F1x208 [System Fabric ID Mask]
122  *	DF2	DieIdShift	[27:24]
123  *
124  *	DF3	N/A
125  *	DF3p5	N/A
126  *	DF4	N/A
127  *	DF4p5	N/A
128  */
129 #define DF2_DIE_ID_SHIFT	GENMASK(27, 24)
130 
131 /*
132  * DRAM Address Range Valid
133  *
134  * Access type: Instance
135  *
136  * Register
137  *	Rev	Fieldname	Bits
138  *
139  *	D18F0x110 [DRAM Base Address]
140  *	DF2	AddrRngVal	[0]
141  *	DF3	AddrRngVal	[0]
142  *	DF3p5	AddrRngVal	[0]
143  *
144  *	D18F7xE08 [DRAM Address Control]
145  *	DF4	AddrRngVal	[0]
146  *
147  *	D18F7x208 [DRAM Address Control]
148  *	DF4p5	AddrRngVal	[0]
149  */
150 #define DF_ADDR_RANGE_VAL	BIT(0)
151 
152 /*
153  * DRAM Base Address
154  *
155  * Access type: Instance
156  *
157  * Register
158  *	Rev	Fieldname	Bits
159  *
160  *	D18F0x110 [DRAM Base Address]
161  *	DF2	DramBaseAddr	[31:12]
162  *	DF3	DramBaseAddr	[31:12]
163  *	DF3p5	DramBaseAddr	[31:12]
164  *
165  *	D18F7xE00 [DRAM Base Address]
166  *	DF4	DramBaseAddr	[27:0]
167  *
168  *	D18F7x200 [DRAM Base Address]
169  *	DF4p5	DramBaseAddr	[27:0]
170  */
171 #define DF2_BASE_ADDR		GENMASK(31, 12)
172 #define DF4_BASE_ADDR		GENMASK(27, 0)
173 
174 /*
175  * DRAM Hole Base
176  *
177  * Access type: Broadcast
178  *
179  * Register
180  *	Rev	Fieldname	Bits
181  *
182  *	D18F0x104 [DRAM Hole Control]
183  *	DF2	DramHoleBase	[31:24]
184  *	DF3	DramHoleBase	[31:24]
185  *	DF3p5	DramHoleBase	[31:24]
186  *
187  *	D18F7x104 [DRAM Hole Control]
188  *	DF4	DramHoleBase	[31:24]
189  *	DF4p5	DramHoleBase	[31:24]
190  */
191 #define DF_DRAM_HOLE_BASE_MASK	GENMASK(31, 24)
192 
193 /*
194  * DRAM Limit Address
195  *
196  * Access type: Instance
197  *
198  * Register
199  *	Rev	Fieldname	Bits
200  *
201  *	D18F0x114 [DRAM Limit Address]
202  *	DF2	DramLimitAddr	[31:12]
203  *	DF3	DramLimitAddr	[31:12]
204  *	DF3p5	DramLimitAddr	[31:12]
205  *
206  *	D18F7xE04 [DRAM Limit Address]
207  *	DF4	DramLimitAddr	[27:0]
208  *
209  *	D18F7x204 [DRAM Limit Address]
210  *	DF4p5	DramLimitAddr	[27:0]
211  */
212 #define DF2_DRAM_LIMIT_ADDR	GENMASK(31, 12)
213 #define DF4_DRAM_LIMIT_ADDR	GENMASK(27, 0)
214 
215 /*
216  * Hash Interleave Controls
217  *
218  * Access type: Instance
219  *
220  * Register
221  *	Rev	Fieldname	Bits
222  *
223  *	DF2	N/A
224  *
225  *	D18F0x3F8 [DF Global Control]
226  *	DF3	GlbHashIntlvCtl64K	[20]
227  *		GlbHashIntlvCtl2M	[21]
228  *		GlbHashIntlvCtl1G	[22]
229  *
230  *	DF3p5	GlbHashIntlvCtl64K	[20]
231  *		GlbHashIntlvCtl2M	[21]
232  *		GlbHashIntlvCtl1G	[22]
233  *
234  *	D18F7xE08 [DRAM Address Control]
235  *	DF4	HashIntlvCtl64K		[8]
236  *		HashIntlvCtl2M		[9]
237  *		HashIntlvCtl1G		[10]
238  *
239  *	D18F7x208 [DRAM Address Control]
240  *	DF4p5	HashIntlvCtl4K		[7]
241  *		HashIntlvCtl64K		[8]
242  *		HashIntlvCtl2M		[9]
243  *		HashIntlvCtl1G		[10]
244  *		HashIntlvCtl1T		[15]
245  */
246 #define DF3_HASH_CTL_64K		BIT(20)
247 #define DF3_HASH_CTL_2M			BIT(21)
248 #define DF3_HASH_CTL_1G			BIT(22)
249 #define DF4_HASH_CTL_64K		BIT(8)
250 #define DF4_HASH_CTL_2M			BIT(9)
251 #define DF4_HASH_CTL_1G			BIT(10)
252 #define DF4p5_HASH_CTL_4K		BIT(7)
253 #define DF4p5_HASH_CTL_1T		BIT(15)
254 
255 /*
256  * High Address Offset
257  *
258  * Access type: Instance
259  *
260  * Register
261  *	Rev	Fieldname	Bits
262  *
263  *	D18F0x1B4 [DRAM Offset]
264  *	DF2	HiAddrOffset	[31:20]
265  *	DF3	HiAddrOffset	[31:12]
266  *	DF3p5	HiAddrOffset	[31:12]
267  *
268  *	D18F7x140 [DRAM Offset]
269  *	DF4	HiAddrOffset	[24:1]
270  *	DF4p5	HiAddrOffset	[24:1]
271  *	MI300	HiAddrOffset	[31:1]
272  */
273 #define DF2_HI_ADDR_OFFSET	GENMASK(31, 20)
274 #define DF3_HI_ADDR_OFFSET	GENMASK(31, 12)
275 
276 /* Follow reference code by including reserved bits for simplicity. */
277 #define DF4_HI_ADDR_OFFSET	GENMASK(31, 1)
278 
279 /*
280  * High Address Offset Enable
281  *
282  * Access type: Instance
283  *
284  * Register
285  *	Rev	Fieldname	Bits
286  *
287  *	D18F0x1B4 [DRAM Offset]
288  *	DF2	HiAddrOffsetEn	[0]
289  *	DF3	HiAddrOffsetEn	[0]
290  *	DF3p5	HiAddrOffsetEn	[0]
291  *
292  *	D18F7x140 [DRAM Offset]
293  *	DF4	HiAddrOffsetEn	[0]
294  *	DF4p5	HiAddrOffsetEn	[0]
295  */
296 #define DF_HI_ADDR_OFFSET_EN	BIT(0)
297 
298 /*
299  * Interleave Address Select
300  *
301  * Access type: Instance
302  *
303  * Register
304  *	Rev	Fieldname	Bits
305  *
306  *	D18F0x110 [DRAM Base Address]
307  *	DF2	IntLvAddrSel	[10:8]
308  *	DF3	IntLvAddrSel	[11:9]
309  *	DF3p5	IntLvAddrSel	[11:9]
310  *
311  *	D18F7xE0C [DRAM Address Interleave]
312  *	DF4	IntLvAddrSel	[2:0]
313  *
314  *	D18F7x20C [DRAM Address Interleave]
315  *	DF4p5	IntLvAddrSel	[2:0]
316  */
317 #define DF2_INTLV_ADDR_SEL	GENMASK(10, 8)
318 #define DF3_INTLV_ADDR_SEL	GENMASK(11, 9)
319 #define DF4_INTLV_ADDR_SEL	GENMASK(2, 0)
320 
321 /*
322  * Interleave Number of Channels
323  *
324  * Access type: Instance
325  *
326  * Register
327  *	Rev	Fieldname	Bits
328  *
329  *	D18F0x110 [DRAM Base Address]
330  *	DF2	IntLvNumChan	[7:4]
331  *	DF3	IntLvNumChan	[5:2]
332  *	DF3p5	IntLvNumChan	[6:2]
333  *
334  *	D18F7xE0C [DRAM Address Interleave]
335  *	DF4	IntLvNumChan	[8:4]
336  *
337  *	D18F7x20C [DRAM Address Interleave]
338  *	DF4p5	IntLvNumChan	[9:4]
339  */
340 #define DF2_INTLV_NUM_CHAN	GENMASK(7, 4)
341 #define DF3_INTLV_NUM_CHAN	GENMASK(5, 2)
342 #define DF3p5_INTLV_NUM_CHAN	GENMASK(6, 2)
343 #define DF4_INTLV_NUM_CHAN	GENMASK(8, 4)
344 #define DF4p5_INTLV_NUM_CHAN	GENMASK(9, 4)
345 
346 /*
347  * Interleave Number of Dies
348  *
349  * Access type: Instance
350  *
351  * Register
352  *	Rev	Fieldname	Bits
353  *
354  *	D18F0x114 [DRAM Limit Address]
355  *	DF2	IntLvNumDies	[11:10]
356  *
357  *	D18F0x110 [DRAM Base Address]
358  *	DF3	IntLvNumDies	[7:6]
359  *	DF3p5	IntLvNumDies	[7]
360  *
361  *	D18F7xE0C [DRAM Address Interleave]
362  *	DF4	IntLvNumDies	[13:12]
363  *
364  *	D18F7x20C [DRAM Address Interleave]
365  *	DF4p5	IntLvNumDies	[13:12]
366  */
367 #define DF2_INTLV_NUM_DIES	GENMASK(11, 10)
368 #define DF3_INTLV_NUM_DIES	GENMASK(7, 6)
369 #define DF3p5_INTLV_NUM_DIES	BIT(7)
370 #define DF4_INTLV_NUM_DIES	GENMASK(13, 12)
371 
372 /*
373  * Interleave Number of Sockets
374  *
375  * Access type: Instance
376  *
377  * Register
378  *	Rev	Fieldname	Bits
379  *
380  *	D18F0x114 [DRAM Limit Address]
381  *	DF2	IntLvNumSockets	[8]
382  *
383  *	D18F0x110 [DRAM Base Address]
384  *	DF3	IntLvNumSockets	[8]
385  *	DF3p5	IntLvNumSockets	[8]
386  *
387  *	D18F7xE0C [DRAM Address Interleave]
388  *	DF4	IntLvNumSockets	[18]
389  *
390  *	D18F7x20C [DRAM Address Interleave]
391  *	DF4p5	IntLvNumSockets	[18]
392  */
393 #define DF2_INTLV_NUM_SOCKETS	BIT(8)
394 #define DF4_INTLV_NUM_SOCKETS	BIT(18)
395 
396 /*
397  * Legacy MMIO Hole Enable
398  *
399  * Access type: Instance
400  *
401  * Register
402  *	Rev	Fieldname	Bits
403  *
404  *	D18F0x110 [DRAM Base Address]
405  *	DF2	LgcyMmioHoleEn	[1]
406  *	DF3	LgcyMmioHoleEn	[1]
407  *	DF3p5	LgcyMmioHoleEn	[1]
408  *
409  *	D18F7xE08 [DRAM Address Control]
410  *	DF4	LgcyMmioHoleEn	[1]
411  *
412  *	D18F7x208 [DRAM Address Control]
413  *	DF4p5	LgcyMmioHoleEn	[1]
414  */
415 #define DF_LEGACY_MMIO_HOLE_EN	BIT(1)
416 
417 /*
418  * Log2 Address 64K Space 0
419  *
420  * Access type: Instance
421  *
422  * Register
423  *	Rev	Fieldname		Bits
424  *
425  *	DF2	N/A
426  *
427  *	D18F2x90 [Non-power-of-2 channel Configuration Register for COH_ST DRAM Address Maps]
428  *	DF3	Log2Addr64KSpace0	[5:0]
429  *
430  *	DF3p5	N/A
431  *	DF4	N/A
432  *	DF4p5	N/A
433  */
434 #define DF_LOG2_ADDR_64K_SPACE0		GENMASK(5, 0)
435 
436 /*
437  * Major Revision
438  *
439  * Access type: Broadcast
440  *
441  * Register
442  *	Rev	Fieldname	Bits
443  *
444  *	DF2	N/A
445  *	DF3	N/A
446  *	DF3p5	N/A
447  *
448  *	D18F0x040 [Fabric Block Instance Count]
449  *	DF4	MajorRevision	[27:24]
450  *	DF4p5	MajorRevision	[27:24]
451  */
452 #define DF_MAJOR_REVISION	GENMASK(27, 24)
453 
454 /*
455  * Minor Revision
456  *
457  * Access type: Broadcast
458  *
459  * Register
460  *	Rev	Fieldname	Bits
461  *
462  *	DF2	N/A
463  *	DF3	N/A
464  *	DF3p5	N/A
465  *
466  *	D18F0x040 [Fabric Block Instance Count]
467  *	DF4	MinorRevision	[23:16]
468  *	DF4p5	MinorRevision	[23:16]
469  */
470 #define DF_MINOR_REVISION	GENMASK(23, 16)
471 
472 /*
473  * Node ID Mask
474  *
475  * Access type: Broadcast
476  *
477  * Register
478  *	Rev	Fieldname	Bits
479  *
480  *	DF2	N/A
481  *
482  *	D18F1x208 [System Fabric ID Mask 0]
483  *	DF3	NodeIdMask	[25:16]
484  *
485  *	D18F1x150 [System Fabric ID Mask 0]
486  *	DF3p5	NodeIdMask	[31:16]
487  *
488  *	D18F4x1B0 [System Fabric ID Mask 0]
489  *	DF4	NodeIdMask	[31:16]
490  *	DF4p5	NodeIdMask	[31:16]
491  */
492 #define DF3_NODE_ID_MASK	GENMASK(25, 16)
493 #define DF4_NODE_ID_MASK	GENMASK(31, 16)
494 
495 /*
496  * Node ID Shift
497  *
498  * Access type: Broadcast
499  *
500  * Register
501  *	Rev	Fieldname	Bits
502  *
503  *	DF2	N/A
504  *
505  *	D18F1x20C [System Fabric ID Mask 1]
506  *	DF3	NodeIdShift	[3:0]
507  *
508  *	D18F1x154 [System Fabric ID Mask 1]
509  *	DF3p5	NodeIdShift	[3:0]
510  *
511  *	D18F4x1B4 [System Fabric ID Mask 1]
512  *	DF4	NodeIdShift	[3:0]
513  *	DF4p5	NodeIdShift	[3:0]
514  */
515 #define DF3_NODE_ID_SHIFT	GENMASK(3, 0)
516 
517 /*
518  * Remap Enable
519  *
520  * Access type: Instance
521  *
522  * Register
523  *	Rev	Fieldname	Bits
524  *
525  *	DF2	N/A
526  *	DF3	N/A
527  *	DF3p5	N/A
528  *
529  *	D18F7xE08 [DRAM Address Control]
530  *	DF4	RemapEn		[4]
531  *
532  *	D18F7x208 [DRAM Address Control]
533  *	DF4p5	RemapEn		[4]
534  */
535 #define DF4_REMAP_EN		BIT(4)
536 
537 /*
538  * Remap Select
539  *
540  * Access type: Instance
541  *
542  * Register
543  *	Rev	Fieldname	Bits
544  *
545  *	DF2	N/A
546  *	DF3	N/A
547  *	DF3p5	N/A
548  *
549  *	D18F7xE08 [DRAM Address Control]
550  *	DF4	RemapSel	[7:5]
551  *
552  *	D18F7x208 [DRAM Address Control]
553  *	DF4p5	RemapSel	[6:5]
554  */
555 #define DF4_REMAP_SEL		GENMASK(7, 5)
556 #define DF4p5_REMAP_SEL		GENMASK(6, 5)
557 
558 /*
559  * Socket ID Mask
560  *
561  * Access type: Broadcast
562  *
563  * Register
564  *	Rev	Fieldname	Bits
565  *
566  * D18F1x208 [System Fabric ID Mask]
567  *	DF2	SocketIdMask	[23:16]
568  *
569  * D18F1x20C [System Fabric ID Mask 1]
570  *	DF3	SocketIdMask	[26:24]
571  *
572  * D18F1x158 [System Fabric ID Mask 2]
573  *	DF3p5	SocketIdMask	[31:16]
574  *
575  * D18F4x1B8 [System Fabric ID Mask 2]
576  *	DF4	SocketIdMask	[31:16]
577  *	DF4p5	SocketIdMask	[31:16]
578  */
579 #define DF2_SOCKET_ID_MASK	GENMASK(23, 16)
580 #define DF3_SOCKET_ID_MASK	GENMASK(26, 24)
581 #define DF4_SOCKET_ID_MASK	GENMASK(31, 16)
582 
583 /*
584  * Socket ID Shift
585  *
586  * Access type: Broadcast
587  *
588  * Register
589  *		Rev	Fieldname	Bits
590  *
591  * D18F1x208 [System Fabric ID Mask]
592  *	DF2	SocketIdShift	[31:28]
593  *
594  * D18F1x20C [System Fabric ID Mask 1]
595  *	DF3	SocketIdShift	[9:8]
596  *
597  * D18F1x158 [System Fabric ID Mask 2]
598  *	DF3p5	SocketIdShift	[11:8]
599  *
600  * D18F4x1B4 [System Fabric ID Mask 1]
601  *	DF4	SocketIdShift	[11:8]
602  *	DF4p5	SocketIdShift	[11:8]
603  */
604 #define DF2_SOCKET_ID_SHIFT	GENMASK(31, 28)
605 #define DF3_SOCKET_ID_SHIFT	GENMASK(9, 8)
606 #define DF4_SOCKET_ID_SHIFT	GENMASK(11, 8)
607