1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 *
5 * Author: Vitor Soares <vitor.soares@synopsys.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/i3c/master.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/iopoll.h>
18 #include <linux/list.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26
27 #include "../internals.h"
28 #include "dw-i3c-master.h"
29
30 #define DEVICE_CTRL 0x0
31 #define DEV_CTRL_ENABLE BIT(31)
32 #define DEV_CTRL_RESUME BIT(30)
33 #define DEV_CTRL_HOT_JOIN_NACK BIT(8)
34 #define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7)
35
36 #define DEVICE_ADDR 0x4
37 #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31)
38 #define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16))
39
40 #define HW_CAPABILITY 0x8
41 #define COMMAND_QUEUE_PORT 0xc
42 #define COMMAND_PORT_TOC BIT(30)
43 #define COMMAND_PORT_READ_TRANSFER BIT(28)
44 #define COMMAND_PORT_SDAP BIT(27)
45 #define COMMAND_PORT_ROC BIT(26)
46 #define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21))
47 #define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16))
48 #define COMMAND_PORT_CP BIT(15)
49 #define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7))
50 #define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3))
51
52 #define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16))
53 #define COMMAND_PORT_ARG_DATA_LEN_MAX 65536
54 #define COMMAND_PORT_TRANSFER_ARG 0x01
55
56 #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24))
57 #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16))
58 #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8))
59 #define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5)
60 #define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4)
61 #define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3)
62 #define COMMAND_PORT_SHORT_DATA_ARG 0x02
63
64 #define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21))
65 #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03
66
67 #define RESPONSE_QUEUE_PORT 0x10
68 #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28)
69 #define RESPONSE_NO_ERROR 0
70 #define RESPONSE_ERROR_CRC 1
71 #define RESPONSE_ERROR_PARITY 2
72 #define RESPONSE_ERROR_FRAME 3
73 #define RESPONSE_ERROR_IBA_NACK 4
74 #define RESPONSE_ERROR_ADDRESS_NACK 5
75 #define RESPONSE_ERROR_OVER_UNDER_FLOW 6
76 #define RESPONSE_ERROR_TRANSF_ABORT 8
77 #define RESPONSE_ERROR_I2C_W_NACK_ERR 9
78 #define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24)
79 #define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0))
80
81 #define RX_TX_DATA_PORT 0x14
82 #define IBI_QUEUE_STATUS 0x18
83 #define IBI_QUEUE_STATUS_IBI_ID(x) (((x) & GENMASK(15, 8)) >> 8)
84 #define IBI_QUEUE_STATUS_DATA_LEN(x) ((x) & GENMASK(7, 0))
85 #define IBI_QUEUE_IBI_ADDR(x) (IBI_QUEUE_STATUS_IBI_ID(x) >> 1)
86 #define IBI_QUEUE_IBI_RNW(x) (IBI_QUEUE_STATUS_IBI_ID(x) & BIT(0))
87 #define IBI_TYPE_MR(x) \
88 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
89 #define IBI_TYPE_HJ(x) \
90 ((IBI_QUEUE_IBI_ADDR(x) == I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
91 #define IBI_TYPE_SIRQ(x) \
92 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && IBI_QUEUE_IBI_RNW(x))
93
94 #define QUEUE_THLD_CTRL 0x1c
95 #define QUEUE_THLD_CTRL_IBI_STAT_MASK GENMASK(31, 24)
96 #define QUEUE_THLD_CTRL_IBI_STAT(x) (((x) - 1) << 24)
97 #define QUEUE_THLD_CTRL_IBI_DATA_MASK GENMASK(20, 16)
98 #define QUEUE_THLD_CTRL_IBI_DATA(x) ((x) << 16)
99 #define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8)
100 #define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8)
101
102 #define DATA_BUFFER_THLD_CTRL 0x20
103 #define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8)
104
105 #define IBI_QUEUE_CTRL 0x24
106 #define IBI_MR_REQ_REJECT 0x2C
107 #define IBI_SIR_REQ_REJECT 0x30
108 #define IBI_REQ_REJECT_ALL GENMASK(31, 0)
109
110 #define RESET_CTRL 0x34
111 #define RESET_CTRL_IBI_QUEUE BIT(5)
112 #define RESET_CTRL_RX_FIFO BIT(4)
113 #define RESET_CTRL_TX_FIFO BIT(3)
114 #define RESET_CTRL_RESP_QUEUE BIT(2)
115 #define RESET_CTRL_CMD_QUEUE BIT(1)
116 #define RESET_CTRL_SOFT BIT(0)
117
118 #define SLV_EVENT_CTRL 0x38
119 #define INTR_STATUS 0x3c
120 #define INTR_STATUS_EN 0x40
121 #define INTR_SIGNAL_EN 0x44
122 #define INTR_FORCE 0x48
123 #define INTR_BUSOWNER_UPDATE_STAT BIT(13)
124 #define INTR_IBI_UPDATED_STAT BIT(12)
125 #define INTR_READ_REQ_RECV_STAT BIT(11)
126 #define INTR_DEFSLV_STAT BIT(10)
127 #define INTR_TRANSFER_ERR_STAT BIT(9)
128 #define INTR_DYN_ADDR_ASSGN_STAT BIT(8)
129 #define INTR_CCC_UPDATED_STAT BIT(6)
130 #define INTR_TRANSFER_ABORT_STAT BIT(5)
131 #define INTR_RESP_READY_STAT BIT(4)
132 #define INTR_CMD_QUEUE_READY_STAT BIT(3)
133 #define INTR_IBI_THLD_STAT BIT(2)
134 #define INTR_RX_THLD_STAT BIT(1)
135 #define INTR_TX_THLD_STAT BIT(0)
136 #define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \
137 INTR_IBI_UPDATED_STAT | \
138 INTR_READ_REQ_RECV_STAT | \
139 INTR_DEFSLV_STAT | \
140 INTR_TRANSFER_ERR_STAT | \
141 INTR_DYN_ADDR_ASSGN_STAT | \
142 INTR_CCC_UPDATED_STAT | \
143 INTR_TRANSFER_ABORT_STAT | \
144 INTR_RESP_READY_STAT | \
145 INTR_CMD_QUEUE_READY_STAT | \
146 INTR_IBI_THLD_STAT | \
147 INTR_TX_THLD_STAT | \
148 INTR_RX_THLD_STAT)
149
150 #define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \
151 INTR_RESP_READY_STAT)
152
153 #define QUEUE_STATUS_LEVEL 0x4c
154 #define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24)
155 #define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16)
156 #define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8)
157 #define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0))
158
159 #define DATA_BUFFER_STATUS_LEVEL 0x50
160 #define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0))
161
162 #define PRESENT_STATE 0x54
163 #define CCC_DEVICE_STATUS 0x58
164 #define DEVICE_ADDR_TABLE_POINTER 0x5c
165 #define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16)
166 #define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0))
167
168 #define DEV_CHAR_TABLE_POINTER 0x60
169 #define VENDOR_SPECIFIC_REG_POINTER 0x6c
170 #define SLV_PID_VALUE 0x74
171 #define SLV_CHAR_CTRL 0x78
172 #define SLV_MAX_LEN 0x7c
173 #define MAX_READ_TURNAROUND 0x80
174 #define MAX_DATA_SPEED 0x84
175 #define SLV_DEBUG_STATUS 0x88
176 #define SLV_INTR_REQ 0x8c
177 #define DEVICE_CTRL_EXTENDED 0xb0
178 #define SCL_I3C_OD_TIMING 0xb4
179 #define SCL_I3C_PP_TIMING 0xb8
180 #define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
181 #define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0))
182 #define SCL_I3C_TIMING_CNT_MIN 5
183
184 #define SCL_I2C_FM_TIMING 0xbc
185 #define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16))
186 #define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
187
188 #define SCL_I2C_FMP_TIMING 0xc0
189 #define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
190 #define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
191
192 #define SCL_EXT_LCNT_TIMING 0xc8
193 #define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24))
194 #define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16))
195 #define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8))
196 #define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0))
197
198 #define SCL_EXT_TERMN_LCNT_TIMING 0xcc
199 #define BUS_FREE_TIMING 0xd4
200 #define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0))
201
202 #define BUS_IDLE_TIMING 0xd8
203 #define I3C_VER_ID 0xe0
204 #define I3C_VER_TYPE 0xe4
205 #define EXTENDED_CAPABILITY 0xe8
206 #define SLAVE_CONFIG 0xec
207
208 #define DYN_ADDR_LO_MASK GENMASK(4, 0)
209 #define DYN_ADDR_HI_MASK GENMASK(6, 5)
210 #define IBI_SIR_BIT_MOD 32 /* 32-bit vector */
211
212 #define DW_I3C_DEV_NACK_RETRY_CNT_MAX 0x3
213 #define DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK GENMASK(30, 29)
214 #define DEV_ADDR_TABLE_DYNAMIC_MASK GENMASK(23, 16)
215 #define DEV_ADDR_TABLE_STATIC_MASK GENMASK(6, 0)
216 #define DEV_ADDR_TABLE_IBI_MDB BIT(12)
217 #define DEV_ADDR_TABLE_SIR_REJECT BIT(13)
218 #define DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(x) \
219 FIELD_PREP(DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK, (x))
220 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31)
221 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_DYNAMIC_MASK, x)
222 #define DEV_ADDR_TABLE_STATIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_STATIC_MASK, x)
223 #define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2))
224 #define DEV_ADDR_TABLE_GET_DYNAMIC_ADDR(x) FIELD_GET(DEV_ADDR_TABLE_DYNAMIC_MASK, x)
225
226 #define I3C_BUS_SDR1_SCL_RATE 8000000
227 #define I3C_BUS_SDR2_SCL_RATE 6000000
228 #define I3C_BUS_SDR3_SCL_RATE 4000000
229 #define I3C_BUS_SDR4_SCL_RATE 2000000
230 #define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300
231 #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500
232 #define I3C_BUS_THIGH_MAX_NS 41
233
234 #define XFER_TIMEOUT (msecs_to_jiffies(1000))
235 #define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */
236
237 /* Timing values to configure 12.5MHz frequency */
238 #define AMD_I3C_OD_TIMING 0x4C007C
239 #define AMD_I3C_PP_TIMING 0x8001A
240
241 /* List of quirks */
242 #define AMD_I3C_OD_PP_TIMING BIT(1)
243 #define DW_I3C_DISABLE_RUNTIME_PM_QUIRK BIT(2)
244
245 struct dw_i3c_cmd {
246 u32 cmd_lo;
247 u32 cmd_hi;
248 u16 tx_len;
249 const void *tx_buf;
250 u16 rx_len;
251 void *rx_buf;
252 u8 error;
253 };
254
255 struct dw_i3c_xfer {
256 struct list_head node;
257 struct completion comp;
258 int ret;
259 unsigned int ncmds;
260 struct dw_i3c_cmd cmds[] __counted_by(ncmds);
261 };
262
263 struct dw_i3c_i2c_dev_data {
264 u8 index;
265 struct i3c_generic_ibi_pool *ibi_pool;
266 };
267
268 struct dw_i3c_drvdata {
269 u32 flags;
270 };
271
get_ibi_sir_bit_index(u8 addr)272 static inline u32 get_ibi_sir_bit_index(u8 addr)
273 {
274 u32 lo = FIELD_GET(DYN_ADDR_LO_MASK, addr);
275 u32 hi = FIELD_GET(DYN_ADDR_HI_MASK, addr);
276
277 return (lo + hi) % IBI_SIR_BIT_MOD;
278 }
279
dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller * m,const struct i3c_ccc_cmd * cmd)280 static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
281 const struct i3c_ccc_cmd *cmd)
282 {
283 if (cmd->ndests > 1)
284 return false;
285
286 switch (cmd->id) {
287 case I3C_CCC_ENEC(true):
288 case I3C_CCC_ENEC(false):
289 case I3C_CCC_DISEC(true):
290 case I3C_CCC_DISEC(false):
291 case I3C_CCC_ENTAS(0, true):
292 case I3C_CCC_ENTAS(0, false):
293 case I3C_CCC_RSTDAA(true):
294 case I3C_CCC_RSTDAA(false):
295 case I3C_CCC_ENTDAA:
296 case I3C_CCC_SETMWL(true):
297 case I3C_CCC_SETMWL(false):
298 case I3C_CCC_SETMRL(true):
299 case I3C_CCC_SETMRL(false):
300 case I3C_CCC_ENTHDR(0):
301 case I3C_CCC_SETDASA:
302 case I3C_CCC_SETNEWDA:
303 case I3C_CCC_GETMWL:
304 case I3C_CCC_GETMRL:
305 case I3C_CCC_GETPID:
306 case I3C_CCC_GETBCR:
307 case I3C_CCC_GETDCR:
308 case I3C_CCC_GETSTATUS:
309 case I3C_CCC_GETMXDS:
310 case I3C_CCC_GETHDRCAP:
311 return true;
312 default:
313 return false;
314 }
315 }
316
317 static inline struct dw_i3c_master *
to_dw_i3c_master(struct i3c_master_controller * master)318 to_dw_i3c_master(struct i3c_master_controller *master)
319 {
320 return container_of(master, struct dw_i3c_master, base);
321 }
322
dw_i3c_master_disable(struct dw_i3c_master * master)323 static void dw_i3c_master_disable(struct dw_i3c_master *master)
324 {
325 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE,
326 master->regs + DEVICE_CTRL);
327 }
328
dw_i3c_master_enable(struct dw_i3c_master * master)329 static void dw_i3c_master_enable(struct dw_i3c_master *master)
330 {
331 u32 dev_ctrl;
332
333 dev_ctrl = readl(master->regs + DEVICE_CTRL);
334 /* For now don't support Hot-Join */
335 dev_ctrl |= DEV_CTRL_HOT_JOIN_NACK;
336 if (master->i2c_slv_prsnt)
337 dev_ctrl |= DEV_CTRL_I2C_SLAVE_PRESENT;
338 writel(dev_ctrl | DEV_CTRL_ENABLE,
339 master->regs + DEVICE_CTRL);
340 }
341
dw_i3c_master_get_addr_pos(struct dw_i3c_master * master,u8 addr)342 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr)
343 {
344 int pos;
345
346 for (pos = 0; pos < master->maxdevs; pos++) {
347 if (addr == master->devs[pos].addr)
348 return pos;
349 }
350
351 return -EINVAL;
352 }
353
dw_i3c_master_get_free_pos(struct dw_i3c_master * master)354 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
355 {
356 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))
357 return -ENOSPC;
358
359 return ffs(master->free_pos) - 1;
360 }
361
dw_i3c_master_wr_tx_fifo(struct dw_i3c_master * master,const u8 * bytes,int nbytes)362 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
363 const u8 *bytes, int nbytes)
364 {
365 i3c_writel_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes);
366 }
367
dw_i3c_master_read_rx_fifo(struct dw_i3c_master * master,u8 * bytes,int nbytes)368 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
369 u8 *bytes, int nbytes)
370 {
371 i3c_readl_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes);
372 }
373
dw_i3c_master_read_ibi_fifo(struct dw_i3c_master * master,u8 * bytes,int nbytes)374 static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master,
375 u8 *bytes, int nbytes)
376 {
377 i3c_readl_fifo(master->regs + IBI_QUEUE_STATUS, bytes, nbytes);
378 }
379
380 static struct dw_i3c_xfer *
dw_i3c_master_alloc_xfer(struct dw_i3c_master * master,unsigned int ncmds)381 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
382 {
383 struct dw_i3c_xfer *xfer;
384
385 xfer = kzalloc_flex(*xfer, cmds, ncmds);
386 if (!xfer)
387 return NULL;
388
389 INIT_LIST_HEAD(&xfer->node);
390 xfer->ncmds = ncmds;
391 xfer->ret = -ETIMEDOUT;
392
393 return xfer;
394 }
395
dw_i3c_master_free_xfer(struct dw_i3c_xfer * xfer)396 static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer)
397 {
398 kfree(xfer);
399 }
400
dw_i3c_master_start_xfer_locked(struct dw_i3c_master * master)401 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master)
402 {
403 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
404 unsigned int i;
405 u32 thld_ctrl;
406
407 if (!xfer)
408 return;
409
410 for (i = 0; i < xfer->ncmds; i++) {
411 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
412
413 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len);
414 }
415
416 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
417 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
418 thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds);
419 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
420
421 for (i = 0; i < xfer->ncmds; i++) {
422 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
423
424 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT);
425 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT);
426 }
427 }
428
dw_i3c_master_enqueue_xfer(struct dw_i3c_master * master,struct dw_i3c_xfer * xfer)429 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master,
430 struct dw_i3c_xfer *xfer)
431 {
432 init_completion(&xfer->comp);
433 guard(spinlock_irqsave)(&master->xferqueue.lock);
434 if (master->xferqueue.cur) {
435 list_add_tail(&xfer->node, &master->xferqueue.list);
436 } else {
437 master->xferqueue.cur = xfer;
438 dw_i3c_master_start_xfer_locked(master);
439 }
440 }
441
dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master * master,struct dw_i3c_xfer * xfer)442 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master,
443 struct dw_i3c_xfer *xfer)
444 {
445 if (master->xferqueue.cur == xfer) {
446 u32 status;
447
448 master->xferqueue.cur = NULL;
449
450 writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO |
451 RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE,
452 master->regs + RESET_CTRL);
453
454 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status,
455 !status, 10, 1000000);
456 } else {
457 list_del_init(&xfer->node);
458 }
459 }
460
dw_i3c_master_dequeue_xfer(struct dw_i3c_master * master,struct dw_i3c_xfer * xfer)461 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master,
462 struct dw_i3c_xfer *xfer)
463 {
464 guard(spinlock_irqsave)(&master->xferqueue.lock);
465 dw_i3c_master_dequeue_xfer_locked(master, xfer);
466 }
467
dw_i3c_master_end_xfer_locked(struct dw_i3c_master * master,u32 isr)468 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr)
469 {
470 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
471 int i, ret = 0;
472 u32 nresp;
473
474 if (!xfer)
475 return;
476
477 nresp = readl(master->regs + QUEUE_STATUS_LEVEL);
478 nresp = QUEUE_STATUS_LEVEL_RESP(nresp);
479
480 for (i = 0; i < nresp; i++) {
481 struct dw_i3c_cmd *cmd;
482 u32 resp;
483
484 resp = readl(master->regs + RESPONSE_QUEUE_PORT);
485
486 cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)];
487 cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp);
488 cmd->error = RESPONSE_PORT_ERR_STATUS(resp);
489 if (cmd->rx_len && !cmd->error)
490 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf,
491 cmd->rx_len);
492 }
493
494 for (i = 0; i < nresp; i++) {
495 switch (xfer->cmds[i].error) {
496 case RESPONSE_NO_ERROR:
497 break;
498 case RESPONSE_ERROR_PARITY:
499 case RESPONSE_ERROR_IBA_NACK:
500 case RESPONSE_ERROR_TRANSF_ABORT:
501 case RESPONSE_ERROR_CRC:
502 case RESPONSE_ERROR_FRAME:
503 ret = -EIO;
504 break;
505 case RESPONSE_ERROR_OVER_UNDER_FLOW:
506 ret = -ENOSPC;
507 break;
508 case RESPONSE_ERROR_I2C_W_NACK_ERR:
509 case RESPONSE_ERROR_ADDRESS_NACK:
510 default:
511 ret = -EINVAL;
512 break;
513 }
514 }
515
516 xfer->ret = ret;
517 complete(&xfer->comp);
518
519 if (ret < 0) {
520 dw_i3c_master_dequeue_xfer_locked(master, xfer);
521 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
522 master->regs + DEVICE_CTRL);
523 }
524
525 xfer = list_first_entry_or_null(&master->xferqueue.list,
526 struct dw_i3c_xfer,
527 node);
528 if (xfer)
529 list_del_init(&xfer->node);
530
531 master->xferqueue.cur = xfer;
532 dw_i3c_master_start_xfer_locked(master);
533 }
534
dw_i3c_master_set_intr_regs(struct dw_i3c_master * master)535 static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master)
536 {
537 u32 thld_ctrl;
538
539 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
540 thld_ctrl &= ~(QUEUE_THLD_CTRL_RESP_BUF_MASK |
541 QUEUE_THLD_CTRL_IBI_STAT_MASK |
542 QUEUE_THLD_CTRL_IBI_DATA_MASK);
543 thld_ctrl |= QUEUE_THLD_CTRL_IBI_STAT(1) |
544 QUEUE_THLD_CTRL_IBI_DATA(31);
545 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
546
547 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
548 thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF;
549 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
550
551 writel(INTR_ALL, master->regs + INTR_STATUS);
552 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
553 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
554
555 master->sir_rej_mask = IBI_REQ_REJECT_ALL;
556 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT);
557
558 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
559 }
560
dw_i3c_clk_cfg(struct dw_i3c_master * master)561 static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
562 {
563 unsigned long core_rate, core_period;
564 u32 scl_timing;
565 u8 hcnt, lcnt;
566
567 core_rate = clk_get_rate(master->core_clk);
568 if (!core_rate)
569 return -EINVAL;
570
571 core_period = DIV_ROUND_UP(1000000000, core_rate);
572
573 hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1;
574 if (hcnt < SCL_I3C_TIMING_CNT_MIN)
575 hcnt = SCL_I3C_TIMING_CNT_MIN;
576
577 lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt;
578 if (lcnt < SCL_I3C_TIMING_CNT_MIN)
579 lcnt = SCL_I3C_TIMING_CNT_MIN;
580
581 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
582 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
583 master->i3c_pp_timing = scl_timing;
584
585 /*
586 * In pure i3c mode, MST_FREE represents tCAS. In shared mode, this
587 * will be set up by dw_i2c_clk_cfg as tLOW.
588 */
589 if (master->base.bus.mode == I3C_BUS_MODE_PURE) {
590 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
591 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt);
592 }
593
594 lcnt = max_t(u8,
595 DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt);
596 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
597 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
598 master->i3c_od_timing = scl_timing;
599
600 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt;
601 scl_timing = SCL_EXT_LCNT_1(lcnt);
602 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt;
603 scl_timing |= SCL_EXT_LCNT_2(lcnt);
604 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt;
605 scl_timing |= SCL_EXT_LCNT_3(lcnt);
606 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt;
607 scl_timing |= SCL_EXT_LCNT_4(lcnt);
608 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
609 master->ext_lcnt_timing = scl_timing;
610
611 return 0;
612 }
613
dw_i2c_clk_cfg(struct dw_i3c_master * master)614 static int dw_i2c_clk_cfg(struct dw_i3c_master *master)
615 {
616 unsigned long core_rate, core_period;
617 u16 hcnt, lcnt;
618 u32 scl_timing;
619
620 core_rate = clk_get_rate(master->core_clk);
621 if (!core_rate)
622 return -EINVAL;
623
624 core_period = DIV_ROUND_UP(1000000000, core_rate);
625
626 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period);
627 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE) - lcnt;
628 scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) |
629 SCL_I2C_FMP_TIMING_LCNT(lcnt);
630 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
631 master->i2c_fmp_timing = scl_timing;
632
633 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period);
634 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_MAX_RATE) - lcnt;
635 scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) |
636 SCL_I2C_FM_TIMING_LCNT(lcnt);
637 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
638 master->i2c_fm_timing = scl_timing;
639
640 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
641 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt);
642
643 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
644 master->regs + DEVICE_CTRL);
645 master->i2c_slv_prsnt = true;
646
647 return 0;
648 }
649
dw_i3c_master_bus_init(struct i3c_master_controller * m)650 static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
651 {
652 struct dw_i3c_master *master = to_dw_i3c_master(m);
653 struct i3c_bus *bus = i3c_master_get_bus(m);
654 struct i3c_device_info info = { };
655 int ret;
656
657 ret = pm_runtime_resume_and_get(master->dev);
658 if (ret < 0) {
659 dev_err(master->dev,
660 "<%s> cannot resume i3c bus master, err: %d\n",
661 __func__, ret);
662 return ret;
663 }
664
665 ret = master->platform_ops->init(master);
666 if (ret)
667 goto rpm_out;
668
669 switch (bus->mode) {
670 case I3C_BUS_MODE_MIXED_FAST:
671 case I3C_BUS_MODE_MIXED_LIMITED:
672 ret = dw_i2c_clk_cfg(master);
673 if (ret)
674 goto rpm_out;
675 fallthrough;
676 case I3C_BUS_MODE_PURE:
677 ret = dw_i3c_clk_cfg(master);
678 if (ret)
679 goto rpm_out;
680 break;
681 default:
682 ret = -EINVAL;
683 goto rpm_out;
684 }
685
686 ret = i3c_master_get_free_addr(m, 0);
687 if (ret < 0)
688 goto rpm_out;
689
690 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret),
691 master->regs + DEVICE_ADDR);
692 master->dev_addr = ret;
693 memset(&info, 0, sizeof(info));
694 info.dyn_addr = ret;
695
696 ret = i3c_master_set_info(&master->base, &info);
697 if (ret)
698 goto rpm_out;
699
700 dw_i3c_master_set_intr_regs(master);
701 dw_i3c_master_enable(master);
702
703 rpm_out:
704 pm_runtime_put_autosuspend(master->dev);
705 return ret;
706 }
707
dw_i3c_master_bus_cleanup(struct i3c_master_controller * m)708 static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m)
709 {
710 struct dw_i3c_master *master = to_dw_i3c_master(m);
711
712 dw_i3c_master_disable(master);
713 }
714
dw_i3c_ccc_set(struct dw_i3c_master * master,struct i3c_ccc_cmd * ccc)715 static int dw_i3c_ccc_set(struct dw_i3c_master *master,
716 struct i3c_ccc_cmd *ccc)
717 {
718 struct dw_i3c_xfer *xfer;
719 struct dw_i3c_cmd *cmd;
720 int ret, pos = 0;
721
722 if (ccc->id & I3C_CCC_DIRECT) {
723 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
724 if (pos < 0)
725 return pos;
726 }
727
728 xfer = dw_i3c_master_alloc_xfer(master, 1);
729 if (!xfer)
730 return -ENOMEM;
731
732 cmd = xfer->cmds;
733 cmd->tx_buf = ccc->dests[0].payload.data;
734 cmd->tx_len = ccc->dests[0].payload.len;
735
736 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
737 COMMAND_PORT_TRANSFER_ARG;
738
739 cmd->cmd_lo = COMMAND_PORT_CP |
740 COMMAND_PORT_DEV_INDEX(pos) |
741 COMMAND_PORT_CMD(ccc->id) |
742 COMMAND_PORT_TOC |
743 COMMAND_PORT_ROC;
744
745 dw_i3c_master_enqueue_xfer(master, xfer);
746 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
747 dw_i3c_master_dequeue_xfer(master, xfer);
748
749 ret = xfer->ret;
750 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
751 ccc->err = I3C_ERROR_M2;
752
753 dw_i3c_master_free_xfer(xfer);
754
755 return ret;
756 }
757
dw_i3c_ccc_get(struct dw_i3c_master * master,struct i3c_ccc_cmd * ccc)758 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc)
759 {
760 struct dw_i3c_xfer *xfer;
761 struct dw_i3c_cmd *cmd;
762 int ret, pos;
763
764 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
765 if (pos < 0)
766 return pos;
767
768 xfer = dw_i3c_master_alloc_xfer(master, 1);
769 if (!xfer)
770 return -ENOMEM;
771
772 cmd = xfer->cmds;
773 cmd->rx_buf = ccc->dests[0].payload.data;
774 cmd->rx_len = ccc->dests[0].payload.len;
775
776 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
777 COMMAND_PORT_TRANSFER_ARG;
778
779 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
780 COMMAND_PORT_CP |
781 COMMAND_PORT_DEV_INDEX(pos) |
782 COMMAND_PORT_CMD(ccc->id) |
783 COMMAND_PORT_TOC |
784 COMMAND_PORT_ROC;
785
786 dw_i3c_master_enqueue_xfer(master, xfer);
787 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
788 dw_i3c_master_dequeue_xfer(master, xfer);
789
790 ret = xfer->ret;
791 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
792 ccc->err = I3C_ERROR_M2;
793 dw_i3c_master_free_xfer(xfer);
794
795 return ret;
796 }
797
amd_configure_od_pp_quirk(struct dw_i3c_master * master)798 static void amd_configure_od_pp_quirk(struct dw_i3c_master *master)
799 {
800 master->i3c_od_timing = AMD_I3C_OD_TIMING;
801 master->i3c_pp_timing = AMD_I3C_PP_TIMING;
802 }
803
dw_i3c_master_send_ccc_cmd(struct i3c_master_controller * m,struct i3c_ccc_cmd * ccc)804 static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
805 struct i3c_ccc_cmd *ccc)
806 {
807 struct dw_i3c_master *master = to_dw_i3c_master(m);
808 int ret = 0;
809
810 if (ccc->id == I3C_CCC_ENTDAA)
811 return -EINVAL;
812
813 /* AMD platform specific OD and PP timings */
814 if (master->quirks & AMD_I3C_OD_PP_TIMING) {
815 amd_configure_od_pp_quirk(master);
816 writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
817 writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
818 }
819
820 ret = pm_runtime_resume_and_get(master->dev);
821 if (ret < 0) {
822 dev_err(master->dev,
823 "<%s> cannot resume i3c bus master, err: %d\n",
824 __func__, ret);
825 return ret;
826 }
827
828 if (ccc->rnw)
829 ret = dw_i3c_ccc_get(master, ccc);
830 else
831 ret = dw_i3c_ccc_set(master, ccc);
832
833 pm_runtime_put_autosuspend(master->dev);
834 return ret;
835 }
836
dw_i3c_master_daa(struct i3c_master_controller * m)837 static int dw_i3c_master_daa(struct i3c_master_controller *m)
838 {
839 struct dw_i3c_master *master = to_dw_i3c_master(m);
840 struct dw_i3c_xfer *xfer;
841 struct dw_i3c_cmd *cmd;
842 u32 olddevs, newdevs;
843 u8 last_addr = 0;
844 int ret, pos;
845
846 ret = pm_runtime_resume_and_get(master->dev);
847 if (ret < 0) {
848 dev_err(master->dev,
849 "<%s> cannot resume i3c bus master, err: %d\n",
850 __func__, ret);
851 return ret;
852 }
853
854 olddevs = ~(master->free_pos);
855
856 /* Prepare DAT before launching DAA. */
857 for (pos = 0; pos < master->maxdevs; pos++) {
858 if (olddevs & BIT(pos))
859 continue;
860
861 ret = i3c_master_get_free_addr(m, last_addr + 1);
862 if (ret < 0) {
863 ret = -ENOSPC;
864 goto rpm_out;
865 }
866
867 master->devs[pos].addr = ret;
868 last_addr = ret;
869
870 ret |= parity8(ret) ? 0 : BIT(7);
871
872 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret),
873 master->regs +
874 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
875
876 ret = 0;
877 }
878
879 xfer = dw_i3c_master_alloc_xfer(master, 1);
880 if (!xfer) {
881 ret = -ENOMEM;
882 goto rpm_out;
883 }
884
885 pos = dw_i3c_master_get_free_pos(master);
886 if (pos < 0) {
887 dw_i3c_master_free_xfer(xfer);
888 ret = pos;
889 goto rpm_out;
890 }
891 cmd = &xfer->cmds[0];
892 cmd->cmd_hi = 0x1;
893 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) |
894 COMMAND_PORT_DEV_INDEX(pos) |
895 COMMAND_PORT_CMD(I3C_CCC_ENTDAA) |
896 COMMAND_PORT_ADDR_ASSGN_CMD |
897 COMMAND_PORT_TOC |
898 COMMAND_PORT_ROC;
899
900 dw_i3c_master_enqueue_xfer(master, xfer);
901 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
902 dw_i3c_master_dequeue_xfer(master, xfer);
903
904 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);
905 newdevs &= ~olddevs;
906
907 for (pos = 0; pos < master->maxdevs; pos++) {
908 if (newdevs & BIT(pos))
909 i3c_master_add_i3c_dev_locked(m, master->devs[pos].addr);
910 }
911
912 dw_i3c_master_free_xfer(xfer);
913
914 rpm_out:
915 pm_runtime_put_autosuspend(master->dev);
916 return ret;
917 }
918
dw_i3c_master_i3c_xfers(struct i3c_dev_desc * dev,struct i3c_xfer * i3c_xfers,int i3c_nxfers,enum i3c_xfer_mode mode)919 static int dw_i3c_master_i3c_xfers(struct i3c_dev_desc *dev,
920 struct i3c_xfer *i3c_xfers,
921 int i3c_nxfers, enum i3c_xfer_mode mode)
922 {
923 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
924 struct i3c_master_controller *m = i3c_dev_get_master(dev);
925 struct dw_i3c_master *master = to_dw_i3c_master(m);
926 unsigned int nrxwords = 0, ntxwords = 0;
927 struct dw_i3c_xfer *xfer;
928 int i, ret = 0;
929
930 if (!i3c_nxfers)
931 return 0;
932
933 if (i3c_nxfers > master->caps.cmdfifodepth)
934 return -EOPNOTSUPP;
935
936 for (i = 0; i < i3c_nxfers; i++) {
937 if (i3c_xfers[i].rnw)
938 nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
939 else
940 ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
941 }
942
943 if (ntxwords > master->caps.datafifodepth ||
944 nrxwords > master->caps.datafifodepth)
945 return -EOPNOTSUPP;
946
947 xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers);
948 if (!xfer)
949 return -ENOMEM;
950
951 ret = pm_runtime_resume_and_get(master->dev);
952 if (ret < 0) {
953 dev_err(master->dev,
954 "<%s> cannot resume i3c bus master, err: %d\n",
955 __func__, ret);
956 return ret;
957 }
958
959 for (i = 0; i < i3c_nxfers; i++) {
960 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
961
962 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) |
963 COMMAND_PORT_TRANSFER_ARG;
964
965 if (i3c_xfers[i].rnw) {
966 cmd->rx_buf = i3c_xfers[i].data.in;
967 cmd->rx_len = i3c_xfers[i].len;
968 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
969 COMMAND_PORT_SPEED(dev->info.max_read_ds);
970
971 } else {
972 cmd->tx_buf = i3c_xfers[i].data.out;
973 cmd->tx_len = i3c_xfers[i].len;
974 cmd->cmd_lo =
975 COMMAND_PORT_SPEED(dev->info.max_write_ds);
976 }
977
978 cmd->cmd_lo |= COMMAND_PORT_TID(i) |
979 COMMAND_PORT_DEV_INDEX(data->index) |
980 COMMAND_PORT_ROC;
981
982 if (i == (i3c_nxfers - 1))
983 cmd->cmd_lo |= COMMAND_PORT_TOC;
984 }
985
986 dw_i3c_master_enqueue_xfer(master, xfer);
987 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
988 dw_i3c_master_dequeue_xfer(master, xfer);
989
990 for (i = 0; i < i3c_nxfers; i++) {
991 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
992
993 if (i3c_xfers[i].rnw)
994 i3c_xfers[i].len = cmd->rx_len;
995 }
996
997 ret = xfer->ret;
998 dw_i3c_master_free_xfer(xfer);
999
1000 pm_runtime_put_autosuspend(master->dev);
1001 return ret;
1002 }
1003
dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc * dev,u8 old_dyn_addr)1004 static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
1005 u8 old_dyn_addr)
1006 {
1007 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1008 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1009 struct dw_i3c_master *master = to_dw_i3c_master(m);
1010 int pos;
1011
1012 pos = dw_i3c_master_get_free_pos(master);
1013
1014 if (data->index > pos && pos > 0) {
1015 writel(0,
1016 master->regs +
1017 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1018
1019 master->devs[data->index].addr = 0;
1020 master->free_pos |= BIT(data->index);
1021
1022 data->index = pos;
1023 master->devs[pos].addr = dev->info.dyn_addr;
1024 master->free_pos &= ~BIT(pos);
1025 }
1026
1027 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr),
1028 master->regs +
1029 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1030
1031 master->devs[data->index].addr = dev->info.dyn_addr;
1032
1033 return 0;
1034 }
1035
dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc * dev)1036 static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
1037 {
1038 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1039 struct dw_i3c_master *master = to_dw_i3c_master(m);
1040 struct dw_i3c_i2c_dev_data *data;
1041 int pos;
1042
1043 pos = dw_i3c_master_get_free_pos(master);
1044 if (pos < 0)
1045 return pos;
1046
1047 data = kzalloc_obj(*data);
1048 if (!data)
1049 return -ENOMEM;
1050
1051 data->index = pos;
1052 master->devs[pos].addr = dev->info.dyn_addr ? : dev->info.static_addr;
1053 master->free_pos &= ~BIT(pos);
1054 i3c_dev_set_master_data(dev, data);
1055
1056 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr),
1057 master->regs +
1058 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1059
1060 return 0;
1061 }
1062
dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc * dev)1063 static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
1064 {
1065 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1066 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1067 struct dw_i3c_master *master = to_dw_i3c_master(m);
1068
1069 writel(0,
1070 master->regs +
1071 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1072
1073 i3c_dev_set_master_data(dev, NULL);
1074 master->devs[data->index].addr = 0;
1075 master->free_pos |= BIT(data->index);
1076 kfree(data);
1077 }
1078
dw_i3c_master_i2c_xfers(struct i2c_dev_desc * dev,struct i2c_msg * i2c_xfers,int i2c_nxfers)1079 static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
1080 struct i2c_msg *i2c_xfers,
1081 int i2c_nxfers)
1082 {
1083 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1084 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1085 struct dw_i3c_master *master = to_dw_i3c_master(m);
1086 unsigned int nrxwords = 0, ntxwords = 0;
1087 struct dw_i3c_xfer *xfer;
1088 int i, ret = 0;
1089
1090 if (!i2c_nxfers)
1091 return 0;
1092
1093 if (i2c_nxfers > master->caps.cmdfifodepth)
1094 return -EOPNOTSUPP;
1095
1096 for (i = 0; i < i2c_nxfers; i++) {
1097 if (i2c_xfers[i].flags & I2C_M_RD)
1098 nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
1099 else
1100 ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
1101 }
1102
1103 if (ntxwords > master->caps.datafifodepth ||
1104 nrxwords > master->caps.datafifodepth)
1105 return -EOPNOTSUPP;
1106
1107 xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers);
1108 if (!xfer)
1109 return -ENOMEM;
1110
1111 ret = pm_runtime_resume_and_get(master->dev);
1112 if (ret < 0) {
1113 dev_err(master->dev,
1114 "<%s> cannot resume i3c bus master, err: %d\n",
1115 __func__, ret);
1116 dw_i3c_master_free_xfer(xfer);
1117 return ret;
1118 }
1119
1120 for (i = 0; i < i2c_nxfers; i++) {
1121 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
1122
1123 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) |
1124 COMMAND_PORT_TRANSFER_ARG;
1125
1126 cmd->cmd_lo = COMMAND_PORT_TID(i) |
1127 COMMAND_PORT_DEV_INDEX(data->index) |
1128 COMMAND_PORT_ROC;
1129
1130 if (i2c_xfers[i].flags & I2C_M_RD) {
1131 cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER;
1132 cmd->rx_buf = i2c_xfers[i].buf;
1133 cmd->rx_len = i2c_xfers[i].len;
1134 } else {
1135 cmd->tx_buf = i2c_xfers[i].buf;
1136 cmd->tx_len = i2c_xfers[i].len;
1137 }
1138
1139 if (i == (i2c_nxfers - 1))
1140 cmd->cmd_lo |= COMMAND_PORT_TOC;
1141 }
1142
1143 dw_i3c_master_enqueue_xfer(master, xfer);
1144 if (!wait_for_completion_timeout(&xfer->comp, m->i2c.timeout))
1145 dw_i3c_master_dequeue_xfer(master, xfer);
1146
1147 ret = xfer->ret;
1148 dw_i3c_master_free_xfer(xfer);
1149
1150 pm_runtime_put_autosuspend(master->dev);
1151 return ret;
1152 }
1153
dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc * dev)1154 static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
1155 {
1156 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1157 struct dw_i3c_master *master = to_dw_i3c_master(m);
1158 struct dw_i3c_i2c_dev_data *data;
1159 int pos;
1160
1161 pos = dw_i3c_master_get_free_pos(master);
1162 if (pos < 0)
1163 return pos;
1164
1165 data = kzalloc_obj(*data);
1166 if (!data)
1167 return -ENOMEM;
1168
1169 data->index = pos;
1170 master->devs[pos].addr = dev->addr;
1171 master->devs[pos].is_i2c_addr = true;
1172 master->free_pos &= ~BIT(pos);
1173 i2c_dev_set_master_data(dev, data);
1174
1175 writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1176 DEV_ADDR_TABLE_STATIC_ADDR(dev->addr),
1177 master->regs +
1178 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1179
1180 return 0;
1181 }
1182
dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc * dev)1183 static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1184 {
1185 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1186 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1187 struct dw_i3c_master *master = to_dw_i3c_master(m);
1188
1189 writel(0,
1190 master->regs +
1191 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1192
1193 i2c_dev_set_master_data(dev, NULL);
1194 master->devs[data->index].addr = 0;
1195 master->free_pos |= BIT(data->index);
1196 kfree(data);
1197 }
1198
dw_i3c_master_request_ibi(struct i3c_dev_desc * dev,const struct i3c_ibi_setup * req)1199 static int dw_i3c_master_request_ibi(struct i3c_dev_desc *dev,
1200 const struct i3c_ibi_setup *req)
1201 {
1202 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1203 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1204 struct dw_i3c_master *master = to_dw_i3c_master(m);
1205
1206 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
1207 if (IS_ERR(data->ibi_pool))
1208 return PTR_ERR(data->ibi_pool);
1209
1210 guard(spinlock_irqsave)(&master->devs_lock);
1211 master->devs[data->index].ibi_dev = dev;
1212
1213 return 0;
1214 }
1215
dw_i3c_master_free_ibi(struct i3c_dev_desc * dev)1216 static void dw_i3c_master_free_ibi(struct i3c_dev_desc *dev)
1217 {
1218 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1219 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1220 struct dw_i3c_master *master = to_dw_i3c_master(m);
1221
1222 scoped_guard(spinlock_irqsave, &master->devs_lock) {
1223 master->devs[data->index].ibi_dev = NULL;
1224 }
1225
1226 i3c_generic_ibi_free_pool(data->ibi_pool);
1227 data->ibi_pool = NULL;
1228 }
1229
dw_i3c_master_enable_sir_signal(struct dw_i3c_master * master,bool enable)1230 static void dw_i3c_master_enable_sir_signal(struct dw_i3c_master *master, bool enable)
1231 {
1232 u32 reg;
1233
1234 reg = readl(master->regs + INTR_STATUS_EN);
1235 reg &= ~INTR_IBI_THLD_STAT;
1236 if (enable)
1237 reg |= INTR_IBI_THLD_STAT;
1238 writel(reg, master->regs + INTR_STATUS_EN);
1239
1240 reg = readl(master->regs + INTR_SIGNAL_EN);
1241 reg &= ~INTR_IBI_THLD_STAT;
1242 if (enable)
1243 reg |= INTR_IBI_THLD_STAT;
1244 writel(reg, master->regs + INTR_SIGNAL_EN);
1245 }
1246
dw_i3c_master_set_sir_enabled(struct dw_i3c_master * master,struct i3c_dev_desc * dev,u8 idx,bool enable)1247 static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master,
1248 struct i3c_dev_desc *dev,
1249 u8 idx, bool enable)
1250 {
1251 u32 dat_entry, reg;
1252 bool global;
1253 u8 dynamic_addr;
1254
1255 dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx);
1256
1257 guard(spinlock_irqsave)(&master->devs_lock);
1258 reg = readl(master->regs + dat_entry);
1259 dynamic_addr = DEV_ADDR_TABLE_GET_DYNAMIC_ADDR(reg);
1260
1261 if (!dynamic_addr)
1262 dev_warn(master->dev,
1263 "<%s> unassigned slave device, dynamic addr:%x\n",
1264 __func__, dynamic_addr);
1265
1266 if (enable) {
1267 reg &= ~DEV_ADDR_TABLE_SIR_REJECT;
1268 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD)
1269 reg |= DEV_ADDR_TABLE_IBI_MDB;
1270 } else {
1271 reg |= DEV_ADDR_TABLE_SIR_REJECT;
1272 }
1273 master->platform_ops->set_dat_ibi(master, dev, enable, ®);
1274 writel(reg, master->regs + dat_entry);
1275
1276 if (enable) {
1277 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL);
1278 master->sir_rej_mask &= ~BIT(get_ibi_sir_bit_index(dynamic_addr));
1279 } else {
1280 bool hj_rejected = !!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_HOT_JOIN_NACK);
1281
1282 master->sir_rej_mask |= BIT(get_ibi_sir_bit_index(dynamic_addr));
1283 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL) && hj_rejected;
1284 }
1285 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT);
1286
1287 if (global)
1288 dw_i3c_master_enable_sir_signal(master, enable);
1289 }
1290
dw_i3c_master_enable_hotjoin(struct i3c_master_controller * m)1291 static int dw_i3c_master_enable_hotjoin(struct i3c_master_controller *m)
1292 {
1293 struct dw_i3c_master *master = to_dw_i3c_master(m);
1294 int ret;
1295
1296 ret = pm_runtime_resume_and_get(master->dev);
1297 if (ret < 0) {
1298 dev_err(master->dev,
1299 "<%s> cannot resume i3c bus master, err: %d\n",
1300 __func__, ret);
1301 return ret;
1302 }
1303
1304 dw_i3c_master_enable_sir_signal(master, true);
1305 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_HOT_JOIN_NACK,
1306 master->regs + DEVICE_CTRL);
1307
1308 return 0;
1309 }
1310
dw_i3c_master_disable_hotjoin(struct i3c_master_controller * m)1311 static int dw_i3c_master_disable_hotjoin(struct i3c_master_controller *m)
1312 {
1313 struct dw_i3c_master *master = to_dw_i3c_master(m);
1314
1315 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
1316 master->regs + DEVICE_CTRL);
1317
1318 pm_runtime_put_autosuspend(master->dev);
1319 return 0;
1320 }
1321
dw_i3c_master_enable_ibi(struct i3c_dev_desc * dev)1322 static int dw_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
1323 {
1324 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1325 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1326 struct dw_i3c_master *master = to_dw_i3c_master(m);
1327 int rc;
1328
1329 rc = pm_runtime_resume_and_get(master->dev);
1330 if (rc < 0) {
1331 dev_err(master->dev,
1332 "<%s> cannot resume i3c bus master, err: %d\n",
1333 __func__, rc);
1334 return rc;
1335 }
1336
1337 dw_i3c_master_set_sir_enabled(master, dev, data->index, true);
1338
1339 rc = i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1340
1341 if (rc) {
1342 dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
1343 pm_runtime_put_autosuspend(master->dev);
1344 }
1345
1346 return rc;
1347 }
1348
dw_i3c_master_disable_ibi(struct i3c_dev_desc * dev)1349 static int dw_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
1350 {
1351 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1352 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1353 struct dw_i3c_master *master = to_dw_i3c_master(m);
1354 int rc;
1355
1356 rc = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1357 if (rc)
1358 return rc;
1359
1360 dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
1361
1362 pm_runtime_put_autosuspend(master->dev);
1363 return 0;
1364 }
1365
dw_i3c_master_recycle_ibi_slot(struct i3c_dev_desc * dev,struct i3c_ibi_slot * slot)1366 static void dw_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
1367 struct i3c_ibi_slot *slot)
1368 {
1369 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1370
1371 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
1372 }
1373
dw_i3c_master_drain_ibi_queue(struct dw_i3c_master * master,int len)1374 static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master,
1375 int len)
1376 {
1377 int i;
1378
1379 for (i = 0; i < DIV_ROUND_UP(len, 4); i++)
1380 readl(master->regs + IBI_QUEUE_STATUS);
1381 }
1382
dw_i3c_master_handle_ibi_sir(struct dw_i3c_master * master,u32 status)1383 static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master,
1384 u32 status)
1385 {
1386 struct dw_i3c_i2c_dev_data *data;
1387 struct i3c_ibi_slot *slot;
1388 struct i3c_dev_desc *dev;
1389 u8 addr, len;
1390 int idx;
1391
1392 addr = IBI_QUEUE_IBI_ADDR(status);
1393 len = IBI_QUEUE_STATUS_DATA_LEN(status);
1394
1395 /*
1396 * We be tempted to check the error status in bit 30; however, due
1397 * to the PEC errata workaround on some platform implementations (see
1398 * ast2600_i3c_set_dat_ibi()), those will almost always have a PEC
1399 * error on IBI payload data, as well as losing the last byte of
1400 * payload.
1401 *
1402 * If we implement error status checking on that bit, we may need
1403 * a new platform op to validate it.
1404 */
1405
1406 guard(spinlock_irqsave)(&master->devs_lock);
1407 idx = dw_i3c_master_get_addr_pos(master, addr);
1408 if (idx < 0) {
1409 dev_dbg_ratelimited(&master->base.dev,
1410 "IBI from unknown addr 0x%x\n", addr);
1411 goto err_drain;
1412 }
1413
1414 dev = master->devs[idx].ibi_dev;
1415 if (!dev || !dev->ibi) {
1416 dev_dbg_ratelimited(&master->base.dev,
1417 "IBI from non-requested dev idx %d\n", idx);
1418 goto err_drain;
1419 }
1420
1421 data = i3c_dev_get_master_data(dev);
1422 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
1423 if (!slot) {
1424 dev_dbg_ratelimited(&master->base.dev,
1425 "No IBI slots available\n");
1426 goto err_drain;
1427 }
1428
1429 if (dev->ibi->max_payload_len < len) {
1430 dev_dbg_ratelimited(&master->base.dev,
1431 "IBI payload len %d greater than max %d\n",
1432 len, dev->ibi->max_payload_len);
1433 goto err_drain;
1434 }
1435
1436 if (len) {
1437 dw_i3c_master_read_ibi_fifo(master, slot->data, len);
1438 slot->len = len;
1439 }
1440 i3c_master_queue_ibi(dev, slot);
1441
1442 return;
1443
1444 err_drain:
1445 dw_i3c_master_drain_ibi_queue(master, len);
1446 }
1447
1448 /* "ibis": referring to In-Band Interrupts, and not
1449 * https://en.wikipedia.org/wiki/Australian_white_ibis. The latter should
1450 * not be handled.
1451 */
dw_i3c_master_irq_handle_ibis(struct dw_i3c_master * master)1452 static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master)
1453 {
1454 unsigned int i, len, n_ibis;
1455 u32 reg;
1456
1457 reg = readl(master->regs + QUEUE_STATUS_LEVEL);
1458 n_ibis = QUEUE_STATUS_IBI_STATUS_CNT(reg);
1459 if (!n_ibis)
1460 return;
1461
1462 for (i = 0; i < n_ibis; i++) {
1463 reg = readl(master->regs + IBI_QUEUE_STATUS);
1464
1465 if (IBI_TYPE_SIRQ(reg)) {
1466 dw_i3c_master_handle_ibi_sir(master, reg);
1467 } else if (IBI_TYPE_HJ(reg)) {
1468 queue_work(master->base.wq, &master->hj_work);
1469 } else {
1470 len = IBI_QUEUE_STATUS_DATA_LEN(reg);
1471 dev_info(&master->base.dev,
1472 "unsupported IBI type 0x%lx len %d\n",
1473 IBI_QUEUE_STATUS_IBI_ID(reg), len);
1474 dw_i3c_master_drain_ibi_queue(master, len);
1475 }
1476 }
1477 }
1478
dw_i3c_master_irq_handler(int irq,void * dev_id)1479 static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
1480 {
1481 struct dw_i3c_master *master = dev_id;
1482 u32 status;
1483
1484 status = readl(master->regs + INTR_STATUS);
1485
1486 if (!(status & readl(master->regs + INTR_STATUS_EN))) {
1487 writel(INTR_ALL, master->regs + INTR_STATUS);
1488 return IRQ_NONE;
1489 }
1490
1491 spin_lock(&master->xferqueue.lock);
1492 dw_i3c_master_end_xfer_locked(master, status);
1493 if (status & INTR_TRANSFER_ERR_STAT)
1494 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
1495 spin_unlock(&master->xferqueue.lock);
1496
1497 if (status & INTR_IBI_THLD_STAT)
1498 dw_i3c_master_irq_handle_ibis(master);
1499
1500 return IRQ_HANDLED;
1501 }
1502
dw_i3c_master_set_dev_nack_retry(struct i3c_master_controller * m,unsigned long dev_nack_retry_cnt)1503 static int dw_i3c_master_set_dev_nack_retry(struct i3c_master_controller *m,
1504 unsigned long dev_nack_retry_cnt)
1505 {
1506 struct dw_i3c_master *master = to_dw_i3c_master(m);
1507 u32 reg;
1508 int i;
1509
1510 if (dev_nack_retry_cnt > DW_I3C_DEV_NACK_RETRY_CNT_MAX) {
1511 dev_err(&master->base.dev,
1512 "Value %ld exceeds maximum %d\n",
1513 dev_nack_retry_cnt, DW_I3C_DEV_NACK_RETRY_CNT_MAX);
1514 return -ERANGE;
1515 }
1516
1517 /*
1518 * Update DAT entries for all currently attached devices.
1519 * We directly iterate through the master's device array.
1520 */
1521 for (i = 0; i < master->maxdevs; i++) {
1522 /* Skip free/empty slots */
1523 if (master->free_pos & BIT(i))
1524 continue;
1525
1526 reg = readl(master->regs +
1527 DEV_ADDR_TABLE_LOC(master->datstartaddr, i));
1528 reg &= ~DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK;
1529 reg |= DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(dev_nack_retry_cnt);
1530 writel(reg, master->regs +
1531 DEV_ADDR_TABLE_LOC(master->datstartaddr, i));
1532 }
1533
1534 return 0;
1535 }
1536
1537 static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
1538 .bus_init = dw_i3c_master_bus_init,
1539 .bus_cleanup = dw_i3c_master_bus_cleanup,
1540 .attach_i3c_dev = dw_i3c_master_attach_i3c_dev,
1541 .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev,
1542 .detach_i3c_dev = dw_i3c_master_detach_i3c_dev,
1543 .do_daa = dw_i3c_master_daa,
1544 .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd,
1545 .send_ccc_cmd = dw_i3c_master_send_ccc_cmd,
1546 .i3c_xfers = dw_i3c_master_i3c_xfers,
1547 .attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
1548 .detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
1549 .i2c_xfers = dw_i3c_master_i2c_xfers,
1550 .request_ibi = dw_i3c_master_request_ibi,
1551 .free_ibi = dw_i3c_master_free_ibi,
1552 .enable_ibi = dw_i3c_master_enable_ibi,
1553 .disable_ibi = dw_i3c_master_disable_ibi,
1554 .recycle_ibi_slot = dw_i3c_master_recycle_ibi_slot,
1555 .enable_hotjoin = dw_i3c_master_enable_hotjoin,
1556 .disable_hotjoin = dw_i3c_master_disable_hotjoin,
1557 .set_dev_nack_retry = dw_i3c_master_set_dev_nack_retry,
1558 };
1559
1560 /* default platform ops implementations */
dw_i3c_platform_init_nop(struct dw_i3c_master * i3c)1561 static int dw_i3c_platform_init_nop(struct dw_i3c_master *i3c)
1562 {
1563 return 0;
1564 }
1565
dw_i3c_platform_set_dat_ibi_nop(struct dw_i3c_master * i3c,struct i3c_dev_desc * dev,bool enable,u32 * dat)1566 static void dw_i3c_platform_set_dat_ibi_nop(struct dw_i3c_master *i3c,
1567 struct i3c_dev_desc *dev,
1568 bool enable, u32 *dat)
1569 {
1570 }
1571
1572 static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = {
1573 .init = dw_i3c_platform_init_nop,
1574 .set_dat_ibi = dw_i3c_platform_set_dat_ibi_nop,
1575 };
1576
dw_i3c_hj_work(struct work_struct * work)1577 static void dw_i3c_hj_work(struct work_struct *work)
1578 {
1579 struct dw_i3c_master *master =
1580 container_of(work, typeof(*master), hj_work);
1581
1582 i3c_master_do_daa(&master->base);
1583 }
1584
dw_i3c_common_probe(struct dw_i3c_master * master,struct platform_device * pdev)1585 int dw_i3c_common_probe(struct dw_i3c_master *master,
1586 struct platform_device *pdev)
1587 {
1588 int ret, irq;
1589 const struct dw_i3c_drvdata *drvdata;
1590 unsigned long quirks = 0;
1591
1592 if (!master->platform_ops)
1593 master->platform_ops = &dw_i3c_platform_ops_default;
1594
1595 master->dev = &pdev->dev;
1596
1597 master->regs = devm_platform_ioremap_resource(pdev, 0);
1598 if (IS_ERR(master->regs))
1599 return PTR_ERR(master->regs);
1600
1601 master->core_clk = devm_clk_get_enabled(&pdev->dev, NULL);
1602 if (IS_ERR(master->core_clk))
1603 return PTR_ERR(master->core_clk);
1604
1605 master->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
1606 if (IS_ERR(master->pclk))
1607 return PTR_ERR(master->pclk);
1608
1609 master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
1610 "core_rst");
1611 if (IS_ERR(master->core_rst))
1612 return PTR_ERR(master->core_rst);
1613
1614 reset_control_deassert(master->core_rst);
1615
1616 spin_lock_init(&master->xferqueue.lock);
1617 INIT_LIST_HEAD(&master->xferqueue.list);
1618
1619 spin_lock_init(&master->devs_lock);
1620
1621 writel(INTR_ALL, master->regs + INTR_STATUS);
1622 irq = platform_get_irq(pdev, 0);
1623 ret = devm_request_irq(&pdev->dev, irq,
1624 dw_i3c_master_irq_handler, 0,
1625 dev_name(&pdev->dev), master);
1626 if (ret)
1627 goto err_assert_rst;
1628
1629 platform_set_drvdata(pdev, master);
1630
1631 pm_runtime_set_autosuspend_delay(&pdev->dev, RPM_AUTOSUSPEND_TIMEOUT);
1632 pm_runtime_use_autosuspend(&pdev->dev);
1633 pm_runtime_set_active(&pdev->dev);
1634 pm_runtime_enable(&pdev->dev);
1635
1636 /* Information regarding the FIFOs/QUEUEs depth */
1637 ret = readl(master->regs + QUEUE_STATUS_LEVEL);
1638 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
1639
1640 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL);
1641 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret);
1642
1643 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER);
1644 master->datstartaddr = ret;
1645 master->maxdevs = ret >> 16;
1646 master->free_pos = GENMASK(master->maxdevs - 1, 0);
1647
1648 if (has_acpi_companion(&pdev->dev)) {
1649 quirks = (unsigned long)device_get_match_data(&pdev->dev);
1650 } else if (pdev->dev.of_node) {
1651 drvdata = device_get_match_data(&pdev->dev);
1652 if (drvdata)
1653 quirks = drvdata->flags;
1654 }
1655 master->quirks = quirks;
1656
1657 /* Keep controller enabled by preventing runtime suspend */
1658 if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)
1659 pm_runtime_get_noresume(&pdev->dev);
1660
1661 INIT_WORK(&master->hj_work, dw_i3c_hj_work);
1662 ret = i3c_master_register(&master->base, &pdev->dev,
1663 &dw_mipi_i3c_ops, false);
1664 if (ret)
1665 goto err_disable_pm;
1666
1667 return 0;
1668
1669 err_disable_pm:
1670 pm_runtime_disable(&pdev->dev);
1671 pm_runtime_set_suspended(&pdev->dev);
1672 pm_runtime_dont_use_autosuspend(&pdev->dev);
1673
1674 err_assert_rst:
1675 reset_control_assert(master->core_rst);
1676
1677 return ret;
1678 }
1679 EXPORT_SYMBOL_GPL(dw_i3c_common_probe);
1680
dw_i3c_common_remove(struct dw_i3c_master * master)1681 void dw_i3c_common_remove(struct dw_i3c_master *master)
1682 {
1683 cancel_work_sync(&master->hj_work);
1684 i3c_master_unregister(&master->base);
1685
1686 /* Balance pm_runtime_get_noresume() from probe() */
1687 if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)
1688 pm_runtime_put_noidle(master->dev);
1689
1690 pm_runtime_disable(master->dev);
1691 pm_runtime_set_suspended(master->dev);
1692 pm_runtime_dont_use_autosuspend(master->dev);
1693 }
1694 EXPORT_SYMBOL_GPL(dw_i3c_common_remove);
1695
1696 /* base platform implementation */
1697
dw_i3c_probe(struct platform_device * pdev)1698 static int dw_i3c_probe(struct platform_device *pdev)
1699 {
1700 struct dw_i3c_master *master;
1701
1702 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1703 if (!master)
1704 return -ENOMEM;
1705
1706 return dw_i3c_common_probe(master, pdev);
1707 }
1708
dw_i3c_remove(struct platform_device * pdev)1709 static void dw_i3c_remove(struct platform_device *pdev)
1710 {
1711 struct dw_i3c_master *master = platform_get_drvdata(pdev);
1712
1713 dw_i3c_common_remove(master);
1714 }
1715
dw_i3c_master_restore_addrs(struct dw_i3c_master * master)1716 static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master)
1717 {
1718 u32 pos, reg_val;
1719
1720 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(master->dev_addr),
1721 master->regs + DEVICE_ADDR);
1722
1723 for (pos = 0; pos < master->maxdevs; pos++) {
1724 if (master->free_pos & BIT(pos))
1725 continue;
1726
1727 reg_val = readl(master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
1728
1729 if (master->devs[pos].is_i2c_addr) {
1730 reg_val &= ~DEV_ADDR_TABLE_STATIC_MASK;
1731 reg_val |= DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1732 DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr);
1733 } else {
1734 reg_val &= ~DEV_ADDR_TABLE_DYNAMIC_MASK;
1735 reg_val |= DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr);
1736 }
1737
1738 writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
1739 }
1740 }
1741
dw_i3c_master_restore_timing_regs(struct dw_i3c_master * master)1742 static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master)
1743 {
1744 /* AMD platform specific OD and PP timings */
1745 if (master->quirks & AMD_I3C_OD_PP_TIMING)
1746 amd_configure_od_pp_quirk(master);
1747
1748 writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
1749 writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING);
1750 writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
1751 writel(master->ext_lcnt_timing, master->regs + SCL_EXT_LCNT_TIMING);
1752
1753 if (master->i2c_slv_prsnt) {
1754 writel(master->i2c_fmp_timing, master->regs + SCL_I2C_FMP_TIMING);
1755 writel(master->i2c_fm_timing, master->regs + SCL_I2C_FM_TIMING);
1756 }
1757 }
1758
dw_i3c_master_enable_clks(struct dw_i3c_master * master)1759 static int dw_i3c_master_enable_clks(struct dw_i3c_master *master)
1760 {
1761 int ret = 0;
1762
1763 ret = clk_prepare_enable(master->core_clk);
1764 if (ret)
1765 return ret;
1766
1767 ret = clk_prepare_enable(master->pclk);
1768 if (ret) {
1769 clk_disable_unprepare(master->core_clk);
1770 return ret;
1771 }
1772
1773 return 0;
1774 }
1775
dw_i3c_master_disable_clks(struct dw_i3c_master * master)1776 static inline void dw_i3c_master_disable_clks(struct dw_i3c_master *master)
1777 {
1778 clk_disable_unprepare(master->pclk);
1779 clk_disable_unprepare(master->core_clk);
1780 }
1781
dw_i3c_master_runtime_suspend(struct device * dev)1782 static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev)
1783 {
1784 struct dw_i3c_master *master = dev_get_drvdata(dev);
1785
1786 dw_i3c_master_disable(master);
1787
1788 reset_control_assert(master->core_rst);
1789 dw_i3c_master_disable_clks(master);
1790 pinctrl_pm_select_sleep_state(dev);
1791 return 0;
1792 }
1793
dw_i3c_master_runtime_resume(struct device * dev)1794 static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev)
1795 {
1796 struct dw_i3c_master *master = dev_get_drvdata(dev);
1797
1798 pinctrl_pm_select_default_state(dev);
1799 dw_i3c_master_enable_clks(master);
1800 reset_control_deassert(master->core_rst);
1801
1802 dw_i3c_master_set_intr_regs(master);
1803 dw_i3c_master_restore_timing_regs(master);
1804 dw_i3c_master_restore_addrs(master);
1805
1806 dw_i3c_master_enable(master);
1807 return 0;
1808 }
1809
1810 static const struct dev_pm_ops dw_i3c_pm_ops = {
1811 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1812 SET_RUNTIME_PM_OPS(dw_i3c_master_runtime_suspend, dw_i3c_master_runtime_resume, NULL)
1813 };
1814
dw_i3c_shutdown(struct platform_device * pdev)1815 static void dw_i3c_shutdown(struct platform_device *pdev)
1816 {
1817 struct dw_i3c_master *master = platform_get_drvdata(pdev);
1818 int ret;
1819
1820 ret = pm_runtime_resume_and_get(master->dev);
1821 if (ret < 0) {
1822 dev_err(master->dev,
1823 "<%s> cannot resume i3c bus master, err: %d\n",
1824 __func__, ret);
1825 return;
1826 }
1827
1828 cancel_work_sync(&master->hj_work);
1829
1830 /* Disable interrupts */
1831 writel((u32)~INTR_ALL, master->regs + INTR_STATUS_EN);
1832 writel((u32)~INTR_ALL, master->regs + INTR_SIGNAL_EN);
1833
1834 pm_runtime_put_autosuspend(master->dev);
1835 }
1836
1837 static const struct dw_i3c_drvdata altr_agilex5_drvdata = {
1838 .flags = DW_I3C_DISABLE_RUNTIME_PM_QUIRK,
1839 };
1840
1841 static const struct of_device_id dw_i3c_master_of_match[] = {
1842 { .compatible = "snps,dw-i3c-master-1.00a", },
1843 { .compatible = "altr,agilex5-dw-i3c-master",
1844 .data = &altr_agilex5_drvdata,
1845 },
1846 {},
1847 };
1848 MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match);
1849
1850 static const struct acpi_device_id amd_i3c_device_match[] = {
1851 { "AMDI0015", AMD_I3C_OD_PP_TIMING },
1852 { }
1853 };
1854 MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match);
1855
1856 static struct platform_driver dw_i3c_driver = {
1857 .probe = dw_i3c_probe,
1858 .remove = dw_i3c_remove,
1859 .shutdown = dw_i3c_shutdown,
1860 .driver = {
1861 .name = "dw-i3c-master",
1862 .of_match_table = dw_i3c_master_of_match,
1863 .acpi_match_table = amd_i3c_device_match,
1864 .pm = &dw_i3c_pm_ops,
1865 },
1866 };
1867 module_platform_driver(dw_i3c_driver);
1868
1869 MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>");
1870 MODULE_DESCRIPTION("DesignWare MIPI I3C driver");
1871 MODULE_LICENSE("GPL v2");
1872