1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ/G2L Clock Pulse Generator 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 */ 8 9 #ifndef __RENESAS_RZG2L_CPG_H__ 10 #define __RENESAS_RZG2L_CPG_H__ 11 12 #include <linux/notifier.h> 13 14 #define CPG_SIPLL5_STBY (0x140) 15 #define CPG_SIPLL5_CLK1 (0x144) 16 #define CPG_SIPLL5_CLK3 (0x14C) 17 #define CPG_SIPLL5_CLK4 (0x150) 18 #define CPG_SIPLL5_CLK5 (0x154) 19 #define CPG_SIPLL5_MON (0x15C) 20 #define CPG_PL1_DDIV (0x200) 21 #define CPG_PL2_DDIV (0x204) 22 #define CPG_PL3A_DDIV (0x208) 23 #define CPG_PL6_DDIV (0x210) 24 #define CPG_PL3C_SDIV (0x214) 25 #define CPG_CLKSTATUS (0x280) 26 #define CPG_PL3_SSEL (0x408) 27 #define CPG_PL6_SSEL (0x414) 28 #define CPG_PL6_ETH_SSEL (0x418) 29 #define CPG_PL5_SDIV (0x420) 30 #define CPG_RST_MON (0x680) 31 #define CPG_BUS_ACPU_MSTOP (0xB60) 32 #define CPG_BUS_MCPU1_MSTOP (0xB64) 33 #define CPG_BUS_MCPU2_MSTOP (0xB68) 34 #define CPG_BUS_PERI_COM_MSTOP (0xB6C) 35 #define CPG_BUS_PERI_CPU_MSTOP (0xB70) 36 #define CPG_BUS_PERI_DDR_MSTOP (0xB74) 37 #define CPG_BUS_PERI_VIDEO_MSTOP (0xB78) 38 #define CPG_BUS_REG0_MSTOP (0xB7C) 39 #define CPG_BUS_REG1_MSTOP (0xB80) 40 #define CPG_BUS_TZCDDR_MSTOP (0xB84) 41 #define CPG_MHU_MSTOP (0xB88) 42 #define CPG_BUS_MCPU3_MSTOP (0xB90) 43 #define CPG_BUS_PERI_CPU2_MSTOP (0xB94) 44 #define CPG_OTHERFUNC1_REG (0xBE8) 45 46 #define CPG_SIPLL5_STBY_RESETB BIT(0) 47 #define CPG_SIPLL5_STBY_RESETB_WEN BIT(16) 48 #define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18) 49 #define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20) 50 #define CPG_SIPLL5_CLK4_RESV_LSB (0xFF) 51 #define CPG_SIPLL5_MON_PLL5_LOCK BIT(4) 52 53 #define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16) 54 55 #define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16) 56 #define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24) 57 58 #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) 59 #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) 60 61 #define CPG_SAM_PLL_CONF(stby) ((stby) << 12) 62 #define CPG_PLL_CONF(stby, setting) ((stby) << 12 | (setting)) 63 64 #define DDIV_PACK(offset, bitpos, size) \ 65 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 66 #define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) 67 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) 68 #define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2) 69 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) 70 #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) 71 #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) 72 #define DIVPL3E DDIV_PACK(CPG_PL3C_SDIV, 8, 5) 73 #define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) 74 75 #define SEL_PLL_PACK(offset, bitpos, size) \ 76 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 77 78 #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) 79 #define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1) 80 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) 81 #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) 82 83 #define MSTOP(name, bitmask) ((CPG_##name##_MSTOP) << 16 | (bitmask)) 84 85 #define EXTAL_FREQ_IN_MEGA_HZ (24) 86 87 /** 88 * Definitions of CPG Core Clocks 89 * 90 * These include: 91 * - Clock outputs exported to DT 92 * - External input clocks 93 * - Internal CPG clocks 94 */ 95 struct cpg_core_clk { 96 const char *name; 97 unsigned int id; 98 unsigned int parent; 99 unsigned int div; 100 unsigned int mult; 101 unsigned int type; 102 unsigned int conf; 103 unsigned int sconf; 104 const struct clk_div_table *dtable; 105 const u32 *mtable; 106 const unsigned long invalid_rate; 107 union { 108 const unsigned long max_rate; 109 const unsigned long default_rate; 110 }; 111 const char * const *parent_names; 112 notifier_fn_t notifier; 113 u32 flag; 114 u32 mux_flags; 115 int num_parents; 116 }; 117 118 enum clk_types { 119 /* Generic */ 120 CLK_TYPE_IN, /* External Clock Input */ 121 CLK_TYPE_FF, /* Fixed Factor Clock */ 122 CLK_TYPE_SAM_PLL, 123 CLK_TYPE_G3L_PLL, 124 CLK_TYPE_G3S_PLL, 125 126 /* Clock with divider */ 127 CLK_TYPE_DIV, 128 CLK_TYPE_G3S_DIV, 129 130 /* Clock with clock source selector */ 131 CLK_TYPE_MUX, 132 133 /* Clock with SD clock source selector */ 134 CLK_TYPE_SD_MUX, 135 136 /* Clock for SIPLL5 */ 137 CLK_TYPE_SIPLL5, 138 139 /* Clock for PLL5_4 clock source selector */ 140 CLK_TYPE_PLL5_4_MUX, 141 142 /* Clock for DSI divider */ 143 CLK_TYPE_DSI_DIV, 144 145 }; 146 147 #define DEF_TYPE(_name, _id, _type...) \ 148 { .name = _name, .id = _id, .type = _type } 149 #define DEF_BASE(_name, _id, _type, _parent...) \ 150 DEF_TYPE(_name, _id, _type, .parent = _parent) 151 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ 152 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) 153 #define DEF_G3L_PLL(_name, _id, _parent, _conf, _default_rate) \ 154 DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLL, .parent = _parent, .conf = _conf, \ 155 .default_rate = _default_rate) 156 #define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \ 157 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \ 158 .default_rate = _default_rate) 159 #define DEF_INPUT(_name, _id) \ 160 DEF_TYPE(_name, _id, CLK_TYPE_IN) 161 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 162 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 163 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ 164 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 165 .parent = _parent, .dtable = _dtable, \ 166 .flag = CLK_DIVIDER_HIWORD_MASK) 167 #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ 168 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 169 .parent = _parent, .dtable = _dtable, \ 170 .flag = CLK_DIVIDER_READ_ONLY) 171 #define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \ 172 _max_rate, _clk_flags, _notif) \ 173 DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \ 174 .parent = _parent, .dtable = _dtable, \ 175 .invalid_rate = _invalid_rate, \ 176 .max_rate = _max_rate, .flag = (_clk_flags), \ 177 .notifier = _notif) 178 #define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \ 179 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 180 .parent_names = _parent_names, \ 181 .num_parents = ARRAY_SIZE(_parent_names), \ 182 .mux_flags = CLK_MUX_HIWORD_MASK, \ 183 .flag = _flag) 184 #define DEF_MUX(_name, _id, _conf, _parent_names) \ 185 DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, 0) 186 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ 187 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 188 .parent_names = _parent_names, \ 189 .num_parents = ARRAY_SIZE(_parent_names), \ 190 .mux_flags = CLK_MUX_READ_ONLY) 191 #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \ 192 DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \ 193 .parent_names = _parent_names, \ 194 .num_parents = ARRAY_SIZE(_parent_names), \ 195 .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier) 196 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ 197 DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) 198 #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ 199 DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ 200 .parent_names = _parent_names, \ 201 .num_parents = ARRAY_SIZE(_parent_names)) 202 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ 203 DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) 204 205 /** 206 * struct rzg2l_mod_clk - Module Clocks definitions 207 * 208 * @name: handle between common and hardware-specific interfaces 209 * @id: clock index in array containing all Core and Module Clocks 210 * @parent: id of parent clock 211 * @mstop_conf: MSTOP configuration 212 * @off: register offset 213 * @bit: ON/MON bit 214 * @is_coupled: flag to indicate coupled clock 215 */ 216 struct rzg2l_mod_clk { 217 const char *name; 218 unsigned int id; 219 unsigned int parent; 220 u32 mstop_conf; 221 u16 off; 222 u8 bit; 223 bool is_coupled; 224 }; 225 226 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \ 227 { \ 228 .name = _name, \ 229 .id = MOD_CLK_BASE + (_id), \ 230 .parent = (_parent), \ 231 .mstop_conf = (_mstop_conf), \ 232 .off = (_off), \ 233 .bit = (_bit), \ 234 .is_coupled = (_is_coupled), \ 235 } 236 237 #define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \ 238 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false) 239 240 #define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \ 241 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true) 242 243 /** 244 * struct rzg2l_reset - Reset definitions 245 * 246 * @off: register offset 247 * @bit: reset bit 248 * @monbit: monitor bit in CPG_RST_MON register, -1 if none 249 */ 250 struct rzg2l_reset { 251 u16 off; 252 u8 bit; 253 s8 monbit; 254 }; 255 256 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ 257 [_id] = { \ 258 .off = (_off), \ 259 .bit = (_bit), \ 260 .monbit = (_monbit) \ 261 } 262 #define DEF_RST(_id, _off, _bit) \ 263 DEF_RST_MON(_id, _off, _bit, -1) 264 265 /** 266 * struct rzg2l_cpg_info - SoC-specific CPG Description 267 * 268 * @core_clks: Array of Core Clock definitions 269 * @num_core_clks: Number of entries in core_clks[] 270 * @last_dt_core_clk: ID of the last Core Clock exported to DT 271 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 272 * 273 * @mod_clks: Array of Module Clock definitions 274 * @num_mod_clks: Number of entries in mod_clks[] 275 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 276 * 277 * @resets: Array of Module Reset definitions 278 * @num_resets: Number of entries in resets[] 279 * 280 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that 281 * should not be disabled without a knowledgeable driver 282 * @num_crit_mod_clks: Number of entries in crit_mod_clks[] 283 * @crit_resets: Array with Reset IDs of critical resets that should not be 284 * asserted without a knowledgeable driver 285 * @num_crit_resets: Number of entries in crit_resets[] 286 * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers 287 */ 288 struct rzg2l_cpg_info { 289 /* Core Clocks */ 290 const struct cpg_core_clk *core_clks; 291 unsigned int num_core_clks; 292 unsigned int last_dt_core_clk; 293 unsigned int num_total_core_clks; 294 295 /* Module Clocks */ 296 const struct rzg2l_mod_clk *mod_clks; 297 unsigned int num_mod_clks; 298 unsigned int num_hw_mod_clks; 299 300 /* No PM Module Clocks */ 301 const unsigned int *no_pm_mod_clks; 302 unsigned int num_no_pm_mod_clks; 303 304 /* Resets */ 305 const struct rzg2l_reset *resets; 306 unsigned int num_resets; 307 308 /* Critical Module Clocks that should not be disabled */ 309 const unsigned int *crit_mod_clks; 310 unsigned int num_crit_mod_clks; 311 312 /* Critical Resets that should not be asserted */ 313 const unsigned int *crit_resets; 314 unsigned int num_crit_resets; 315 316 bool has_clk_mon_regs; 317 }; 318 319 extern const struct rzg2l_cpg_info r9a07g043_cpg_info; 320 extern const struct rzg2l_cpg_info r9a07g044_cpg_info; 321 extern const struct rzg2l_cpg_info r9a07g054_cpg_info; 322 extern const struct rzg2l_cpg_info r9a08g045_cpg_info; 323 extern const struct rzg2l_cpg_info r9a08g046_cpg_info; 324 extern const struct rzg2l_cpg_info r9a09g011_cpg_info; 325 326 int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data); 327 int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); 328 329 #endif 330