1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Renesas RZ/V2H(P) Clock Pulse Generator 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #ifndef __RENESAS_RZV2H_CPG_H__ 9 #define __RENESAS_RZV2H_CPG_H__ 10 11 #include <linux/bitfield.h> 12 13 /** 14 * struct pll - Structure for PLL configuration 15 * 16 * @offset: STBY register offset 17 * @has_clkn: Flag to indicate if CLK1/2 are accessible or not 18 */ 19 struct pll { 20 unsigned int offset:9; 21 unsigned int has_clkn:1; 22 }; 23 24 #define PLL_PACK(_offset, _has_clkn) \ 25 ((struct pll){ \ 26 .offset = _offset, \ 27 .has_clkn = _has_clkn \ 28 }) 29 30 #define PLLCA55 PLL_PACK(0x60, 1) 31 #define PLLGPU PLL_PACK(0x120, 1) 32 33 /** 34 * struct ddiv - Structure for dynamic switching divider 35 * 36 * @offset: register offset 37 * @shift: position of the divider bit 38 * @width: width of the divider 39 * @monbit: monitor bit in CPG_CLKSTATUS0 register 40 * @no_rmw: flag to indicate if the register is read-modify-write 41 * (1: no RMW, 0: RMW) 42 */ 43 struct ddiv { 44 unsigned int offset:11; 45 unsigned int shift:4; 46 unsigned int width:4; 47 unsigned int monbit:5; 48 unsigned int no_rmw:1; 49 }; 50 51 /* 52 * On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits, 53 * while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value 54 * `0x1f` to indicate that monitor bits are not supported for static divider 55 * clocks. 56 */ 57 #define CSDIV_NO_MON (0x1f) 58 59 #define DDIV_PACK(_offset, _shift, _width, _monbit) \ 60 ((struct ddiv){ \ 61 .offset = _offset, \ 62 .shift = _shift, \ 63 .width = _width, \ 64 .monbit = _monbit \ 65 }) 66 67 #define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \ 68 ((struct ddiv){ \ 69 .offset = (_offset), \ 70 .shift = (_shift), \ 71 .width = (_width), \ 72 .monbit = (_monbit), \ 73 .no_rmw = 1 \ 74 }) 75 76 /** 77 * struct smuxed - Structure for static muxed clocks 78 * 79 * @offset: register offset 80 * @shift: position of the divider field 81 * @width: width of the divider field 82 */ 83 struct smuxed { 84 unsigned int offset:11; 85 unsigned int shift:4; 86 unsigned int width:4; 87 }; 88 89 #define SMUX_PACK(_offset, _shift, _width) \ 90 ((struct smuxed){ \ 91 .offset = (_offset), \ 92 .shift = (_shift), \ 93 .width = (_width), \ 94 }) 95 96 #define CPG_SSEL1 (0x304) 97 #define CPG_CDDIV0 (0x400) 98 #define CPG_CDDIV1 (0x404) 99 #define CPG_CDDIV3 (0x40C) 100 #define CPG_CDDIV4 (0x410) 101 #define CPG_CSDIV0 (0x500) 102 103 #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) 104 #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) 105 #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) 106 #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5) 107 #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6) 108 #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7) 109 #define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13) 110 #define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14) 111 #define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15) 112 #define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16) 113 #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) 114 #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) 115 116 #define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON) 117 118 #define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1) 119 #define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1) 120 121 #define BUS_MSTOP_IDX_MASK GENMASK(31, 16) 122 #define BUS_MSTOP_BITS_MASK GENMASK(15, 0) 123 #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \ 124 FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask))) 125 #define BUS_MSTOP_NONE GENMASK(31, 0) 126 127 /** 128 * Definitions of CPG Core Clocks 129 * 130 * These include: 131 * - Clock outputs exported to DT 132 * - External input clocks 133 * - Internal CPG clocks 134 */ 135 struct cpg_core_clk { 136 const char *name; 137 unsigned int id; 138 unsigned int parent; 139 unsigned int div; 140 unsigned int mult; 141 unsigned int type; 142 union { 143 unsigned int conf; 144 struct ddiv ddiv; 145 struct pll pll; 146 struct smuxed smux; 147 } cfg; 148 const struct clk_div_table *dtable; 149 const char * const *parent_names; 150 unsigned int num_parents; 151 u8 mux_flags; 152 u32 flag; 153 }; 154 155 enum clk_types { 156 /* Generic */ 157 CLK_TYPE_IN, /* External Clock Input */ 158 CLK_TYPE_FF, /* Fixed Factor Clock */ 159 CLK_TYPE_PLL, 160 CLK_TYPE_DDIV, /* Dynamic Switching Divider */ 161 CLK_TYPE_SMUX, /* Static Mux */ 162 }; 163 164 #define DEF_TYPE(_name, _id, _type...) \ 165 { .name = _name, .id = _id, .type = _type } 166 #define DEF_BASE(_name, _id, _type, _parent...) \ 167 DEF_TYPE(_name, _id, _type, .parent = _parent) 168 #define DEF_PLL(_name, _id, _parent, _pll_packed) \ 169 DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed) 170 #define DEF_INPUT(_name, _id) \ 171 DEF_TYPE(_name, _id, CLK_TYPE_IN) 172 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 173 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 174 #define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ 175 DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \ 176 .cfg.ddiv = _ddiv_packed, \ 177 .parent = _parent, \ 178 .dtable = _dtable, \ 179 .flag = CLK_DIVIDER_HIWORD_MASK) 180 #define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ 181 DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) 182 #define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \ 183 DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \ 184 .cfg.smux = _smux_packed, \ 185 .parent_names = _parent_names, \ 186 .num_parents = ARRAY_SIZE(_parent_names), \ 187 .flag = CLK_SET_RATE_PARENT, \ 188 .mux_flags = CLK_MUX_HIWORD_MASK) 189 190 /** 191 * struct rzv2h_mod_clk - Module Clocks definitions 192 * 193 * @name: handle between common and hardware-specific interfaces 194 * @mstop_data: packed data mstop register offset and mask 195 * @parent: id of parent clock 196 * @critical: flag to indicate the clock is critical 197 * @no_pm: flag to indicate PM is not supported 198 * @on_index: control register index 199 * @on_bit: ON bit 200 * @mon_index: monitor register index 201 * @mon_bit: monitor bit 202 */ 203 struct rzv2h_mod_clk { 204 const char *name; 205 u32 mstop_data; 206 u16 parent; 207 bool critical; 208 bool no_pm; 209 u8 on_index; 210 u8 on_bit; 211 s8 mon_index; 212 u8 mon_bit; 213 }; 214 215 #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \ 216 { \ 217 .name = (_name), \ 218 .mstop_data = (_mstop), \ 219 .parent = (_parent), \ 220 .critical = (_critical), \ 221 .no_pm = (_no_pm), \ 222 .on_index = (_onindex), \ 223 .on_bit = (_onbit), \ 224 .mon_index = (_monindex), \ 225 .mon_bit = (_monbit), \ 226 } 227 228 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 229 DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) 230 231 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 232 DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit) 233 234 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 235 DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit) 236 237 /** 238 * struct rzv2h_reset - Reset definitions 239 * 240 * @reset_index: reset register index 241 * @reset_bit: reset bit 242 * @mon_index: monitor register index 243 * @mon_bit: monitor bit 244 */ 245 struct rzv2h_reset { 246 u8 reset_index; 247 u8 reset_bit; 248 u8 mon_index; 249 u8 mon_bit; 250 }; 251 252 #define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) \ 253 { \ 254 .reset_index = (_resindex), \ 255 .reset_bit = (_resbit), \ 256 .mon_index = (_monindex), \ 257 .mon_bit = (_monbit), \ 258 } 259 260 #define DEF_RST(_resindex, _resbit, _monindex, _monbit) \ 261 DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) 262 263 /** 264 * struct rzv2h_cpg_info - SoC-specific CPG Description 265 * 266 * @core_clks: Array of Core Clock definitions 267 * @num_core_clks: Number of entries in core_clks[] 268 * @last_dt_core_clk: ID of the last Core Clock exported to DT 269 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 270 * 271 * @mod_clks: Array of Module Clock definitions 272 * @num_mod_clks: Number of entries in mod_clks[] 273 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 274 * 275 * @resets: Array of Module Reset definitions 276 * @num_resets: Number of entries in resets[] 277 * 278 * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the 279 * number of CPG_BUS_m_MSTOP registers multiplied by 16. 280 */ 281 struct rzv2h_cpg_info { 282 /* Core Clocks */ 283 const struct cpg_core_clk *core_clks; 284 unsigned int num_core_clks; 285 unsigned int last_dt_core_clk; 286 unsigned int num_total_core_clks; 287 288 /* Module Clocks */ 289 const struct rzv2h_mod_clk *mod_clks; 290 unsigned int num_mod_clks; 291 unsigned int num_hw_mod_clks; 292 293 /* Resets */ 294 const struct rzv2h_reset *resets; 295 unsigned int num_resets; 296 297 unsigned int num_mstop_bits; 298 }; 299 300 extern const struct rzv2h_cpg_info r9a09g047_cpg_info; 301 extern const struct rzv2h_cpg_info r9a09g056_cpg_info; 302 extern const struct rzv2h_cpg_info r9a09g057_cpg_info; 303 304 #endif /* __RENESAS_RZV2H_CPG_H__ */ 305