1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 #include "grph_object_ctrl_defs.h" 42 43 #include "dm_cp_psp.h" 44 45 /* forward declarations */ 46 struct dc_plane_state; 47 struct dc_stream_state; 48 struct dc_link; 49 struct dc_sink; 50 struct dal; 51 struct dc_dmub_srv; 52 53 /******************************** 54 * Environment definitions 55 ********************************/ 56 enum dce_environment { 57 DCE_ENV_PRODUCTION_DRV = 0, 58 /* Emulation on FPGA, in "Maximus" System. 59 * This environment enforces that *only* DC registers accessed. 60 * (access to non-DC registers will hang FPGA) */ 61 DCE_ENV_FPGA_MAXIMUS, 62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 63 * requirements of Diagnostics team. */ 64 DCE_ENV_DIAG, 65 /* 66 * Guest VM system, DC HW may exist but is not virtualized and 67 * should not be used. SW support for VDI only. 68 */ 69 DCE_ENV_VIRTUAL_HW 70 }; 71 72 struct dc_perf_trace { 73 unsigned long read_count; 74 unsigned long write_count; 75 unsigned long last_entry_read; 76 unsigned long last_entry_write; 77 }; 78 79 #define MAX_SURFACE_NUM 6 80 #define NUM_PIXEL_FORMATS 10 81 82 enum tiling_mode { 83 TILING_MODE_INVALID, 84 TILING_MODE_LINEAR, 85 TILING_MODE_TILED, 86 TILING_MODE_COUNT 87 }; 88 89 enum view_3d_format { 90 VIEW_3D_FORMAT_NONE = 0, 91 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 92 VIEW_3D_FORMAT_SIDE_BY_SIDE, 93 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 94 VIEW_3D_FORMAT_COUNT, 95 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 96 }; 97 98 enum plane_stereo_format { 99 PLANE_STEREO_FORMAT_NONE = 0, 100 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 101 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 102 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 103 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 104 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 105 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 106 }; 107 108 /* TODO: Find way to calculate number of bits 109 * Please increase if pixel_format enum increases 110 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 111 */ 112 113 enum dc_edid_connector_type { 114 DC_EDID_CONNECTOR_UNKNOWN = 0, 115 DC_EDID_CONNECTOR_ANALOG = 1, 116 DC_EDID_CONNECTOR_DIGITAL = 10, 117 DC_EDID_CONNECTOR_DVI = 11, 118 DC_EDID_CONNECTOR_HDMIA = 12, 119 DC_EDID_CONNECTOR_MDDI = 14, 120 DC_EDID_CONNECTOR_DISPLAYPORT = 15 121 }; 122 123 enum dc_edid_status { 124 EDID_OK, 125 EDID_BAD_INPUT, 126 EDID_NO_RESPONSE, 127 EDID_BAD_CHECKSUM, 128 EDID_THE_SAME, 129 EDID_FALL_BACK, 130 EDID_PARTIAL_VALID, 131 }; 132 133 enum act_return_status { 134 ACT_SUCCESS, 135 ACT_LINK_LOST, 136 ACT_FAILED 137 }; 138 139 /* audio capability from EDID*/ 140 struct dc_cea_audio_mode { 141 uint8_t format_code; /* ucData[0] [6:3]*/ 142 uint8_t channel_count; /* ucData[0] [2:0]*/ 143 uint8_t sample_rate; /* ucData[1]*/ 144 union { 145 uint8_t sample_size; /* for LPCM*/ 146 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 147 uint8_t max_bit_rate; 148 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 149 }; 150 }; 151 152 struct dc_edid { 153 uint32_t length; 154 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 155 }; 156 157 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 158 * is used. In this case we assume speaker location are: front left, front 159 * right and front center. */ 160 #define DEFAULT_SPEAKER_LOCATION 5 161 162 #define DC_MAX_AUDIO_DESC_COUNT 16 163 164 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 165 166 struct dc_panel_patch { 167 unsigned int dppowerup_delay; 168 unsigned int extra_t12_ms; 169 unsigned int extra_delay_backlight_off; 170 unsigned int extra_t7_ms; 171 unsigned int skip_scdc_overwrite; 172 unsigned int delay_ignore_msa; 173 unsigned int disable_fec; 174 unsigned int extra_t3_ms; 175 unsigned int max_dsc_target_bpp_limit; 176 unsigned int embedded_tiled_slave; 177 unsigned int disable_fams; 178 unsigned int skip_avmute; 179 unsigned int mst_start_top_delay; 180 unsigned int remove_sink_ext_caps; 181 }; 182 183 struct dc_edid_caps { 184 /* sink identification */ 185 uint16_t manufacturer_id; 186 uint16_t product_id; 187 uint32_t serial_number; 188 uint8_t manufacture_week; 189 uint8_t manufacture_year; 190 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 191 192 /* audio caps */ 193 uint8_t speaker_flags; 194 uint32_t audio_mode_count; 195 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 196 uint32_t audio_latency; 197 uint32_t video_latency; 198 199 uint8_t qs_bit; 200 uint8_t qy_bit; 201 202 uint32_t max_tmds_clk_mhz; 203 204 /*HDMI 2.0 caps*/ 205 bool lte_340mcsc_scramble; 206 207 bool edid_hdmi; 208 bool hdr_supported; 209 210 struct dc_panel_patch panel_patch; 211 }; 212 213 struct dc_mode_flags { 214 /* note: part of refresh rate flag*/ 215 uint32_t INTERLACE :1; 216 /* native display timing*/ 217 uint32_t NATIVE :1; 218 /* preferred is the recommended mode, one per display */ 219 uint32_t PREFERRED :1; 220 /* true if this mode should use reduced blanking timings 221 *_not_ related to the Reduced Blanking adjustment*/ 222 uint32_t REDUCED_BLANKING :1; 223 /* note: part of refreshrate flag*/ 224 uint32_t VIDEO_OPTIMIZED_RATE :1; 225 /* should be reported to upper layers as mode_flags*/ 226 uint32_t PACKED_PIXEL_FORMAT :1; 227 /*< preferred view*/ 228 uint32_t PREFERRED_VIEW :1; 229 /* this timing should be used only in tiled mode*/ 230 uint32_t TILED_MODE :1; 231 uint32_t DSE_MODE :1; 232 /* Refresh rate divider when Miracast sink is using a 233 different rate than the output display device 234 Must be zero for wired displays and non-zero for 235 Miracast displays*/ 236 uint32_t MIRACAST_REFRESH_DIVIDER; 237 }; 238 239 240 enum dc_timing_source { 241 TIMING_SOURCE_UNDEFINED, 242 243 /* explicitly specifed by user, most important*/ 244 TIMING_SOURCE_USER_FORCED, 245 TIMING_SOURCE_USER_OVERRIDE, 246 TIMING_SOURCE_CUSTOM, 247 TIMING_SOURCE_EXPLICIT, 248 249 /* explicitly specified by the display device, more important*/ 250 TIMING_SOURCE_EDID_CEA_SVD_3D, 251 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 252 TIMING_SOURCE_EDID_CEA_SVD_420, 253 TIMING_SOURCE_EDID_DETAILED, 254 TIMING_SOURCE_EDID_ESTABLISHED, 255 TIMING_SOURCE_EDID_STANDARD, 256 TIMING_SOURCE_EDID_CEA_SVD, 257 TIMING_SOURCE_EDID_CVT_3BYTE, 258 TIMING_SOURCE_EDID_4BYTE, 259 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 260 TIMING_SOURCE_EDID_CEA_RID, 261 TIMING_SOURCE_VBIOS, 262 TIMING_SOURCE_CV, 263 TIMING_SOURCE_TV, 264 TIMING_SOURCE_HDMI_VIC, 265 266 /* implicitly specified by display device, still safe but less important*/ 267 TIMING_SOURCE_DEFAULT, 268 269 /* only used for custom base modes */ 270 TIMING_SOURCE_CUSTOM_BASE, 271 272 /* these timing might not work, least important*/ 273 TIMING_SOURCE_RANGELIMIT, 274 TIMING_SOURCE_OS_FORCED, 275 TIMING_SOURCE_IMPLICIT, 276 277 /* only used by default mode list*/ 278 TIMING_SOURCE_BASICMODE, 279 280 TIMING_SOURCE_COUNT 281 }; 282 283 284 struct stereo_3d_features { 285 bool supported ; 286 bool allTimings ; 287 bool cloneMode ; 288 bool scaling ; 289 bool singleFrameSWPacked; 290 }; 291 292 enum dc_timing_support_method { 293 TIMING_SUPPORT_METHOD_UNDEFINED, 294 TIMING_SUPPORT_METHOD_EXPLICIT, 295 TIMING_SUPPORT_METHOD_IMPLICIT, 296 TIMING_SUPPORT_METHOD_NATIVE 297 }; 298 299 struct dc_mode_info { 300 uint32_t pixel_width; 301 uint32_t pixel_height; 302 uint32_t field_rate; 303 /* Vertical refresh rate for progressive modes. 304 * Field rate for interlaced modes.*/ 305 306 enum dc_timing_standard timing_standard; 307 enum dc_timing_source timing_source; 308 struct dc_mode_flags flags; 309 }; 310 311 enum dc_power_state { 312 DC_POWER_STATE_ON = 1, 313 DC_POWER_STATE_STANDBY, 314 DC_POWER_STATE_SUSPEND, 315 DC_POWER_STATE_OFF 316 }; 317 318 /* DC PowerStates */ 319 enum dc_video_power_state { 320 DC_VIDEO_POWER_UNSPECIFIED = 0, 321 DC_VIDEO_POWER_ON = 1, 322 DC_VIDEO_POWER_STANDBY, 323 DC_VIDEO_POWER_SUSPEND, 324 DC_VIDEO_POWER_OFF, 325 DC_VIDEO_POWER_HIBERNATE, 326 DC_VIDEO_POWER_SHUTDOWN, 327 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 328 DC_VIDEO_POWER_AFTER_RESET, 329 DC_VIDEO_POWER_MAXIMUM 330 }; 331 332 enum dc_acpi_cm_power_state { 333 DC_ACPI_CM_POWER_STATE_D0 = 1, 334 DC_ACPI_CM_POWER_STATE_D1 = 2, 335 DC_ACPI_CM_POWER_STATE_D2 = 4, 336 DC_ACPI_CM_POWER_STATE_D3 = 8 337 }; 338 339 enum dc_connection_type { 340 dc_connection_none, 341 dc_connection_single, 342 dc_connection_mst_branch, 343 dc_connection_sst_branch 344 }; 345 346 struct dc_csc_adjustments { 347 struct fixed31_32 contrast; 348 struct fixed31_32 saturation; 349 struct fixed31_32 brightness; 350 struct fixed31_32 hue; 351 }; 352 353 /* Scaling format */ 354 enum scaling_transformation { 355 SCALING_TRANSFORMATION_UNINITIALIZED, 356 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 357 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 358 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 359 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 360 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 361 SCALING_TRANSFORMATION_INVALID = 0x80000000, 362 363 /* Flag the first and last */ 364 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 365 SCALING_TRANSFORMATION_END = 366 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 367 }; 368 369 enum display_content_type { 370 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 371 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 372 DISPLAY_CONTENT_TYPE_PHOTO = 2, 373 DISPLAY_CONTENT_TYPE_CINEMA = 4, 374 DISPLAY_CONTENT_TYPE_GAME = 8 375 }; 376 377 enum cm_gamut_adjust_type { 378 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 379 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 380 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 381 }; 382 383 struct cm_grph_csc_adjustment { 384 struct fixed31_32 temperature_matrix[12]; 385 enum cm_gamut_adjust_type gamut_adjust_type; 386 enum cm_gamut_coef_format gamut_coef_format; 387 }; 388 389 /* writeback */ 390 struct dwb_stereo_params { 391 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 392 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 393 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 394 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 395 }; 396 397 struct dc_dwb_cnv_params { 398 unsigned int src_width; /* input active width */ 399 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 400 unsigned int crop_width; /* cropped window width at cnv output */ 401 bool crop_en; /* window cropping enable in cnv */ 402 unsigned int crop_height; /* cropped window height at cnv output */ 403 unsigned int crop_x; /* cropped window start x value at cnv output */ 404 unsigned int crop_y; /* cropped window start y value at cnv output */ 405 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 406 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 407 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 408 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 409 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 410 }; 411 412 struct dc_dwb_params { 413 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 414 unsigned int hdr_mult; /* must be in FP1.6.12 */ 415 struct cm_grph_csc_adjustment csc_params; 416 struct dwb_stereo_params stereo_params; 417 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 418 unsigned int dest_width; /* Destination width */ 419 unsigned int dest_height; /* Destination height */ 420 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 421 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 422 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 423 struct scaling_taps scaler_taps; /* Scaling taps */ 424 enum dwb_subsample_position subsample_position; 425 const struct dc_transfer_func *out_transfer_func; 426 }; 427 428 /* audio*/ 429 430 union audio_sample_rates { 431 struct sample_rates { 432 uint8_t RATE_32:1; 433 uint8_t RATE_44_1:1; 434 uint8_t RATE_48:1; 435 uint8_t RATE_88_2:1; 436 uint8_t RATE_96:1; 437 uint8_t RATE_176_4:1; 438 uint8_t RATE_192:1; 439 } rate; 440 441 uint8_t all; 442 }; 443 444 struct audio_speaker_flags { 445 uint32_t FL_FR:1; 446 uint32_t LFE:1; 447 uint32_t FC:1; 448 uint32_t RL_RR:1; 449 uint32_t RC:1; 450 uint32_t FLC_FRC:1; 451 uint32_t RLC_RRC:1; 452 uint32_t SUPPORT_AI:1; 453 }; 454 455 struct audio_speaker_info { 456 uint32_t ALLSPEAKERS:7; 457 uint32_t SUPPORT_AI:1; 458 }; 459 460 461 struct audio_info_flags { 462 463 union { 464 465 struct audio_speaker_flags speaker_flags; 466 struct audio_speaker_info info; 467 468 uint8_t all; 469 }; 470 }; 471 472 enum audio_format_code { 473 AUDIO_FORMAT_CODE_FIRST = 1, 474 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 475 476 AUDIO_FORMAT_CODE_AC3, 477 /*Layers 1 & 2 */ 478 AUDIO_FORMAT_CODE_MPEG1, 479 /*MPEG1 Layer 3 */ 480 AUDIO_FORMAT_CODE_MP3, 481 /*multichannel */ 482 AUDIO_FORMAT_CODE_MPEG2, 483 AUDIO_FORMAT_CODE_AAC, 484 AUDIO_FORMAT_CODE_DTS, 485 AUDIO_FORMAT_CODE_ATRAC, 486 AUDIO_FORMAT_CODE_1BITAUDIO, 487 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 488 AUDIO_FORMAT_CODE_DTS_HD, 489 AUDIO_FORMAT_CODE_MAT_MLP, 490 AUDIO_FORMAT_CODE_DST, 491 AUDIO_FORMAT_CODE_WMAPRO, 492 AUDIO_FORMAT_CODE_LAST, 493 AUDIO_FORMAT_CODE_COUNT = 494 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 495 }; 496 497 struct audio_mode { 498 /* ucData[0] [6:3] */ 499 enum audio_format_code format_code; 500 /* ucData[0] [2:0] */ 501 uint8_t channel_count; 502 /* ucData[1] */ 503 union audio_sample_rates sample_rates; 504 union { 505 /* for LPCM */ 506 uint8_t sample_size; 507 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 508 uint8_t max_bit_rate; 509 /* for Audio Formats 9-15 */ 510 uint8_t vendor_specific; 511 }; 512 }; 513 514 struct audio_info { 515 struct audio_info_flags flags; 516 uint32_t video_latency; 517 uint32_t audio_latency; 518 uint32_t display_index; 519 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 520 uint32_t manufacture_id; 521 uint32_t product_id; 522 /* PortID used for ContainerID when defined */ 523 uint32_t port_id[2]; 524 uint32_t mode_count; 525 /* this field must be last in this struct */ 526 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 527 }; 528 struct audio_check { 529 unsigned int audio_packet_type; 530 unsigned int max_audiosample_rate; 531 unsigned int acat; 532 }; 533 enum dc_infoframe_type { 534 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 535 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 536 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 537 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 538 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 539 }; 540 541 struct dc_info_packet { 542 bool valid; 543 uint8_t hb0; 544 uint8_t hb1; 545 uint8_t hb2; 546 uint8_t hb3; 547 uint8_t sb[32]; 548 }; 549 550 struct dc_info_packet_128 { 551 bool valid; 552 uint8_t hb0; 553 uint8_t hb1; 554 uint8_t hb2; 555 uint8_t hb3; 556 uint8_t sb[128]; 557 }; 558 559 #define DC_PLANE_UPDATE_TIMES_MAX 10 560 561 struct dc_plane_flip_time { 562 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 563 unsigned int index; 564 unsigned int prev_update_time_in_us; 565 }; 566 567 enum dc_psr_state { 568 PSR_STATE0 = 0x0, 569 PSR_STATE1, 570 PSR_STATE1a, 571 PSR_STATE2, 572 PSR_STATE2a, 573 PSR_STATE2b, 574 PSR_STATE3, 575 PSR_STATE3Init, 576 PSR_STATE4, 577 PSR_STATE4a, 578 PSR_STATE4b, 579 PSR_STATE4c, 580 PSR_STATE4d, 581 PSR_STATE4_FULL_FRAME, 582 PSR_STATE4a_FULL_FRAME, 583 PSR_STATE4b_FULL_FRAME, 584 PSR_STATE4c_FULL_FRAME, 585 PSR_STATE4_FULL_FRAME_POWERUP, 586 PSR_STATE4_FULL_FRAME_HW_LOCK, 587 PSR_STATE5, 588 PSR_STATE5a, 589 PSR_STATE5b, 590 PSR_STATE5c, 591 PSR_STATE_HWLOCK_MGR, 592 PSR_STATE_POLLVUPDATE, 593 PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME, 594 PSR_STATE_INVALID = 0xFF 595 }; 596 597 struct psr_config { 598 unsigned char psr_version; 599 unsigned int psr_rfb_setup_time; 600 bool psr_exit_link_training_required; 601 bool psr_frame_capture_indication_req; 602 unsigned int psr_sdp_transmit_line_num_deadline; 603 bool allow_smu_optimizations; 604 bool allow_multi_disp_optimizations; 605 /* Panel self refresh 2 selective update granularity required */ 606 bool su_granularity_required; 607 /* psr2 selective update y granularity capability */ 608 uint8_t su_y_granularity; 609 unsigned int line_time_in_us; 610 uint8_t rate_control_caps; 611 uint16_t dsc_slice_height; 612 }; 613 614 union dmcu_psr_level { 615 struct { 616 unsigned int SKIP_CRC:1; 617 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 618 unsigned int SKIP_PHY_POWER_DOWN:1; 619 unsigned int SKIP_AUX_ACK_CHECK:1; 620 unsigned int SKIP_CRTC_DISABLE:1; 621 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 622 unsigned int SKIP_SMU_NOTIFICATION:1; 623 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 624 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 625 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 626 unsigned int DISABLE_ALPM:1; 627 unsigned int ALPM_DEFAULT_PD_MODE:1; 628 unsigned int RESERVED:20; 629 } bits; 630 unsigned int u32all; 631 }; 632 633 enum physical_phy_id { 634 PHYLD_0, 635 PHYLD_1, 636 PHYLD_2, 637 PHYLD_3, 638 PHYLD_4, 639 PHYLD_5, 640 PHYLD_6, 641 PHYLD_7, 642 PHYLD_8, 643 PHYLD_9, 644 PHYLD_COUNT, 645 PHYLD_UNKNOWN = (-1L) 646 }; 647 648 enum phy_type { 649 PHY_TYPE_UNKNOWN = 1, 650 PHY_TYPE_PCIE_PHY = 2, 651 PHY_TYPE_UNIPHY = 3, 652 }; 653 654 struct psr_context { 655 /* ddc line */ 656 enum channel_id channel; 657 /* Transmitter id */ 658 enum transmitter transmitterId; 659 /* Engine Id is used for Dig Be source select */ 660 enum engine_id engineId; 661 /* Controller Id used for Dig Fe source select */ 662 enum controller_id controllerId; 663 /* Pcie or Uniphy */ 664 enum phy_type phyType; 665 /* Physical PHY Id used by SMU interpretation */ 666 enum physical_phy_id smuPhyId; 667 /* Vertical total pixels from crtc timing. 668 * This is used for static screen detection. 669 * ie. If we want to detect half a frame, 670 * we use this to determine the hyst lines. 671 */ 672 unsigned int crtcTimingVerticalTotal; 673 /* PSR supported from panel capabilities and 674 * current display configuration 675 */ 676 bool psrSupportedDisplayConfig; 677 /* Whether fast link training is supported by the panel */ 678 bool psrExitLinkTrainingRequired; 679 /* If RFB setup time is greater than the total VBLANK time, 680 * it is not possible for the sink to capture the video frame 681 * in the same frame the SDP is sent. In this case, 682 * the frame capture indication bit should be set and an extra 683 * static frame should be transmitted to the sink. 684 */ 685 bool psrFrameCaptureIndicationReq; 686 /* Set the last possible line SDP may be transmitted without violating 687 * the RFB setup time or entering the active video frame. 688 */ 689 unsigned int sdpTransmitLineNumDeadline; 690 /* The VSync rate in Hz used to calculate the 691 * step size for smooth brightness feature 692 */ 693 unsigned int vsync_rate_hz; 694 unsigned int skipPsrWaitForPllLock; 695 unsigned int numberOfControllers; 696 /* Unused, for future use. To indicate that first changed frame from 697 * state3 shouldn't result in psr_inactive, but rather to perform 698 * an automatic single frame rfb_update. 699 */ 700 bool rfb_update_auto_en; 701 /* Number of frame before entering static screen */ 702 unsigned int timehyst_frames; 703 /* Partial frames before entering static screen */ 704 unsigned int hyst_lines; 705 /* # of repeated AUX transaction attempts to make before 706 * indicating failure to the driver 707 */ 708 unsigned int aux_repeats; 709 /* Controls hw blocks to power down during PSR active state */ 710 union dmcu_psr_level psr_level; 711 /* Controls additional delay after remote frame capture before 712 * continuing powerd own 713 */ 714 unsigned int frame_delay; 715 bool allow_smu_optimizations; 716 bool allow_multi_disp_optimizations; 717 /* Panel self refresh 2 selective update granularity required */ 718 bool su_granularity_required; 719 /* psr2 selective update y granularity capability */ 720 uint8_t su_y_granularity; 721 unsigned int line_time_in_us; 722 uint8_t rate_control_caps; 723 uint16_t dsc_slice_height; 724 }; 725 726 struct colorspace_transform { 727 struct fixed31_32 matrix[12]; 728 bool enable_remap; 729 }; 730 731 enum i2c_mot_mode { 732 I2C_MOT_UNDEF, 733 I2C_MOT_TRUE, 734 I2C_MOT_FALSE 735 }; 736 737 struct AsicStateEx { 738 unsigned int memoryClock; 739 unsigned int displayClock; 740 unsigned int engineClock; 741 unsigned int maxSupportedDppClock; 742 unsigned int dppClock; 743 unsigned int socClock; 744 unsigned int dcfClockDeepSleep; 745 unsigned int fClock; 746 unsigned int phyClock; 747 }; 748 749 750 enum dc_clock_type { 751 DC_CLOCK_TYPE_DISPCLK = 0, 752 DC_CLOCK_TYPE_DPPCLK = 1, 753 }; 754 755 struct dc_clock_config { 756 uint32_t max_clock_khz; 757 uint32_t min_clock_khz; 758 uint32_t bw_requirequired_clock_khz; 759 uint32_t current_clock_khz;/*current clock in use*/ 760 }; 761 762 struct hw_asic_id { 763 uint32_t chip_id; 764 uint32_t chip_family; 765 uint32_t pci_revision_id; 766 uint32_t hw_internal_rev; 767 uint32_t vram_type; 768 uint32_t vram_width; 769 uint32_t feature_flags; 770 uint32_t fake_paths_num; 771 void *atombios_base_address; 772 }; 773 774 struct dc_context { 775 struct dc *dc; 776 777 void *driver_context; /* e.g. amdgpu_device */ 778 struct dal_logger *logger; 779 struct dc_perf_trace *perf_trace; 780 void *cgs_device; 781 782 enum dce_environment dce_environment; 783 struct hw_asic_id asic_id; 784 785 /* todo: below should probably move to dc. to facilitate removal 786 * of AS we will store these here 787 */ 788 enum dce_version dce_version; 789 struct dc_bios *dc_bios; 790 bool created_bios; 791 struct gpio_service *gpio_service; 792 uint32_t dc_sink_id_count; 793 uint32_t dc_stream_id_count; 794 uint32_t dc_edp_id_count; 795 uint64_t fbc_gpu_addr; 796 struct dc_dmub_srv *dmub_srv; 797 struct cp_psp cp_psp; 798 uint32_t *dcn_reg_offsets; 799 uint32_t *nbio_reg_offsets; 800 uint32_t *clk_reg_offsets; 801 }; 802 803 /* DSC DPCD capabilities */ 804 union dsc_slice_caps1 { 805 struct { 806 uint8_t NUM_SLICES_1 : 1; 807 uint8_t NUM_SLICES_2 : 1; 808 uint8_t RESERVED : 1; 809 uint8_t NUM_SLICES_4 : 1; 810 uint8_t NUM_SLICES_6 : 1; 811 uint8_t NUM_SLICES_8 : 1; 812 uint8_t NUM_SLICES_10 : 1; 813 uint8_t NUM_SLICES_12 : 1; 814 } bits; 815 uint8_t raw; 816 }; 817 818 union dsc_slice_caps2 { 819 struct { 820 uint8_t NUM_SLICES_16 : 1; 821 uint8_t NUM_SLICES_20 : 1; 822 uint8_t NUM_SLICES_24 : 1; 823 uint8_t RESERVED : 5; 824 } bits; 825 uint8_t raw; 826 }; 827 828 union dsc_color_formats { 829 struct { 830 uint8_t RGB : 1; 831 uint8_t YCBCR_444 : 1; 832 uint8_t YCBCR_SIMPLE_422 : 1; 833 uint8_t YCBCR_NATIVE_422 : 1; 834 uint8_t YCBCR_NATIVE_420 : 1; 835 uint8_t RESERVED : 3; 836 } bits; 837 uint8_t raw; 838 }; 839 840 union dsc_color_depth { 841 struct { 842 uint8_t RESERVED1 : 1; 843 uint8_t COLOR_DEPTH_8_BPC : 1; 844 uint8_t COLOR_DEPTH_10_BPC : 1; 845 uint8_t COLOR_DEPTH_12_BPC : 1; 846 uint8_t RESERVED2 : 3; 847 } bits; 848 uint8_t raw; 849 }; 850 851 struct dsc_dec_dpcd_caps { 852 bool is_dsc_supported; 853 uint8_t dsc_version; 854 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 855 union dsc_slice_caps1 slice_caps1; 856 union dsc_slice_caps2 slice_caps2; 857 int32_t lb_bit_depth; 858 bool is_block_pred_supported; 859 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 860 union dsc_color_formats color_formats; 861 union dsc_color_depth color_depth; 862 int32_t throughput_mode_0_mps; /* In MPs */ 863 int32_t throughput_mode_1_mps; /* In MPs */ 864 int32_t max_slice_width; 865 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 866 867 /* Extended DSC caps */ 868 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 869 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 870 uint32_t branch_max_line_width; 871 bool is_dp; /* Decoded format */ 872 }; 873 874 struct dc_golden_table { 875 uint16_t dc_golden_table_ver; 876 uint32_t aux_dphy_rx_control0_val; 877 uint32_t aux_dphy_tx_control_val; 878 uint32_t aux_dphy_rx_control1_val; 879 uint32_t dc_gpio_aux_ctrl_0_val; 880 uint32_t dc_gpio_aux_ctrl_1_val; 881 uint32_t dc_gpio_aux_ctrl_2_val; 882 uint32_t dc_gpio_aux_ctrl_3_val; 883 uint32_t dc_gpio_aux_ctrl_4_val; 884 uint32_t dc_gpio_aux_ctrl_5_val; 885 }; 886 887 enum dc_gpu_mem_alloc_type { 888 DC_MEM_ALLOC_TYPE_GART, 889 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 890 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 891 DC_MEM_ALLOC_TYPE_AGP 892 }; 893 894 enum dc_link_encoding_format { 895 DC_LINK_ENCODING_UNSPECIFIED = 0, 896 DC_LINK_ENCODING_DP_8b_10b, 897 DC_LINK_ENCODING_DP_128b_132b, 898 DC_LINK_ENCODING_HDMI_TMDS, 899 DC_LINK_ENCODING_HDMI_FRL 900 }; 901 902 enum dc_psr_version { 903 DC_PSR_VERSION_1 = 0, 904 DC_PSR_VERSION_SU_1 = 1, 905 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 906 }; 907 908 /* Possible values of display_endpoint_id.endpoint */ 909 enum display_endpoint_type { 910 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 911 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 912 DISPLAY_ENDPOINT_UNKNOWN = -1 913 }; 914 915 /* Extends graphics_object_id with an additional member 'ep_type' for 916 * distinguishing between physical endpoints (with entries in BIOS connector table) and 917 * logical endpoints. 918 */ 919 struct display_endpoint_id { 920 struct graphics_object_id link_id; 921 enum display_endpoint_type ep_type; 922 }; 923 924 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 925 struct otg_phy_mux { 926 uint8_t phy_output_num; 927 uint8_t otg_output_num; 928 }; 929 #endif 930 931 enum dc_detect_reason { 932 DETECT_REASON_BOOT, 933 DETECT_REASON_RESUMEFROMS3S4, 934 DETECT_REASON_HPD, 935 DETECT_REASON_HPDRX, 936 DETECT_REASON_FALLBACK, 937 DETECT_REASON_RETRAIN, 938 DETECT_REASON_TDR, 939 }; 940 941 struct dc_link_status { 942 bool link_active; 943 struct dpcd_caps *dpcd_caps; 944 }; 945 946 union hdcp_rx_caps { 947 struct { 948 uint8_t version; 949 uint8_t reserved; 950 struct { 951 uint8_t repeater : 1; 952 uint8_t hdcp_capable : 1; 953 uint8_t reserved : 6; 954 } byte0; 955 } fields; 956 uint8_t raw[3]; 957 }; 958 959 union hdcp_bcaps { 960 struct { 961 uint8_t HDCP_CAPABLE:1; 962 uint8_t REPEATER:1; 963 uint8_t RESERVED:6; 964 } bits; 965 uint8_t raw; 966 }; 967 968 struct hdcp_caps { 969 union hdcp_rx_caps rx_caps; 970 union hdcp_bcaps bcaps; 971 }; 972 973 /* DP MST stream allocation (payload bandwidth number) */ 974 struct link_mst_stream_allocation { 975 /* DIG front */ 976 const struct stream_encoder *stream_enc; 977 /* HPO DP Stream Encoder */ 978 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 979 /* associate DRM payload table with DC stream encoder */ 980 uint8_t vcp_id; 981 /* number of slots required for the DP stream in transport packet */ 982 uint8_t slot_count; 983 }; 984 985 #define MAX_CONTROLLER_NUM 6 986 987 /* DP MST stream allocation table */ 988 struct link_mst_stream_allocation_table { 989 /* number of DP video streams */ 990 int stream_count; 991 /* array of stream allocations */ 992 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 993 }; 994 995 /* PSR feature flags */ 996 struct psr_settings { 997 bool psr_feature_enabled; // PSR is supported by sink 998 bool psr_allow_active; // PSR is currently active 999 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD 1000 bool psr_vtotal_control_support; // Vtotal control is supported by sink 1001 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU 1002 1003 /* These parameters are calculated in Driver, 1004 * based on display timing and Sink capabilities. 1005 * If VBLANK region is too small and Sink takes a long time 1006 * to set up RFB, it may take an extra frame to enter PSR state. 1007 */ 1008 bool psr_frame_capture_indication_req; 1009 unsigned int psr_sdp_transmit_line_num_deadline; 1010 uint8_t force_ffu_mode; 1011 unsigned int psr_power_opt; 1012 }; 1013 1014 enum replay_coasting_vtotal_type { 1015 PR_COASTING_TYPE_NOM = 0, 1016 PR_COASTING_TYPE_STATIC, 1017 PR_COASTING_TYPE_FULL_SCREEN_VIDEO, 1018 PR_COASTING_TYPE_TEST_HARNESS, 1019 PR_COASTING_TYPE_NUM, 1020 }; 1021 1022 enum replay_link_off_frame_count_level { 1023 PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0, 1024 PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2, 1025 PR_LINK_OFF_FRAME_COUNT_BEST = 0x6, 1026 }; 1027 1028 /* 1029 * This is general Interface for Replay to 1030 * set an 32 bit variable to dmub 1031 * The Message_type indicates which variable 1032 * passed to DMUB. 1033 */ 1034 enum replay_FW_Message_type { 1035 Replay_Msg_Not_Support = -1, 1036 Replay_Set_Timing_Sync_Supported, 1037 Replay_Set_Residency_Frameupdate_Timer, 1038 Replay_Set_Pseudo_VTotal, 1039 Replay_Disabled_Adaptive_Sync_SDP, 1040 Replay_Set_General_Cmd, 1041 }; 1042 1043 union replay_error_status { 1044 struct { 1045 unsigned char STATE_TRANSITION_ERROR :1; 1046 unsigned char LINK_CRC_ERROR :1; 1047 unsigned char DESYNC_ERROR :1; 1048 unsigned char RESERVED :5; 1049 } bits; 1050 unsigned char raw; 1051 }; 1052 1053 union replay_low_refresh_rate_enable_options { 1054 struct { 1055 //BIT[0-3]: Replay Low Hz Support control 1056 unsigned int ENABLE_LOW_RR_SUPPORT :1; 1057 unsigned int RESERVED_1_3 :3; 1058 //BIT[4-15]: Replay Low Hz Enable Scenarios 1059 unsigned int ENABLE_STATIC_SCREEN :1; 1060 unsigned int ENABLE_FULL_SCREEN_VIDEO :1; 1061 unsigned int ENABLE_GENERAL_UI :1; 1062 unsigned int RESERVED_7_15 :9; 1063 //BIT[16-31]: Replay Low Hz Enable Check 1064 unsigned int ENABLE_STATIC_FLICKER_CHECK :1; 1065 unsigned int RESERVED_17_31 :15; 1066 } bits; 1067 unsigned int raw; 1068 }; 1069 1070 struct replay_config { 1071 /* Replay feature is supported */ 1072 bool replay_supported; 1073 /* Replay caps support DPCD & EDID caps*/ 1074 bool replay_cap_support; 1075 /* Power opt flags that are supported */ 1076 unsigned int replay_power_opt_supported; 1077 /* SMU optimization is supported */ 1078 bool replay_smu_opt_supported; 1079 /* Replay enablement option */ 1080 unsigned int replay_enable_option; 1081 /* Replay debug flags */ 1082 uint32_t debug_flags; 1083 /* Replay sync is supported */ 1084 bool replay_timing_sync_supported; 1085 /* Replay Disable desync error check. */ 1086 bool force_disable_desync_error_check; 1087 /* Replay Received Desync Error HPD. */ 1088 bool received_desync_error_hpd; 1089 /* Replay feature is supported long vblank */ 1090 bool replay_support_fast_resync_in_ultra_sleep_mode; 1091 /* Replay error status */ 1092 union replay_error_status replay_error_status; 1093 /* Replay Low Hz enable Options */ 1094 union replay_low_refresh_rate_enable_options low_rr_enable_options; 1095 }; 1096 1097 /* Replay feature flags*/ 1098 struct replay_settings { 1099 /* Replay configuration */ 1100 struct replay_config config; 1101 /* Replay feature is ready for activating */ 1102 bool replay_feature_enabled; 1103 /* Replay is currently active */ 1104 bool replay_allow_active; 1105 /* Replay is currently active */ 1106 bool replay_allow_long_vblank; 1107 /* Power opt flags that are activated currently */ 1108 unsigned int replay_power_opt_active; 1109 /* SMU optimization is enabled */ 1110 bool replay_smu_opt_enable; 1111 /* Current Coasting vtotal */ 1112 uint32_t coasting_vtotal; 1113 /* Coasting vtotal table */ 1114 uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1115 /* Defer Update Coasting vtotal table */ 1116 uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1117 /* Maximum link off frame count */ 1118 uint32_t link_off_frame_count; 1119 /* Replay pseudo vtotal for abm + ips on full screen video which can improve ips residency */ 1120 uint16_t abm_with_ips_on_full_screen_video_pseudo_vtotal; 1121 /* Replay last pseudo vtotal set to DMUB */ 1122 uint16_t last_pseudo_vtotal; 1123 }; 1124 1125 /* To split out "global" and "per-panel" config settings. 1126 * Add a struct dc_panel_config under dc_link 1127 */ 1128 struct dc_panel_config { 1129 /* extra panel power sequence parameters */ 1130 struct pps { 1131 unsigned int extra_t3_ms; 1132 unsigned int extra_t7_ms; 1133 unsigned int extra_delay_backlight_off; 1134 unsigned int extra_post_t7_ms; 1135 unsigned int extra_pre_t11_ms; 1136 unsigned int extra_t12_ms; 1137 unsigned int extra_post_OUI_ms; 1138 } pps; 1139 /* nit brightness */ 1140 struct nits_brightness { 1141 unsigned int peak; /* nits */ 1142 unsigned int max_avg; /* nits */ 1143 unsigned int min; /* 1/10000 nits */ 1144 unsigned int max_nonboost_brightness_millinits; 1145 unsigned int min_brightness_millinits; 1146 } nits_brightness; 1147 /* PSR */ 1148 struct psr { 1149 bool disable_psr; 1150 bool disallow_psrsu; 1151 bool disallow_replay; 1152 bool rc_disable; 1153 bool rc_allow_static_screen; 1154 bool rc_allow_fullscreen_VPB; 1155 unsigned int replay_enable_option; 1156 } psr; 1157 /* ABM */ 1158 struct varib { 1159 unsigned int varibright_feature_enable; 1160 unsigned int def_varibright_level; 1161 unsigned int abm_config_setting; 1162 } varib; 1163 /* edp DSC */ 1164 struct dsc { 1165 bool disable_dsc_edp; 1166 unsigned int force_dsc_edp_policy; 1167 } dsc; 1168 /* eDP ILR */ 1169 struct ilr { 1170 bool optimize_edp_link_rate; /* eDP ILR */ 1171 } ilr; 1172 }; 1173 1174 #define MAX_SINKS_PER_LINK 4 1175 1176 /* 1177 * USB4 DPIA BW ALLOCATION STRUCTS 1178 */ 1179 struct dc_dpia_bw_alloc { 1180 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks 1181 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already 1182 int link_max_bw; // The Max BW that link can require/support 1183 int allocated_bw; // The Actual Allocated BW for this DPIA 1184 int estimated_bw; // The estimated available BW for this DPIA 1185 int bw_granularity; // BW Granularity 1186 int dp_overhead; // DP overhead in dp tunneling 1187 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM 1188 bool response_ready; // Response ready from the CM side 1189 uint8_t nrd_max_lane_count; // Non-reduced max lane count 1190 uint8_t nrd_max_link_rate; // Non-reduced max link rate 1191 }; 1192 1193 enum dc_hpd_enable_select { 1194 HPD_EN_FOR_ALL_EDP = 0, 1195 HPD_EN_FOR_PRIMARY_EDP_ONLY, 1196 HPD_EN_FOR_SECONDARY_EDP_ONLY, 1197 }; 1198 1199 enum dc_cm2_shaper_3dlut_setting { 1200 DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL, 1201 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER, 1202 /* Bypassing Shaper will always bypass 3DLUT */ 1203 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT 1204 }; 1205 1206 enum dc_cm2_gpu_mem_layout { 1207 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB, 1208 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR, 1209 DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR 1210 }; 1211 1212 enum dc_cm2_gpu_mem_pixel_component_order { 1213 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA, 1214 }; 1215 1216 enum dc_cm2_gpu_mem_format { 1217 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB, 1218 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB, 1219 DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10 1220 }; 1221 1222 struct dc_cm2_gpu_mem_format_parameters { 1223 enum dc_cm2_gpu_mem_format format; 1224 union { 1225 struct { 1226 /* bias & scale for float only */ 1227 uint16_t bias; 1228 uint16_t scale; 1229 } float_params; 1230 }; 1231 }; 1232 1233 enum dc_cm2_gpu_mem_size { 1234 DC_CM2_GPU_MEM_SIZE_171717, 1235 DC_CM2_GPU_MEM_SIZE_TRANSFORMED 1236 }; 1237 1238 struct dc_cm2_gpu_mem_parameters { 1239 struct dc_plane_address addr; 1240 enum dc_cm2_gpu_mem_layout layout; 1241 struct dc_cm2_gpu_mem_format_parameters format_params; 1242 enum dc_cm2_gpu_mem_pixel_component_order component_order; 1243 enum dc_cm2_gpu_mem_size size; 1244 }; 1245 1246 enum dc_cm2_transfer_func_source { 1247 DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM, 1248 DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM 1249 }; 1250 1251 struct dc_cm2_component_settings { 1252 enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting; 1253 bool lut1d_enable; 1254 }; 1255 1256 /* 1257 * All pointers in this struct must remain valid for as long as the 3DLUTs are used 1258 */ 1259 struct dc_cm2_func_luts { 1260 const struct dc_transfer_func *shaper; 1261 struct { 1262 enum dc_cm2_transfer_func_source lut3d_src; 1263 union { 1264 const struct dc_3dlut *lut3d_func; 1265 struct dc_cm2_gpu_mem_parameters gpu_mem_params; 1266 }; 1267 } lut3d_data; 1268 const struct dc_transfer_func *lut1d_func; 1269 }; 1270 1271 struct dc_cm2_parameters { 1272 struct dc_cm2_component_settings component_settings; 1273 struct dc_cm2_func_luts cm2_luts; 1274 }; 1275 1276 enum mall_stream_type { 1277 SUBVP_NONE, // subvp not in use 1278 SUBVP_MAIN, // subvp in use, this stream is main stream 1279 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 1280 }; 1281 1282 enum dc_power_source_type { 1283 DC_POWER_SOURCE_AC, // wall power 1284 DC_POWER_SOURCE_DC, // battery power 1285 }; 1286 1287 struct dc_state_create_params { 1288 enum dc_power_source_type power_source; 1289 }; 1290 1291 struct dc_commit_streams_params { 1292 struct dc_stream_state **streams; 1293 uint8_t stream_count; 1294 enum dc_power_source_type power_source; 1295 }; 1296 1297 #endif /* DC_TYPES_H_ */ 1298