1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #ifndef TEGRA_DC_H 8 #define TEGRA_DC_H 1 9 10 #include <linux/host1x.h> 11 12 #include <drm/drm_crtc.h> 13 14 #include "drm.h" 15 16 struct tegra_output; 17 18 #define TEGRA_DC_LEGACY_PLANES_NUM 7 19 20 struct tegra_dc_state { 21 struct drm_crtc_state base; 22 23 struct clk *clk; 24 unsigned long pclk; 25 unsigned int div; 26 27 u32 planes; 28 }; 29 30 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) 31 { 32 if (state) 33 return container_of(state, struct tegra_dc_state, base); 34 35 return NULL; 36 } 37 38 struct tegra_dc_stats { 39 unsigned long frames; 40 unsigned long vblank; 41 unsigned long underflow; 42 unsigned long overflow; 43 44 unsigned long frames_total; 45 unsigned long vblank_total; 46 unsigned long underflow_total; 47 unsigned long overflow_total; 48 }; 49 50 struct tegra_windowgroup_soc { 51 unsigned int index; 52 unsigned int dc; 53 const unsigned int *windows; 54 unsigned int num_windows; 55 }; 56 57 struct tegra_dc_soc_info { 58 bool supports_background_color; 59 bool supports_interlacing; 60 bool supports_cursor; 61 bool supports_block_linear; 62 bool supports_sector_layout; 63 bool has_legacy_blending; 64 unsigned int pitch_align; 65 bool has_powergate; 66 bool coupled_pm; 67 bool has_nvdisplay; 68 const struct tegra_windowgroup_soc *wgrps; 69 unsigned int num_wgrps; 70 const u32 *primary_formats; 71 unsigned int num_primary_formats; 72 const u32 *overlay_formats; 73 unsigned int num_overlay_formats; 74 const u64 *modifiers; 75 bool has_win_a_without_filters; 76 bool has_win_b_vfilter_mem_client; 77 bool has_win_c_without_vert_filter; 78 bool plane_tiled_memory_bandwidth_x2; 79 bool has_pll_d2_out0; 80 }; 81 82 struct tegra_dc { 83 struct host1x_client client; 84 struct host1x_syncpt *syncpt; 85 struct device *dev; 86 87 struct drm_crtc base; 88 unsigned int powergate; 89 int pipe; 90 91 struct clk *clk; 92 struct reset_control *rst; 93 void __iomem *regs; 94 int irq; 95 96 struct tegra_output *rgb; 97 struct tegra_pmc *pmc; 98 99 struct tegra_dc_stats stats; 100 struct list_head list; 101 102 struct drm_info_list *debugfs_files; 103 104 const struct tegra_dc_soc_info *soc; 105 106 bool has_opp_table; 107 108 u64 *cmu_output_lut; 109 dma_addr_t cmu_output_lut_phys; 110 }; 111 112 static inline struct tegra_dc * 113 host1x_client_to_dc(struct host1x_client *client) 114 { 115 return container_of(client, struct tegra_dc, client); 116 } 117 118 static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) 119 { 120 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; 121 } 122 123 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, 124 unsigned int offset) 125 { 126 trace_dc_writel(dc->dev, offset, value); 127 writel(value, dc->regs + (offset << 2)); 128 } 129 130 static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) 131 { 132 u32 value = readl(dc->regs + (offset << 2)); 133 134 trace_dc_readl(dc->dev, offset, value); 135 136 return value; 137 } 138 139 struct tegra_dc_window { 140 struct { 141 unsigned int x; 142 unsigned int y; 143 unsigned int w; 144 unsigned int h; 145 } src; 146 struct { 147 unsigned int x; 148 unsigned int y; 149 unsigned int w; 150 unsigned int h; 151 } dst; 152 unsigned int bits_per_pixel; 153 unsigned int stride[2]; 154 unsigned long base[3]; 155 unsigned int zpos; 156 bool reflect_x; 157 bool reflect_y; 158 159 struct tegra_bo_tiling tiling; 160 u32 format; 161 u32 swap; 162 }; 163 164 /* from dc.c */ 165 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev); 166 void tegra_dc_commit(struct tegra_dc *dc); 167 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 168 struct drm_crtc_state *crtc_state, 169 struct clk *clk, unsigned long pclk, 170 unsigned int div); 171 void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, 172 struct drm_atomic_commit *state); 173 174 /* from rgb.c */ 175 int tegra_dc_rgb_probe(struct tegra_dc *dc); 176 void tegra_dc_rgb_remove(struct tegra_dc *dc); 177 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); 178 int tegra_dc_rgb_exit(struct tegra_dc *dc); 179 180 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 181 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 182 #define SYNCPT_CNTRL_NO_STALL (1 << 8) 183 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) 184 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 185 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 186 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 187 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 188 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 189 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 190 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 191 #define DC_CMD_WIN_C_INCR_SYNCPT 0x018 192 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 193 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a 194 #define DC_CMD_CONT_SYNCPT_VSYNC 0x028 195 #define SYNCPT_VSYNC_ENABLE (1 << 8) 196 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 197 #define DC_CMD_DISPLAY_COMMAND 0x032 198 #define DISP_CTRL_MODE_STOP (0 << 5) 199 #define DISP_CTRL_MODE_C_DISPLAY (1 << 5) 200 #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) 201 #define DISP_CTRL_MODE_MASK (3 << 5) 202 #define DC_CMD_SIGNAL_RAISE 0x033 203 #define DC_CMD_DISPLAY_POWER_CONTROL 0x036 204 #define PW0_ENABLE (1 << 0) 205 #define PW1_ENABLE (1 << 2) 206 #define PW2_ENABLE (1 << 4) 207 #define PW3_ENABLE (1 << 6) 208 #define PW4_ENABLE (1 << 8) 209 #define PM0_ENABLE (1 << 16) 210 #define PM1_ENABLE (1 << 18) 211 212 #define DC_CMD_INT_STATUS 0x037 213 #define DC_CMD_INT_MASK 0x038 214 #define DC_CMD_INT_ENABLE 0x039 215 #define DC_CMD_INT_TYPE 0x03a 216 #define DC_CMD_INT_POLARITY 0x03b 217 #define CTXSW_INT (1 << 0) 218 #define FRAME_END_INT (1 << 1) 219 #define VBLANK_INT (1 << 2) 220 #define V_PULSE3_INT (1 << 4) 221 #define V_PULSE2_INT (1 << 5) 222 #define REGION_CRC_INT (1 << 6) 223 #define REG_TMOUT_INT (1 << 7) 224 #define WIN_A_UF_INT (1 << 8) 225 #define WIN_B_UF_INT (1 << 9) 226 #define WIN_C_UF_INT (1 << 10) 227 #define MSF_INT (1 << 12) 228 #define WIN_A_OF_INT (1 << 14) 229 #define WIN_B_OF_INT (1 << 15) 230 #define WIN_C_OF_INT (1 << 16) 231 #define HEAD_UF_INT (1 << 23) 232 #define SD3_BUCKET_WALK_DONE_INT (1 << 24) 233 #define DSC_OBUF_UF_INT (1 << 26) 234 #define DSC_RBUF_UF_INT (1 << 27) 235 #define DSC_BBUF_UF_INT (1 << 28) 236 #define DSC_TO_UF_INT (1 << 29) 237 238 #define DC_CMD_SIGNAL_RAISE1 0x03c 239 #define DC_CMD_SIGNAL_RAISE2 0x03d 240 #define DC_CMD_SIGNAL_RAISE3 0x03e 241 242 #define DC_CMD_STATE_ACCESS 0x040 243 #define READ_MUX (1 << 0) 244 #define WRITE_MUX (1 << 2) 245 246 #define DC_CMD_STATE_CONTROL 0x041 247 #define GENERAL_ACT_REQ (1 << 0) 248 #define WIN_A_ACT_REQ (1 << 1) 249 #define WIN_B_ACT_REQ (1 << 2) 250 #define WIN_C_ACT_REQ (1 << 3) 251 #define CURSOR_ACT_REQ (1 << 7) 252 #define GENERAL_UPDATE (1 << 8) 253 #define WIN_A_UPDATE (1 << 9) 254 #define WIN_B_UPDATE (1 << 10) 255 #define WIN_C_UPDATE (1 << 11) 256 #define CURSOR_UPDATE (1 << 15) 257 #define COMMON_ACTREQ (1 << 16) 258 #define COMMON_UPDATE (1 << 17) 259 #define NC_HOST_TRIG (1 << 24) 260 261 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 262 #define WINDOW_A_SELECT (1 << 4) 263 #define WINDOW_B_SELECT (1 << 5) 264 #define WINDOW_C_SELECT (1 << 6) 265 266 #define DC_CMD_REG_ACT_CONTROL 0x043 267 268 #define DC_COM_CRC_CONTROL 0x300 269 #define DC_COM_CRC_CONTROL_ALWAYS (1 << 3) 270 #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2) 271 #define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2) 272 #define DC_COM_CRC_CONTROL_WAIT (1 << 1) 273 #define DC_COM_CRC_CONTROL_ENABLE (1 << 0) 274 #define DC_COM_CRC_CHECKSUM 0x301 275 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) 276 #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) 277 #define LVS_OUTPUT_POLARITY_LOW (1 << 28) 278 #define LHS_OUTPUT_POLARITY_LOW (1 << 30) 279 #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x)) 280 #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x)) 281 #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x)) 282 #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x)) 283 284 #define DC_COM_PIN_MISC_CONTROL 0x31b 285 #define DC_COM_PIN_PM0_CONTROL 0x31c 286 #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d 287 #define DC_COM_PIN_PM1_CONTROL 0x31e 288 #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f 289 290 #define DC_COM_SPI_CONTROL 0x320 291 #define DC_COM_SPI_START_BYTE 0x321 292 #define DC_COM_HSPI_WRITE_DATA_AB 0x322 293 #define DC_COM_HSPI_WRITE_DATA_CD 0x323 294 #define DC_COM_HSPI_CS_DC 0x324 295 #define DC_COM_SCRATCH_REGISTER_A 0x325 296 #define DC_COM_SCRATCH_REGISTER_B 0x326 297 #define DC_COM_GPIO_CTRL 0x327 298 #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 299 #define DC_COM_CRC_CHECKSUM_LATCHED 0x329 300 301 #define DC_COM_RG_UNDERFLOW 0x365 302 #define UNDERFLOW_MODE_RED (1 << 8) 303 #define UNDERFLOW_REPORT_ENABLE (1 << 0) 304 305 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 306 #define H_PULSE0_ENABLE (1 << 8) 307 #define H_PULSE1_ENABLE (1 << 10) 308 #define H_PULSE2_ENABLE (1 << 12) 309 310 #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 311 312 #define DC_DISP_DISP_WIN_OPTIONS 0x402 313 #define HDMI_ENABLE (1 << 30) 314 #define DSI_ENABLE (1 << 29) 315 #define SOR1_TIMING_CYA (1 << 27) 316 #define CURSOR_ENABLE (1 << 16) 317 318 #define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x)))) 319 320 #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 321 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) 322 #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) 323 #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8) 324 #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0) 325 326 #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 327 #define CURSOR_DELAY(x) (((x) & 0x3f) << 24) 328 #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16) 329 #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8) 330 #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0) 331 332 #define DC_DISP_DISP_TIMING_OPTIONS 0x405 333 #define VSYNC_H_POSITION(x) ((x) & 0xfff) 334 335 #define DC_DISP_REF_TO_SYNC 0x406 336 #define DC_DISP_SYNC_WIDTH 0x407 337 #define DC_DISP_BACK_PORCH 0x408 338 #define DC_DISP_ACTIVE 0x409 339 #define DC_DISP_FRONT_PORCH 0x40a 340 #define DC_DISP_H_PULSE0_CONTROL 0x40b 341 #define DC_DISP_H_PULSE0_POSITION_A 0x40c 342 #define DC_DISP_H_PULSE0_POSITION_B 0x40d 343 #define DC_DISP_H_PULSE0_POSITION_C 0x40e 344 #define DC_DISP_H_PULSE0_POSITION_D 0x40f 345 #define DC_DISP_H_PULSE1_CONTROL 0x410 346 #define DC_DISP_H_PULSE1_POSITION_A 0x411 347 #define DC_DISP_H_PULSE1_POSITION_B 0x412 348 #define DC_DISP_H_PULSE1_POSITION_C 0x413 349 #define DC_DISP_H_PULSE1_POSITION_D 0x414 350 #define DC_DISP_H_PULSE2_CONTROL 0x415 351 #define DC_DISP_H_PULSE2_POSITION_A 0x416 352 #define DC_DISP_H_PULSE2_POSITION_B 0x417 353 #define DC_DISP_H_PULSE2_POSITION_C 0x418 354 #define DC_DISP_H_PULSE2_POSITION_D 0x419 355 #define DC_DISP_V_PULSE0_CONTROL 0x41a 356 #define DC_DISP_V_PULSE0_POSITION_A 0x41b 357 #define DC_DISP_V_PULSE0_POSITION_B 0x41c 358 #define DC_DISP_V_PULSE0_POSITION_C 0x41d 359 #define DC_DISP_V_PULSE1_CONTROL 0x41e 360 #define DC_DISP_V_PULSE1_POSITION_A 0x41f 361 #define DC_DISP_V_PULSE1_POSITION_B 0x420 362 #define DC_DISP_V_PULSE1_POSITION_C 0x421 363 #define DC_DISP_V_PULSE2_CONTROL 0x422 364 #define DC_DISP_V_PULSE2_POSITION_A 0x423 365 #define DC_DISP_V_PULSE3_CONTROL 0x424 366 #define DC_DISP_V_PULSE3_POSITION_A 0x425 367 #define DC_DISP_M0_CONTROL 0x426 368 #define DC_DISP_M1_CONTROL 0x427 369 #define DC_DISP_DI_CONTROL 0x428 370 #define DC_DISP_PP_CONTROL 0x429 371 #define DC_DISP_PP_SELECT_A 0x42a 372 #define DC_DISP_PP_SELECT_B 0x42b 373 #define DC_DISP_PP_SELECT_C 0x42c 374 #define DC_DISP_PP_SELECT_D 0x42d 375 376 #define PULSE_MODE_NORMAL (0 << 3) 377 #define PULSE_MODE_ONE_CLOCK (1 << 3) 378 #define PULSE_POLARITY_HIGH (0 << 4) 379 #define PULSE_POLARITY_LOW (1 << 4) 380 #define PULSE_QUAL_ALWAYS (0 << 6) 381 #define PULSE_QUAL_VACTIVE (2 << 6) 382 #define PULSE_QUAL_VACTIVE1 (3 << 6) 383 #define PULSE_LAST_START_A (0 << 8) 384 #define PULSE_LAST_END_A (1 << 8) 385 #define PULSE_LAST_START_B (2 << 8) 386 #define PULSE_LAST_END_B (3 << 8) 387 #define PULSE_LAST_START_C (4 << 8) 388 #define PULSE_LAST_END_C (5 << 8) 389 #define PULSE_LAST_START_D (6 << 8) 390 #define PULSE_LAST_END_D (7 << 8) 391 392 #define PULSE_START(x) (((x) & 0xfff) << 0) 393 #define PULSE_END(x) (((x) & 0xfff) << 16) 394 395 #define DC_DISP_DISP_CLOCK_CONTROL 0x42e 396 #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) 397 #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) 398 #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) 399 #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) 400 #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) 401 #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) 402 #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) 403 #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) 404 #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) 405 #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) 406 #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) 407 #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) 408 #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) 409 #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) 410 411 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f 412 #define DISP_DATA_FORMAT_DF1P1C (0 << 0) 413 #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) 414 #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) 415 #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) 416 #define DISP_DATA_FORMAT_DF2S (4 << 0) 417 #define DISP_DATA_FORMAT_DF3S (5 << 0) 418 #define DISP_DATA_FORMAT_DFSPI (6 << 0) 419 #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) 420 #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) 421 #define DISP_ALIGNMENT_MSB (0 << 8) 422 #define DISP_ALIGNMENT_LSB (1 << 8) 423 #define DISP_ORDER_RED_BLUE (0 << 9) 424 #define DISP_ORDER_BLUE_RED (1 << 9) 425 426 #define DC_DISP_DISP_COLOR_CONTROL 0x430 427 #define BASE_COLOR_SIZE666 ( 0 << 0) 428 #define BASE_COLOR_SIZE111 ( 1 << 0) 429 #define BASE_COLOR_SIZE222 ( 2 << 0) 430 #define BASE_COLOR_SIZE333 ( 3 << 0) 431 #define BASE_COLOR_SIZE444 ( 4 << 0) 432 #define BASE_COLOR_SIZE555 ( 5 << 0) 433 #define BASE_COLOR_SIZE565 ( 6 << 0) 434 #define BASE_COLOR_SIZE332 ( 7 << 0) 435 #define BASE_COLOR_SIZE888 ( 8 << 0) 436 #define BASE_COLOR_SIZE101010 (10 << 0) 437 #define BASE_COLOR_SIZE121212 (12 << 0) 438 #define DITHER_CONTROL_MASK (3 << 8) 439 #define DITHER_CONTROL_DISABLE (0 << 8) 440 #define DITHER_CONTROL_ORDERED (2 << 8) 441 #define DITHER_CONTROL_ERRDIFF (3 << 8) 442 #define BASE_COLOR_SIZE_MASK (0xf << 0) 443 #define BASE_COLOR_SIZE_666 ( 0 << 0) 444 #define BASE_COLOR_SIZE_111 ( 1 << 0) 445 #define BASE_COLOR_SIZE_222 ( 2 << 0) 446 #define BASE_COLOR_SIZE_333 ( 3 << 0) 447 #define BASE_COLOR_SIZE_444 ( 4 << 0) 448 #define BASE_COLOR_SIZE_555 ( 5 << 0) 449 #define BASE_COLOR_SIZE_565 ( 6 << 0) 450 #define BASE_COLOR_SIZE_332 ( 7 << 0) 451 #define BASE_COLOR_SIZE_888 ( 8 << 0) 452 #define BASE_COLOR_SIZE_101010 ( 10 << 0) 453 #define BASE_COLOR_SIZE_121212 ( 12 << 0) 454 #define CMU_ENABLE_ENABLE (1 << 20) 455 456 #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 457 #define SC1_H_QUALIFIER_NONE (1 << 16) 458 #define SC0_H_QUALIFIER_NONE (1 << 0) 459 460 #define DC_DISP_DATA_ENABLE_OPTIONS 0x432 461 #define DE_SELECT_ACTIVE_BLANK (0 << 0) 462 #define DE_SELECT_ACTIVE (1 << 0) 463 #define DE_SELECT_ACTIVE_IS (2 << 0) 464 #define DE_CONTROL_ONECLK (0 << 2) 465 #define DE_CONTROL_NORMAL (1 << 2) 466 #define DE_CONTROL_EARLY_EXT (2 << 2) 467 #define DE_CONTROL_EARLY (3 << 2) 468 #define DE_CONTROL_ACTIVE_BLANK (4 << 2) 469 470 #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433 471 #define DC_DISP_LCD_SPI_OPTIONS 0x434 472 #define DC_DISP_BORDER_COLOR 0x435 473 #define DC_DISP_COLOR_KEY0_LOWER 0x436 474 #define DC_DISP_COLOR_KEY0_UPPER 0x437 475 #define DC_DISP_COLOR_KEY1_LOWER 0x438 476 #define DC_DISP_COLOR_KEY1_UPPER 0x439 477 478 #define DC_DISP_CURSOR_FOREGROUND 0x43c 479 #define DC_DISP_CURSOR_BACKGROUND 0x43d 480 481 #define DC_DISP_CURSOR_START_ADDR 0x43e 482 #define CURSOR_CLIP_DISPLAY (0 << 28) 483 #define CURSOR_CLIP_WIN_A (1 << 28) 484 #define CURSOR_CLIP_WIN_B (2 << 28) 485 #define CURSOR_CLIP_WIN_C (3 << 28) 486 #define CURSOR_SIZE_32x32 (0 << 24) 487 #define CURSOR_SIZE_64x64 (1 << 24) 488 #define CURSOR_SIZE_128x128 (2 << 24) 489 #define CURSOR_SIZE_256x256 (3 << 24) 490 #define DC_DISP_CURSOR_START_ADDR_NS 0x43f 491 492 #define DC_DISP_CURSOR_POSITION 0x440 493 #define DC_DISP_CURSOR_POSITION_NS 0x441 494 495 #define DC_DISP_INIT_SEQ_CONTROL 0x442 496 #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443 497 #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444 498 #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445 499 #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446 500 501 #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 502 #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481 503 #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482 504 #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483 505 #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484 506 507 #define DC_DISP_DAC_CRT_CTRL 0x4c0 508 #define DC_DISP_DISP_MISC_CONTROL 0x4c1 509 #define DC_DISP_SD_CONTROL 0x4c2 510 #define DC_DISP_SD_CSC_COEFF 0x4c3 511 #define DC_DISP_SD_LUT(x) (0x4c4 + (x)) 512 #define DC_DISP_SD_FLICKER_CONTROL 0x4cd 513 #define DC_DISP_DC_PIXEL_COUNT 0x4ce 514 #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x)) 515 #define DC_DISP_SD_BL_PARAMETERS 0x4d7 516 #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x)) 517 #define DC_DISP_SD_BL_CONTROL 0x4dc 518 #define DC_DISP_SD_HW_K_VALUES 0x4dd 519 #define DC_DISP_SD_MAN_K_VALUES 0x4de 520 521 #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4 522 #define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24) 523 #define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16) 524 #define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8) 525 #define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0) 526 527 #define DC_DISP_INTERLACE_CONTROL 0x4e5 528 #define INTERLACE_STATUS (1 << 2) 529 #define INTERLACE_START (1 << 1) 530 #define INTERLACE_ENABLE (1 << 0) 531 532 #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec 533 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 534 #define CURSOR_COMPOSITION_MODE_BLEND (0 << 25) 535 #define CURSOR_COMPOSITION_MODE_XOR (1 << 25) 536 #define CURSOR_MODE_LEGACY (0 << 24) 537 #define CURSOR_MODE_NORMAL (1 << 24) 538 #define CURSOR_DST_BLEND_ZERO (0 << 16) 539 #define CURSOR_DST_BLEND_K1 (1 << 16) 540 #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16) 541 #define CURSOR_DST_BLEND_MASK (3 << 16) 542 #define CURSOR_SRC_BLEND_K1 (0 << 8) 543 #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8) 544 #define CURSOR_SRC_BLEND_MASK (3 << 8) 545 #define CURSOR_ALPHA 0xff 546 547 #define DC_WIN_CORE_ACT_CONTROL 0x50e 548 #define VCOUNTER (0 << 0) 549 #define HCOUNTER (1 << 0) 550 551 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543 552 #define LATENCY_CTL_MODE_ENABLE (1 << 2) 553 554 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544 555 #define WATERMARK_MASK 0x1fffffff 556 557 #define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560 558 #define PIPE_METER_INT(x) (((x) & 0xff) << 8) 559 #define PIPE_METER_FRAC(x) (((x) & 0xff) << 0) 560 561 #define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561 562 #define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0) 563 564 #define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562 565 #define SLOTS(x) (((x) & 0xff) << 0) 566 567 #define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563 568 #define MODE_TWO_LINES (0 << 14) 569 #define MODE_FOUR_LINES (1 << 14) 570 571 #define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568 572 #define THREAD_NUM_MASK (0x1f << 1) 573 #define THREAD_NUM(x) (((x) & 0x1f) << 1) 574 #define THREAD_GROUP_ENABLE (1 << 0) 575 576 #define DC_WIN_H_FILTER_P(p) (0x601 + (p)) 577 #define DC_WIN_V_FILTER_P(p) (0x619 + (p)) 578 579 #define DC_WIN_CSC_YOF 0x611 580 #define DC_WIN_CSC_KYRGB 0x612 581 #define DC_WIN_CSC_KUR 0x613 582 #define DC_WIN_CSC_KVR 0x614 583 #define DC_WIN_CSC_KUG 0x615 584 #define DC_WIN_CSC_KVG 0x616 585 #define DC_WIN_CSC_KUB 0x617 586 #define DC_WIN_CSC_KVB 0x618 587 588 #define DC_WIN_WIN_OPTIONS 0x700 589 #define H_DIRECTION (1 << 0) 590 #define V_DIRECTION (1 << 2) 591 #define COLOR_EXPAND (1 << 6) 592 #define H_FILTER (1 << 8) 593 #define V_FILTER (1 << 10) 594 #define CSC_ENABLE (1 << 18) 595 #define WIN_ENABLE (1 << 30) 596 597 #define DC_WIN_BYTE_SWAP 0x701 598 #define BYTE_SWAP_NOSWAP (0 << 0) 599 #define BYTE_SWAP_SWAP2 (1 << 0) 600 #define BYTE_SWAP_SWAP4 (2 << 0) 601 #define BYTE_SWAP_SWAP4HW (3 << 0) 602 603 #define DC_WIN_BUFFER_CONTROL 0x702 604 #define BUFFER_CONTROL_HOST (0 << 0) 605 #define BUFFER_CONTROL_VI (1 << 0) 606 #define BUFFER_CONTROL_EPP (2 << 0) 607 #define BUFFER_CONTROL_MPEGE (3 << 0) 608 #define BUFFER_CONTROL_SB2D (4 << 0) 609 610 #define DC_WIN_COLOR_DEPTH 0x703 611 #define WIN_COLOR_DEPTH_P1 0 612 #define WIN_COLOR_DEPTH_P2 1 613 #define WIN_COLOR_DEPTH_P4 2 614 #define WIN_COLOR_DEPTH_P8 3 615 #define WIN_COLOR_DEPTH_B4G4R4A4 4 616 #define WIN_COLOR_DEPTH_B5G5R5A1 5 617 #define WIN_COLOR_DEPTH_B5G6R5 6 618 #define WIN_COLOR_DEPTH_A1B5G5R5 7 619 #define WIN_COLOR_DEPTH_B8G8R8A8 12 620 #define WIN_COLOR_DEPTH_R8G8B8A8 13 621 #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14 622 #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15 623 #define WIN_COLOR_DEPTH_YCbCr422 16 624 #define WIN_COLOR_DEPTH_YUV422 17 625 #define WIN_COLOR_DEPTH_YCbCr420P 18 626 #define WIN_COLOR_DEPTH_YUV420P 19 627 #define WIN_COLOR_DEPTH_YCbCr422P 20 628 #define WIN_COLOR_DEPTH_YUV422P 21 629 #define WIN_COLOR_DEPTH_YCbCr422R 22 630 #define WIN_COLOR_DEPTH_YUV422R 23 631 #define WIN_COLOR_DEPTH_YCbCr422RA 24 632 #define WIN_COLOR_DEPTH_YUV422RA 25 633 #define WIN_COLOR_DEPTH_R4G4B4A4 27 634 #define WIN_COLOR_DEPTH_R5G5B5A 28 635 #define WIN_COLOR_DEPTH_AR5G5B5 29 636 #define WIN_COLOR_DEPTH_B5G5R5X1 30 637 #define WIN_COLOR_DEPTH_X1B5G5R5 31 638 #define WIN_COLOR_DEPTH_R5G5B5X1 32 639 #define WIN_COLOR_DEPTH_X1R5G5B5 33 640 #define WIN_COLOR_DEPTH_R5G6B5 34 641 #define WIN_COLOR_DEPTH_A8R8G8B8 35 642 #define WIN_COLOR_DEPTH_A8B8G8R8 36 643 #define WIN_COLOR_DEPTH_B8G8R8X8 37 644 #define WIN_COLOR_DEPTH_R8G8B8X8 38 645 #define WIN_COLOR_DEPTH_YCbCr444P 41 646 #define WIN_COLOR_DEPTH_YCrCb420SP 42 647 #define WIN_COLOR_DEPTH_YCbCr420SP 43 648 #define WIN_COLOR_DEPTH_YCrCb422SP 44 649 #define WIN_COLOR_DEPTH_YCbCr422SP 45 650 #define WIN_COLOR_DEPTH_YCrCb444SP 48 651 #define WIN_COLOR_DEPTH_YCbCr444SP 49 652 #define WIN_COLOR_DEPTH_X8B8G8R8 65 653 #define WIN_COLOR_DEPTH_X8R8G8B8 66 654 655 #define DC_WIN_POSITION 0x704 656 #define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ 657 #define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ 658 659 #define DC_WIN_SIZE 0x705 660 #define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ 661 #define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ 662 663 #define DC_WIN_PRESCALED_SIZE 0x706 664 #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) 665 #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ 666 667 #define DC_WIN_H_INITIAL_DDA 0x707 668 #define DC_WIN_V_INITIAL_DDA 0x708 669 #define DC_WIN_DDA_INC 0x709 670 #define H_DDA_INC(x) (((x) & 0xffff) << 0) 671 #define V_DDA_INC(x) (((x) & 0xffff) << 16) 672 673 #define DC_WIN_LINE_STRIDE 0x70a 674 #define DC_WIN_BUF_STRIDE 0x70b 675 #define DC_WIN_UV_BUF_STRIDE 0x70c 676 #define DC_WIN_BUFFER_ADDR_MODE 0x70d 677 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0) 678 #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0) 679 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16) 680 #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16) 681 682 #define DC_WIN_DV_CONTROL 0x70e 683 684 #define DC_WIN_BLEND_NOKEY 0x70f 685 #define BLEND_WEIGHT1(x) (((x) & 0xff) << 16) 686 #define BLEND_WEIGHT0(x) (((x) & 0xff) << 8) 687 688 #define DC_WIN_BLEND_1WIN 0x710 689 #define BLEND_CONTROL_FIX (0 << 2) 690 #define BLEND_CONTROL_ALPHA (1 << 2) 691 #define BLEND_COLOR_KEY_NONE (0 << 0) 692 #define BLEND_COLOR_KEY_0 (1 << 0) 693 #define BLEND_COLOR_KEY_1 (2 << 0) 694 #define BLEND_COLOR_KEY_BOTH (3 << 0) 695 696 #define DC_WIN_BLEND_2WIN_X 0x711 697 #define BLEND_CONTROL_DEPENDENT (2 << 2) 698 699 #define DC_WIN_BLEND_2WIN_Y 0x712 700 #define DC_WIN_BLEND_3WIN_XY 0x713 701 702 #define DC_WIN_HP_FETCH_CONTROL 0x714 703 704 #define DC_WINBUF_START_ADDR 0x800 705 #define DC_WINBUF_START_ADDR_NS 0x801 706 #define DC_WINBUF_START_ADDR_U 0x802 707 #define DC_WINBUF_START_ADDR_U_NS 0x803 708 #define DC_WINBUF_START_ADDR_V 0x804 709 #define DC_WINBUF_START_ADDR_V_NS 0x805 710 711 #define DC_WINBUF_ADDR_H_OFFSET 0x806 712 #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 713 #define DC_WINBUF_ADDR_V_OFFSET 0x808 714 #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 715 716 #define DC_WINBUF_UFLOW_STATUS 0x80a 717 #define DC_WINBUF_SURFACE_KIND 0x80b 718 #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0) 719 #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0) 720 #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) 721 #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) 722 723 #define DC_WINBUF_START_ADDR_HI 0x80d 724 725 #define DC_WINBUF_START_ADDR_HI_U 0x80f 726 #define DC_WINBUF_START_ADDR_HI_V 0x811 727 728 #define DC_WINBUF_CDE_CONTROL 0x82f 729 #define ENABLE_SURFACE (1 << 0) 730 731 #define DC_WINBUF_AD_UFLOW_STATUS 0xbca 732 #define DC_WINBUF_BD_UFLOW_STATUS 0xdca 733 #define DC_WINBUF_CD_UFLOW_STATUS 0xfca 734 735 /* Tegra186 and later */ 736 #define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x)) 737 #define PROTOCOL_MASK (0xf << 8) 738 #define PROTOCOL_SINGLE_TMDS_A (0x1 << 8) 739 740 #define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT 0x431 741 #define OUTPUT_LUT_MODE_MASK (3 << 5) 742 #define OUTPUT_LUT_MODE_INTERPOLATE (1 << 5) 743 #define OUTPUT_LUT_SIZE_MASK (3 << 1) 744 #define OUTPUT_LUT_SIZE_SIZE_1025 (2 << 1) 745 746 #define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE 0x432 747 #define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI 0x433 748 749 #define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR 0x442 750 #define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR 0x446 751 752 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPA 0x500 753 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPB 0x501 754 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPC 0x502 755 #define MAX_PIXELS_5TAP444(x) ((x) & 0xffff) 756 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPD 0x503 757 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPE 0x504 758 #define MAX_PIXELS_2TAP444(x) ((x) & 0xffff) 759 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPF 0x505 760 761 #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702 762 #define OWNER_MASK (0xf << 0) 763 #define OWNER(x) (((x) & 0xf) << 0) 764 765 #define DC_WIN_CROPPED_SIZE 0x706 766 767 #define DC_WIN_SET_INPUT_SCALER_H_START_PHASE 0x707 768 #define DC_WIN_SET_INPUT_SCALER_V_START_PHASE 0x708 769 770 #define DC_WIN_PLANAR_STORAGE 0x709 771 #define PITCH(x) (((x) >> 6) & 0x1fff) 772 773 #define DC_WIN_PLANAR_STORAGE_UV 0x70a 774 #define PITCH_U(x) ((((x) >> 6) & 0x1fff) << 0) 775 #define PITCH_V(x) ((((x) >> 6) & 0x1fff) << 16) 776 777 #define DC_WIN_SET_INPUT_SCALER_HPHASE_INCR 0x70b 778 #define DC_WIN_SET_INPUT_SCALER_VPHASE_INCR 0x70c 779 780 #define DC_WIN_SET_PARAMS 0x70d 781 #define CLAMP_BEFORE_BLEND (1 << 15) 782 #define DEGAMMA_NONE (0 << 13) 783 #define DEGAMMA_SRGB (1 << 13) 784 #define DEGAMMA_YUV8_10 (2 << 13) 785 #define DEGAMMA_YUV12 (3 << 13) 786 #define INPUT_RANGE_BYPASS (0 << 10) 787 #define INPUT_RANGE_LIMITED (1 << 10) 788 #define INPUT_RANGE_FULL (2 << 10) 789 #define COLOR_SPACE_RGB (0 << 8) 790 #define COLOR_SPACE_YUV_601 (1 << 8) 791 #define COLOR_SPACE_YUV_709 (2 << 8) 792 #define COLOR_SPACE_YUV_2020 (3 << 8) 793 794 #define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e 795 #define HORIZONTAL_TAPS_2 (1 << 3) 796 #define HORIZONTAL_TAPS_5 (4 << 3) 797 #define VERTICAL_TAPS_2 (1 << 0) 798 #define VERTICAL_TAPS_5 (4 << 0) 799 800 #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_COEFF 0x70f 801 #define COEFF_INDEX(x) (((x) & 0xff) << 15) 802 #define COEFF_DATA(x) (((x) & 0x3ff) << 0) 803 804 #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711 805 #define INPUT_SCALER_USE422 (1 << 2) 806 #define INPUT_SCALER_VBYPASS (1 << 1) 807 #define INPUT_SCALER_HBYPASS (1 << 0) 808 809 #define DC_WIN_BLEND_LAYER_CONTROL 0x716 810 #define COLOR_KEY_NONE (0 << 25) 811 #define COLOR_KEY_SRC (1 << 25) 812 #define COLOR_KEY_DST (2 << 25) 813 #define BLEND_BYPASS (1 << 24) 814 #define K2(x) (((x) & 0xff) << 16) 815 #define K1(x) (((x) & 0xff) << 8) 816 #define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0) 817 818 #define DC_WIN_BLEND_MATCH_SELECT 0x717 819 #define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12) 820 #define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12) 821 #define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12) 822 #define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12) 823 #define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8) 824 #define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8) 825 #define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8) 826 #define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8) 827 #define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4) 828 #define BLEND_FACTOR_DST_COLOR_ONE (1 << 4) 829 #define BLEND_FACTOR_DST_COLOR_K1 (2 << 4) 830 #define BLEND_FACTOR_DST_COLOR_K2 (3 << 4) 831 #define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4) 832 #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4) 833 #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4) 834 #define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4) 835 #define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0) 836 #define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0) 837 #define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0) 838 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0) 839 #define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0) 840 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0) 841 842 #define DC_WIN_BLEND_NOMATCH_SELECT 0x718 843 844 #define DC_WIN_PRECOMP_WGRP_PARAMS 0x724 845 #define SWAP_UV (1 << 0) 846 847 #define DC_WIN_WINDOW_SET_CONTROL 0x730 848 #define CONTROL_CSC_ENABLE (1 << 5) 849 850 #define DC_WINBUF_CROPPED_POINT 0x806 851 #define OFFSET_Y(x) (((x) & 0xffff) << 16) 852 #define OFFSET_X(x) (((x) & 0xffff) << 0) 853 854 #endif /* TEGRA_DC_H */ 855