1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SH7264 Setup
4 *
5 * Copyright (C) 2012 Renesas Electronics Europe Ltd
6 */
7 #include <linux/platform_device.h>
8 #include <linux/init.h>
9 #include <linux/serial.h>
10 #include <linux/serial_sci.h>
11 #include <linux/usb/r8a66597.h>
12 #include <linux/sh_timer.h>
13 #include <linux/io.h>
14 #include <asm/platform_early.h>
15
16 enum {
17 UNUSED = 0,
18
19 /* interrupt sources */
20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
21 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
22
23 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
24 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
25 USB, VDC3, CMT0, CMT1, BSC, WDT,
26 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
27 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
28 PWMT1, PWMT2, ADC_ADI,
29 SSIF0, SSII1, SSII2, SSII3,
30 RSPDIF,
31 IIC30, IIC31, IIC32, IIC33,
32 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
33 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
34 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
35 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
36 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
37 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
38 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
39 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
40 SIO_FIFO, RSPIC0, RSPIC1,
41 RCAN0, RCAN1, IEBC, CD_ROMD,
42 NFMC, SDHI, RTC,
43 SRCC0, SRCC1, DCOMU, OFFI, IFEI,
44
45 /* interrupt groups */
46 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
47 };
48
49 static struct intc_vect vectors[] __initdata = {
50 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
51 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
52 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
53 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
54
55 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
56 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
57 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
58 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
59
60 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
61 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
62 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
63 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
64 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
65 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
66 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
67 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
68 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
69 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
70 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
71 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
72 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
73 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
74 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
75 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
76
77 INTC_IRQ(USB, 170),
78 INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
79 INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
80 INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
81 INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
82
83 INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
84 INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
85 INTC_IRQ(MTU0_VEF, 183),
86 INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
87 INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
88 INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
89 INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
90 INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
91 INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
92 INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
93 INTC_IRQ(MTU3_TCI3V, 198),
94 INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
95 INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
96 INTC_IRQ(MTU4_TCI4V, 203),
97
98 INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
99
100 INTC_IRQ(ADC_ADI, 206),
101
102 INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
103 INTC_IRQ(SSIF0, 209),
104 INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
105 INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
106 INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
107
108 INTC_IRQ(RSPDIF, 216),
109
110 INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
111 INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
112 INTC_IRQ(IIC30, 221),
113 INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
114 INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
115 INTC_IRQ(IIC31, 226),
116 INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
117 INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
118 INTC_IRQ(IIC32, 231),
119
120 INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
121 INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
122 INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
123 INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
124 INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
125 INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
126 INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
127 INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
128 INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
129 INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
130 INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
131 INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
132 INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
133 INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
134 INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
135 INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
136
137 INTC_IRQ(SIO_FIFO, 264),
138
139 INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
140 INTC_IRQ(RSPIC0, 267),
141 INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
142 INTC_IRQ(RSPIC1, 270),
143
144 INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
145 INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
146 INTC_IRQ(RCAN0, 275),
147 INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
148 INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
149 INTC_IRQ(RCAN1, 280),
150
151 INTC_IRQ(IEBC, 281),
152
153 INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
154 INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
155 INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
156
157 INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
158 INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
159
160 INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
161 INTC_IRQ(SDHI, 294),
162
163 INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
164 INTC_IRQ(RTC, 298),
165
166 INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
167 INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
168 INTC_IRQ(SRCC0, 303),
169 INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
170 INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
171 INTC_IRQ(SRCC1, 308),
172
173 INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
174 INTC_IRQ(DCOMU, 312),
175 };
176
177 static struct intc_group groups[] __initdata = {
178 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
179 PINT4, PINT5, PINT6, PINT7),
180 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
181 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
182 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
183 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
184 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
185 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
186 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
187 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
188 };
189
190 static struct intc_prio_reg prio_registers[] __initdata = {
191 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
192 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
193 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
194 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
195 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
196 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
197 DMAC10, DMAC11 } },
198 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
199 DMAC14, DMAC15 } },
200 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
201 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
202 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU,
203 MTU2_AB, MTU2_VU } },
204 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V,
205 MTU4_ABCD, MTU4_TCI4V } },
206 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } },
207 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } },
208 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } },
209 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
210 { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
211 { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
212 { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } },
213 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
214 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
215 };
216
217 static struct intc_mask_reg mask_registers[] __initdata = {
218 { 0xfffe0808, 0, 16, /* PINTER */
219 { 0, 0, 0, 0, 0, 0, 0, 0,
220 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
221 };
222
223 static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
224 mask_registers, prio_registers, NULL);
225
226 static struct plat_sci_port scif0_platform_data = {
227 .scscr = SCSCR_REIE,
228 .type = PORT_SCIF,
229 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
230 };
231
232 static struct resource scif0_resources[] = {
233 DEFINE_RES_MEM(0xfffe8000, 0x100),
234 DEFINE_RES_IRQ(233),
235 DEFINE_RES_IRQ(234),
236 DEFINE_RES_IRQ(235),
237 DEFINE_RES_IRQ(232),
238 };
239
240 static struct platform_device scif0_device = {
241 .name = "sh-sci",
242 .id = 0,
243 .resource = scif0_resources,
244 .num_resources = ARRAY_SIZE(scif0_resources),
245 .dev = {
246 .platform_data = &scif0_platform_data,
247 },
248 };
249
250 static struct plat_sci_port scif1_platform_data = {
251 .scscr = SCSCR_REIE,
252 .type = PORT_SCIF,
253 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
254 };
255
256 static struct resource scif1_resources[] = {
257 DEFINE_RES_MEM(0xfffe8800, 0x100),
258 DEFINE_RES_IRQ(237),
259 DEFINE_RES_IRQ(238),
260 DEFINE_RES_IRQ(239),
261 DEFINE_RES_IRQ(236),
262 };
263
264 static struct platform_device scif1_device = {
265 .name = "sh-sci",
266 .id = 1,
267 .resource = scif1_resources,
268 .num_resources = ARRAY_SIZE(scif1_resources),
269 .dev = {
270 .platform_data = &scif1_platform_data,
271 },
272 };
273
274 static struct plat_sci_port scif2_platform_data = {
275 .scscr = SCSCR_REIE,
276 .type = PORT_SCIF,
277 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
278 };
279
280 static struct resource scif2_resources[] = {
281 DEFINE_RES_MEM(0xfffe9000, 0x100),
282 DEFINE_RES_IRQ(241),
283 DEFINE_RES_IRQ(242),
284 DEFINE_RES_IRQ(243),
285 DEFINE_RES_IRQ(240),
286 };
287
288 static struct platform_device scif2_device = {
289 .name = "sh-sci",
290 .id = 2,
291 .resource = scif2_resources,
292 .num_resources = ARRAY_SIZE(scif2_resources),
293 .dev = {
294 .platform_data = &scif2_platform_data,
295 },
296 };
297
298 static struct plat_sci_port scif3_platform_data = {
299 .scscr = SCSCR_REIE,
300 .type = PORT_SCIF,
301 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
302 };
303
304 static struct resource scif3_resources[] = {
305 DEFINE_RES_MEM(0xfffe9800, 0x100),
306 DEFINE_RES_IRQ(245),
307 DEFINE_RES_IRQ(246),
308 DEFINE_RES_IRQ(247),
309 DEFINE_RES_IRQ(244),
310 };
311
312 static struct platform_device scif3_device = {
313 .name = "sh-sci",
314 .id = 3,
315 .resource = scif3_resources,
316 .num_resources = ARRAY_SIZE(scif3_resources),
317 .dev = {
318 .platform_data = &scif3_platform_data,
319 },
320 };
321
322 static struct plat_sci_port scif4_platform_data = {
323 .scscr = SCSCR_REIE,
324 .type = PORT_SCIF,
325 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
326 };
327
328 static struct resource scif4_resources[] = {
329 DEFINE_RES_MEM(0xfffea000, 0x100),
330 DEFINE_RES_IRQ(249),
331 DEFINE_RES_IRQ(250),
332 DEFINE_RES_IRQ(251),
333 DEFINE_RES_IRQ(248),
334 };
335
336 static struct platform_device scif4_device = {
337 .name = "sh-sci",
338 .id = 4,
339 .resource = scif4_resources,
340 .num_resources = ARRAY_SIZE(scif4_resources),
341 .dev = {
342 .platform_data = &scif4_platform_data,
343 },
344 };
345
346 static struct plat_sci_port scif5_platform_data = {
347 .scscr = SCSCR_REIE,
348 .type = PORT_SCIF,
349 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
350 };
351
352 static struct resource scif5_resources[] = {
353 DEFINE_RES_MEM(0xfffea800, 0x100),
354 DEFINE_RES_IRQ(253),
355 DEFINE_RES_IRQ(254),
356 DEFINE_RES_IRQ(255),
357 DEFINE_RES_IRQ(252),
358 };
359
360 static struct platform_device scif5_device = {
361 .name = "sh-sci",
362 .id = 5,
363 .resource = scif5_resources,
364 .num_resources = ARRAY_SIZE(scif5_resources),
365 .dev = {
366 .platform_data = &scif5_platform_data,
367 },
368 };
369
370 static struct plat_sci_port scif6_platform_data = {
371 .scscr = SCSCR_REIE,
372 .type = PORT_SCIF,
373 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
374 };
375
376 static struct resource scif6_resources[] = {
377 DEFINE_RES_MEM(0xfffeb000, 0x100),
378 DEFINE_RES_IRQ(257),
379 DEFINE_RES_IRQ(258),
380 DEFINE_RES_IRQ(259),
381 DEFINE_RES_IRQ(256),
382 };
383
384 static struct platform_device scif6_device = {
385 .name = "sh-sci",
386 .id = 6,
387 .resource = scif6_resources,
388 .num_resources = ARRAY_SIZE(scif6_resources),
389 .dev = {
390 .platform_data = &scif6_platform_data,
391 },
392 };
393
394 static struct plat_sci_port scif7_platform_data = {
395 .scscr = SCSCR_REIE,
396 .type = PORT_SCIF,
397 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
398 };
399
400 static struct resource scif7_resources[] = {
401 DEFINE_RES_MEM(0xfffeb800, 0x100),
402 DEFINE_RES_IRQ(261),
403 DEFINE_RES_IRQ(262),
404 DEFINE_RES_IRQ(263),
405 DEFINE_RES_IRQ(260),
406 };
407
408 static struct platform_device scif7_device = {
409 .name = "sh-sci",
410 .id = 7,
411 .resource = scif7_resources,
412 .num_resources = ARRAY_SIZE(scif7_resources),
413 .dev = {
414 .platform_data = &scif7_platform_data,
415 },
416 };
417
418 static struct sh_timer_config cmt_platform_data = {
419 .channels_mask = 3,
420 };
421
422 static struct resource cmt_resources[] = {
423 DEFINE_RES_MEM(0xfffec000, 0x10),
424 DEFINE_RES_IRQ(175),
425 DEFINE_RES_IRQ(176),
426 };
427
428 static struct platform_device cmt_device = {
429 .name = "sh-cmt-16",
430 .id = 0,
431 .dev = {
432 .platform_data = &cmt_platform_data,
433 },
434 .resource = cmt_resources,
435 .num_resources = ARRAY_SIZE(cmt_resources),
436 };
437
438 static struct resource mtu2_resources[] = {
439 DEFINE_RES_MEM(0xfffe4000, 0x400),
440 DEFINE_RES_IRQ_NAMED(179, "tgi0a"),
441 DEFINE_RES_IRQ_NAMED(186, "tgi1a"),
442 };
443
444 static struct platform_device mtu2_device = {
445 .name = "sh-mtu2",
446 .id = -1,
447 .resource = mtu2_resources,
448 .num_resources = ARRAY_SIZE(mtu2_resources),
449 };
450
451 static struct resource rtc_resources[] = {
452 [0] = {
453 .start = 0xfffe6000,
454 .end = 0xfffe6000 + 0x30 - 1,
455 .flags = IORESOURCE_IO,
456 },
457 [1] = {
458 /* Shared Period/Carry/Alarm IRQ */
459 .start = 296,
460 .flags = IORESOURCE_IRQ,
461 },
462 };
463
464 static struct platform_device rtc_device = {
465 .name = "sh-rtc",
466 .id = -1,
467 .num_resources = ARRAY_SIZE(rtc_resources),
468 .resource = rtc_resources,
469 };
470
471 /* USB Host */
usb_port_power(int port,int power)472 static void usb_port_power(int port, int power)
473 {
474 __raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
475 }
476
477 static struct r8a66597_platdata r8a66597_data = {
478 .on_chip = 1,
479 .endian = 1,
480 .port_power = usb_port_power,
481 };
482
483 static struct resource r8a66597_usb_host_resources[] = {
484 [0] = {
485 .start = 0xffffc000,
486 .end = 0xffffc0e4,
487 .flags = IORESOURCE_MEM,
488 },
489 [1] = {
490 .start = 170,
491 .end = 170,
492 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
493 },
494 };
495
496 static struct platform_device r8a66597_usb_host_device = {
497 .name = "r8a66597_hcd",
498 .id = 0,
499 .dev = {
500 .dma_mask = NULL, /* not use dma */
501 .coherent_dma_mask = 0xffffffff,
502 .platform_data = &r8a66597_data,
503 },
504 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
505 .resource = r8a66597_usb_host_resources,
506 };
507
508 static struct platform_device *sh7264_devices[] __initdata = {
509 &scif0_device,
510 &scif1_device,
511 &scif2_device,
512 &scif3_device,
513 &scif4_device,
514 &scif5_device,
515 &scif6_device,
516 &scif7_device,
517 &cmt_device,
518 &mtu2_device,
519 &rtc_device,
520 &r8a66597_usb_host_device,
521 };
522
sh7264_devices_setup(void)523 static int __init sh7264_devices_setup(void)
524 {
525 return platform_add_devices(sh7264_devices,
526 ARRAY_SIZE(sh7264_devices));
527 }
528 arch_initcall(sh7264_devices_setup);
529
plat_irq_setup(void)530 void __init plat_irq_setup(void)
531 {
532 register_intc_controller(&intc_desc);
533 }
534
535 static struct platform_device *sh7264_early_devices[] __initdata = {
536 &scif0_device,
537 &scif1_device,
538 &scif2_device,
539 &scif3_device,
540 &scif4_device,
541 &scif5_device,
542 &scif6_device,
543 &scif7_device,
544 &cmt_device,
545 &mtu2_device,
546 };
547
plat_early_device_setup(void)548 void __init plat_early_device_setup(void)
549 {
550 sh_early_platform_add_devices(sh7264_early_devices,
551 ARRAY_SIZE(sh7264_early_devices));
552 }
553