1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas I3C Controller driver
4 * Copyright (C) 2023-25 Renesas Electronics Corp.
5 *
6 * TODO: IBI support, HotJoin support, Target support
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/i2c.h>
16 #include <linux/i3c/master.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/iopoll.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26 #include "../internals.h"
27
28 #define PRTS 0x00
29 #define PRTS_PRTMD BIT(0)
30
31 #define BCTL 0x14
32 #define BCTL_INCBA BIT(0)
33 #define BCTL_HJACKCTL BIT(8)
34 #define BCTL_ABT BIT(29)
35 #define BCTL_BUSE BIT(31)
36
37 #define MSDVAD 0x18
38 #define MSDVAD_MDYAD(x) FIELD_PREP(GENMASK(21, 16), x)
39 #define MSDVAD_MDYADV BIT(31)
40
41 #define RSTCTL 0x20
42 #define RSTCTL_RI3CRST BIT(0)
43 #define RSTCTL_INTLRST BIT(16)
44
45 #define INST 0x30
46
47 #define IBINCTL 0x58
48 #define IBINCTL_NRHJCTL BIT(0)
49 #define IBINCTL_NRMRCTL BIT(1)
50 #define IBINCTL_NRSIRCTL BIT(3)
51
52 #define SVCTL 0x64
53
54 #define REFCKCTL 0x70
55 #define REFCKCTL_IREFCKS(x) FIELD_PREP(GENMASK(2, 0), x)
56
57 #define STDBR 0x74
58 #define STDBR_SBRLO(cond, x) FIELD_PREP(GENMASK(7, 0), (x) >> (cond))
59 #define STDBR_SBRHO(cond, x) FIELD_PREP(GENMASK(15, 8), (x) >> (cond))
60 #define STDBR_SBRLP(x) FIELD_PREP(GENMASK(21, 16), x)
61 #define STDBR_SBRHP(x) FIELD_PREP(GENMASK(29, 24), x)
62 #define STDBR_DSBRPO BIT(31)
63
64 #define EXTBR 0x78
65 #define EXTBR_EBRLO(x) FIELD_PREP(GENMASK(7, 0), x)
66 #define EXTBR_EBRHO(x) FIELD_PREP(GENMASK(15, 8), x)
67 #define EXTBR_EBRLP(x) FIELD_PREP(GENMASK(21, 16), x)
68 #define EXTBR_EBRHP(x) FIELD_PREP(GENMASK(29, 24), x)
69
70 #define BFRECDT 0x7c
71 #define BFRECDT_FRECYC(x) FIELD_PREP(GENMASK(8, 0), x)
72
73 #define BAVLCDT 0x80
74 #define BAVLCDT_AVLCYC(x) FIELD_PREP(GENMASK(8, 0), x)
75
76 #define BIDLCDT 0x84
77 #define BIDLCDT_IDLCYC(x) FIELD_PREP(GENMASK(17, 0), x)
78
79 #define ACKCTL 0xa0
80 #define ACKCTL_ACKT BIT(1)
81 #define ACKCTL_ACKTWP BIT(2)
82
83 #define SCSTRCTL 0xa4
84 #define SCSTRCTL_ACKTWE BIT(0)
85 #define SCSTRCTL_RWE BIT(1)
86
87 #define SCSTLCTL 0xb0
88
89 #define CNDCTL 0x140
90 #define CNDCTL_STCND BIT(0)
91 #define CNDCTL_SRCND BIT(1)
92 #define CNDCTL_SPCND BIT(2)
93
94 #define NCMDQP 0x150 /* Normal Command Queue */
95 #define NCMDQP_CMD_ATTR(x) FIELD_PREP(GENMASK(2, 0), x)
96 #define NCMDQP_IMMED_XFER 0x01
97 #define NCMDQP_ADDR_ASSGN 0x02
98 #define NCMDQP_TID(x) FIELD_PREP(GENMASK(6, 3), x)
99 #define NCMDQP_CMD(x) FIELD_PREP(GENMASK(14, 7), x)
100 #define NCMDQP_CP BIT(15)
101 #define NCMDQP_DEV_INDEX(x) FIELD_PREP(GENMASK(20, 16), x)
102 #define NCMDQP_BYTE_CNT(x) FIELD_PREP(GENMASK(25, 23), x)
103 #define NCMDQP_DEV_COUNT(x) FIELD_PREP(GENMASK(29, 26), x)
104 #define NCMDQP_MODE(x) FIELD_PREP(GENMASK(28, 26), x)
105 #define NCMDQP_RNW(x) FIELD_PREP(GENMASK(29, 29), x)
106 #define NCMDQP_ROC BIT(30)
107 #define NCMDQP_TOC BIT(31)
108 #define NCMDQP_DATA_LENGTH(x) FIELD_PREP(GENMASK(31, 16), x)
109
110 #define NRSPQP 0x154 /* Normal Respone Queue */
111 #define NRSPQP_NO_ERROR 0
112 #define NRSPQP_ERROR_CRC 1
113 #define NRSPQP_ERROR_PARITY 2
114 #define NRSPQP_ERROR_FRAME 3
115 #define NRSPQP_ERROR_IBA_NACK 4
116 #define NRSPQP_ERROR_ADDRESS_NACK 5
117 #define NRSPQP_ERROR_OVER_UNDER_FLOW 6
118 #define NRSPQP_ERROR_TRANSF_ABORT 8
119 #define NRSPQP_ERROR_I2C_W_NACK_ERR 9
120 #define NRSPQP_ERROR_UNSUPPORTED 10
121 #define NRSPQP_DATA_LEN(x) FIELD_GET(GENMASK(15, 0), x)
122 #define NRSPQP_ERR_STATUS(x) FIELD_GET(GENMASK(31, 28), x)
123
124 #define NTDTBP0 0x158 /* Normal Transfer Data Buffer */
125 #define NTDTBP0_DEPTH 16
126
127 #define NQTHCTL 0x190
128 #define NQTHCTL_CMDQTH(x) FIELD_PREP(GENMASK(1, 0), x)
129 #define NQTHCTL_IBIDSSZ(x) FIELD_PREP(GENMASK(23, 16), x)
130
131 #define NTBTHCTL0 0x194
132
133 #define NRQTHCTL 0x1c0
134
135 #define BST 0x1d0
136 #define BST_STCNDDF BIT(0)
137 #define BST_SPCNDDF BIT(1)
138 #define BST_NACKDF BIT(4)
139 #define BST_TENDF BIT(8)
140
141 #define BSTE 0x1d4
142 #define BSTE_STCNDDE BIT(0)
143 #define BSTE_SPCNDDE BIT(1)
144 #define BSTE_NACKDE BIT(4)
145 #define BSTE_TENDE BIT(8)
146 #define BSTE_ALE BIT(16)
147 #define BSTE_TODE BIT(20)
148 #define BSTE_WUCNDDE BIT(24)
149 #define BSTE_ALL_FLAG (BSTE_STCNDDE | BSTE_SPCNDDE |\
150 BSTE_NACKDE | BSTE_TENDE |\
151 BSTE_ALE | BSTE_TODE | BSTE_WUCNDDE)
152
153 #define BIE 0x1d8
154 #define BIE_STCNDDIE BIT(0)
155 #define BIE_SPCNDDIE BIT(1)
156 #define BIE_NACKDIE BIT(4)
157 #define BIE_TENDIE BIT(8)
158
159 #define NTST 0x1e0
160 #define NTST_TDBEF0 BIT(0)
161 #define NTST_RDBFF0 BIT(1)
162 #define NTST_CMDQEF BIT(3)
163 #define NTST_RSPQFF BIT(4)
164 #define NTST_TABTF BIT(5)
165 #define NTST_TEF BIT(9)
166
167 #define NTSTE 0x1e4
168 #define NTSTE_TDBEE0 BIT(0)
169 #define NTSTE_RDBFE0 BIT(1)
170 #define NTSTE_IBIQEFE BIT(2)
171 #define NTSTE_CMDQEE BIT(3)
172 #define NTSTE_RSPQFE BIT(4)
173 #define NTSTE_TABTE BIT(5)
174 #define NTSTE_TEE BIT(9)
175 #define NTSTE_RSQFE BIT(20)
176 #define NTSTE_ALL_FLAG (NTSTE_TDBEE0 | NTSTE_RDBFE0 |\
177 NTSTE_IBIQEFE | NTSTE_CMDQEE |\
178 NTSTE_RSPQFE | NTSTE_TABTE |\
179 NTSTE_TEE | NTSTE_RSQFE)
180
181 #define NTIE 0x1e8
182 #define NTIE_TDBEIE0 BIT(0)
183 #define NTIE_RDBFIE0 BIT(1)
184 #define NTIE_IBIQEFIE BIT(2)
185 #define NTIE_RSPQFIE BIT(4)
186 #define NTIE_RSQFIE BIT(20)
187
188 #define BCST 0x210
189 #define BCST_BFREF BIT(0)
190
191 #define DATBAS(x) (0x224 + 0x8 * (x))
192 #define DATBAS_DVSTAD(x) FIELD_PREP(GENMASK(6, 0), x)
193 #define DATBAS_DVDYAD(x) FIELD_PREP(GENMASK(23, 16), x)
194
195 #define NDBSTLV0 0x398
196 #define NDBSTLV0_RDBLV(x) FIELD_GET(GENMASK(15, 8), x)
197
198 #define RENESAS_I3C_MAX_DEVS 8
199 #define I2C_INIT_MSG -1
200
201 #define RENESAS_I3C_TCLK_IDX 1
202
203 enum i3c_internal_state {
204 I3C_INTERNAL_STATE_DISABLED,
205 I3C_INTERNAL_STATE_CONTROLLER_IDLE,
206 I3C_INTERNAL_STATE_CONTROLLER_ENTDAA,
207 I3C_INTERNAL_STATE_CONTROLLER_SETDASA,
208 I3C_INTERNAL_STATE_CONTROLLER_WRITE,
209 I3C_INTERNAL_STATE_CONTROLLER_READ,
210 I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE,
211 I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ,
212 };
213
214 enum renesas_i3c_event {
215 I3C_COMMAND_ADDRESS_ASSIGNMENT,
216 I3C_WRITE,
217 I3C_READ,
218 I3C_COMMAND_WRITE,
219 I3C_COMMAND_READ,
220 };
221
222 struct renesas_i3c_cmd {
223 u32 cmd0;
224 u32 len;
225 const void *tx_buf;
226 u32 tx_count;
227 void *rx_buf;
228 u32 rx_count;
229 u32 err;
230 u8 rnw;
231 /* i2c xfer */
232 int i2c_bytes_left;
233 int i2c_is_last;
234 u8 *i2c_buf;
235 const struct i2c_msg *msg;
236 };
237
238 struct renesas_i3c_xfer {
239 struct list_head node;
240 struct completion comp;
241 int ret;
242 bool is_i2c_xfer;
243 unsigned int ncmds;
244 struct renesas_i3c_cmd cmds[] __counted_by(ncmds);
245 };
246
247 struct renesas_i3c_xferqueue {
248 struct list_head list;
249 struct renesas_i3c_xfer *cur;
250 /* Lock for accessing the xfer queue */
251 spinlock_t lock;
252 };
253
254 struct renesas_i3c {
255 struct i3c_master_controller base;
256 enum i3c_internal_state internal_state;
257 u16 maxdevs;
258 u32 free_pos;
259 u32 dyn_addr;
260 u32 i2c_STDBR;
261 u32 i3c_STDBR;
262 unsigned long rate;
263 u8 addrs[RENESAS_I3C_MAX_DEVS];
264 struct renesas_i3c_xferqueue xferqueue;
265 void __iomem *regs;
266 u32 *DATBASn;
267 struct clk_bulk_data *clks;
268 struct reset_control *presetn;
269 struct reset_control *tresetn;
270 u8 num_clks;
271 u8 refclk_div;
272 };
273
274 struct renesas_i3c_i2c_dev_data {
275 u8 index;
276 };
277
278 struct renesas_i3c_irq_desc {
279 const char *name;
280 irq_handler_t isr;
281 const char *desc;
282 };
283
renesas_i3c_reg_update(void __iomem * reg,u32 mask,u32 val)284 static inline void renesas_i3c_reg_update(void __iomem *reg, u32 mask, u32 val)
285 {
286 u32 data = readl(reg);
287
288 data &= ~mask;
289 data |= (val & mask);
290 writel(data, reg);
291 }
292
renesas_readl(void __iomem * base,u32 reg)293 static inline u32 renesas_readl(void __iomem *base, u32 reg)
294 {
295 return readl(base + reg);
296 }
297
renesas_writel(void __iomem * base,u32 reg,u32 val)298 static inline void renesas_writel(void __iomem *base, u32 reg, u32 val)
299 {
300 writel(val, base + reg);
301 }
302
renesas_set_bit(void __iomem * base,u32 reg,u32 val)303 static void renesas_set_bit(void __iomem *base, u32 reg, u32 val)
304 {
305 renesas_i3c_reg_update(base + reg, val, val);
306 }
307
renesas_clear_bit(void __iomem * base,u32 reg,u32 val)308 static void renesas_clear_bit(void __iomem *base, u32 reg, u32 val)
309 {
310 renesas_i3c_reg_update(base + reg, val, 0);
311 }
312
to_renesas_i3c(struct i3c_master_controller * m)313 static inline struct renesas_i3c *to_renesas_i3c(struct i3c_master_controller *m)
314 {
315 return container_of(m, struct renesas_i3c, base);
316 }
317
datbas_dvdyad_with_parity(u8 addr)318 static inline u32 datbas_dvdyad_with_parity(u8 addr)
319 {
320 return DATBAS_DVDYAD(addr | (parity8(addr) ? 0 : BIT(7)));
321 }
322
renesas_i3c_get_free_pos(struct renesas_i3c * i3c)323 static int renesas_i3c_get_free_pos(struct renesas_i3c *i3c)
324 {
325 if (!(i3c->free_pos & GENMASK(i3c->maxdevs - 1, 0)))
326 return -ENOSPC;
327
328 return ffs(i3c->free_pos) - 1;
329 }
330
renesas_i3c_get_addr_pos(struct renesas_i3c * i3c,u8 addr)331 static int renesas_i3c_get_addr_pos(struct renesas_i3c *i3c, u8 addr)
332 {
333 int pos;
334
335 for (pos = 0; pos < i3c->maxdevs; pos++) {
336 if (addr == i3c->addrs[pos])
337 return pos;
338 }
339
340 return -EINVAL;
341 }
342
renesas_i3c_alloc_xfer(struct renesas_i3c * i3c,unsigned int ncmds)343 static struct renesas_i3c_xfer *renesas_i3c_alloc_xfer(struct renesas_i3c *i3c,
344 unsigned int ncmds)
345 {
346 struct renesas_i3c_xfer *xfer;
347
348 xfer = kzalloc_flex(*xfer, cmds, ncmds);
349 if (!xfer)
350 return NULL;
351
352 INIT_LIST_HEAD(&xfer->node);
353 xfer->ncmds = ncmds;
354 xfer->ret = -ETIMEDOUT;
355
356 return xfer;
357 }
358
renesas_i3c_start_xfer_locked(struct renesas_i3c * i3c)359 static void renesas_i3c_start_xfer_locked(struct renesas_i3c *i3c)
360 {
361 struct renesas_i3c_xfer *xfer = i3c->xferqueue.cur;
362 struct renesas_i3c_cmd *cmd;
363 u32 cmd1;
364
365 if (!xfer)
366 return;
367
368 cmd = xfer->cmds;
369
370 switch (i3c->internal_state) {
371 case I3C_INTERNAL_STATE_CONTROLLER_ENTDAA:
372 case I3C_INTERNAL_STATE_CONTROLLER_SETDASA:
373 renesas_set_bit(i3c->regs, NTIE, NTIE_RSPQFIE);
374 renesas_writel(i3c->regs, NCMDQP, cmd->cmd0);
375 renesas_writel(i3c->regs, NCMDQP, 0);
376 break;
377 case I3C_INTERNAL_STATE_CONTROLLER_WRITE:
378 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE:
379 renesas_set_bit(i3c->regs, NTIE, NTIE_RSPQFIE);
380 if (cmd->len <= 4) {
381 cmd->cmd0 |= NCMDQP_CMD_ATTR(NCMDQP_IMMED_XFER);
382 cmd->cmd0 |= NCMDQP_BYTE_CNT(cmd->len);
383 cmd->tx_count = cmd->len;
384 cmd1 = cmd->len == 0 ? 0 : *(u32 *)cmd->tx_buf;
385 } else {
386 cmd1 = NCMDQP_DATA_LENGTH(cmd->len);
387 }
388 renesas_writel(i3c->regs, NCMDQP, cmd->cmd0);
389 renesas_writel(i3c->regs, NCMDQP, cmd1);
390 break;
391 case I3C_INTERNAL_STATE_CONTROLLER_READ:
392 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ:
393 renesas_set_bit(i3c->regs, NTIE, NTIE_RDBFIE0);
394 cmd1 = NCMDQP_DATA_LENGTH(cmd->len);
395 renesas_writel(i3c->regs, NCMDQP, cmd->cmd0);
396 renesas_writel(i3c->regs, NCMDQP, cmd1);
397 break;
398 default:
399 break;
400 }
401
402 /* Clear the command queue empty flag */
403 renesas_clear_bit(i3c->regs, NTST, NTST_CMDQEF);
404 }
405
renesas_i3c_dequeue_xfer_locked(struct renesas_i3c * i3c,struct renesas_i3c_xfer * xfer)406 static void renesas_i3c_dequeue_xfer_locked(struct renesas_i3c *i3c,
407 struct renesas_i3c_xfer *xfer)
408 {
409 if (i3c->xferqueue.cur == xfer)
410 i3c->xferqueue.cur = NULL;
411 else
412 list_del_init(&xfer->node);
413 }
414
renesas_i3c_dequeue_xfer(struct renesas_i3c * i3c,struct renesas_i3c_xfer * xfer)415 static void renesas_i3c_dequeue_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer)
416 {
417 scoped_guard(spinlock_irqsave, &i3c->xferqueue.lock)
418 renesas_i3c_dequeue_xfer_locked(i3c, xfer);
419 }
420
renesas_i3c_enqueue_xfer(struct renesas_i3c * i3c,struct renesas_i3c_xfer * xfer)421 static void renesas_i3c_enqueue_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer)
422 {
423 reinit_completion(&xfer->comp);
424 scoped_guard(spinlock_irqsave, &i3c->xferqueue.lock) {
425 if (i3c->xferqueue.cur) {
426 list_add_tail(&xfer->node, &i3c->xferqueue.list);
427 } else {
428 i3c->xferqueue.cur = xfer;
429 if (!xfer->is_i2c_xfer)
430 renesas_i3c_start_xfer_locked(i3c);
431 }
432 }
433 }
434
renesas_i3c_wait_xfer(struct renesas_i3c * i3c,struct renesas_i3c_xfer * xfer)435 static void renesas_i3c_wait_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer)
436 {
437 unsigned long time_left;
438
439 renesas_i3c_enqueue_xfer(i3c, xfer);
440
441 time_left = wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000));
442 if (!time_left)
443 renesas_i3c_dequeue_xfer(i3c, xfer);
444 }
445
renesas_i3c_set_prts(struct renesas_i3c * i3c,u32 val)446 static void renesas_i3c_set_prts(struct renesas_i3c *i3c, u32 val)
447 {
448 /* Required sequence according to tnrza0140ae */
449 renesas_set_bit(i3c->regs, RSTCTL, RSTCTL_INTLRST);
450 renesas_writel(i3c->regs, PRTS, val);
451 renesas_clear_bit(i3c->regs, RSTCTL, RSTCTL_INTLRST);
452 }
453
renesas_i3c_bus_enable(struct i3c_master_controller * m,bool i3c_mode)454 static void renesas_i3c_bus_enable(struct i3c_master_controller *m, bool i3c_mode)
455 {
456 struct renesas_i3c *i3c = to_renesas_i3c(m);
457
458 /* Setup either I3C or I2C protocol */
459 if (i3c_mode) {
460 renesas_i3c_set_prts(i3c, 0);
461 /* Revisit: INCBA handling, especially after I2C transfers */
462 renesas_set_bit(i3c->regs, BCTL, BCTL_HJACKCTL | BCTL_INCBA);
463 renesas_set_bit(i3c->regs, MSDVAD, MSDVAD_MDYADV);
464 renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR);
465 } else {
466 renesas_i3c_set_prts(i3c, PRTS_PRTMD);
467 renesas_writel(i3c->regs, STDBR, i3c->i2c_STDBR);
468 }
469
470 /* Enable I3C bus */
471 renesas_set_bit(i3c->regs, BCTL, BCTL_BUSE);
472 }
473
renesas_i3c_reset(struct renesas_i3c * i3c)474 static int renesas_i3c_reset(struct renesas_i3c *i3c)
475 {
476 u32 val;
477
478 renesas_writel(i3c->regs, BCTL, 0);
479 renesas_set_bit(i3c->regs, RSTCTL, RSTCTL_RI3CRST);
480
481 return read_poll_timeout(renesas_readl, val, !(val & RSTCTL_RI3CRST),
482 0, 1000, false, i3c->regs, RSTCTL);
483 }
484
renesas_i3c_hw_init(struct renesas_i3c * i3c)485 static void renesas_i3c_hw_init(struct renesas_i3c *i3c)
486 {
487 u32 val;
488
489 /* Disable Slave Mode */
490 renesas_writel(i3c->regs, SVCTL, 0);
491
492 /* Initialize Queue/Buffer threshold */
493 renesas_writel(i3c->regs, NQTHCTL, NQTHCTL_IBIDSSZ(6) |
494 NQTHCTL_CMDQTH(1));
495
496 /* The only supported configuration is two entries*/
497 renesas_writel(i3c->regs, NTBTHCTL0, 0);
498 /* Interrupt when there is one entry in the queue */
499 renesas_writel(i3c->regs, NRQTHCTL, 0);
500
501 /* Enable all Bus/Transfer Status Flags */
502 renesas_writel(i3c->regs, BSTE, BSTE_ALL_FLAG);
503 renesas_writel(i3c->regs, NTSTE, NTSTE_ALL_FLAG);
504
505 /* Interrupt enable settings */
506 renesas_writel(i3c->regs, BIE, BIE_NACKDIE | BIE_TENDIE);
507 renesas_writel(i3c->regs, NTIE, 0);
508
509 /* Clear Status register */
510 renesas_writel(i3c->regs, NTST, 0);
511 renesas_writel(i3c->regs, INST, 0);
512 renesas_writel(i3c->regs, BST, 0);
513
514 /* Hot-Join Acknowlege setting. */
515 renesas_set_bit(i3c->regs, BCTL, BCTL_HJACKCTL);
516
517 renesas_writel(i3c->regs, IBINCTL, IBINCTL_NRHJCTL | IBINCTL_NRMRCTL |
518 IBINCTL_NRSIRCTL);
519
520 renesas_writel(i3c->regs, SCSTLCTL, 0);
521 renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_ACKTWE);
522
523 /* Bus condition timing */
524 val = DIV_ROUND_UP(I3C_BUS_TBUF_MIXED_FM_MIN_NS,
525 NSEC_PER_SEC / i3c->rate);
526 renesas_writel(i3c->regs, BFRECDT, BFRECDT_FRECYC(val));
527
528 val = DIV_ROUND_UP(I3C_BUS_TAVAL_MIN_NS,
529 NSEC_PER_SEC / i3c->rate);
530 renesas_writel(i3c->regs, BAVLCDT, BAVLCDT_AVLCYC(val));
531
532 val = DIV_ROUND_UP(I3C_BUS_TIDLE_MIN_NS,
533 NSEC_PER_SEC / i3c->rate);
534 renesas_writel(i3c->regs, BIDLCDT, BIDLCDT_IDLCYC(val));
535 }
536
renesas_i3c_bus_init(struct i3c_master_controller * m)537 static int renesas_i3c_bus_init(struct i3c_master_controller *m)
538 {
539 struct renesas_i3c *i3c = to_renesas_i3c(m);
540 struct i3c_bus *bus = i3c_master_get_bus(m);
541 struct i3c_device_info info = {};
542 struct i2c_timings t;
543 u32 double_SBR;
544 int cks, pp_high_ticks, pp_low_ticks, i3c_total_ticks;
545 int od_high_ticks, od_low_ticks, i2c_total_ticks;
546 int ret;
547
548 i3c->rate = clk_get_rate(i3c->clks[RENESAS_I3C_TCLK_IDX].clk);
549 if (!i3c->rate)
550 return -EINVAL;
551
552 ret = renesas_i3c_reset(i3c);
553 if (ret)
554 return ret;
555
556 i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c);
557 i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c);
558
559 i2c_parse_fw_timings(&m->dev, &t, true);
560
561 for (cks = 0; cks < 7; cks++) {
562 /* SCL low-period calculation in Open-drain mode */
563 od_low_ticks = ((i2c_total_ticks * 6) / 10);
564
565 /* SCL clock calculation in Push-Pull mode */
566 if (bus->mode == I3C_BUS_MODE_PURE)
567 pp_high_ticks = ((i3c_total_ticks * 5) / 10);
568 else
569 pp_high_ticks = DIV_ROUND_UP(I3C_BUS_THIGH_MIXED_MAX_NS,
570 NSEC_PER_SEC / i3c->rate);
571 pp_low_ticks = i3c_total_ticks - pp_high_ticks;
572
573 if ((od_low_ticks / 2) <= 0xFF && pp_low_ticks < 0x3F)
574 break;
575
576 i2c_total_ticks /= 2;
577 i3c_total_ticks /= 2;
578 i3c->rate /= 2;
579 }
580
581 /* SCL clock period calculation in Open-drain mode */
582 if ((od_low_ticks / 2) > 0xFF || pp_low_ticks > 0x3F) {
583 dev_err(&m->dev, "invalid speed (i2c-scl = %lu Hz, i3c-scl = %lu Hz). Too slow.\n",
584 (unsigned long)bus->scl_rate.i2c, (unsigned long)bus->scl_rate.i3c);
585 return -EINVAL;
586 }
587
588 /* SCL high-period calculation in Open-drain mode */
589 od_high_ticks = i2c_total_ticks - od_low_ticks;
590
591 /* Standard Bit Rate setting */
592 double_SBR = od_low_ticks > 0xFF ? 1 : 0;
593 i3c->i3c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) |
594 STDBR_SBRLO(double_SBR, od_low_ticks) |
595 STDBR_SBRHO(double_SBR, od_high_ticks) |
596 STDBR_SBRLP(pp_low_ticks) |
597 STDBR_SBRHP(pp_high_ticks);
598
599 od_low_ticks -= t.scl_fall_ns / (NSEC_PER_SEC / i3c->rate) + 1;
600 od_high_ticks -= t.scl_rise_ns / (NSEC_PER_SEC / i3c->rate) + 1;
601 i3c->i2c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) |
602 STDBR_SBRLO(double_SBR, od_low_ticks) |
603 STDBR_SBRHO(double_SBR, od_high_ticks) |
604 STDBR_SBRLP(pp_low_ticks) |
605 STDBR_SBRHP(pp_high_ticks);
606 renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR);
607
608 /* Extended Bit Rate setting */
609 renesas_writel(i3c->regs, EXTBR, EXTBR_EBRLO(od_low_ticks) |
610 EXTBR_EBRHO(od_high_ticks) |
611 EXTBR_EBRLP(pp_low_ticks) |
612 EXTBR_EBRHP(pp_high_ticks));
613
614 renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks));
615 i3c->refclk_div = cks;
616
617 /* I3C hw init*/
618 renesas_i3c_hw_init(i3c);
619
620 ret = i3c_master_get_free_addr(m, 0);
621 if (ret < 0)
622 return ret;
623
624 i3c->dyn_addr = ret;
625 renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYAD(ret) | MSDVAD_MDYADV);
626
627 memset(&info, 0, sizeof(info));
628 info.dyn_addr = ret;
629 return i3c_master_set_info(&i3c->base, &info);
630 }
631
renesas_i3c_bus_cleanup(struct i3c_master_controller * m)632 static void renesas_i3c_bus_cleanup(struct i3c_master_controller *m)
633 {
634 struct renesas_i3c *i3c = to_renesas_i3c(m);
635
636 renesas_i3c_reset(i3c);
637 }
638
renesas_i3c_daa(struct i3c_master_controller * m)639 static int renesas_i3c_daa(struct i3c_master_controller *m)
640 {
641 struct renesas_i3c *i3c = to_renesas_i3c(m);
642 struct renesas_i3c_cmd *cmd;
643 u32 olddevs, newdevs;
644 u8 last_addr = 0, pos;
645 int ret;
646
647 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1);
648 if (!xfer)
649 return -ENOMEM;
650
651 /* Enable I3C bus. */
652 renesas_i3c_bus_enable(m, true);
653
654 olddevs = ~(i3c->free_pos);
655 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_ENTDAA;
656
657 /* Setting DATBASn registers for target devices. */
658 for (pos = 0; pos < i3c->maxdevs; pos++) {
659 if (olddevs & BIT(pos))
660 continue;
661
662 ret = i3c_master_get_free_addr(m, last_addr + 1);
663 if (ret < 0)
664 return -ENOSPC;
665
666 i3c->addrs[pos] = ret;
667 last_addr = ret;
668
669 renesas_writel(i3c->regs, DATBAS(pos), datbas_dvdyad_with_parity(ret));
670 }
671
672 init_completion(&xfer->comp);
673 cmd = xfer->cmds;
674 cmd->rx_count = 0;
675
676 ret = renesas_i3c_get_free_pos(i3c);
677 if (ret < 0)
678 return ret;
679
680 /*
681 * Setup the command descriptor to start the ENTDAA command
682 * and starting at the selected device index.
683 */
684 cmd->cmd0 = NCMDQP_CMD_ATTR(NCMDQP_ADDR_ASSGN) | NCMDQP_ROC |
685 NCMDQP_TID(I3C_COMMAND_ADDRESS_ASSIGNMENT) |
686 NCMDQP_CMD(I3C_CCC_ENTDAA) | NCMDQP_DEV_INDEX(ret) |
687 NCMDQP_DEV_COUNT(i3c->maxdevs - ret) | NCMDQP_TOC;
688
689 renesas_i3c_wait_xfer(i3c, xfer);
690
691 newdevs = GENMASK(i3c->maxdevs - cmd->rx_count - 1, 0);
692 newdevs &= ~olddevs;
693
694 for (pos = 0; pos < i3c->maxdevs; pos++) {
695 if (newdevs & BIT(pos))
696 i3c_master_add_i3c_dev_locked(m, i3c->addrs[pos]);
697 }
698
699 return 0;
700 }
701
renesas_i3c_supports_ccc_cmd(struct i3c_master_controller * m,const struct i3c_ccc_cmd * cmd)702 static bool renesas_i3c_supports_ccc_cmd(struct i3c_master_controller *m,
703 const struct i3c_ccc_cmd *cmd)
704 {
705 if (cmd->ndests > 1)
706 return false;
707
708 switch (cmd->id) {
709 case I3C_CCC_ENEC(true):
710 case I3C_CCC_ENEC(false):
711 case I3C_CCC_DISEC(true):
712 case I3C_CCC_DISEC(false):
713 case I3C_CCC_ENTAS(0, true):
714 case I3C_CCC_ENTAS(1, true):
715 case I3C_CCC_ENTAS(2, true):
716 case I3C_CCC_ENTAS(3, true):
717 case I3C_CCC_ENTAS(0, false):
718 case I3C_CCC_ENTAS(1, false):
719 case I3C_CCC_ENTAS(2, false):
720 case I3C_CCC_ENTAS(3, false):
721 case I3C_CCC_RSTDAA(true):
722 case I3C_CCC_RSTDAA(false):
723 case I3C_CCC_ENTDAA:
724 case I3C_CCC_DEFSLVS:
725 case I3C_CCC_SETMWL(true):
726 case I3C_CCC_SETMWL(false):
727 case I3C_CCC_SETMRL(true):
728 case I3C_CCC_SETMRL(false):
729 case I3C_CCC_ENTTM:
730 case I3C_CCC_SETDASA:
731 case I3C_CCC_SETNEWDA:
732 case I3C_CCC_GETMWL:
733 case I3C_CCC_GETMRL:
734 case I3C_CCC_GETPID:
735 case I3C_CCC_GETBCR:
736 case I3C_CCC_GETDCR:
737 case I3C_CCC_GETSTATUS:
738 case I3C_CCC_GETACCMST:
739 case I3C_CCC_GETMXDS:
740 return true;
741 default:
742 return false;
743 }
744 }
745
renesas_i3c_send_ccc_cmd(struct i3c_master_controller * m,struct i3c_ccc_cmd * ccc)746 static int renesas_i3c_send_ccc_cmd(struct i3c_master_controller *m,
747 struct i3c_ccc_cmd *ccc)
748 {
749 struct renesas_i3c *i3c = to_renesas_i3c(m);
750 struct renesas_i3c_xfer *xfer;
751 struct renesas_i3c_cmd *cmd;
752 int ret, pos = 0;
753
754 if (ccc->id & I3C_CCC_DIRECT) {
755 pos = renesas_i3c_get_addr_pos(i3c, ccc->dests[0].addr);
756 if (pos < 0)
757 return pos;
758 }
759
760 xfer = renesas_i3c_alloc_xfer(i3c, 1);
761 if (!xfer)
762 return -ENOMEM;
763
764 renesas_i3c_bus_enable(m, true);
765
766 init_completion(&xfer->comp);
767 cmd = xfer->cmds;
768 cmd->rnw = ccc->rnw;
769 cmd->cmd0 = 0;
770
771 /* Calculate the command descriptor. */
772 switch (ccc->id) {
773 case I3C_CCC_SETDASA:
774 renesas_writel(i3c->regs, DATBAS(pos),
775 DATBAS_DVSTAD(ccc->dests[0].addr) |
776 DATBAS_DVDYAD(*(u8 *)ccc->dests[0].payload.data >> 1));
777 cmd->cmd0 = NCMDQP_CMD_ATTR(NCMDQP_ADDR_ASSGN) | NCMDQP_ROC |
778 NCMDQP_TID(I3C_COMMAND_ADDRESS_ASSIGNMENT) |
779 NCMDQP_CMD(I3C_CCC_SETDASA) | NCMDQP_DEV_INDEX(pos) |
780 NCMDQP_DEV_COUNT(0) | NCMDQP_TOC;
781 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_SETDASA;
782 break;
783 default:
784 /* Calculate the command descriptor. */
785 cmd->cmd0 = NCMDQP_TID(I3C_COMMAND_WRITE) | NCMDQP_MODE(0) |
786 NCMDQP_RNW(ccc->rnw) | NCMDQP_CMD(ccc->id) |
787 NCMDQP_ROC | NCMDQP_TOC | NCMDQP_CP |
788 NCMDQP_DEV_INDEX(pos);
789
790 if (ccc->rnw) {
791 cmd->rx_buf = ccc->dests[0].payload.data;
792 cmd->len = ccc->dests[0].payload.len;
793 cmd->rx_count = 0;
794 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ;
795 } else {
796 cmd->tx_buf = ccc->dests[0].payload.data;
797 cmd->len = ccc->dests[0].payload.len;
798 cmd->tx_count = 0;
799 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE;
800 }
801 }
802
803 renesas_i3c_wait_xfer(i3c, xfer);
804
805 ret = xfer->ret;
806 if (ret)
807 ccc->err = I3C_ERROR_M2;
808
809 kfree(xfer);
810
811 return ret;
812 }
813
renesas_i3c_i3c_xfers(struct i3c_dev_desc * dev,struct i3c_xfer * i3c_xfers,int i3c_nxfers,enum i3c_xfer_mode mode)814 static int renesas_i3c_i3c_xfers(struct i3c_dev_desc *dev, struct i3c_xfer *i3c_xfers,
815 int i3c_nxfers, enum i3c_xfer_mode mode)
816 {
817 struct i3c_master_controller *m = i3c_dev_get_master(dev);
818 struct renesas_i3c *i3c = to_renesas_i3c(m);
819 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
820 struct renesas_i3c_xfer *xfer;
821 int i;
822
823 /* Enable I3C bus. */
824 renesas_i3c_bus_enable(m, true);
825
826 xfer = renesas_i3c_alloc_xfer(i3c, 1);
827 if (!xfer)
828 return -ENOMEM;
829
830 init_completion(&xfer->comp);
831
832 for (i = 0; i < i3c_nxfers; i++) {
833 struct renesas_i3c_cmd *cmd = xfer->cmds;
834
835 /* Calculate the Transfer Command Descriptor */
836 cmd->rnw = i3c_xfers[i].rnw;
837 cmd->cmd0 = NCMDQP_DEV_INDEX(data->index) | NCMDQP_MODE(0) |
838 NCMDQP_RNW(cmd->rnw) | NCMDQP_ROC | NCMDQP_TOC;
839
840 if (i3c_xfers[i].rnw) {
841 cmd->rx_count = 0;
842 cmd->cmd0 |= NCMDQP_TID(I3C_READ);
843 cmd->rx_buf = i3c_xfers[i].data.in;
844 cmd->len = i3c_xfers[i].len;
845 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_READ;
846 } else {
847 cmd->tx_count = 0;
848 cmd->cmd0 |= NCMDQP_TID(I3C_WRITE);
849 cmd->tx_buf = i3c_xfers[i].data.out;
850 cmd->len = i3c_xfers[i].len;
851 i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_WRITE;
852 }
853
854 if (!i3c_xfers[i].rnw && i3c_xfers[i].len > 4) {
855 i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len);
856 if (cmd->len > NTDTBP0_DEPTH * sizeof(u32))
857 renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
858 }
859
860 renesas_i3c_wait_xfer(i3c, xfer);
861 }
862
863 return 0;
864 }
865
renesas_i3c_attach_i3c_dev(struct i3c_dev_desc * dev)866 static int renesas_i3c_attach_i3c_dev(struct i3c_dev_desc *dev)
867 {
868 struct i3c_master_controller *m = i3c_dev_get_master(dev);
869 struct renesas_i3c *i3c = to_renesas_i3c(m);
870 struct renesas_i3c_i2c_dev_data *data;
871 int pos;
872
873 pos = renesas_i3c_get_free_pos(i3c);
874 if (pos < 0)
875 return pos;
876
877 data = kzalloc_obj(*data);
878 if (!data)
879 return -ENOMEM;
880
881 data->index = pos;
882 i3c->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr;
883 i3c->free_pos &= ~BIT(pos);
884
885 renesas_writel(i3c->regs, DATBAS(pos), DATBAS_DVSTAD(dev->info.static_addr) |
886 datbas_dvdyad_with_parity(i3c->addrs[pos]));
887 i3c_dev_set_master_data(dev, data);
888
889 return 0;
890 }
891
renesas_i3c_reattach_i3c_dev(struct i3c_dev_desc * dev,u8 old_dyn_addr)892 static int renesas_i3c_reattach_i3c_dev(struct i3c_dev_desc *dev,
893 u8 old_dyn_addr)
894 {
895 struct i3c_master_controller *m = i3c_dev_get_master(dev);
896 struct renesas_i3c *i3c = to_renesas_i3c(m);
897 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
898
899 i3c->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr :
900 dev->info.static_addr;
901
902 return 0;
903 }
904
renesas_i3c_detach_i3c_dev(struct i3c_dev_desc * dev)905 static void renesas_i3c_detach_i3c_dev(struct i3c_dev_desc *dev)
906 {
907 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
908 struct i3c_master_controller *m = i3c_dev_get_master(dev);
909 struct renesas_i3c *i3c = to_renesas_i3c(m);
910
911 i3c_dev_set_master_data(dev, NULL);
912 i3c->addrs[data->index] = 0;
913 i3c->free_pos |= BIT(data->index);
914 kfree(data);
915 }
916
renesas_i3c_i2c_xfers(struct i2c_dev_desc * dev,struct i2c_msg * i2c_xfers,int i2c_nxfers)917 static int renesas_i3c_i2c_xfers(struct i2c_dev_desc *dev,
918 struct i2c_msg *i2c_xfers,
919 int i2c_nxfers)
920 {
921 struct i3c_master_controller *m = i2c_dev_get_master(dev);
922 struct renesas_i3c *i3c = to_renesas_i3c(m);
923 struct renesas_i3c_cmd *cmd;
924 u8 start_bit = CNDCTL_STCND;
925 int i;
926
927 struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1);
928 if (!xfer)
929 return -ENOMEM;
930
931 if (!i2c_nxfers)
932 return 0;
933
934 renesas_i3c_bus_enable(m, false);
935
936 init_completion(&xfer->comp);
937 xfer->is_i2c_xfer = true;
938 cmd = xfer->cmds;
939
940 if (!(renesas_readl(i3c->regs, BCST) & BCST_BFREF)) {
941 cmd->err = -EBUSY;
942 return cmd->err;
943 }
944
945 renesas_writel(i3c->regs, BST, 0);
946
947 renesas_i3c_enqueue_xfer(i3c, xfer);
948
949 for (i = 0; i < i2c_nxfers; i++) {
950 cmd->i2c_bytes_left = I2C_INIT_MSG;
951 cmd->i2c_buf = i2c_xfers[i].buf;
952 cmd->msg = &i2c_xfers[i];
953 cmd->i2c_is_last = (i == i2c_nxfers - 1);
954
955 renesas_set_bit(i3c->regs, BIE, BIE_NACKDIE);
956 renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
957 renesas_set_bit(i3c->regs, BIE, BIE_STCNDDIE);
958
959 /* Issue Start condition */
960 renesas_set_bit(i3c->regs, CNDCTL, start_bit);
961
962 renesas_set_bit(i3c->regs, NTSTE, NTSTE_TDBEE0);
963
964 wait_for_completion_timeout(&xfer->comp, m->i2c.timeout);
965
966 if (cmd->err)
967 break;
968
969 start_bit = CNDCTL_SRCND;
970 }
971
972 renesas_i3c_dequeue_xfer(i3c, xfer);
973 return cmd->err;
974 }
975
renesas_i3c_attach_i2c_dev(struct i2c_dev_desc * dev)976 static int renesas_i3c_attach_i2c_dev(struct i2c_dev_desc *dev)
977 {
978 struct i3c_master_controller *m = i2c_dev_get_master(dev);
979 struct renesas_i3c *i3c = to_renesas_i3c(m);
980 struct renesas_i3c_i2c_dev_data *data;
981 int pos;
982
983 pos = renesas_i3c_get_free_pos(i3c);
984 if (pos < 0)
985 return pos;
986
987 data = kzalloc_obj(*data);
988 if (!data)
989 return -ENOMEM;
990
991 data->index = pos;
992 i3c->addrs[pos] = dev->addr;
993 i3c->free_pos &= ~BIT(pos);
994 i2c_dev_set_master_data(dev, data);
995
996 return 0;
997 }
998
renesas_i3c_detach_i2c_dev(struct i2c_dev_desc * dev)999 static void renesas_i3c_detach_i2c_dev(struct i2c_dev_desc *dev)
1000 {
1001 struct renesas_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1002 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1003 struct renesas_i3c *i3c = to_renesas_i3c(m);
1004
1005 i2c_dev_set_master_data(dev, NULL);
1006 i3c->addrs[data->index] = 0;
1007 i3c->free_pos |= BIT(data->index);
1008 kfree(data);
1009 }
1010
renesas_i3c_tx_isr(int irq,void * data)1011 static irqreturn_t renesas_i3c_tx_isr(int irq, void *data)
1012 {
1013 struct renesas_i3c *i3c = data;
1014 struct renesas_i3c_xfer *xfer;
1015 struct renesas_i3c_cmd *cmd;
1016 u8 val;
1017
1018 scoped_guard(spinlock, &i3c->xferqueue.lock) {
1019 xfer = i3c->xferqueue.cur;
1020 cmd = xfer->cmds;
1021
1022 if (xfer->is_i2c_xfer) {
1023 if (!cmd->i2c_bytes_left)
1024 return IRQ_NONE;
1025
1026 if (cmd->i2c_bytes_left != I2C_INIT_MSG) {
1027 val = *cmd->i2c_buf;
1028 cmd->i2c_buf++;
1029 cmd->i2c_bytes_left--;
1030 renesas_writel(i3c->regs, NTDTBP0, val);
1031 }
1032
1033 if (cmd->i2c_bytes_left == 0) {
1034 renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
1035 renesas_set_bit(i3c->regs, BIE, BIE_TENDIE);
1036 }
1037
1038 /* Clear the Transmit Buffer Empty status flag. */
1039 renesas_clear_bit(i3c->regs, NTST, NTST_TDBEF0);
1040 } else {
1041 i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len);
1042 }
1043 }
1044
1045 return IRQ_HANDLED;
1046 }
1047
renesas_i3c_resp_isr(int irq,void * data)1048 static irqreturn_t renesas_i3c_resp_isr(int irq, void *data)
1049 {
1050 struct renesas_i3c *i3c = data;
1051 struct renesas_i3c_xfer *xfer;
1052 struct renesas_i3c_cmd *cmd;
1053 u32 resp_descriptor = renesas_readl(i3c->regs, NRSPQP);
1054 u32 bytes_remaining = 0;
1055 u32 ntst, data_len;
1056 int ret = 0;
1057
1058 scoped_guard(spinlock, &i3c->xferqueue.lock) {
1059 xfer = i3c->xferqueue.cur;
1060 cmd = xfer->cmds;
1061
1062 /* Clear the Respone Queue Full status flag*/
1063 renesas_clear_bit(i3c->regs, NTST, NTST_RSPQFF);
1064
1065 data_len = NRSPQP_DATA_LEN(resp_descriptor);
1066
1067 switch (i3c->internal_state) {
1068 case I3C_INTERNAL_STATE_CONTROLLER_ENTDAA:
1069 cmd->rx_count = data_len;
1070 break;
1071 case I3C_INTERNAL_STATE_CONTROLLER_WRITE:
1072 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE:
1073 /* Disable the transmit IRQ if it hasn't been disabled already. */
1074 renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
1075 break;
1076 case I3C_INTERNAL_STATE_CONTROLLER_READ:
1077 case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ:
1078 if (NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) && !cmd->err)
1079 bytes_remaining = data_len - cmd->rx_count;
1080
1081 i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, bytes_remaining);
1082 renesas_clear_bit(i3c->regs, NTIE, NTIE_RDBFIE0);
1083 break;
1084 default:
1085 break;
1086 }
1087
1088 switch (NRSPQP_ERR_STATUS(resp_descriptor)) {
1089 case NRSPQP_NO_ERROR:
1090 break;
1091 case NRSPQP_ERROR_PARITY:
1092 case NRSPQP_ERROR_IBA_NACK:
1093 case NRSPQP_ERROR_TRANSF_ABORT:
1094 case NRSPQP_ERROR_CRC:
1095 case NRSPQP_ERROR_FRAME:
1096 ret = -EIO;
1097 break;
1098 case NRSPQP_ERROR_OVER_UNDER_FLOW:
1099 ret = -ENOSPC;
1100 break;
1101 case NRSPQP_ERROR_UNSUPPORTED:
1102 ret = -EOPNOTSUPP;
1103 break;
1104 case NRSPQP_ERROR_I2C_W_NACK_ERR:
1105 case NRSPQP_ERROR_ADDRESS_NACK:
1106 default:
1107 ret = -EINVAL;
1108 break;
1109 }
1110
1111 /*
1112 * If the transfer was aborted, then the abort flag must be cleared
1113 * before notifying the application that a transfer has completed.
1114 */
1115 ntst = renesas_readl(i3c->regs, NTST);
1116 if (ntst & NTST_TABTF)
1117 renesas_clear_bit(i3c->regs, BCTL, BCTL_ABT);
1118
1119 /* Clear error status flags. */
1120 renesas_clear_bit(i3c->regs, NTST, NTST_TEF | NTST_TABTF);
1121
1122 xfer->ret = ret;
1123 complete(&xfer->comp);
1124
1125 xfer = list_first_entry_or_null(&i3c->xferqueue.list,
1126 struct renesas_i3c_xfer, node);
1127 if (xfer)
1128 list_del_init(&xfer->node);
1129
1130 i3c->xferqueue.cur = xfer;
1131 }
1132
1133 return IRQ_HANDLED;
1134 }
1135
renesas_i3c_tend_isr(int irq,void * data)1136 static irqreturn_t renesas_i3c_tend_isr(int irq, void *data)
1137 {
1138 struct renesas_i3c *i3c = data;
1139 struct renesas_i3c_xfer *xfer;
1140 struct renesas_i3c_cmd *cmd;
1141
1142 scoped_guard(spinlock, &i3c->xferqueue.lock) {
1143 xfer = i3c->xferqueue.cur;
1144 cmd = xfer->cmds;
1145
1146 if (xfer->is_i2c_xfer) {
1147 if (renesas_readl(i3c->regs, BST) & BST_NACKDF) {
1148 /* We got a NACKIE */
1149 renesas_readl(i3c->regs, NTDTBP0); /* dummy read */
1150 renesas_clear_bit(i3c->regs, BST, BST_NACKDF);
1151 cmd->err = -ENXIO;
1152 } else if (cmd->i2c_bytes_left) {
1153 renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
1154 return IRQ_NONE;
1155 }
1156
1157 if (cmd->i2c_is_last || cmd->err) {
1158 renesas_clear_bit(i3c->regs, BIE, BIE_TENDIE);
1159 renesas_set_bit(i3c->regs, BIE, BIE_SPCNDDIE);
1160 renesas_set_bit(i3c->regs, CNDCTL, CNDCTL_SPCND);
1161 } else {
1162 /* Transfer is complete, but do not send STOP */
1163 renesas_clear_bit(i3c->regs, NTSTE, NTSTE_TDBEE0);
1164 renesas_clear_bit(i3c->regs, BIE, BIE_TENDIE);
1165 xfer->ret = 0;
1166 complete(&xfer->comp);
1167 }
1168 }
1169
1170 /* Clear the Transmit Buffer Empty status flag. */
1171 renesas_clear_bit(i3c->regs, BST, BST_TENDF);
1172 }
1173
1174 return IRQ_HANDLED;
1175 }
1176
renesas_i3c_rx_isr(int irq,void * data)1177 static irqreturn_t renesas_i3c_rx_isr(int irq, void *data)
1178 {
1179 struct renesas_i3c *i3c = data;
1180 struct renesas_i3c_xfer *xfer;
1181 struct renesas_i3c_cmd *cmd;
1182 int read_bytes;
1183
1184 /* If resp_isr already read the data and updated 'xfer', we can just leave */
1185 if (!(renesas_readl(i3c->regs, NTIE) & NTIE_RDBFIE0))
1186 return IRQ_NONE;
1187
1188 scoped_guard(spinlock, &i3c->xferqueue.lock) {
1189 xfer = i3c->xferqueue.cur;
1190 cmd = xfer->cmds;
1191
1192 if (xfer->is_i2c_xfer) {
1193 if (!cmd->i2c_bytes_left)
1194 return IRQ_NONE;
1195
1196 if (cmd->i2c_bytes_left == I2C_INIT_MSG) {
1197 cmd->i2c_bytes_left = cmd->msg->len;
1198 renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_RWE);
1199 renesas_readl(i3c->regs, NTDTBP0); /* dummy read */
1200 if (cmd->i2c_bytes_left == 1)
1201 renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKT | ACKCTL_ACKTWP);
1202 return IRQ_HANDLED;
1203 }
1204
1205 if (cmd->i2c_bytes_left == 1) {
1206 /* STOP must come before we set ACKCTL! */
1207 if (cmd->i2c_is_last) {
1208 renesas_set_bit(i3c->regs, BIE, BIE_SPCNDDIE);
1209 renesas_clear_bit(i3c->regs, BST, BST_SPCNDDF);
1210 renesas_set_bit(i3c->regs, CNDCTL, CNDCTL_SPCND);
1211 }
1212 renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKT | ACKCTL_ACKTWP);
1213 } else {
1214 renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKTWP);
1215 }
1216
1217 /* Reading acks the RIE interrupt */
1218 *cmd->i2c_buf = renesas_readl(i3c->regs, NTDTBP0);
1219 cmd->i2c_buf++;
1220 cmd->i2c_bytes_left--;
1221 } else {
1222 read_bytes = NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) * sizeof(u32);
1223 i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, read_bytes);
1224 cmd->rx_count = read_bytes;
1225 }
1226
1227 /* Clear the Read Buffer Full status flag. */
1228 renesas_clear_bit(i3c->regs, NTST, NTST_RDBFF0);
1229 }
1230
1231 return IRQ_HANDLED;
1232 }
1233
renesas_i3c_stop_isr(int irq,void * data)1234 static irqreturn_t renesas_i3c_stop_isr(int irq, void *data)
1235 {
1236 struct renesas_i3c *i3c = data;
1237 struct renesas_i3c_xfer *xfer;
1238
1239 scoped_guard(spinlock, &i3c->xferqueue.lock) {
1240 xfer = i3c->xferqueue.cur;
1241
1242 /* read back registers to confirm writes have fully propagated */
1243 renesas_writel(i3c->regs, BST, 0);
1244 renesas_readl(i3c->regs, BST);
1245 renesas_writel(i3c->regs, BIE, 0);
1246 renesas_clear_bit(i3c->regs, NTST, NTST_TDBEF0 | NTST_RDBFF0);
1247 renesas_clear_bit(i3c->regs, SCSTRCTL, SCSTRCTL_RWE);
1248
1249 xfer->ret = 0;
1250 complete(&xfer->comp);
1251 }
1252
1253 return IRQ_HANDLED;
1254 }
1255
renesas_i3c_start_isr(int irq,void * data)1256 static irqreturn_t renesas_i3c_start_isr(int irq, void *data)
1257 {
1258 struct renesas_i3c *i3c = data;
1259 struct renesas_i3c_xfer *xfer;
1260 struct renesas_i3c_cmd *cmd;
1261 u8 val;
1262
1263 scoped_guard(spinlock, &i3c->xferqueue.lock) {
1264 xfer = i3c->xferqueue.cur;
1265 cmd = xfer->cmds;
1266
1267 if (xfer->is_i2c_xfer) {
1268 if (!cmd->i2c_bytes_left)
1269 return IRQ_NONE;
1270
1271 if (cmd->i2c_bytes_left == I2C_INIT_MSG) {
1272 if (cmd->msg->flags & I2C_M_RD) {
1273 /* On read, switch over to receive interrupt */
1274 renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
1275 renesas_set_bit(i3c->regs, NTIE, NTIE_RDBFIE0);
1276 } else {
1277 /* On write, initialize length */
1278 cmd->i2c_bytes_left = cmd->msg->len;
1279 }
1280
1281 val = i2c_8bit_addr_from_msg(cmd->msg);
1282 renesas_writel(i3c->regs, NTDTBP0, val);
1283 }
1284 }
1285
1286 renesas_clear_bit(i3c->regs, BIE, BIE_STCNDDIE);
1287 renesas_clear_bit(i3c->regs, BST, BST_STCNDDF);
1288 }
1289
1290 return IRQ_HANDLED;
1291 }
1292
1293 static const struct i3c_master_controller_ops renesas_i3c_ops = {
1294 .bus_init = renesas_i3c_bus_init,
1295 .bus_cleanup = renesas_i3c_bus_cleanup,
1296 .attach_i3c_dev = renesas_i3c_attach_i3c_dev,
1297 .reattach_i3c_dev = renesas_i3c_reattach_i3c_dev,
1298 .detach_i3c_dev = renesas_i3c_detach_i3c_dev,
1299 .do_daa = renesas_i3c_daa,
1300 .supports_ccc_cmd = renesas_i3c_supports_ccc_cmd,
1301 .send_ccc_cmd = renesas_i3c_send_ccc_cmd,
1302 .i3c_xfers = renesas_i3c_i3c_xfers,
1303 .attach_i2c_dev = renesas_i3c_attach_i2c_dev,
1304 .detach_i2c_dev = renesas_i3c_detach_i2c_dev,
1305 .i2c_xfers = renesas_i3c_i2c_xfers,
1306 };
1307
1308 static const struct renesas_i3c_irq_desc renesas_i3c_irqs[] = {
1309 { .name = "resp", .isr = renesas_i3c_resp_isr, .desc = "i3c-resp" },
1310 { .name = "rx", .isr = renesas_i3c_rx_isr, .desc = "i3c-rx" },
1311 { .name = "tx", .isr = renesas_i3c_tx_isr, .desc = "i3c-tx" },
1312 { .name = "st", .isr = renesas_i3c_start_isr, .desc = "i3c-start" },
1313 { .name = "sp", .isr = renesas_i3c_stop_isr, .desc = "i3c-stop" },
1314 { .name = "tend", .isr = renesas_i3c_tend_isr, .desc = "i3c-tend" },
1315 { .name = "nack", .isr = renesas_i3c_tend_isr, .desc = "i3c-nack" },
1316 };
1317
renesas_i3c_probe(struct platform_device * pdev)1318 static int renesas_i3c_probe(struct platform_device *pdev)
1319 {
1320 struct renesas_i3c *i3c;
1321 int ret, i;
1322
1323 i3c = devm_kzalloc(&pdev->dev, sizeof(*i3c), GFP_KERNEL);
1324 if (!i3c)
1325 return -ENOMEM;
1326
1327 i3c->regs = devm_platform_ioremap_resource(pdev, 0);
1328 if (IS_ERR(i3c->regs))
1329 return PTR_ERR(i3c->regs);
1330
1331 ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &i3c->clks);
1332 if (ret <= RENESAS_I3C_TCLK_IDX)
1333 return dev_err_probe(&pdev->dev, ret < 0 ? ret : -EINVAL,
1334 "Failed to get clocks (need > %d, got %d)\n",
1335 RENESAS_I3C_TCLK_IDX, ret);
1336 i3c->num_clks = ret;
1337
1338 i3c->tresetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "tresetn");
1339 if (IS_ERR(i3c->tresetn))
1340 return dev_err_probe(&pdev->dev, PTR_ERR(i3c->tresetn),
1341 "Error: missing tresetn ctrl\n");
1342
1343 i3c->presetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "presetn");
1344 if (IS_ERR(i3c->presetn))
1345 return dev_err_probe(&pdev->dev, PTR_ERR(i3c->presetn),
1346 "Error: missing presetn ctrl\n");
1347
1348 spin_lock_init(&i3c->xferqueue.lock);
1349 INIT_LIST_HEAD(&i3c->xferqueue.list);
1350
1351 ret = renesas_i3c_reset(i3c);
1352 if (ret)
1353 return ret;
1354
1355 for (i = 0; i < ARRAY_SIZE(renesas_i3c_irqs); i++) {
1356 ret = platform_get_irq_byname(pdev, renesas_i3c_irqs[i].name);
1357 if (ret < 0)
1358 return ret;
1359
1360 ret = devm_request_irq(&pdev->dev, ret, renesas_i3c_irqs[i].isr,
1361 0, renesas_i3c_irqs[i].desc, i3c);
1362 if (ret)
1363 return ret;
1364 }
1365
1366 platform_set_drvdata(pdev, i3c);
1367
1368 i3c->maxdevs = RENESAS_I3C_MAX_DEVS;
1369 i3c->free_pos = GENMASK(i3c->maxdevs - 1, 0);
1370
1371 /* Allocate dynamic Device Address Table backup. */
1372 i3c->DATBASn = devm_kzalloc(&pdev->dev, sizeof(u32) * i3c->maxdevs,
1373 GFP_KERNEL);
1374 if (!i3c->DATBASn)
1375 return -ENOMEM;
1376
1377 return i3c_master_register(&i3c->base, &pdev->dev, &renesas_i3c_ops, false);
1378 }
1379
renesas_i3c_remove(struct platform_device * pdev)1380 static void renesas_i3c_remove(struct platform_device *pdev)
1381 {
1382 struct renesas_i3c *i3c = platform_get_drvdata(pdev);
1383
1384 i3c_master_unregister(&i3c->base);
1385 }
1386
renesas_i3c_suspend_noirq(struct device * dev)1387 static int renesas_i3c_suspend_noirq(struct device *dev)
1388 {
1389 struct renesas_i3c *i3c = dev_get_drvdata(dev);
1390 int i, ret;
1391
1392 i2c_mark_adapter_suspended(&i3c->base.i2c);
1393
1394 /* Store Device Address Table values. */
1395 for (i = 0; i < i3c->maxdevs; i++)
1396 i3c->DATBASn[i] = renesas_readl(i3c->regs, DATBAS(i));
1397
1398 ret = reset_control_assert(i3c->presetn);
1399 if (ret)
1400 goto err_mark_resumed;
1401
1402 ret = reset_control_assert(i3c->tresetn);
1403 if (ret)
1404 goto err_presetn;
1405
1406 clk_bulk_disable(i3c->num_clks, i3c->clks);
1407
1408 return 0;
1409
1410 err_presetn:
1411 reset_control_deassert(i3c->presetn);
1412 err_mark_resumed:
1413 i2c_mark_adapter_resumed(&i3c->base.i2c);
1414
1415 return ret;
1416 }
1417
renesas_i3c_resume_noirq(struct device * dev)1418 static int renesas_i3c_resume_noirq(struct device *dev)
1419 {
1420 struct renesas_i3c *i3c = dev_get_drvdata(dev);
1421 int i, ret;
1422
1423 ret = reset_control_deassert(i3c->presetn);
1424 if (ret)
1425 return ret;
1426
1427 ret = reset_control_deassert(i3c->tresetn);
1428 if (ret)
1429 goto err_presetn;
1430
1431 ret = clk_bulk_enable(i3c->num_clks, i3c->clks);
1432 if (ret)
1433 goto err_tresetn;
1434
1435 /* Re-store I3C registers value. */
1436 renesas_writel(i3c->regs, REFCKCTL,
1437 REFCKCTL_IREFCKS(i3c->refclk_div));
1438 renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYADV |
1439 MSDVAD_MDYAD(i3c->dyn_addr));
1440
1441 /* Restore Device Address Table values. */
1442 for (i = 0; i < i3c->maxdevs; i++)
1443 renesas_writel(i3c->regs, DATBAS(i), i3c->DATBASn[i]);
1444
1445 /* I3C hw init. */
1446 renesas_i3c_hw_init(i3c);
1447
1448 i2c_mark_adapter_resumed(&i3c->base.i2c);
1449
1450 return 0;
1451
1452 err_tresetn:
1453 reset_control_assert(i3c->tresetn);
1454 err_presetn:
1455 reset_control_assert(i3c->presetn);
1456 return ret;
1457 }
1458
1459 static const struct dev_pm_ops renesas_i3c_pm_ops = {
1460 NOIRQ_SYSTEM_SLEEP_PM_OPS(renesas_i3c_suspend_noirq,
1461 renesas_i3c_resume_noirq)
1462 };
1463
1464 static const struct of_device_id renesas_i3c_of_ids[] = {
1465 { .compatible = "renesas,r9a08g045-i3c" },
1466 { .compatible = "renesas,r9a09g047-i3c" },
1467 { /* sentinel */ },
1468 };
1469 MODULE_DEVICE_TABLE(of, renesas_i3c_of_ids);
1470
1471 static struct platform_driver renesas_i3c = {
1472 .probe = renesas_i3c_probe,
1473 .remove = renesas_i3c_remove,
1474 .driver = {
1475 .name = "renesas-i3c",
1476 .of_match_table = renesas_i3c_of_ids,
1477 .pm = pm_sleep_ptr(&renesas_i3c_pm_ops),
1478 },
1479 };
1480 module_platform_driver(renesas_i3c);
1481
1482 MODULE_AUTHOR("Wolfram Sang <wsa+renesas@sang-engineering.com>");
1483 MODULE_AUTHOR("Renesas BSP teams");
1484 MODULE_DESCRIPTION("Renesas I3C controller driver");
1485 MODULE_LICENSE("GPL");
1486