1 /* SPDX-License-Identifier: GPL-2.0-only 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. 3 * All rights reserved. 4 * 5 * tegra210_admaif.h - Tegra ADMAIF registers 6 * 7 */ 8 9 #ifndef __TEGRA_ADMAIF_H__ 10 #define __TEGRA_ADMAIF_H__ 11 12 #define TEGRA_ADMAIF_CHANNEL_REG_STRIDE 0x40 13 /* Tegra210 specific */ 14 #define TEGRA210_ADMAIF_LAST_REG 0x75f 15 #define TEGRA210_ADMAIF_CHANNEL_COUNT 10 16 #define TEGRA210_ADMAIF_RX_BASE 0x0 17 #define TEGRA210_ADMAIF_TX_BASE 0x300 18 #define TEGRA210_ADMAIF_GLOBAL_BASE 0x700 19 #define TEGRA210_ADMAIF_MAX_CHANNEL 16 20 /* Tegra186 specific */ 21 #define TEGRA186_ADMAIF_LAST_REG 0xd5f 22 #define TEGRA186_ADMAIF_CHANNEL_COUNT 20 23 #define TEGRA186_ADMAIF_RX_BASE 0x0 24 #define TEGRA186_ADMAIF_TX_BASE 0x500 25 #define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00 26 #define TEGRA186_ADMAIF_MAX_CHANNEL 16 27 /* Tegra264 specific */ 28 #define TEGRA264_ADMAIF_LAST_REG 0x205f 29 #define TEGRA264_ADMAIF_CHANNEL_COUNT 32 30 #define TEGRA264_ADMAIF_RX_BASE 0x0 31 #define TEGRA264_ADMAIF_TX_BASE 0x1000 32 #define TEGRA264_ADMAIF_GLOBAL_BASE 0x2000 33 #define TEGRA264_ADMAIF_MAX_CHANNEL 32 34 /* Global registers */ 35 #define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0 36 #define TEGRA_ADMAIF_GLOBAL_CG_0 0x8 37 #define TEGRA_ADMAIF_GLOBAL_STATUS 0x10 38 #define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20 39 #define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24 40 /* RX channel registers */ 41 #define TEGRA_ADMAIF_RX_ENABLE 0x0 42 #define TEGRA_ADMAIF_RX_SOFT_RESET 0x4 43 #define TEGRA_ADMAIF_RX_STATUS 0xc 44 #define TEGRA_ADMAIF_RX_INT_STATUS 0x10 45 #define TEGRA_ADMAIF_RX_INT_MASK 0x14 46 #define TEGRA_ADMAIF_RX_INT_SET 0x18 47 #define TEGRA_ADMAIF_RX_INT_CLEAR 0x1c 48 #define TEGRA_ADMAIF_CH_ACIF_RX_CTRL 0x20 49 #define TEGRA_ADMAIF_RX_FIFO_CTRL 0x28 50 #define TEGRA_ADMAIF_RX_FIFO_READ 0x2c 51 /* TX channel registers */ 52 #define TEGRA_ADMAIF_TX_ENABLE 0x0 53 #define TEGRA_ADMAIF_TX_SOFT_RESET 0x4 54 #define TEGRA_ADMAIF_TX_STATUS 0xc 55 #define TEGRA_ADMAIF_TX_INT_STATUS 0x10 56 #define TEGRA_ADMAIF_TX_INT_MASK 0x14 57 #define TEGRA_ADMAIF_TX_INT_SET 0x18 58 #define TEGRA_ADMAIF_TX_INT_CLEAR 0x1c 59 #define TEGRA_ADMAIF_CH_ACIF_TX_CTRL 0x20 60 #define TEGRA_ADMAIF_TX_FIFO_CTRL 0x28 61 #define TEGRA_ADMAIF_TX_FIFO_WRITE 0x2c 62 /* Bit fields */ 63 #define PACK8_EN_SHIFT 31 64 #define PACK8_EN_MASK BIT(PACK8_EN_SHIFT) 65 #define PACK8_EN BIT(PACK8_EN_SHIFT) 66 #define PACK16_EN_SHIFT 30 67 #define PACK16_EN_MASK BIT(PACK16_EN_SHIFT) 68 #define PACK16_EN BIT(PACK16_EN_SHIFT) 69 #define TX_ENABLE_SHIFT 0 70 #define TX_ENABLE_MASK BIT(TX_ENABLE_SHIFT) 71 #define TX_ENABLE BIT(TX_ENABLE_SHIFT) 72 #define RX_ENABLE_SHIFT 0 73 #define RX_ENABLE_MASK BIT(RX_ENABLE_SHIFT) 74 #define RX_ENABLE BIT(RX_ENABLE_SHIFT) 75 #define SW_RESET_MASK 1 76 #define SW_RESET 1 77 /* Default values - Tegra210 */ 78 #define TEGRA210_ADMAIF_CIF_REG_DEFAULT 0x00007700 79 #define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 80 #define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 81 #define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000208 82 #define TEGRA210_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000020b 83 #define TEGRA210_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020e 84 #define TEGRA210_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000211 85 #define TEGRA210_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000214 86 #define TEGRA210_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000217 87 #define TEGRA210_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021a 88 #define TEGRA210_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021d 89 #define TEGRA210_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 90 #define TEGRA210_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 91 #define TEGRA210_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800208 92 #define TEGRA210_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0180020b 93 #define TEGRA210_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020e 94 #define TEGRA210_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800211 95 #define TEGRA210_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800214 96 #define TEGRA210_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800217 97 #define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021a 98 #define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021d 99 /* Default values - Tegra186 */ 100 #define TEGRA186_ADMAIF_CIF_REG_DEFAULT 0x00007700 101 #define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 102 #define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 103 #define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000308 104 #define TEGRA186_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000030c 105 #define TEGRA186_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x00000210 106 #define TEGRA186_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000213 107 #define TEGRA186_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000216 108 #define TEGRA186_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000219 109 #define TEGRA186_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021c 110 #define TEGRA186_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021f 111 #define TEGRA186_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x00000222 112 #define TEGRA186_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000225 113 #define TEGRA186_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000228 114 #define TEGRA186_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x0000022b 115 #define TEGRA186_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022e 116 #define TEGRA186_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x00000231 117 #define TEGRA186_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000234 118 #define TEGRA186_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000237 119 #define TEGRA186_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x0000023a 120 #define TEGRA186_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x0000023d 121 #define TEGRA186_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 122 #define TEGRA186_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 123 #define TEGRA186_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x02000308 124 #define TEGRA186_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0200030c 125 #define TEGRA186_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x01800210 126 #define TEGRA186_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800213 127 #define TEGRA186_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800216 128 #define TEGRA186_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800219 129 #define TEGRA186_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021c 130 #define TEGRA186_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021f 131 #define TEGRA186_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x01800222 132 #define TEGRA186_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800225 133 #define TEGRA186_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800228 134 #define TEGRA186_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x0180022b 135 #define TEGRA186_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022e 136 #define TEGRA186_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x01800231 137 #define TEGRA186_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800234 138 #define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800237 139 #define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x0180023a 140 #define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x0180023d 141 /* Default values - Tegra264 */ 142 #define TEGRA264_ADMAIF_CIF_REG_DEFAULT 0x00003f00 143 #define TEGRA264_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000200 144 #define TEGRA264_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000203 145 #define TEGRA264_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000206 146 #define TEGRA264_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x00000209 147 #define TEGRA264_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020c 148 #define TEGRA264_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x0000020f 149 #define TEGRA264_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000212 150 #define TEGRA264_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000215 151 #define TEGRA264_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x00000218 152 #define TEGRA264_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021b 153 #define TEGRA264_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x0000021e 154 #define TEGRA264_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000221 155 #define TEGRA264_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000224 156 #define TEGRA264_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x00000227 157 #define TEGRA264_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022a 158 #define TEGRA264_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x0000022d 159 #define TEGRA264_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000230 160 #define TEGRA264_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000233 161 #define TEGRA264_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x00000236 162 #define TEGRA264_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x00000239 163 #define TEGRA264_ADMAIF_RX21_FIFO_CTRL_REG_DEFAULT 0x0000023c 164 #define TEGRA264_ADMAIF_RX22_FIFO_CTRL_REG_DEFAULT 0x0000023f 165 #define TEGRA264_ADMAIF_RX23_FIFO_CTRL_REG_DEFAULT 0x00000242 166 #define TEGRA264_ADMAIF_RX24_FIFO_CTRL_REG_DEFAULT 0x00000245 167 #define TEGRA264_ADMAIF_RX25_FIFO_CTRL_REG_DEFAULT 0x00000248 168 #define TEGRA264_ADMAIF_RX26_FIFO_CTRL_REG_DEFAULT 0x0000024b 169 #define TEGRA264_ADMAIF_RX27_FIFO_CTRL_REG_DEFAULT 0x0000024e 170 #define TEGRA264_ADMAIF_RX28_FIFO_CTRL_REG_DEFAULT 0x00000251 171 #define TEGRA264_ADMAIF_RX29_FIFO_CTRL_REG_DEFAULT 0x00000254 172 #define TEGRA264_ADMAIF_RX30_FIFO_CTRL_REG_DEFAULT 0x00000257 173 #define TEGRA264_ADMAIF_RX31_FIFO_CTRL_REG_DEFAULT 0x0000025a 174 #define TEGRA264_ADMAIF_RX32_FIFO_CTRL_REG_DEFAULT 0x0000025d 175 #define TEGRA264_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x01800200 176 #define TEGRA264_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x01800203 177 #define TEGRA264_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800206 178 #define TEGRA264_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x01800209 179 #define TEGRA264_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020c 180 #define TEGRA264_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x0180020f 181 #define TEGRA264_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800212 182 #define TEGRA264_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800215 183 #define TEGRA264_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x01800218 184 #define TEGRA264_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021b 185 #define TEGRA264_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x0180021e 186 #define TEGRA264_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800221 187 #define TEGRA264_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800224 188 #define TEGRA264_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x01800227 189 #define TEGRA264_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022a 190 #define TEGRA264_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x0180022d 191 #define TEGRA264_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800230 192 #define TEGRA264_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800233 193 #define TEGRA264_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x01800236 194 #define TEGRA264_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x01800239 195 #define TEGRA264_ADMAIF_TX21_FIFO_CTRL_REG_DEFAULT 0x0180023c 196 #define TEGRA264_ADMAIF_TX22_FIFO_CTRL_REG_DEFAULT 0x0180023f 197 #define TEGRA264_ADMAIF_TX23_FIFO_CTRL_REG_DEFAULT 0x01800242 198 #define TEGRA264_ADMAIF_TX24_FIFO_CTRL_REG_DEFAULT 0x01800245 199 #define TEGRA264_ADMAIF_TX25_FIFO_CTRL_REG_DEFAULT 0x01800248 200 #define TEGRA264_ADMAIF_TX26_FIFO_CTRL_REG_DEFAULT 0x0180024b 201 #define TEGRA264_ADMAIF_TX27_FIFO_CTRL_REG_DEFAULT 0x0180024e 202 #define TEGRA264_ADMAIF_TX28_FIFO_CTRL_REG_DEFAULT 0x01800251 203 #define TEGRA264_ADMAIF_TX29_FIFO_CTRL_REG_DEFAULT 0x01800254 204 #define TEGRA264_ADMAIF_TX30_FIFO_CTRL_REG_DEFAULT 0x01800257 205 #define TEGRA264_ADMAIF_TX31_FIFO_CTRL_REG_DEFAULT 0x0180025a 206 #define TEGRA264_ADMAIF_TX32_FIFO_CTRL_REG_DEFAULT 0x0180025d 207 208 enum { 209 DATA_8BIT, 210 DATA_16BIT, 211 DATA_32BIT 212 }; 213 214 enum { 215 ADMAIF_RX_PATH, 216 ADMAIF_TX_PATH, 217 ADMAIF_PATHS, 218 }; 219 220 struct tegra_admaif_soc_data { 221 const struct snd_soc_component_driver *cmpnt; 222 const struct regmap_config *regmap_conf; 223 struct snd_soc_dai_driver *dais; 224 unsigned int global_base; 225 unsigned int tx_base; 226 unsigned int rx_base; 227 unsigned int num_ch; 228 unsigned int max_stream_ch; 229 }; 230 231 struct tegra_admaif { 232 struct snd_dmaengine_dai_dma_data *capture_dma_data; 233 struct snd_dmaengine_dai_dma_data *playback_dma_data; 234 const struct tegra_admaif_soc_data *soc_data; 235 unsigned int *mono_to_stereo[ADMAIF_PATHS]; 236 unsigned int *stereo_to_mono[ADMAIF_PATHS]; 237 struct regmap *regmap; 238 struct tegra_adma_isomgr *adma_isomgr; 239 }; 240 241 #endif 242