1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/leds.h> 14 #include <linux/led-class-multicolor.h> 15 #include <linux/workqueue.h> 16 #include <net/mac80211.h> 17 18 struct rtw89_dev; 19 struct rtw89_bb_ctx; 20 struct rtw89_pci_info; 21 struct rtw89_usb_info; 22 struct rtw89_mac_gen_def; 23 struct rtw89_phy_gen_def; 24 struct rtw89_fw_blacklist; 25 struct rtw89_efuse_block_cfg; 26 struct rtw89_h2c_rf_tssi; 27 struct rtw89_fw_txpwr_track_cfg; 28 struct rtw89_phy_rfk_log_fmt; 29 struct rtw89_phy_calc_efuse_gain; 30 union rtw89_phy_sts_ie09; 31 struct rtw89_phy_sts_ie10; 32 struct rtw89_debugfs; 33 struct rtw89_regd_data; 34 struct rtw89_wow_cam_info; 35 struct rtw89_bb_wrap_data; 36 struct rtw89_fw_cmd_ofld_info; 37 38 extern const struct ieee80211_ops rtw89_ops; 39 40 #define MASKBYTE0 0xff 41 #define MASKBYTE1 0xff00 42 #define MASKBYTE2 0xff0000 43 #define MASKBYTE3 0xff000000 44 #define MASKBYTE4 0xff00000000ULL 45 #define MASKHWORD 0xffff0000 46 #define MASKLWORD 0x0000ffff 47 #define MASKDWORD 0xffffffff 48 #define RFREG_MASK 0xfffff 49 #define INV_RF_DATA 0xffffffff 50 #define BYPASS_CR_DATA 0xbabecafe 51 #define RTW89_R32_EA 0xEAEAEAEA 52 #define RTW89_R32_DEAD 0xDEADBEEF 53 54 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 55 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100) 56 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 57 #define RTW89_PS_HANG_MAX_CNT 3 58 #define CFO_TRACK_MAX_USER 64 59 #define MAX_RSSI 110 60 #define RSSI_FACTOR 1 61 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 62 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 63 #define DELTA_SWINGIDX_SIZE 30 64 65 #define RTW89_RADIOTAP_ROOM_VHT sizeof(struct ieee80211_radiotap_vht) 66 #define RTW89_RADIOTAP_ROOM_HE (sizeof(struct ieee80211_radiotap_he) + \ 67 sizeof(struct ieee80211_radiotap_he_mu)) 68 #define RTW89_RADIOTAP_ROOM_EHT \ 69 (sizeof(struct ieee80211_radiotap_tlv) + \ 70 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 71 sizeof(struct ieee80211_radiotap_tlv) + \ 72 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 73 #define RTW89_RADIOTAP_ROOM \ 74 ALIGN(max3(RTW89_RADIOTAP_ROOM_VHT, RTW89_RADIOTAP_ROOM_HE, \ 75 RTW89_RADIOTAP_ROOM_EHT), 64) 76 77 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 78 #define RTW89_HTC_VARIANT_HE 3 79 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 80 #define RTW89_HTC_VARIANT_HE_CID_OM 1 81 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 82 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 83 84 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 85 enum htc_om_channel_width { 86 HTC_OM_CHANNEL_WIDTH_20 = 0, 87 HTC_OM_CHANNEL_WIDTH_40 = 1, 88 HTC_OM_CHANNEL_WIDTH_80 = 2, 89 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 90 }; 91 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 92 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 93 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 94 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 95 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 96 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 97 98 #define RTW89_TF_PAD GENMASK(11, 0) 99 #define RTW89_TF_BASIC_USER_INFO_SZ 6 100 101 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 102 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 103 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 104 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 105 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 106 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 107 108 enum rtw89_subband { 109 RTW89_CH_2G = 0, 110 RTW89_CH_5G_BAND_1 = 1, 111 /* RTW89_CH_5G_BAND_2 = 2, unused */ 112 RTW89_CH_5G_BAND_3 = 3, 113 RTW89_CH_5G_BAND_4 = 4, 114 115 RTW89_CH_6G_BAND_IDX0, /* Low */ 116 RTW89_CH_6G_BAND_IDX1, /* Low */ 117 RTW89_CH_6G_BAND_IDX2, /* Mid */ 118 RTW89_CH_6G_BAND_IDX3, /* Mid */ 119 RTW89_CH_6G_BAND_IDX4, /* High */ 120 RTW89_CH_6G_BAND_IDX5, /* High */ 121 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 122 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 123 124 RTW89_SUBBAND_NR, 125 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 126 }; 127 128 enum rtw89_tx_comp_band { 129 RTW89_TX_COMP_BAND_2GHZ, 130 RTW89_TX_COMP_BAND_5GHZ_L, 131 RTW89_TX_COMP_BAND_5GHZ_H, 132 RTW89_TX_COMP_BAND_6GHZ_M, 133 RTW89_TX_COMP_BAND_6GHZ_UH, 134 135 RTW89_TX_COMP_BAND_NR, 136 }; 137 138 enum rtw89_gain_offset { 139 RTW89_GAIN_OFFSET_2G_CCK, 140 RTW89_GAIN_OFFSET_2G_OFDM, 141 RTW89_GAIN_OFFSET_5G_LOW, 142 RTW89_GAIN_OFFSET_5G_MID, 143 RTW89_GAIN_OFFSET_5G_HIGH, 144 RTW89_GAIN_OFFSET_6G_L0, 145 RTW89_GAIN_OFFSET_6G_L1, 146 RTW89_GAIN_OFFSET_6G_M0, 147 RTW89_GAIN_OFFSET_6G_M1, 148 RTW89_GAIN_OFFSET_6G_H0, 149 RTW89_GAIN_OFFSET_6G_H1, 150 RTW89_GAIN_OFFSET_6G_UH0, 151 RTW89_GAIN_OFFSET_6G_UH1, 152 153 RTW89_GAIN_OFFSET_NR, 154 }; 155 156 enum rtw89_hci_type { 157 RTW89_HCI_TYPE_PCIE, 158 RTW89_HCI_TYPE_USB, 159 RTW89_HCI_TYPE_SDIO, 160 161 RTW89_HCI_TYPE_NUM, 162 }; 163 164 enum rtw89_hci_dle_type { 165 RTW89_HCI_DLE_TYPE_PCIE, 166 RTW89_HCI_DLE_TYPE_USB2, 167 RTW89_HCI_DLE_TYPE_USB3, 168 RTW89_HCI_DLE_TYPE_SDIO, 169 170 RTW89_HCI_DLE_TYPE_NUM, 171 }; 172 173 enum rtw89_core_chip_id { 174 RTL8852A, 175 RTL8852B, 176 RTL8852BT, 177 RTL8852C, 178 RTL8851B, 179 RTL8922A, 180 RTL8922D, 181 }; 182 183 enum rtw89_core_chip_cid { 184 RTL8922D_CID7025 = 0x74, 185 RTL8922D_CID7090 = 0x79, 186 }; 187 188 enum rtw89_core_chip_aid { 189 RTL8922D_AID1348 = 0x1348, 190 RTL8922D_AID7060 = 0x7060, 191 RTL8922D_AID7102 = 0x7102, 192 }; 193 194 enum rtw89_chip_gen { 195 RTW89_CHIP_AX, 196 RTW89_CHIP_BE, 197 198 RTW89_CHIP_GEN_NUM, 199 }; 200 201 enum rtw89_cv { 202 CHIP_CAV, 203 CHIP_CBV, 204 CHIP_CCV, 205 CHIP_CDV, 206 CHIP_CEV, 207 CHIP_CFV, 208 CHIP_CV_MAX, 209 CHIP_CV_INVALID = CHIP_CV_MAX, 210 }; 211 212 enum rtw89_bacam_ver { 213 RTW89_BACAM_V0, 214 RTW89_BACAM_V1, 215 RTW89_BACAM_G7, 216 217 RTW89_BACAM_V0_EXT = 99, 218 }; 219 220 enum rtw89_core_tx_type { 221 RTW89_CORE_TX_TYPE_DATA, 222 RTW89_CORE_TX_TYPE_MGMT, 223 RTW89_CORE_TX_TYPE_FWCMD, 224 }; 225 226 enum rtw89_core_rx_type { 227 RTW89_CORE_RX_TYPE_WIFI = 0, 228 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 229 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 230 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 231 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 232 RTW89_CORE_RX_TYPE_SS2FW = 5, 233 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 234 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 235 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 236 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 237 RTW89_CORE_RX_TYPE_C2H = 10, 238 RTW89_CORE_RX_TYPE_CSI = 11, 239 RTW89_CORE_RX_TYPE_CQI = 12, 240 RTW89_CORE_RX_TYPE_H2C = 13, 241 RTW89_CORE_RX_TYPE_FWDL = 14, 242 }; 243 244 enum rtw89_txq_flags { 245 RTW89_TXQ_F_AMPDU = 0, 246 RTW89_TXQ_F_BLOCK_BA = 1, 247 RTW89_TXQ_F_FORBID_BA = 2, 248 249 NUM_OF_RTW89_TXQ_FLAGS, 250 }; 251 252 enum rtw89_net_type { 253 RTW89_NET_TYPE_NO_LINK = 0, 254 RTW89_NET_TYPE_AD_HOC = 1, 255 RTW89_NET_TYPE_INFRA = 2, 256 RTW89_NET_TYPE_AP_MODE = 3, 257 }; 258 259 enum rtw89_wifi_role { 260 RTW89_WIFI_ROLE_NONE, 261 RTW89_WIFI_ROLE_STATION, 262 RTW89_WIFI_ROLE_AP, 263 RTW89_WIFI_ROLE_AP_VLAN, 264 RTW89_WIFI_ROLE_ADHOC, 265 RTW89_WIFI_ROLE_ADHOC_MASTER, 266 RTW89_WIFI_ROLE_MESH_POINT, 267 RTW89_WIFI_ROLE_MONITOR, 268 RTW89_WIFI_ROLE_P2P_DEVICE, 269 RTW89_WIFI_ROLE_P2P_CLIENT, 270 RTW89_WIFI_ROLE_P2P_GO, 271 RTW89_WIFI_ROLE_NAN, 272 RTW89_WIFI_ROLE_MLME_MAX 273 }; 274 275 enum rtw89_upd_mode { 276 RTW89_ROLE_CREATE, 277 RTW89_ROLE_REMOVE, 278 RTW89_ROLE_TYPE_CHANGE, 279 RTW89_ROLE_INFO_CHANGE, 280 RTW89_ROLE_CON_DISCONN, 281 RTW89_ROLE_BAND_SW, 282 RTW89_ROLE_FW_RESTORE, 283 }; 284 285 enum rtw89_self_role { 286 RTW89_SELF_ROLE_CLIENT, 287 RTW89_SELF_ROLE_AP, 288 RTW89_SELF_ROLE_AP_CLIENT 289 }; 290 291 enum rtw89_msk_sO_el { 292 RTW89_NO_MSK, 293 RTW89_SMA, 294 RTW89_TMA, 295 RTW89_BSSID 296 }; 297 298 enum rtw89_sch_tx_sel { 299 RTW89_SCH_TX_SEL_ALL, 300 RTW89_SCH_TX_SEL_HIQ, 301 RTW89_SCH_TX_SEL_MG0, 302 RTW89_SCH_TX_SEL_MACID, 303 }; 304 305 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 306 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 307 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 308 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 309 */ 310 enum rtw89_add_cam_sec_mode { 311 RTW89_ADDR_CAM_SEC_NONE = 0, 312 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 313 RTW89_ADDR_CAM_SEC_NORMAL = 2, 314 RTW89_ADDR_CAM_SEC_4GROUP = 3, 315 }; 316 317 enum rtw89_sec_key_type { 318 RTW89_SEC_KEY_TYPE_NONE = 0, 319 RTW89_SEC_KEY_TYPE_WEP40 = 1, 320 RTW89_SEC_KEY_TYPE_WEP104 = 2, 321 RTW89_SEC_KEY_TYPE_TKIP = 3, 322 RTW89_SEC_KEY_TYPE_WAPI = 4, 323 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 324 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 325 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 326 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 327 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 328 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 329 }; 330 331 enum rtw89_port { 332 RTW89_PORT_0 = 0, 333 RTW89_PORT_1 = 1, 334 RTW89_PORT_2 = 2, 335 RTW89_PORT_3 = 3, 336 RTW89_PORT_4 = 4, 337 RTW89_PORT_NUM 338 }; 339 340 enum rtw89_band { 341 RTW89_BAND_2G = 0, 342 RTW89_BAND_5G = 1, 343 RTW89_BAND_6G = 2, 344 RTW89_BAND_NUM, 345 }; 346 347 enum rtw89_hw_rate { 348 RTW89_HW_RATE_CCK1 = 0x0, 349 RTW89_HW_RATE_CCK2 = 0x1, 350 RTW89_HW_RATE_CCK5_5 = 0x2, 351 RTW89_HW_RATE_CCK11 = 0x3, 352 RTW89_HW_RATE_OFDM6 = 0x4, 353 RTW89_HW_RATE_OFDM9 = 0x5, 354 RTW89_HW_RATE_OFDM12 = 0x6, 355 RTW89_HW_RATE_OFDM18 = 0x7, 356 RTW89_HW_RATE_OFDM24 = 0x8, 357 RTW89_HW_RATE_OFDM36 = 0x9, 358 RTW89_HW_RATE_OFDM48 = 0xA, 359 RTW89_HW_RATE_OFDM54 = 0xB, 360 RTW89_HW_RATE_MCS0 = 0x80, 361 RTW89_HW_RATE_MCS1 = 0x81, 362 RTW89_HW_RATE_MCS2 = 0x82, 363 RTW89_HW_RATE_MCS3 = 0x83, 364 RTW89_HW_RATE_MCS4 = 0x84, 365 RTW89_HW_RATE_MCS5 = 0x85, 366 RTW89_HW_RATE_MCS6 = 0x86, 367 RTW89_HW_RATE_MCS7 = 0x87, 368 RTW89_HW_RATE_MCS8 = 0x88, 369 RTW89_HW_RATE_MCS9 = 0x89, 370 RTW89_HW_RATE_MCS10 = 0x8A, 371 RTW89_HW_RATE_MCS11 = 0x8B, 372 RTW89_HW_RATE_MCS12 = 0x8C, 373 RTW89_HW_RATE_MCS13 = 0x8D, 374 RTW89_HW_RATE_MCS14 = 0x8E, 375 RTW89_HW_RATE_MCS15 = 0x8F, 376 RTW89_HW_RATE_MCS16 = 0x90, 377 RTW89_HW_RATE_MCS17 = 0x91, 378 RTW89_HW_RATE_MCS18 = 0x92, 379 RTW89_HW_RATE_MCS19 = 0x93, 380 RTW89_HW_RATE_MCS20 = 0x94, 381 RTW89_HW_RATE_MCS21 = 0x95, 382 RTW89_HW_RATE_MCS22 = 0x96, 383 RTW89_HW_RATE_MCS23 = 0x97, 384 RTW89_HW_RATE_MCS24 = 0x98, 385 RTW89_HW_RATE_MCS25 = 0x99, 386 RTW89_HW_RATE_MCS26 = 0x9A, 387 RTW89_HW_RATE_MCS27 = 0x9B, 388 RTW89_HW_RATE_MCS28 = 0x9C, 389 RTW89_HW_RATE_MCS29 = 0x9D, 390 RTW89_HW_RATE_MCS30 = 0x9E, 391 RTW89_HW_RATE_MCS31 = 0x9F, 392 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 393 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 394 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 395 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 396 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 397 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 398 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 399 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 400 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 401 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 402 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 403 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 404 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 405 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 406 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 407 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 408 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 409 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 410 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 411 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 412 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 413 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 414 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 415 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 416 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 417 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 418 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 419 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 420 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 421 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 422 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 423 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 424 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 425 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 426 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 427 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 428 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 429 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 430 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 431 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 432 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 433 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 434 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 435 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 436 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 437 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 438 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 439 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 440 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 441 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 442 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 443 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 444 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 445 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 446 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 447 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 448 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 449 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 450 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 451 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 452 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 453 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 454 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 455 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 456 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 457 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 458 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 459 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 460 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 461 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 462 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 463 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 464 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 465 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 466 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 467 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 468 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 469 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 470 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 471 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 472 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 473 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 474 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 475 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 476 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 477 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 478 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 479 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 480 481 RTW89_HW_RATE_V1_MCS0 = 0x100, 482 RTW89_HW_RATE_V1_MCS1 = 0x101, 483 RTW89_HW_RATE_V1_MCS2 = 0x102, 484 RTW89_HW_RATE_V1_MCS3 = 0x103, 485 RTW89_HW_RATE_V1_MCS4 = 0x104, 486 RTW89_HW_RATE_V1_MCS5 = 0x105, 487 RTW89_HW_RATE_V1_MCS6 = 0x106, 488 RTW89_HW_RATE_V1_MCS7 = 0x107, 489 RTW89_HW_RATE_V1_MCS8 = 0x108, 490 RTW89_HW_RATE_V1_MCS9 = 0x109, 491 RTW89_HW_RATE_V1_MCS10 = 0x10A, 492 RTW89_HW_RATE_V1_MCS11 = 0x10B, 493 RTW89_HW_RATE_V1_MCS12 = 0x10C, 494 RTW89_HW_RATE_V1_MCS13 = 0x10D, 495 RTW89_HW_RATE_V1_MCS14 = 0x10E, 496 RTW89_HW_RATE_V1_MCS15 = 0x10F, 497 RTW89_HW_RATE_V1_MCS16 = 0x110, 498 RTW89_HW_RATE_V1_MCS17 = 0x111, 499 RTW89_HW_RATE_V1_MCS18 = 0x112, 500 RTW89_HW_RATE_V1_MCS19 = 0x113, 501 RTW89_HW_RATE_V1_MCS20 = 0x114, 502 RTW89_HW_RATE_V1_MCS21 = 0x115, 503 RTW89_HW_RATE_V1_MCS22 = 0x116, 504 RTW89_HW_RATE_V1_MCS23 = 0x117, 505 RTW89_HW_RATE_V1_MCS24 = 0x118, 506 RTW89_HW_RATE_V1_MCS25 = 0x119, 507 RTW89_HW_RATE_V1_MCS26 = 0x11A, 508 RTW89_HW_RATE_V1_MCS27 = 0x11B, 509 RTW89_HW_RATE_V1_MCS28 = 0x11C, 510 RTW89_HW_RATE_V1_MCS29 = 0x11D, 511 RTW89_HW_RATE_V1_MCS30 = 0x11E, 512 RTW89_HW_RATE_V1_MCS31 = 0x11F, 513 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 514 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 515 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 516 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 517 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 518 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 519 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 520 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 521 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 522 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 523 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 524 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 525 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 526 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 527 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 528 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 529 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 530 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 531 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 532 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 533 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 534 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 535 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 536 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 537 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 538 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 539 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 540 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 541 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 542 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 543 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 544 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 545 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 546 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 547 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 548 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 549 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 550 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 551 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 552 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 553 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 554 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 555 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 556 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 557 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 558 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 559 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 560 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 561 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 562 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 563 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 564 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 565 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 566 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 567 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 568 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 569 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 570 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 571 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 572 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 573 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 574 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 575 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 576 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 577 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 578 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 579 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 580 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 581 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 582 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 583 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 584 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 585 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 586 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 587 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 588 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 589 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 590 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 591 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 592 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 593 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 594 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 595 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 596 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 597 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 598 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 599 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 600 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 601 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 602 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 603 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 604 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 605 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 606 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 607 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 608 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 609 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 610 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 611 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 612 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 613 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 614 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 615 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 616 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 617 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 618 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 619 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 620 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 621 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 622 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 623 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 624 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 625 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 626 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 627 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 628 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 629 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 630 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 631 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 632 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 633 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 634 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 635 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 636 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 637 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 638 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 639 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 640 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 641 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 642 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 643 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 644 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 645 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 646 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 647 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 648 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 649 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 650 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 651 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 652 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 653 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 654 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 655 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 656 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 657 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 658 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 659 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 660 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 661 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 662 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 663 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 664 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 665 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 666 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 667 668 RTW89_HW_RATE_NR, 669 RTW89_HW_RATE_INVAL, 670 671 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 672 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 673 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 674 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 675 }; 676 677 /* 2G channels, 678 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 679 */ 680 #define RTW89_2G_CH_NUM 14 681 682 /* 5G channels, 683 * 36, 38, 40, 42, 44, 46, 48, 50, 684 * 52, 54, 56, 58, 60, 62, 64, 685 * 100, 102, 104, 106, 108, 110, 112, 114, 686 * 116, 118, 120, 122, 124, 126, 128, 130, 687 * 132, 134, 136, 138, 140, 142, 144, 688 * 149, 151, 153, 155, 157, 159, 161, 163, 689 * 165, 167, 169, 171, 173, 175, 177 690 */ 691 #define RTW89_5G_CH_NUM 53 692 693 /* 6G channels, 694 * 1, 3, 5, 7, 9, 11, 13, 15, 695 * 17, 19, 21, 23, 25, 27, 29, 33, 696 * 35, 37, 39, 41, 43, 45, 47, 49, 697 * 51, 53, 55, 57, 59, 61, 65, 67, 698 * 69, 71, 73, 75, 77, 79, 81, 83, 699 * 85, 87, 89, 91, 93, 97, 99, 101, 700 * 103, 105, 107, 109, 111, 113, 115, 117, 701 * 119, 121, 123, 125, 129, 131, 133, 135, 702 * 137, 139, 141, 143, 145, 147, 149, 151, 703 * 153, 155, 157, 161, 163, 165, 167, 169, 704 * 171, 173, 175, 177, 179, 181, 183, 185, 705 * 187, 189, 193, 195, 197, 199, 201, 203, 706 * 205, 207, 209, 211, 213, 215, 217, 219, 707 * 221, 225, 227, 229, 231, 233, 235, 237, 708 * 239, 241, 243, 245, 247, 249, 251, 253, 709 */ 710 #define RTW89_6G_CH_NUM 120 711 712 enum rtw89_rate_section { 713 RTW89_RS_CCK, 714 RTW89_RS_OFDM, 715 RTW89_RS_MCS, /* for HT/VHT/HE */ 716 RTW89_RS_HEDCM, 717 RTW89_RS_OFFSET, 718 RTW89_RS_NUM, 719 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 720 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 721 }; 722 723 enum rtw89_rate_offset_indexes { 724 RTW89_RATE_OFFSET_HE, 725 RTW89_RATE_OFFSET_VHT, 726 RTW89_RATE_OFFSET_HT, 727 RTW89_RATE_OFFSET_OFDM, 728 RTW89_RATE_OFFSET_CCK, 729 RTW89_RATE_OFFSET_DLRU_EHT, 730 RTW89_RATE_OFFSET_DLRU_HE, 731 RTW89_RATE_OFFSET_EHT, 732 __RTW89_RATE_OFFSET_NUM, 733 734 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 735 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 736 }; 737 738 enum rtw89_rate_num { 739 RTW89_RATE_CCK_NUM = 4, 740 RTW89_RATE_OFDM_NUM = 8, 741 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 742 743 RTW89_RATE_MCS_NUM_AX = 12, 744 RTW89_RATE_MCS_NUM_BE = 16, 745 __RTW89_RATE_MCS_NUM = 16, 746 }; 747 748 enum rtw89_nss { 749 RTW89_NSS_1 = 0, 750 RTW89_NSS_2 = 1, 751 /* HE DCM only support 1ss and 2ss */ 752 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 753 RTW89_NSS_3 = 2, 754 RTW89_NSS_4 = 3, 755 RTW89_NSS_NUM, 756 }; 757 758 enum rtw89_ntx { 759 RTW89_1TX = 0, 760 RTW89_2TX = 1, 761 RTW89_NTX_NUM, 762 }; 763 764 enum rtw89_beamforming_type { 765 RTW89_NONBF = 0, 766 RTW89_BF = 1, 767 RTW89_BF_NUM, 768 }; 769 770 enum rtw89_ofdma_type { 771 RTW89_NON_OFDMA = 0, 772 RTW89_OFDMA = 1, 773 RTW89_OFDMA_NUM, 774 }; 775 776 /* neither insert new in the middle, nor change any given definition */ 777 enum rtw89_regulation_type { 778 RTW89_WW = 0, 779 RTW89_ETSI = 1, 780 RTW89_FCC = 2, 781 RTW89_MKK = 3, 782 RTW89_NA = 4, 783 RTW89_IC = 5, 784 RTW89_KCC = 6, 785 RTW89_ACMA = 7, 786 RTW89_NCC = 8, 787 RTW89_MEXICO = 9, 788 RTW89_CHILE = 10, 789 RTW89_UKRAINE = 11, 790 RTW89_CN = 12, 791 RTW89_QATAR = 13, 792 RTW89_UK = 14, 793 RTW89_THAILAND = 15, 794 RTW89_NZ = 16, 795 RTW89_BR = 17, 796 RTW89_AR = 18, 797 RTW89_REGD_NUM, 798 }; 799 800 enum rtw89_reg_6ghz_power { 801 RTW89_REG_6GHZ_POWER_VLP = 0, 802 RTW89_REG_6GHZ_POWER_LPI = 1, 803 RTW89_REG_6GHZ_POWER_STD = 2, 804 805 NUM_OF_RTW89_REG_6GHZ_POWER, 806 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 807 }; 808 809 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 810 811 /* calculate based on ieee80211 Transmit Power Envelope */ 812 struct rtw89_reg_6ghz_tpe { 813 bool valid; 814 s8 constraint; /* unit: dBm */ 815 }; 816 817 enum rtw89_fw_pkt_ofld_type { 818 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 819 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 820 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 821 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 822 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 823 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 824 RTW89_PKT_OFLD_TYPE_NDP = 6, 825 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 826 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 827 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 828 RTW89_PKT_OFLD_TYPE_NUM, 829 }; 830 831 struct rtw89_txpwr_byrate { 832 s8 cck[RTW89_RATE_CCK_NUM]; 833 s8 ofdm[RTW89_RATE_OFDM_NUM]; 834 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 835 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 836 s8 offset[__RTW89_RATE_OFFSET_NUM]; 837 s8 trap; 838 }; 839 840 struct rtw89_rate_desc { 841 enum rtw89_nss nss; 842 enum rtw89_rate_section rs; 843 enum rtw89_ofdma_type ofdma; 844 u8 idx; 845 }; 846 847 #define PHY_STS_HDR_LEN 8 848 #define RF_PATH_MAX 4 849 #define RTW89_MAX_PPDU_CNT 8 850 struct rtw89_rx_phy_ppdu { 851 void *buf; 852 u32 len; 853 u8 rssi_avg; 854 u8 rssi[RF_PATH_MAX]; 855 u8 mac_id; 856 u8 chan_idx; 857 u8 phy_idx; 858 u8 ie; /* enum rtw89_phy_status_bitmap */ 859 u16 rate; 860 u8 rpl_avg; 861 u8 rpl_path[RF_PATH_MAX]; 862 u8 rpl_fd[RF_PATH_MAX]; 863 u8 bw_idx; 864 u8 rx_path_en; 865 struct { 866 bool has; 867 u8 avg_snr; 868 u8 evm_max; 869 u8 evm_min; 870 } ofdm; 871 bool has_data; 872 bool has_bcn; 873 bool su; 874 bool ldpc; 875 bool stbc; 876 bool bf; 877 bool to_self; 878 bool valid; 879 bool hdr_2_en; 880 const union rtw89_phy_sts_ie09 *ie09; /* SIG-A */ 881 const struct rtw89_phy_sts_ie10 *ie10; /* SIG-B */ 882 }; 883 884 enum rtw89_mac_idx { 885 RTW89_MAC_0 = 0, 886 RTW89_MAC_1 = 1, 887 RTW89_MAC_NUM, 888 }; 889 890 enum rtw89_phy_idx { 891 RTW89_PHY_0 = 0, 892 RTW89_PHY_1 = 1, 893 RTW89_PHY_NUM, 894 }; 895 896 enum rtw89_fbtc_bt_index { 897 BTC_BT_1ST = 0x0, 898 BTC_BT_2ND = 0x1, 899 BTC_BT_EXT = 0x2, 900 BTC_ALL_BT = 0x2, 901 BTC_ALL_BT_EZL = 0x3 /* BT0+BT1+Ext-ZB(or Thread, or LTE) */ 902 }; 903 904 #define __RTW89_MLD_MAX_LINK_NUM 2 905 #define RTW89_MLD_NON_STA_LINK_NUM 1 906 907 enum rtw89_chanctx_idx { 908 RTW89_CHANCTX_0 = 0, 909 RTW89_CHANCTX_1 = 1, 910 911 NUM_OF_RTW89_CHANCTX, 912 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 913 }; 914 915 enum rtw89_rf_path { 916 RF_PATH_A = 0, 917 RF_PATH_B = 1, 918 RF_PATH_C = 2, 919 RF_PATH_D = 3, 920 RF_PATH_AB, 921 RF_PATH_AC, 922 RF_PATH_AD, 923 RF_PATH_BC, 924 RF_PATH_BD, 925 RF_PATH_CD, 926 RF_PATH_ABC, 927 RF_PATH_ABD, 928 RF_PATH_ACD, 929 RF_PATH_BCD, 930 RF_PATH_ABCD, 931 }; 932 933 enum rtw89_rf_path_bit { 934 RF_A = BIT(0), 935 RF_B = BIT(1), 936 RF_C = BIT(2), 937 RF_D = BIT(3), 938 939 RF_AB = (RF_A | RF_B), 940 RF_AC = (RF_A | RF_C), 941 RF_AD = (RF_A | RF_D), 942 RF_BC = (RF_B | RF_C), 943 RF_BD = (RF_B | RF_D), 944 RF_CD = (RF_C | RF_D), 945 946 RF_ABC = (RF_A | RF_B | RF_C), 947 RF_ABD = (RF_A | RF_B | RF_D), 948 RF_ACD = (RF_A | RF_C | RF_D), 949 RF_BCD = (RF_B | RF_C | RF_D), 950 951 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 952 }; 953 954 enum rtw89_bandwidth { 955 RTW89_CHANNEL_WIDTH_20 = 0, 956 RTW89_CHANNEL_WIDTH_40 = 1, 957 RTW89_CHANNEL_WIDTH_80 = 2, 958 RTW89_CHANNEL_WIDTH_160 = 3, 959 RTW89_CHANNEL_WIDTH_320 = 4, 960 961 /* keep index order above */ 962 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 963 964 RTW89_CHANNEL_WIDTH_80_80 = 5, 965 RTW89_CHANNEL_WIDTH_5 = 6, 966 RTW89_CHANNEL_WIDTH_10 = 7, 967 }; 968 969 enum rtw89_rx_ppdu_type { 970 RTW89_RX_PPDU_T_LCCK = 0, 971 RTW89_RX_PPDU_T_SCCK = 1, 972 RTW89_RX_PPDU_T_OFDM = 2, 973 RTW89_RX_PPDU_T_HT = 3, 974 RTW89_RX_PPDU_T_HTGF = 4, 975 RTW89_RX_PPDU_T_VHT_SU = 5, 976 RTW89_RX_PPDU_T_VHT_MU = 6, 977 RTW89_RX_PPDU_T_HE_SU = 7, 978 RTW89_RX_PPDU_T_HE_ERSU = 8, 979 RTW89_RX_PPDU_T_HE_MU = 9, 980 RTW89_RX_PPDU_T_HE_TB = 10, 981 RTW89_RX_PPDU_T_UNKNOWN = 15, 982 }; 983 984 enum rtw89_ps_mode { 985 RTW89_PS_MODE_NONE = 0, 986 RTW89_PS_MODE_RFOFF = 1, 987 RTW89_PS_MODE_CLK_GATED = 2, 988 RTW89_PS_MODE_PWR_GATED = 3, 989 }; 990 991 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 992 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 993 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 994 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 995 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 996 997 enum rtw89_pe_duration { 998 RTW89_PE_DURATION_0 = 0, 999 RTW89_PE_DURATION_8 = 1, 1000 RTW89_PE_DURATION_16 = 2, 1001 RTW89_PE_DURATION_16_20 = 3, 1002 }; 1003 1004 enum rtw89_ru_bandwidth { 1005 RTW89_RU26 = 0, 1006 RTW89_RU52 = 1, 1007 RTW89_RU106 = 2, 1008 RTW89_RU52_26 = 3, 1009 RTW89_RU106_26 = 4, 1010 RTW89_RU484_242 = 5, 1011 RTW89_RU996_484 = 6, 1012 RTW89_RU996_484_242 = 7, 1013 RTW89_RU_NUM, 1014 }; 1015 1016 enum rtw89_sc_offset { 1017 RTW89_SC_DONT_CARE = 0, 1018 RTW89_SC_20_UPPER = 1, 1019 RTW89_SC_20_LOWER = 2, 1020 RTW89_SC_20_UPMOST = 3, 1021 RTW89_SC_20_LOWEST = 4, 1022 RTW89_SC_20_UP2X = 5, 1023 RTW89_SC_20_LOW2X = 6, 1024 RTW89_SC_20_UP3X = 7, 1025 RTW89_SC_20_LOW3X = 8, 1026 RTW89_SC_40_UPPER = 9, 1027 RTW89_SC_40_LOWER = 10, 1028 }; 1029 1030 enum rtw89_rfsi_ctrl_band { 1031 RFSI_CTRL_BAND_5_6GHZ, 1032 RFSI_CTRL_BAND_2GHZ, 1033 1034 RFSI_CTRL_BAND_NUM, 1035 }; 1036 1037 /* only mgd features can be added to the enum */ 1038 enum rtw89_wow_flags { 1039 RTW89_WOW_FLAG_EN_MAGIC_PKT, 1040 RTW89_WOW_FLAG_EN_REKEY_PKT, 1041 RTW89_WOW_FLAG_EN_DISCONNECT, 1042 RTW89_WOW_FLAG_EN_PATTERN, 1043 RTW89_WOW_FLAG_NUM, 1044 }; 1045 1046 struct rtw89_chan { 1047 u8 channel; 1048 u8 primary_channel; 1049 enum rtw89_band band_type; 1050 enum rtw89_bandwidth band_width; 1051 1052 /* The follow-up are derived from the above. We must ensure that it 1053 * is assigned correctly in rtw89_chan_create() if new one is added. 1054 */ 1055 u32 freq; 1056 enum rtw89_subband subband_type; 1057 enum rtw89_tx_comp_band tx_comp_band; 1058 enum rtw89_sc_offset pri_ch_idx; 1059 u8 pri_sb_idx; 1060 enum rtw89_rfsi_ctrl_band rfsi_band; 1061 }; 1062 1063 struct rtw89_chan_rcd { 1064 u8 prev_primary_channel; 1065 enum rtw89_band prev_band_type; 1066 bool band_changed; 1067 }; 1068 1069 struct rtw89_channel_help_params { 1070 u32 tx_en; 1071 }; 1072 1073 struct rtw89_port_reg { 1074 u32 port_cfg; 1075 u32 tbtt_prohib; 1076 u32 bcn_area; 1077 u32 bcn_early; 1078 u32 tbtt_early; 1079 u32 tbtt_agg; 1080 u32 bcn_space; 1081 u32 bcn_forcetx; 1082 u32 bcn_err_cnt; 1083 u32 bcn_err_flag; 1084 u32 dtim_ctrl; 1085 u32 tbtt_shift; 1086 u32 bcn_cnt_tmr; 1087 u32 tsftr_l; 1088 u32 tsftr_h; 1089 u32 md_tsft; 1090 u32 bss_color; 1091 u32 mbssid; 1092 u32 mbssid_drop; 1093 u32 tsf_sync; 1094 u32 ptcl_dbg; 1095 u32 ptcl_dbg_info; 1096 u32 bcn_drop_all; 1097 u32 bcn_psr_rpt; 1098 u32 hiq_win[RTW89_PORT_NUM]; 1099 }; 1100 1101 struct rtw89_txwd_body { 1102 __le32 dword0; 1103 __le32 dword1; 1104 __le32 dword2; 1105 __le32 dword3; 1106 __le32 dword4; 1107 __le32 dword5; 1108 } __packed; 1109 1110 struct rtw89_txwd_body_v1 { 1111 __le32 dword0; 1112 __le32 dword1; 1113 __le32 dword2; 1114 __le32 dword3; 1115 __le32 dword4; 1116 __le32 dword5; 1117 __le32 dword6; 1118 __le32 dword7; 1119 } __packed; 1120 1121 struct rtw89_txwd_body_v2 { 1122 __le32 dword0; 1123 __le32 dword1; 1124 __le32 dword2; 1125 __le32 dword3; 1126 __le32 dword4; 1127 __le32 dword5; 1128 __le32 dword6; 1129 __le32 dword7; 1130 } __packed; 1131 1132 struct rtw89_txwd_info { 1133 __le32 dword0; 1134 __le32 dword1; 1135 __le32 dword2; 1136 __le32 dword3; 1137 __le32 dword4; 1138 __le32 dword5; 1139 } __packed; 1140 1141 struct rtw89_txwd_info_v2 { 1142 __le32 dword0; 1143 __le32 dword1; 1144 __le32 dword2; 1145 __le32 dword3; 1146 __le32 dword4; 1147 __le32 dword5; 1148 __le32 dword6; 1149 __le32 dword7; 1150 } __packed; 1151 1152 struct rtw89_rx_desc_info { 1153 u16 pkt_size; 1154 u8 pkt_type; 1155 u8 drv_info_size; 1156 u8 phy_rpt_size; 1157 u8 hdr_cnv_size; 1158 u8 shift; 1159 u8 wl_hd_iv_len; 1160 bool long_rxdesc; 1161 bool bb_sel; 1162 bool mac_info_valid; 1163 u16 data_rate; 1164 u8 gi_ltf; 1165 u8 bw; 1166 u32 free_run_cnt; 1167 u8 user_id; 1168 bool sr_en; 1169 u8 ppdu_cnt; 1170 u8 ppdu_type; 1171 bool icv_err; 1172 bool crc32_err; 1173 bool hw_dec; 1174 bool sw_dec; 1175 bool addr1_match; 1176 bool ampdu; 1177 u8 frag; 1178 u16 seq; 1179 u8 frame_type; 1180 u8 rx_pl_id; 1181 bool addr_cam_valid; 1182 u8 addr_cam_id; 1183 u8 sec_cam_id; 1184 u8 sec_type; 1185 u8 mac_id; 1186 u16 offset; 1187 u16 rxd_len; 1188 bool ready; 1189 u16 rssi; 1190 }; 1191 1192 struct rtw89_rxdesc_short { 1193 __le32 dword0; 1194 __le32 dword1; 1195 __le32 dword2; 1196 __le32 dword3; 1197 } __packed; 1198 1199 struct rtw89_rxdesc_short_v2 { 1200 __le32 dword0; 1201 __le32 dword1; 1202 __le32 dword2; 1203 __le32 dword3; 1204 __le32 dword4; 1205 __le32 dword5; 1206 } __packed; 1207 1208 struct rtw89_rxdesc_short_v3 { 1209 __le32 dword0; 1210 __le32 dword1; 1211 __le32 dword2; 1212 __le32 dword3; 1213 __le32 dword4; 1214 __le32 dword5; 1215 } __packed; 1216 1217 struct rtw89_rxdesc_long { 1218 __le32 dword0; 1219 __le32 dword1; 1220 __le32 dword2; 1221 __le32 dword3; 1222 __le32 dword4; 1223 __le32 dword5; 1224 __le32 dword6; 1225 __le32 dword7; 1226 } __packed; 1227 1228 struct rtw89_rxdesc_long_v2 { 1229 __le32 dword0; 1230 __le32 dword1; 1231 __le32 dword2; 1232 __le32 dword3; 1233 __le32 dword4; 1234 __le32 dword5; 1235 __le32 dword6; 1236 __le32 dword7; 1237 __le32 dword8; 1238 __le32 dword9; 1239 } __packed; 1240 1241 struct rtw89_rxdesc_long_v3 { 1242 __le32 dword0; 1243 __le32 dword1; 1244 __le32 dword2; 1245 __le32 dword3; 1246 __le32 dword4; 1247 __le32 dword5; 1248 __le32 dword6; 1249 __le32 dword7; 1250 __le32 dword8; 1251 __le32 dword9; 1252 } __packed; 1253 1254 struct rtw89_rxdesc_phy_rpt_v2 { 1255 __le32 dword0; 1256 __le32 dword1; 1257 } __packed; 1258 1259 struct rtw89_tx_desc_info { 1260 u16 pkt_size; 1261 u8 wp_offset; 1262 u8 mac_id; 1263 u8 qsel; 1264 u8 ch_dma; 1265 u8 hdr_llc_len; 1266 bool is_bmc; 1267 bool en_wd_info; 1268 bool wd_page; 1269 bool use_rate; 1270 bool dis_data_fb; 1271 bool tid_indicate; 1272 bool agg_en; 1273 bool bk; 1274 u8 ampdu_density; 1275 u8 ampdu_num; 1276 bool sec_en; 1277 bool report; 1278 bool tx_cnt_lmt_en; 1279 u8 sn: 4; 1280 u8 tx_cnt_lmt: 6; 1281 u8 addr_info_nr; 1282 u8 sec_keyid; 1283 u8 sec_type; 1284 u8 sec_cam_idx; 1285 u8 sec_seq[6]; 1286 u16 data_rate; 1287 u16 data_retry_lowest_rate; 1288 u8 data_bw; 1289 u8 gi_ltf; 1290 bool fw_dl; 1291 u16 seq; 1292 bool a_ctrl_bsr; 1293 u8 hw_ssn_sel; 1294 #define RTW89_MGMT_HW_SSN_SEL 1 1295 u8 hw_seq_mode; 1296 #define RTW89_MGMT_HW_SEQ_MODE 1 1297 bool hiq; 1298 u8 port; 1299 bool er_cap; 1300 bool stbc; 1301 bool ldpc; 1302 bool upd_wlan_hdr; 1303 bool mlo; 1304 bool sw_mld; 1305 }; 1306 1307 struct rtw89_core_tx_request { 1308 enum rtw89_core_tx_type tx_type; 1309 1310 struct sk_buff *skb; 1311 struct ieee80211_vif *vif; 1312 struct ieee80211_sta *sta; 1313 struct rtw89_vif_link *rtwvif_link; 1314 struct rtw89_sta_link *rtwsta_link; 1315 struct rtw89_tx_desc_info desc_info; 1316 1317 bool with_wait; 1318 }; 1319 1320 struct rtw89_txq { 1321 struct list_head list; 1322 int wait_cnt; 1323 1324 DECLARE_BITMAP(flags, NUM_OF_RTW89_TXQ_FLAGS); 1325 }; 1326 1327 struct rtw89_mac_ax_gnt { 1328 u8 gnt_bt_sw_en; 1329 u8 gnt_bt; 1330 u8 gnt_wl_sw_en; 1331 u8 gnt_wl; 1332 } __packed; 1333 1334 struct rtw89_btc_gnt_ctrl { 1335 u8 gnt_zb_sw_en; 1336 u8 gnt_zb; 1337 u8 gnt_bt1_sw_en; 1338 u8 gnt_bt1; 1339 u8 gnt_bt0_sw_en; 1340 u8 gnt_bt0; 1341 u8 gnt_wl_sw_en; 1342 u8 gnt_wl; 1343 } __packed; 1344 1345 struct rtw89_mac_ax_wl_act { 1346 u8 wlan_act_en; 1347 u8 wlan_act; 1348 } __packed; 1349 1350 #define RTW89_MAC_AX_COEX_GNT_NR 2 1351 struct rtw89_mac_ax_coex_gnt { 1352 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1353 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1354 }; 1355 1356 enum rtw89_btc_ncnt { 1357 BTC_NCNT_POWER_ON = 0x0, 1358 BTC_NCNT_POWER_OFF, 1359 BTC_NCNT_INIT_COEX, 1360 BTC_NCNT_SCAN_START, 1361 BTC_NCNT_SCAN_FINISH, 1362 BTC_NCNT_SPECIAL_PACKET, 1363 BTC_NCNT_SWITCH_BAND, 1364 BTC_NCNT_RFK_TIMEOUT, 1365 BTC_NCNT_SHOW_COEX_INFO, 1366 BTC_NCNT_ROLE_INFO, 1367 BTC_NCNT_CONTROL, 1368 BTC_NCNT_RADIO_STATE, 1369 BTC_NCNT_CUSTOMERIZE, 1370 BTC_NCNT_WL_RFK, 1371 BTC_NCNT_WL_STA, 1372 BTC_NCNT_WL_STA_LAST, 1373 BTC_NCNT_FWINFO, 1374 BTC_NCNT_TIMER, 1375 BTC_NCNT_SWITCH_CHBW, 1376 BTC_NCNT_RESUME_DL_FW, 1377 BTC_NCNT_COUNTRYCODE, 1378 BTC_NCNT_NUM, 1379 }; 1380 1381 enum rtw89_btc_btinfo { 1382 BTC_BTINFO_L0 = 0, 1383 BTC_BTINFO_L1, 1384 BTC_BTINFO_L2, 1385 BTC_BTINFO_L3, 1386 BTC_BTINFO_H0, 1387 BTC_BTINFO_H1, 1388 BTC_BTINFO_H2, 1389 BTC_BTINFO_H3, 1390 BTC_BTINFO_MAX 1391 }; 1392 1393 #define BTC_BTINFO_BISTDMA 0x48 /* cmd value that identifies BISTDMA data */ 1394 1395 enum rtw89_btc_dcnt { 1396 BTC_DCNT_RUN = 0x0, 1397 BTC_DCNT_CX_RUNINFO, 1398 BTC_DCNT_RPT, 1399 BTC_DCNT_RPT_HANG, 1400 BTC_DCNT_CYCLE, 1401 BTC_DCNT_CYCLE_HANG, 1402 BTC_DCNT_W1, 1403 BTC_DCNT_W1_HANG, 1404 BTC_DCNT_B1, 1405 BTC_DCNT_B1_HANG, 1406 BTC_DCNT_TDMA_NONSYNC, 1407 BTC_DCNT_SLOT_NONSYNC, 1408 BTC_DCNT_BTCNT_HANG, 1409 BTC_DCNT_BTTX_HANG, 1410 BTC_DCNT_WL_SLOT_DRIFT, 1411 BTC_DCNT_WL_STA_LAST, 1412 BTC_DCNT_BT_SLOT_DRIFT, 1413 BTC_DCNT_BT_SLOT_FLOOD, 1414 BTC_DCNT_FDDT_TRIG, 1415 BTC_DCNT_E2G, 1416 BTC_DCNT_E2G_HANG, 1417 BTC_DCNT_WL_FW_VER_MATCH, 1418 BTC_DCNT_NULL_TX_FAIL, 1419 BTC_DCNT_WL_STA_NTFY, 1420 BTC_DCNT_W2B_SCBD_NOSYNC, 1421 BTC_DCNT_NUM, 1422 }; 1423 1424 enum rtw89_btc_wl_state_cnt { 1425 BTC_WCNT_SCANAP = 0x0, 1426 BTC_WCNT_DHCP, 1427 BTC_WCNT_EAPOL, 1428 BTC_WCNT_ARP, 1429 BTC_WCNT_SCBDUPDATE, 1430 BTC_WCNT_RFK_REQ, 1431 BTC_WCNT_RFK_GO, 1432 BTC_WCNT_RFK_REJECT, 1433 BTC_WCNT_RFK_TIMEOUT, 1434 BTC_WCNT_CH_UPDATE, 1435 BTC_WCNT_DBCC_ALL_2G, 1436 BTC_WCNT_DBCC_CHG, 1437 BTC_WCNT_RX_OK_LAST, 1438 BTC_WCNT_RX_OK_LAST2S, 1439 BTC_WCNT_RX_ERR_LAST, 1440 BTC_WCNT_RX_ERR_LAST2S, 1441 BTC_WCNT_RX_LAST, 1442 BTC_WCNT_SCBDUPDATE2, 1443 BTC_WCNT_NUM 1444 }; 1445 1446 enum rtw89_btc_bt_state_cnt { 1447 BTC_BCNT_RETRY = 0x0, 1448 BTC_BCNT_REINIT, 1449 BTC_BCNT_REENABLE, 1450 BTC_BCNT_SCBDREAD, 1451 BTC_BCNT_RELINK, 1452 BTC_BCNT_IGNOWL, 1453 BTC_BCNT_INQPAG, 1454 BTC_BCNT_INQ, 1455 BTC_BCNT_PAGE, 1456 BTC_BCNT_ROLESW, 1457 BTC_BCNT_AFH, 1458 BTC_BCNT_INFOUPDATE, 1459 BTC_BCNT_LEAUDIO_INFOUPDATE, 1460 BTC_BCNT_INFOSAME, 1461 BTC_BCNT_LEAUDIO_INFOSAME, 1462 BTC_BCNT_SCBDUPDATE, 1463 BTC_BCNT_HIPRI_TX, 1464 BTC_BCNT_HIPRI_RX, 1465 BTC_BCNT_LOPRI_TX, 1466 BTC_BCNT_LOPRI_RX, 1467 BTC_BCNT_POLUT_NOW, 1468 BTC_BCNT_POLUT_DIFF, 1469 BTC_BCNT_RATECHG, 1470 BTC_BCNT_AFH_CONFLICT, 1471 BTC_BCNT_AFH_LE_CONFLICT, 1472 BTC_BCNT_AFH_UPDATE, 1473 BTC_BCNT_AFH_LE_UPDATE, 1474 BTC_BCNT_AFH_CHN, 1475 BTC_BCNT_AFH_LE_CHN, 1476 BTC_BCNT_TXPWR_UPDATE, 1477 BTC_BCNT_PROTECT, 1478 BTC_BCNT_NUM, 1479 }; 1480 1481 enum rtw89_btc_bt_mech_type { 1482 BTC_MECH_TDD = 0, 1483 BTC_MECH_FDD = 1, 1484 }; 1485 1486 enum rtw89_btc_bt_rf_band { 1487 BTC_BT_B2G = 0x0, /* 2.4GHz */ 1488 BTC_BT_B5G = 0x1, /* 5GHz or 6GHz */ 1489 BTC_BT_BMAX = 0x2 1490 }; 1491 1492 enum rtw89_btc_io_offload_type { 1493 BTC_IO_OFLD_NO_SUPPORT = 0, 1494 BTC_IO_OFLD_MAC_API = 1, 1495 BTC_IO_OFLD_BTC_H2C = 2 1496 }; 1497 1498 enum rtw89_btc_bt_profile { 1499 BTC_BT_NOPROFILE = 0, 1500 BTC_BT_HFP = BIT(0), 1501 BTC_BT_HID = BIT(1), 1502 BTC_BT_A2DP = BIT(2), 1503 BTC_BT_PAN = BIT(3), 1504 BTC_BT_BIS = BIT(4), 1505 BTC_BT_CIS = BIT(5), 1506 BTC_BT_THREAD = BIT(6), 1507 BTC_BT_ULL = BIT(7), 1508 BTC_BT_LEGACY = 0xf, 1509 BTC_BT_FULL = 0x3f, 1510 BTC_PROFILE_MAX = 4, 1511 }; 1512 1513 struct rtw89_btc_ant_info_v0 { 1514 u8 type; /* shared, dedicated */ 1515 u8 num; 1516 u8 isolation; 1517 1518 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1519 u8 diversity: 1; 1520 u8 btg_pos: 2; 1521 u8 stream_cnt: 4; 1522 }; 1523 1524 struct rtw89_btc_ant_info_v7 { 1525 u8 type; /* shared, dedicated(non-shared) */ 1526 u8 num; /* antenna count */ 1527 u8 isolation; 1528 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1529 1530 u8 diversity; /* only for wifi use 1-antenna */ 1531 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1532 u8 stream_cnt; /* spatial_stream count */ 1533 u8 rsvd; 1534 } __packed; 1535 1536 struct rtw89_btc_ant_info_v10 { 1537 u8 type; /* shared, dedicated(non-shared) */ 1538 u8 num; /* antenna count */ 1539 u8 isolation; /* Ant-Iso between WL/BT */ 1540 u8 single_pos; /* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1541 1542 u8 stream_cnt; /* spatial_stream count: Tx[7:4], Rx[3:0] */ 1543 u8 btg_pos; /* BT0 btg-circuit at 0:WL-S0/1:WL-S1 */ 1544 u8 btg1_pos; /* BT1 btg-circuit at 0:WL-S0/1:WL-S1 */ 1545 u8 func[5]; /* function at 1~5 Ant refer to enum btc_bt_func_type */ 1546 u8 ant_xmap[2][4]; 1547 } __packed; 1548 1549 struct rtw89_btc_ant_info_v11 { 1550 u8 type; 1551 u8 num; 1552 u8 isolation; 1553 u8 single_pos; 1554 1555 u8 stream_cnt; 1556 u8 path_pos; /* WL path position: Tx[7:4], Rx[3:0] */ 1557 u8 btg_pos; 1558 u8 btg1_pos; 1559 u8 func[5]; 1560 u8 ant_xmap[2][4]; 1561 u8 rsvd0[3]; 1562 } __packed; 1563 1564 struct rtw89_btc_ant_info { 1565 u8 type; /* shared, dedicated(non-shared) */ 1566 u8 num; /* antenna count */ 1567 u8 isolation; /* Ant-Iso between WL/BT */ 1568 u8 single_pos; /* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1569 1570 u8 stream_cnt; /* spatial_stream count: Tx[7:4], Rx[3:0] */ 1571 u8 btg_pos; /* BT0 btg-circuit at 0:WL-S0/1:WL-S1 */ 1572 u8 btg1_pos; /* BT1 btg-circuit at 0:WL-S0/1:WL-S1 */ 1573 u8 path_pos; /* WL path position: Tx[7:4], Rx[3:0] */ 1574 u8 func[5]; /* function at 1~5 Ant refer to enum btc_bt_func_type */ 1575 u8 ant_xmap[2][4]; 1576 1577 u8 diversity; /* only for wifi use 1-antenna */ 1578 }; 1579 1580 enum rtw89_tfc_dir { 1581 RTW89_TFC_UL, 1582 RTW89_TFC_DL, 1583 }; 1584 1585 struct rtw89_btc_wl_smap { 1586 u32 busy: 1; 1587 u32 scan: 1; 1588 u32 dhcp: 1; 1589 u32 roaming: 1; 1590 u32 transacting: 1; 1591 u32 _4way: 1; 1592 u32 handshake: 1; 1593 u32 rf_off: 1; 1594 u32 rf_off_pre: 1; 1595 u32 ips: 1; 1596 u32 lps: 2; 1597 u32 lps_pre: 2; 1598 u32 lps_exiting: 1; 1599 u32 emlsr: 1; 1600 u32 init_ok: 1; 1601 u32 traffic_dir : 2; 1602 }; 1603 1604 enum rtw89_tfc_interval { 1605 RTW89_TFC_INTERVAL_100MS, 1606 RTW89_TFC_INTERVAL_2SEC, 1607 }; 1608 1609 enum rtw89_tfc_lv { 1610 RTW89_TFC_IDLE, 1611 RTW89_TFC_ULTRA_LOW, 1612 RTW89_TFC_LOW, 1613 RTW89_TFC_MID, 1614 RTW89_TFC_HIGH, 1615 }; 1616 1617 DECLARE_EWMA(tp, 10, 2); 1618 1619 #define RTW89_TCP_TH 40 1620 #define RTW89_UDP_RATIO_TH 70 1621 #define RTW89_RECENT_ACTIVE_HIST GENMASK(4, 0) 1622 1623 struct rtw89_traffic_stats { 1624 /* units in bytes */ 1625 u64 tx_unicast; 1626 u64 rx_unicast; 1627 u32 tx_avg_len; 1628 u32 rx_avg_len; 1629 1630 /* count for packets */ 1631 u64 tx_cnt; 1632 u64 rx_cnt; 1633 1634 /* units in Mbps */ 1635 u32 tx_throughput; 1636 u32 rx_throughput; 1637 u32 tx_throughput_raw; 1638 u32 rx_throughput_raw; 1639 1640 u32 rx_tf_acc; 1641 u32 rx_tf_periodic; 1642 1643 enum rtw89_tfc_lv tx_tfc_lv; 1644 enum rtw89_tfc_lv rx_tfc_lv; 1645 struct ewma_tp tx_ewma_tp; 1646 struct ewma_tp rx_ewma_tp; 1647 1648 u16 tx_rate; 1649 u16 rx_rate; 1650 1651 /* used by rtwvif only */ 1652 u64 tcp, udp, udp_ratio; 1653 u8 active_histogram; 1654 }; 1655 1656 struct rtw89_btc_chdef { 1657 u8 center_ch; 1658 u8 band; 1659 u8 chan; 1660 enum rtw89_sc_offset offset; 1661 enum rtw89_bandwidth bw; 1662 }; 1663 1664 struct rtw89_btc_statistic { 1665 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1666 struct rtw89_traffic_stats traffic; 1667 }; 1668 1669 #define BTC_WL_RSSI_THMAX 4 1670 1671 struct rtw89_btc_wl_link_info { 1672 struct rtw89_btc_chdef chdef; 1673 struct rtw89_btc_statistic stat; 1674 enum rtw89_tfc_dir dir; 1675 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1676 u8 mac_addr[ETH_ALEN]; 1677 u8 busy; 1678 u8 ch; 1679 u8 bw; 1680 u8 band; 1681 u8 role; 1682 u8 pid; 1683 u8 phy; 1684 u8 dtim_period; 1685 u8 mode; 1686 u8 tx_1ss_limit; 1687 1688 u8 mac_id; 1689 u8 tx_retry; 1690 1691 u32 bcn_period; 1692 u32 busy_t; 1693 u32 tx_time; 1694 u32 client_cnt; 1695 u32 rx_rate_drop_cnt; 1696 u32 noa_duration; 1697 1698 u32 active: 1; 1699 u32 noa: 1; 1700 u32 client_ps: 1; 1701 u32 connected: 2; 1702 }; 1703 1704 union rtw89_btc_wl_state_map { 1705 u32 val; 1706 struct rtw89_btc_wl_smap map; 1707 }; 1708 1709 struct rtw89_btc_bt_hfp_desc { 1710 u32 exist: 1; 1711 u32 type: 2; 1712 u32 rsvd: 29; 1713 }; 1714 1715 struct rtw89_btc_bt_hid_desc { 1716 u32 exist: 1; 1717 u32 slot_info: 2; 1718 u32 pair_cnt: 2; 1719 u32 type: 8; 1720 u32 rsvd: 19; 1721 }; 1722 1723 struct rtw89_btc_bt_a2dp_desc { 1724 u8 exist: 1; 1725 u8 exist_last: 1; 1726 u8 play_latency: 1; 1727 u8 type: 3; 1728 u8 active: 1; 1729 u8 sink: 1; 1730 u32 handle_update: 1; 1731 u32 devinfo_query: 1; 1732 u32 no_empty_streak_2s: 8; 1733 u32 no_empty_streak_max: 8; 1734 u32 rsvd: 6; 1735 1736 u8 bitpool; 1737 u16 vendor_id; 1738 u32 device_name; 1739 u32 flush_time; 1740 }; 1741 1742 struct rtw89_btc_bt_pan_desc { 1743 u32 exist: 1; 1744 u32 type: 1; 1745 u32 active: 1; 1746 u32 rsvd: 29; 1747 }; 1748 1749 struct rtw89_btc_bt_rfk_info { 1750 u32 run: 1; 1751 u32 req: 1; 1752 u32 timeout: 1; 1753 u32 rsvd: 29; 1754 }; 1755 1756 union rtw89_btc_bt_rfk_info_map { 1757 u32 val; 1758 struct rtw89_btc_bt_rfk_info map; 1759 }; 1760 1761 struct rtw89_btc_bt_ver_info { 1762 u32 fw_coex; /* match with which coex_ver */ 1763 u32 fw; 1764 }; 1765 1766 struct rtw89_btc_bool_sta_chg { 1767 u8 now: 1; 1768 u8 last: 1; 1769 u8 remain: 1; 1770 u8 srvd: 5; 1771 }; 1772 1773 struct rtw89_btc_u8_sta_chg { 1774 u8 now; 1775 u8 last; 1776 u8 chg; 1777 u8 rsvd; 1778 }; 1779 1780 struct rtw89_btc_wl_scan_info { 1781 u8 band[RTW89_PHY_NUM]; 1782 u8 phy_map; 1783 u8 hw_band_map; 1784 u8 type; 1785 u8 fw_scan; 1786 }; 1787 1788 struct rtw89_btc_wl_dbcc_info { 1789 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1790 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1791 u8 real_band[RTW89_PHY_NUM]; 1792 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1793 }; 1794 1795 struct rtw89_btc_wl_mlo_info_v2 { 1796 u8 wmode[RTW89_PHY_NUM]; 1797 u8 ch_type[RTW89_PHY_NUM]; 1798 u8 hwb_rf_band[RTW89_PHY_NUM]; 1799 u8 path_rf_band[RTW89_PHY_NUM]; 1800 1801 u8 wtype; 1802 u8 mrcx_mode; 1803 u8 mrcx_act_hwb_map; 1804 u8 mrcx_bt_slot_rsp; 1805 1806 u8 rf_combination; 1807 u8 mlo_en; 1808 u8 mlo_adie; 1809 u8 dual_hw_band_en; 1810 1811 __le32 link_status; 1812 } __packed; 1813 1814 struct rtw89_btc_wl_mlo_info { 1815 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */ 1816 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */ 1817 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */ 1818 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */ 1819 1820 u8 wtype; /* enum phl_mr_wtype */ 1821 u8 mrcx_mode; 1822 u8 mrcx_act_hwb_map; 1823 u8 mrcx_bt_slot_rsp; 1824 1825 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */ 1826 u8 mlo_en; /* MLO enable */ 1827 u8 mlo_adie; /* a-die count */ 1828 u8 dual_hw_band_en; /* both 2 HW-band link exist */ 1829 1830 u32 link_status; /* enum mlo_dbcc_mode_type */ 1831 }; 1832 1833 struct rtw89_btc_wl_active_role { 1834 u8 connected: 1; 1835 u8 pid: 3; 1836 u8 phy: 1; 1837 u8 noa: 1; 1838 u8 band: 2; 1839 1840 u8 client_ps: 1; 1841 u8 bw: 7; 1842 1843 u8 role; 1844 u8 ch; 1845 1846 u16 tx_lvl; 1847 u16 rx_lvl; 1848 u16 tx_rate; 1849 u16 rx_rate; 1850 }; 1851 1852 struct rtw89_btc_wl_active_role_v1 { 1853 u8 connected: 1; 1854 u8 pid: 3; 1855 u8 phy: 1; 1856 u8 noa: 1; 1857 u8 band: 2; 1858 1859 u8 client_ps: 1; 1860 u8 bw: 7; 1861 1862 u8 role; 1863 u8 ch; 1864 1865 u16 tx_lvl; 1866 u16 rx_lvl; 1867 u16 tx_rate; 1868 u16 rx_rate; 1869 1870 u32 noa_duration; /* ms */ 1871 }; 1872 1873 struct rtw89_btc_wl_active_role_v2 { 1874 u8 connected: 1; 1875 u8 pid: 3; 1876 u8 phy: 1; 1877 u8 noa: 1; 1878 u8 band: 2; 1879 1880 u8 client_ps: 1; 1881 u8 bw: 7; 1882 1883 u8 role; 1884 u8 ch; 1885 1886 u32 noa_duration; /* ms */ 1887 }; 1888 1889 struct rtw89_btc_wl_active_role_v7 { 1890 u8 connected; 1891 u8 pid; 1892 u8 phy; 1893 u8 noa; 1894 1895 u8 band; 1896 u8 client_ps; 1897 u8 bw; 1898 u8 role; 1899 1900 u8 ch; 1901 u8 noa_dur; 1902 u8 client_cnt; 1903 u8 rsvd2; 1904 } __packed; 1905 1906 struct rtw89_btc_wl_role_info_bpos { 1907 u16 none: 1; 1908 u16 station: 1; 1909 u16 ap: 1; 1910 u16 vap: 1; 1911 u16 adhoc: 1; 1912 u16 adhoc_master: 1; 1913 u16 mesh: 1; 1914 u16 monitor: 1; 1915 u16 p2p_device: 1; 1916 u16 p2p_gc: 1; 1917 u16 p2p_go: 1; 1918 u16 nan: 1; 1919 }; 1920 1921 struct rtw89_btc_eslot_ctrl { 1922 u8 en; /* 1: toggle tx-flow-ctrl (null 0/1), tx-pause by Ext-slot */ 1923 u8 nulltx_role1; 1924 u8 nulltx_role2; 1925 u8 nulltx_pre_time; /* null-tx time prior to EBT-start (from E2G-end) */ 1926 }; 1927 1928 union rtw89_btc_wl_role_info_map { 1929 u16 val; 1930 struct rtw89_btc_wl_role_info_bpos role; 1931 }; 1932 1933 struct rtw89_btc_wl_role_info_v0 { /* struct size must be n*4 bytes */ 1934 u8 connect_cnt; 1935 u8 link_mode; 1936 union rtw89_btc_wl_role_info_map role_map; 1937 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1938 }; 1939 1940 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1941 u8 connect_cnt; 1942 u8 link_mode; 1943 union rtw89_btc_wl_role_info_map role_map; 1944 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1945 u32 mrole_type; /* btc_wl_mrole_type */ 1946 u32 mrole_noa_duration; /* ms */ 1947 1948 u32 dbcc_en: 1; 1949 u32 dbcc_chg: 1; 1950 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1951 u32 link_mode_chg: 1; 1952 u32 rsvd: 27; 1953 }; 1954 1955 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1956 u8 connect_cnt; 1957 u8 link_mode; 1958 union rtw89_btc_wl_role_info_map role_map; 1959 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1960 u32 mrole_type; /* btc_wl_mrole_type */ 1961 u32 mrole_noa_duration; /* ms */ 1962 1963 u32 dbcc_en: 1; 1964 u32 dbcc_chg: 1; 1965 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1966 u32 link_mode_chg: 1; 1967 u32 rsvd: 27; 1968 }; 1969 1970 struct rtw89_btc_wl_rlink_v0 { /* H2C info, struct size must be n*4 bytes */ 1971 u8 connected; 1972 u8 pid; 1973 u8 phy; 1974 u8 noa; 1975 1976 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1977 u8 active; /* 0:rlink is under doze */ 1978 u8 bw; /* enum channel_width */ 1979 u8 role; /*enum role_type */ 1980 1981 u8 ch; 1982 u8 noa_dur; /* ms */ 1983 u8 client_cnt; /* for Role = P2P-Go/AP */ 1984 u8 mode; /* wifi protocol */ 1985 } __packed; 1986 1987 struct rtw89_btc_wl_rlink_v10 { /* H2C info, struct size must be n*4 bytes */ 1988 u8 connected; 1989 u8 pid; 1990 u8 phy; 1991 u8 noa; 1992 1993 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1994 u8 active; /* 0:rlink is under doze */ 1995 u8 bw; /* enum channel_width */ 1996 u8 role; /*enum role_type */ 1997 1998 u8 ch; 1999 u8 noa_dur; /* ms */ 2000 u8 client_cnt; /* for Role = P2P-Go/AP */ 2001 u8 mode; /* wifi protocol */ 2002 2003 u8 mac_id; 2004 u8 rsvd0; 2005 u8 rsvd1; 2006 u8 rsvd2; 2007 } __packed; 2008 2009 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 2010 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 2011 u8 connect_cnt; 2012 u8 link_mode; 2013 u8 link_mode_chg; 2014 u8 p2p_2g; 2015 2016 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 2017 2018 __le32 role_map; 2019 __le32 mrole_type; /* btc_wl_mrole_type */ 2020 __le32 mrole_noa_duration; /* ms */ 2021 __le32 dbcc_en; 2022 __le32 dbcc_chg; 2023 __le32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 2024 } __packed; 2025 2026 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 2027 u8 connect_cnt; 2028 u8 link_mode; 2029 u8 link_mode_chg; 2030 u8 p2p_2g; 2031 2032 u8 pta_req_band; 2033 u8 dbcc_en; /* 1+1 and 2.4G-included */ 2034 u8 dbcc_chg; 2035 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 2036 2037 struct rtw89_btc_wl_rlink_v0 rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2038 2039 __le32 role_map; 2040 __le32 mrole_type; /* btc_wl_mrole_type */ 2041 __le32 mrole_noa_duration; /* ms */ 2042 } __packed; 2043 2044 struct rtw89_btc_wl_role_info_v10 { /* H2C info, struct size must be n*4 bytes */ 2045 struct rtw89_btc_wl_rlink_v10 rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2046 u8 link_mode; 2047 u8 link_mode_hb1; 2048 u8 p2p_exist; 2049 u8 p2p_exist_hb1; 2050 2051 u8 pta_req_band; 2052 u8 dbcc_en; /* 1+1 and 2.4G-included */ 2053 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 2054 u8 rsvd; 2055 2056 __le32 role_map; 2057 __le32 role_map_hb1; 2058 __le32 mrole_type; /* btc_wl_mrole_type: [31:16]:band1, [15:0]:band0 */ 2059 } __packed; 2060 2061 struct rtw89_btc_wl_role_info_v11 { /* H2C info, struct size must be n*4 bytes */ 2062 struct rtw89_btc_wl_rlink_v10 rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2063 u8 link_mode; 2064 u8 link_mode_hb1; 2065 u8 p2p_exist; 2066 u8 p2p_exist_hb1; 2067 2068 u8 pta_req_band; 2069 u8 dbcc_en; /* 1+1 and 2.4G-included */ 2070 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 2071 u8 rsvd; 2072 2073 __le32 role_map; 2074 __le32 role_map_hb1; 2075 __le32 mrole_type; /* btc_wl_mrole_type: [31:16]:band1, [15:0]:band0 */ 2076 } __packed; 2077 2078 struct rtw89_btc_wl_rlink { /* Logic dynamic using */ 2079 u8 connected; 2080 u8 pid; 2081 u8 phy; 2082 u8 noa; 2083 2084 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 2085 u8 active; /* 0:rlink is under doze */ 2086 u8 bw; /* enum channel_width */ 2087 u8 role; /*enum role_type */ 2088 2089 u8 ch; 2090 u8 noa_dur; /* ms */ 2091 u8 client_cnt; /* for Role = P2P-Go/AP */ 2092 u8 mode; /* wifi protocol */ 2093 2094 /*v0 v1*/ 2095 u16 tx_lvl; 2096 u16 rx_lvl; 2097 u16 tx_rate; 2098 u16 rx_rate; 2099 2100 /* v7 */ 2101 u8 client_ps; /*v7 v2 v1 v0*/ 2102 2103 /* v10 */ 2104 u8 mac_id; 2105 u8 rsvd0; 2106 u8 rsvd1; 2107 u8 rsvd2; 2108 }; 2109 2110 struct rtw89_btc_wl_role_info { /* Logic dynamic using */ 2111 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2112 u8 link_mode[RTW89_MAC_NUM]; 2113 u8 p2p_exist[RTW89_MAC_NUM]; 2114 2115 u8 pta_req_band; 2116 u8 dbcc_en; /* 1+1 and 2.4G-included */ 2117 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 2118 u8 rsvd; 2119 2120 u32 role_map[RTW89_MAC_NUM]; 2121 u32 mrole_type; /* btc_wl_mrole_type: [31:16]:band1, [15:0]:band0 */ 2122 2123 /* Before v10 use this linkmode */ 2124 u8 link_mode_v0; 2125 2126 /* v7 */ 2127 u8 connect_cnt; 2128 u32 dbcc_chg; /* v7 v2*/ 2129 2130 /* v8 */ 2131 u8 link_mode_chg; /* v8, v7 v2*/ 2132 u8 p2p_2g; /* v8, v7 */ 2133 u32 mrole_noa_duration; /* v8, v7 v2*/ 2134 }; 2135 2136 struct rtw89_btc_wl_ver_info { 2137 char build_time[12]; 2138 char build_date[12]; 2139 u32 fw_coex; /* match with which coex_ver */ 2140 u32 fw; 2141 u32 mac; 2142 u32 bb; 2143 u32 rf; 2144 }; 2145 2146 struct rtw89_btc_wl_afh_info { 2147 u8 en; 2148 u8 ch; 2149 u8 bw; 2150 u8 band; 2151 } __packed; 2152 2153 struct rtw89_btc_wl_rfk_info { 2154 u32 state: 2; 2155 u32 path_map: 4; 2156 u32 phy_map: 2; 2157 u32 band: 2; 2158 u32 type: 8; 2159 u32 con_rfk: 1; 2160 u32 rsvd: 13; 2161 2162 u32 start_time; 2163 u32 proc_time; 2164 }; 2165 2166 struct rtw89_btc_bt_smap { 2167 u32 connect: 1; 2168 u32 ble_connect: 1; 2169 u32 acl_busy: 1; 2170 u32 sco_busy: 1; 2171 u32 mesh_busy: 1; 2172 u32 inq_pag: 1; 2173 u32 profile_map: 8; 2174 u32 rsvd: 18; 2175 }; 2176 2177 union rtw89_btc_bt_state_map { 2178 u32 val; 2179 struct rtw89_btc_bt_smap map; 2180 }; 2181 2182 #define BTC_BT_RSSI_THMAX 4 2183 #define BTC_BT_AFH_GROUP 12 2184 #define BTC_BT_AFH_LE_GROUP 5 2185 2186 struct rtw89_btc_bt_txpwr_desc { 2187 s8 br_dbm; 2188 s8 le_dbm; 2189 u8 br_gain_index; 2190 u8 le_gain_index; 2191 }; 2192 2193 struct rtw89_btc_bt_leaudio_info { 2194 u8 cmd; 2195 u8 len; 2196 u8 bis_cis; 2197 #define RTW89_BTC_LEAU_INFO_L2_BIS_EX BIT(0) 2198 #define RTW89_BTC_LEAU_INFO_L2_BIS_CNT GENMASK(3, 1) 2199 #define RTW89_BTC_LEAU_INFO_L2_CIS_EX BIT(4) 2200 #define RTW89_BTC_LEAU_INFO_L2_CIS_CNT GENMASK(7, 5) 2201 u8 rssi; 2202 __le32 hbrsvd; 2203 } __packed; 2204 2205 struct rtw89_btc_bt_bistdma_info_le { 2206 u8 cmd; 2207 u8 len; 2208 u8 bis; /* BIT(2) ~ BIT(7) is rsvd */ 2209 #define RTW89_BTC_BIS_INFO_L2_START_END BIT(0) /* 0: BIS start, 1: BIS end */ 2210 #define RTW89_BTC_BIS_INFO_L2_TRX BIT(1) /* 0: BIS Tx, 1: BIS Rx */ 2211 u8 diff_t_lb; 2212 u8 diff_t_hb; /* diff_t = (diff_t_hb * 256 + diff_t_lb) * 0.625 ms */ 2213 u8 hb1rsvd; 2214 u8 hb2rsvd; 2215 u8 hb3rsvd; 2216 } __packed; 2217 2218 struct rtw89_btc_bt_leaudio_desc { 2219 u32 bis_exist: 1; 2220 u32 bis_exist_last: 1; 2221 u32 cis_exist: 1; 2222 u32 cis_exist_last: 1; 2223 u32 bis_cnt: 3; 2224 u32 cis_cnt: 3; 2225 u32 rssi: 8; 2226 u32 bis_cnt_last: 3; 2227 u32 cis_cnt_last: 3; 2228 u32 bis_trx: 1; 2229 u32 bis_start_end: 1; 2230 u32 rsvd: 6; 2231 2232 u16 diff_t; 2233 }; 2234 2235 struct rtw89_btc_bt_link_info { 2236 struct rtw89_btc_u8_sta_chg link_cnt; 2237 struct rtw89_btc_bool_sta_chg multi_link; 2238 struct rtw89_btc_bool_sta_chg relink; 2239 struct rtw89_btc_bt_hfp_desc hfp_desc; 2240 struct rtw89_btc_bt_hid_desc hid_desc; 2241 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 2242 struct rtw89_btc_bt_pan_desc pan_desc; 2243 struct rtw89_btc_bt_leaudio_desc leaudio_desc; 2244 union rtw89_btc_bt_state_map status; 2245 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc; 2246 2247 u8 sut_pwr_level[BTC_PROFILE_MAX]; 2248 u8 golden_rx_shift[BTC_PROFILE_MAX]; 2249 u8 rssi_state[BTC_BT_RSSI_THMAX]; 2250 u8 afh_map[BTC_BT_AFH_GROUP]; 2251 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 2252 u8 rssi; 2253 2254 u8 role_sw: 1; 2255 u8 slave_role: 1; 2256 u8 afh_update: 1; 2257 u8 cqddr: 1; 2258 u8 tx_3m: 1; 2259 u8 inq: 1; 2260 u8 pag: 1; 2261 u8 igno_wl: 1; 2262 2263 u8 ble_scan_en: 1; 2264 u8 reinit: 1; 2265 u8 rsvd: 6; 2266 2267 u8 leaudio_raw_info[BTC_BTINFO_MAX]; /* raw LE audio info from BT mailbox */ 2268 u8 bistdma_raw_info[BTC_BTINFO_MAX]; /* raw BIS-TDMA info from BT mailbox */ 2269 }; 2270 2271 struct rtw89_btc_bind_bt_status { 2272 u8 a2dp_active: 1; 2273 u8 a2dp_sink: 1; 2274 u8 pan_active: 1; 2275 u8 connect: 1; 2276 u8 inq_page: 1; 2277 u8 multi_link: 1; 2278 u8 slave_role: 1; 2279 u8 page: 1; 2280 2281 u8 hfp_exist: 1; 2282 u8 hid_exist: 1; 2283 u8 a2dp_exist: 1; 2284 u8 pan_exist: 1; 2285 u8 bis_exist: 1; 2286 u8 cis_exist: 1; 2287 u8 thread_exist: 1; 2288 u8 ull_exist: 1; 2289 2290 u8 hid_cnt; 2291 u8 hid_type; 2292 u8 cis_cnt; 2293 u8 link_cnt; 2294 2295 u16 a2dp_vendor_id; 2296 }; 2297 2298 struct rtw89_btc_bind_info { 2299 u8 wl_hwb_sel; /* map */ 2300 u8 wl_link_mode; 2301 u8 wl_bg_mode; 2302 u8 rf_band; /* map, 0: no any rf-band bind */ 2303 u8 bt_sel; /* map */ 2304 u8 bt_link_weight; /* select the highest weight between bt/rf-band */ 2305 2306 u32 bt_profile; /* map */ 2307 struct rtw89_btc_bind_bt_status bt_smap; 2308 }; 2309 2310 struct rtw89_btc_extsoc_info { 2311 u8 chip_id; 2312 u8 max_tx_pwr; 2313 u8 rf_band_map; 2314 u8 ant_iso_to_wl; 2315 2316 u8 link_weight[BTC_BT_BMAX]; 2317 2318 u8 func_type; /* 0: none, 1:zigbee, 2:LTE */ 2319 u8 hw_coex; /* Hard-Wire coex interface support */ 2320 u8 pta_type; /* 0: RTK 4-wire mode, 1: 3-wire mode */ 2321 u8 pta_req_exist; 2322 2323 u32 hpta_cfg; 2324 u32 hmbx_cfg; 2325 u32 swout_cfg; 2326 u32 swin_cfg; 2327 u32 profile_map[BTC_BT_BMAX]; 2328 u32 bcnt[BTC_BCNT_NUM]; 2329 }; 2330 2331 struct rtw89_btc_dm_emap { 2332 u32 init: 1; 2333 u32 pta_owner: 1; 2334 u32 wl_rfk_timeout: 1; 2335 u32 bt_rfk_timeout: 1; 2336 u32 wl_fw_hang: 1; 2337 u32 cycle_hang: 1; 2338 u32 w1_hang: 1; 2339 u32 b1_hang: 1; 2340 u32 tdma_no_sync: 1; 2341 u32 slot_no_sync: 1; 2342 u32 wl_slot_drift: 1; 2343 u32 bt_slot_drift: 1; 2344 u32 role_num_mismatch: 1; 2345 u32 null1_tx_late: 1; 2346 u32 bt_afh_conflict: 1; 2347 u32 bt_leafh_conflict: 1; 2348 u32 bt_slot_flood: 1; 2349 u32 wl_e2g_hang: 1; 2350 u32 wl_ver_mismatch: 1; 2351 u32 bt_ver_mismatch: 1; 2352 u32 rfe_type0: 1; 2353 u32 h2c_buffer_over: 1; 2354 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 2355 u32 wl_no_sta_ntfy: 1; 2356 u32 w2b_scbd_no_sync: 1; 2357 2358 u32 h2c_bmap_mismatch: 1; 2359 u32 c2h_bmap_mismatch: 1; 2360 u32 h2c_struct_invalid: 1; 2361 u32 c2h_struct_invalid: 1; 2362 u32 h2c_c2h_buffer_mismatch: 1; 2363 }; 2364 2365 union rtw89_btc_dm_error_map { 2366 u32 val; 2367 struct rtw89_btc_dm_emap map; 2368 }; 2369 2370 struct rtw89_btc_rf_para { 2371 u32 tx_pwr_freerun; 2372 u32 rx_gain_freerun; 2373 u32 tx_pwr_perpkt; 2374 u32 rx_gain_perpkt; 2375 }; 2376 2377 struct rtw89_btc_wl_nhm { 2378 u8 instant_wl_nhm_dbm; 2379 u8 instant_wl_nhm_per_mhz; 2380 u16 valid_record_times; 2381 s8 record_pwr[16]; 2382 u8 record_ratio[16]; 2383 s8 pwr; /* dbm_per_MHz */ 2384 u8 ratio; 2385 u8 current_status; 2386 u8 refresh; 2387 bool start_flag; 2388 s8 pwr_max; 2389 s8 pwr_min; 2390 }; 2391 2392 struct rtw89_btc_wl_info { 2393 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2394 struct rtw89_btc_chdef rf_ch_info[RTW89_PHY_NUM]; 2395 struct rtw89_btc_wl_rfk_info rfk_info; 2396 struct rtw89_btc_wl_ver_info ver_info; 2397 struct rtw89_btc_wl_afh_info afh_info[RTW89_MAC_NUM][RTW89_BAND_NUM]; 2398 struct rtw89_btc_wl_afh_info afh_info_last[RTW89_MAC_NUM][RTW89_BAND_NUM]; 2399 struct rtw89_btc_wl_role_info role_info; 2400 struct rtw89_btc_wl_scan_info scan_info; 2401 struct rtw89_btc_wl_dbcc_info dbcc_info; 2402 struct rtw89_btc_wl_mlo_info mlo_info; 2403 struct rtw89_btc_rf_para rf_para; 2404 struct rtw89_btc_wl_nhm nhm; 2405 union rtw89_btc_wl_state_map status; 2406 2407 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 2408 u8 rssi_level; 2409 u8 rssi; /* min WL RSSI among all active role/HW-band, 0~110% */ 2410 u8 cn_report; 2411 u8 coex_mode; 2412 u8 pta_req_mac; 2413 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 2414 u8 rf_band_map[RTW89_PHY_NUM]; /* rf_band bit-map */ 2415 u8 ch_map[12]; 2416 u8 ch_map_le[5]; 2417 2418 bool is_5g_hi_ch[RTW89_MAC_NUM]; 2419 bool go_client_exist[RTW89_MAC_NUM]; 2420 bool noa_exist[RTW89_MAC_NUM]; 2421 bool pta_reg_mac_chg; 2422 bool bg_mode[RTW89_MAC_NUM]; 2423 bool he_mode; 2424 bool scbd_chg[BTC_ALL_BT]; 2425 bool fw_ver_mismatch; 2426 bool client_cnt_inc_2g; 2427 bool link_mode_chg; 2428 bool dbcc_chg; 2429 u32 scbd[BTC_ALL_BT]; 2430 u32 scbd_rb[BTC_ALL_BT]; 2431 u32 wcnt[BTC_WCNT_NUM]; 2432 }; 2433 2434 struct rtw89_btc_module_v0 { 2435 struct rtw89_btc_ant_info_v0 ant; 2436 u8 rfe_type; 2437 u8 cv; 2438 2439 u8 bt_solo: 1; 2440 u8 bt_pos: 1; 2441 u8 switch_type: 1; 2442 u8 wa_type: 3; 2443 2444 u8 kt_ver_adie; 2445 }; 2446 2447 struct rtw89_btc_module_v7 { 2448 u8 rfe_type; 2449 u8 kt_ver; 2450 u8 bt_solo; 2451 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 2452 2453 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 2454 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 2455 u8 kt_ver_adie; 2456 u8 rsvd; 2457 2458 struct rtw89_btc_ant_info_v7 ant; 2459 } __packed; 2460 2461 struct rtw89_btc_module_v10 { 2462 u8 rfe_type; 2463 u8 wa_type; /* Refer to enum btc_wa_type */ 2464 u8 kt_ver; 2465 u8 kt_ver_adie; 2466 2467 u8 bt0_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 2468 u8 bt0_sw_type; /* BT Ant-switch: None(non-share), Int(BTG), Ext(SPDT)*/ 2469 u8 bt1_pos; /* BTC_BT_ALONE or BTC_BT_BTG */ 2470 u8 bt1_sw_type; 2471 2472 struct rtw89_btc_ant_info_v10 ant; 2473 } __packed; 2474 2475 struct rtw89_btc_module_v11 { 2476 u8 rfe_type; 2477 u8 wa_type; 2478 u8 kt_ver; 2479 u8 kt_ver_adie; 2480 2481 u8 bt0_pos; 2482 u8 bt0_sw_type; 2483 u8 bt1_pos; 2484 u8 bt1_sw_type; 2485 2486 struct rtw89_btc_ant_info_v11 ant; 2487 } __packed; 2488 2489 union rtw89_btc_module_info { 2490 struct rtw89_btc_module_v0 md_v0; 2491 struct rtw89_btc_module_v7 md_v7; 2492 struct rtw89_btc_module_v10 md_v10; 2493 struct rtw89_btc_module_v11 md_v11; 2494 }; 2495 2496 struct rtw89_btc_module { 2497 u8 rfe_type; 2498 u8 wa_type; /* Refer to enum btc_wa_type */ 2499 u8 kt_ver; 2500 u8 kt_ver_adie; 2501 2502 u8 bt0_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 2503 u8 bt0_sw_type; /* BT Ant-switch: None(non-share), Int(BTG), Ext(SPDT)*/ 2504 u8 bt1_pos; /* BTC_BT_ALONE or BTC_BT_BTG */ 2505 u8 bt1_sw_type; 2506 2507 u8 bt_solo; 2508 2509 struct rtw89_btc_ant_info ant; 2510 }; 2511 2512 #define RTW89_BTC_DM_MAXSTEP 30 2513 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 2514 2515 struct rtw89_btc_dm_step { 2516 u16 step[RTW89_BTC_DM_MAXSTEP]; 2517 u8 step_pos; 2518 bool step_ov; 2519 }; 2520 2521 struct rtw89_btc_init_info_v0 { 2522 struct rtw89_btc_module_v0 module; 2523 u8 wl_guard_ch; 2524 2525 u8 wl_only: 1; 2526 u8 wl_init_ok: 1; 2527 u8 dbcc_en: 1; 2528 u8 cx_other: 1; 2529 u8 bt_only: 1; 2530 2531 u16 rsvd; 2532 } __packed; 2533 2534 struct rtw89_btc_init_info_v7 { 2535 u8 wl_guard_ch; 2536 u8 wl_only; 2537 u8 wl_init_ok; 2538 u8 rsvd3; 2539 2540 u8 cx_other; 2541 u8 bt_only; 2542 u8 pta_mode; 2543 u8 pta_direction; 2544 2545 struct rtw89_btc_module_v7 module; 2546 } __packed; 2547 2548 struct rtw89_btc_init_info_v107 { 2549 u8 wl_guard_ch; 2550 u8 wl_only; 2551 u8 wl_init_ok; 2552 u8 dbcc_en; 2553 2554 u8 cx_other; 2555 u8 bt_only; 2556 u8 rsvd; 2557 u8 rsvd1; 2558 2559 struct rtw89_btc_module_v7 module; 2560 } __packed; 2561 2562 struct rtw89_btc_init_info_v10 { 2563 u8 endian_type; /* 0: little-endian, 1:big-endian */ 2564 u8 init_mode; /* refer to enum BTC_MODE_xxx */ 2565 u8 wl_init_ok; 2566 u8 bt0_function; 2567 2568 u8 bt1_function; 2569 u8 bt2_function; 2570 u8 pta_mode; 2571 u8 pta_direction; 2572 2573 struct rtw89_btc_module_v10 module; 2574 } __packed; 2575 2576 struct rtw89_btc_init_info_v11 { 2577 u8 endian_type; /* 0: little-endian, 1:big-endian */ 2578 u8 init_mode; /* refer to enum BTC_MODE_xxx */ 2579 u8 wl_init_ok; 2580 u8 bt0_function; 2581 2582 u8 bt1_function; 2583 u8 bt2_function; 2584 u8 pta_mode; 2585 u8 pta_direction; 2586 2587 struct rtw89_btc_module_v11 module; 2588 }; 2589 2590 union rtw89_btc_init_info_u { 2591 struct rtw89_btc_init_info_v0 init_v0; 2592 struct rtw89_btc_init_info_v7 init_v7; 2593 struct rtw89_btc_init_info_v10 init_v10; 2594 struct rtw89_btc_init_info_v107 init_v107; 2595 struct rtw89_btc_init_info_v11 init_v11; 2596 }; 2597 2598 struct rtw89_btc_init_info { 2599 u8 endian_type; /* 0: little-endian, 1:big-endian */ 2600 u8 init_mode; /* refer to enum BTC_MODE_xxx */ 2601 u8 wl_init_ok; 2602 u8 bt0_function; 2603 2604 u8 bt1_function; 2605 u8 bt2_function; 2606 u8 pta_mode; 2607 u8 pta_direction; 2608 2609 u8 dbcc_en; 2610 u8 cx_other; 2611 u8 bt_only; 2612 u8 wl_only; 2613 2614 u8 wl_guard_ch; 2615 2616 struct rtw89_btc_module module; 2617 }; 2618 2619 struct rtw89_btc_wl_tx_limit_para { 2620 u16 enable; 2621 u32 tx_time; /* unit: us */ 2622 u16 tx_retry; 2623 }; 2624 2625 struct rtw89_btc_wl_trx_nss_para { 2626 u8 tx_limit; 2627 u8 rx_limit; 2628 u8 tx_ss; 2629 u8 rx_ss; 2630 u8 tx_path; 2631 u8 rx_path; 2632 }; 2633 2634 enum rtw89_btc_bt_scan_type { 2635 BTC_SCAN_INQ = 0, 2636 BTC_SCAN_PAGE, 2637 BTC_SCAN_BLE, 2638 BTC_SCAN_INIT, 2639 BTC_SCAN_TV, 2640 BTC_SCAN_ADV, 2641 BTC_SCAN_MAX1, 2642 }; 2643 2644 enum rtw89_btc_ble_scan_type { 2645 CXSCAN_BG = 0, 2646 CXSCAN_INIT, 2647 CXSCAN_LE, 2648 CXSCAN_MAX 2649 }; 2650 2651 enum rtw89_btc_bt_func_type { 2652 BTC_BTF_NONE = 0, 2653 BTC_BTF_BT = BIT(0), 2654 BTC_BTF_ZB = BIT(1), 2655 BTC_BTF_THREAD = BIT(2), 2656 BTC_BTF_24GPRO = BIT(3), /* 2.4GHz Proprietary */ 2657 BTC_BTF_ULL = BIT(4), 2658 }; 2659 2660 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2661 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2662 #define RTW89_BTC_BT_DEF_BR_TX_PWR 10 /* in dBm */ 2663 #define RTW89_BTC_BT_DEF_LE_TX_PWR 10 2664 #define RTW89_BTC_DEFAULT_ANISO 10 2665 2666 struct rtw89_btc_bt_scan_info_v1 { 2667 __le16 win; 2668 __le16 intvl; 2669 __le32 flags; 2670 } __packed; 2671 2672 struct rtw89_btc_bt_scan_info_v2 { 2673 __le16 win; 2674 __le16 intvl; 2675 } __packed; 2676 2677 struct rtw89_btc_fbtc_btscan_v1 { 2678 u8 fver; /* btc_ver::fcxbtscan */ 2679 u8 rsvd; 2680 __le16 rsvd2; 2681 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2682 } __packed; 2683 2684 struct rtw89_btc_fbtc_btscan_v2 { 2685 u8 fver; /* btc_ver::fcxbtscan */ 2686 u8 type; 2687 __le16 rsvd2; 2688 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2689 } __packed; 2690 2691 struct rtw89_btc_fbtc_btscan_v7 { 2692 u8 fver; /* btc_ver::fcxbtscan */ 2693 u8 type; 2694 u8 rsvd0; 2695 u8 rsvd1; 2696 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2697 } __packed; 2698 2699 struct rtw89_btc_fbtc_btscan_v8 { 2700 u8 fver; /* btc_ver::fcxbtscan */ 2701 u8 type; 2702 u8 bt_id; /* 0:BT0, 1:BT1 */ 2703 u8 rsvd1; 2704 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2705 } __packed; 2706 2707 union rtw89_btc_fbtc_btscan { 2708 struct rtw89_btc_fbtc_btscan_v1 v1; 2709 struct rtw89_btc_fbtc_btscan_v2 v2; 2710 struct rtw89_btc_fbtc_btscan_v7 v7; 2711 struct rtw89_btc_fbtc_btscan_v8 v8; 2712 }; 2713 2714 struct rtw89_btc_bt_info { 2715 struct rtw89_btc_bt_link_info link_info; 2716 struct rtw89_btc_bt_link_info link_info_56g; 2717 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2718 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2719 struct rtw89_btc_bt_ver_info ver_info; 2720 struct rtw89_btc_bool_sta_chg enable; 2721 struct rtw89_btc_bool_sta_chg inq_pag; 2722 struct rtw89_btc_rf_para rf_para; 2723 union rtw89_btc_bt_rfk_info_map rfk_info; 2724 2725 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox (2.4G) */ 2726 u8 raw_info_56g[BTC_BTINFO_MAX]; /* raw bt info from mailbox (5/6G) */ 2727 u8 txpwr_info[BTC_BTINFO_MAX]; 2728 u8 link_weight[BTC_BT_BMAX]; /* Link Weight for RF-band/HWB selection */ 2729 u8 rssi_level; 2730 u8 rf_band_map; 2731 u8 func_type; 2732 u8 tx_power_now; 2733 u8 tx_power_now_6g; 2734 u8 ant_iso_to_wl; /* ant isolation between BTx and WL */ 2735 2736 u8 fw_ver_mismatch: 1; 2737 u8 band_56G_support: 1; 2738 u8 hi_lna_rx: 1; 2739 u8 lna_constrain: 3; 2740 u8 hi_lna_rx_6g: 1; 2741 u8 lna_constrain_6g: 3; 2742 u8 rsvd: 6; 2743 2744 u32 scbd; 2745 u32 scbd_rb; 2746 u32 scbd_c2h; 2747 u32 feature; 2748 2749 u32 mbx_avl: 1; 2750 u32 whql_test: 1; 2751 u32 igno_wl: 1; 2752 u32 reinit: 1; 2753 u32 ble_scan_en: 1; 2754 u32 btg_type: 1; 2755 u32 inq: 1; 2756 u32 pag: 1; 2757 u32 run_patch_code: 1; 2758 u32 scan_rx_low_pri: 1; 2759 u32 scan_info_update: 1; 2760 u32 rsvd1: 22; 2761 2762 u32 bcnt[BTC_BCNT_NUM]; 2763 }; 2764 2765 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2766 struct rtw89_btc_rf_trx_para_v0 { 2767 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2768 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2769 u8 bt_tx_power; /* decrease Tx power (dB) */ 2770 u8 bt_rx_gain; /* LNA constrain level */ 2771 }; 2772 2773 struct rtw89_btc_rf_trx_para_v9 { 2774 u32 wl_tx_power[RTW89_PHY_NUM]; /* absolute Tx power (dBm), 1's complement -5->0x85 */ 2775 u32 wl_rx_gain[RTW89_PHY_NUM]; /* rx gain table index (TBD.) */ 2776 u32 bt_tx_power[BTC_ALL_BT]; /* decrease Tx power (dB) */ 2777 u32 bt_rx_gain[BTC_ALL_BT]; /* LNA constrain level */ 2778 u32 zb_tx_power[BTC_ALL_BT]; /* 15.4 devrease Tx power (dB) */ 2779 u32 zb_rx_gain[BTC_ALL_BT]; /* 15.4 constrain level */ 2780 }; 2781 2782 struct rtw89_btc_cx { 2783 struct rtw89_btc_wl_info wl; 2784 struct rtw89_btc_bt_info bt0; 2785 struct rtw89_btc_bt_info bt1; 2786 struct rtw89_btc_extsoc_info bt_ext; 2787 struct rtw89_btc_rf_trx_para_v9 rf_para; 2788 u32 state_map; 2789 }; 2790 2791 struct rtw89_btc_fbtc_tdma { 2792 u8 type; /* btc_ver::fcxtdma */ 2793 u8 rxflctrl; 2794 u8 txflctrl; 2795 u8 bind; 2796 u8 leak_n; 2797 u8 ext_ctrl; 2798 u8 rxflctrl_role; 2799 u8 option_ctrl; 2800 } __packed; 2801 2802 struct rtw89_btc_fbtc_tdma_v3 { 2803 u8 fver; /* btc_ver::fcxtdma */ 2804 u8 rsvd; 2805 __le16 rsvd1; 2806 struct rtw89_btc_fbtc_tdma tdma; 2807 } __packed; 2808 2809 union rtw89_btc_fbtc_tdma_le32 { 2810 struct rtw89_btc_fbtc_tdma v1; 2811 struct rtw89_btc_fbtc_tdma_v3 v3; 2812 }; 2813 2814 #define CXMREG_MAX 30 2815 #define CXMREG_MAX_V2 20 2816 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2817 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2818 2819 enum rtw89_btc_bt_sta_counter { 2820 BTC_BCNT_RFK_REQ = 0, 2821 BTC_BCNT_RFK_GO = 1, 2822 BTC_BCNT_RFK_REJECT = 2, 2823 BTC_BCNT_RFK_FAIL = 3, 2824 BTC_BCNT_RFK_TIMEOUT = 4, 2825 BTC_BCNT_HI_TX = 5, 2826 BTC_BCNT_HI_RX = 6, 2827 BTC_BCNT_LO_TX = 7, 2828 BTC_BCNT_LO_RX = 8, 2829 BTC_BCNT_POLLUTED = 9, 2830 BTC_BCNT_STA_MAX 2831 }; 2832 2833 enum rtw89_btc_bt_sta_counter_v105 { 2834 BTC_BCNT_RFK_REQ_V105 = 0, 2835 BTC_BCNT_HI_TX_V105 = 1, 2836 BTC_BCNT_HI_RX_V105 = 2, 2837 BTC_BCNT_LO_TX_V105 = 3, 2838 BTC_BCNT_LO_RX_V105 = 4, 2839 BTC_BCNT_POLLUTED_V105 = 5, 2840 BTC_BCNT_STA_MAX_V105 2841 }; 2842 2843 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2844 u16 fver; /* btc_ver::fcxbtcrpt */ 2845 u16 rpt_cnt; /* tmr counters */ 2846 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2847 u32 wl_fw_cx_offload; 2848 u32 wl_fw_ver; 2849 u32 rpt_enable; 2850 u32 rpt_para; /* ms */ 2851 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2852 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2853 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2854 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2855 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2856 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2857 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2858 u32 c2h_cnt; /* fw send c2h counter */ 2859 u32 h2c_cnt; /* fw recv h2c counter */ 2860 } __packed; 2861 2862 struct rtw89_btc_fbtc_rpt_ctrl_info { 2863 __le32 cnt; /* fw report counter */ 2864 __le32 en; /* report map */ 2865 __le32 para; /* not used */ 2866 2867 __le32 cnt_c2h; /* fw send c2h counter */ 2868 __le32 cnt_h2c; /* fw recv h2c counter */ 2869 __le32 len_c2h; /* The total length of the last C2H */ 2870 2871 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2872 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2873 } __packed; 2874 2875 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2876 __le32 cx_ver; /* match which driver's coex version */ 2877 __le32 fw_ver; 2878 __le32 en; /* report map */ 2879 2880 __le16 cnt; /* fw report counter */ 2881 __le16 cnt_c2h; /* fw send c2h counter */ 2882 __le16 cnt_h2c; /* fw recv h2c counter */ 2883 __le16 len_c2h; /* The total length of the last C2H */ 2884 2885 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2886 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2887 } __packed; 2888 2889 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2890 __le16 cnt; /* fw report counter */ 2891 __le16 cnt_c2h; /* fw send c2h counter */ 2892 __le16 cnt_h2c; /* fw recv h2c counter */ 2893 __le16 len_c2h; /* The total length of the last C2H */ 2894 2895 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2896 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2897 2898 __le32 cx_ver; /* match which driver's coex version */ 2899 __le32 fw_ver; 2900 __le32 en; /* report map */ 2901 } __packed; 2902 2903 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2904 __le32 cx_ver; /* match which driver's coex version */ 2905 __le32 cx_offload; 2906 __le32 fw_ver; 2907 } __packed; 2908 2909 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2910 __le32 cnt_empty; /* a2dp empty count */ 2911 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2912 __le32 cnt_tx; 2913 __le32 cnt_ack; 2914 __le32 cnt_nack; 2915 } __packed; 2916 2917 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2918 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2919 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2920 __le32 cnt_recv; /* fw recv mailbox counter */ 2921 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2922 } __packed; 2923 2924 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2925 u8 fver; 2926 u8 rsvd; 2927 __le16 rsvd1; 2928 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2929 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2930 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2931 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2932 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2933 } __packed; 2934 2935 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2936 u8 fver; 2937 u8 rsvd; 2938 __le16 rsvd1; 2939 2940 u8 gnt_val[RTW89_PHY_NUM][4]; 2941 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2942 2943 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2944 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2945 } __packed; 2946 2947 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2948 u8 fver; 2949 u8 rsvd; 2950 __le16 rsvd1; 2951 2952 u8 gnt_val[RTW89_PHY_NUM][4]; 2953 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2954 2955 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2956 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2957 } __packed; 2958 2959 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2960 u8 fver; 2961 u8 rsvd0; 2962 u8 rsvd1; 2963 u8 rsvd2; 2964 2965 u8 gnt_val[RTW89_PHY_NUM][4]; 2966 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2967 2968 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2969 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2970 } __packed; 2971 2972 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2973 u8 fver; 2974 u8 rsvd0; 2975 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2976 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2977 2978 u8 gnt_val[RTW89_PHY_NUM][4]; 2979 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2980 2981 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2982 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2983 } __packed; 2984 2985 #define RTW89_BTC_TIME_DATE_FMT 12 2986 struct rtw89_btc_fbtc_rpt_ctrl_v9 { 2987 u8 fver; 2988 u8 ext_req_exist; 2989 u8 pta_owner; 2990 u8 rsvd; 2991 2992 u8 build_time[RTW89_BTC_TIME_DATE_FMT]; 2993 u8 build_date[RTW89_BTC_TIME_DATE_FMT]; 2994 2995 u8 gnt_val[RTW89_PHY_NUM][4]; /* gwl/gbt012 refer to struct btc_gnt_ctrl */ 2996 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2997 2998 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2999 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 3000 } __packed; 3001 3002 struct rtw89_btc_fbtc_rpt_ctrl_v11 { 3003 u8 fver; 3004 u8 rsvd0; 3005 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 3006 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 3007 3008 u8 build_time[12]; 3009 u8 build_date[12]; 3010 3011 u8 gnt_val[RTW89_PHY_NUM][8]; /* gwl/gbt012 refer to struct btc_gnt_ctrl */ 3012 __le16 bt_cnt[BTC_ALL_BT_EZL][BTC_BCNT_STA_MAX_V105]; 3013 3014 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 3015 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 3016 3017 __le32 error_code; 3018 __le32 scbd_w2b[2]; 3019 __le32 scbd_b2w[2]; 3020 } __packed; 3021 3022 struct rtw89_btc_fbtc_rpt_ctrl_v205 { 3023 u8 fver; 3024 u8 rsvd; 3025 u8 build_time[RTW89_BTC_TIME_DATE_FMT]; 3026 u8 build_date[RTW89_BTC_TIME_DATE_FMT]; 3027 __le16 rsvd1; 3028 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 3029 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 3030 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 3031 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 3032 u8 gnt_val[RTW89_PHY_NUM][4]; 3033 } __packed; 3034 3035 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 3036 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 3037 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 3038 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 3039 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 3040 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 3041 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 3042 struct rtw89_btc_fbtc_rpt_ctrl_v9 v9; 3043 struct rtw89_btc_fbtc_rpt_ctrl_v11 v11; 3044 struct rtw89_btc_fbtc_rpt_ctrl_v205 v205; 3045 }; 3046 3047 enum rtw89_fbtc_ext_ctrl_type { 3048 CXECTL_OFF = 0x0, /* tdma off */ 3049 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 3050 CXECTL_EXT = 0x2, 3051 CXECTL_MAX 3052 }; 3053 3054 union rtw89_btc_fbtc_rxflct { 3055 u8 val; 3056 u8 type: 3; 3057 u8 tgln_n: 5; 3058 }; 3059 3060 enum rtw89_btc_cxst_state { 3061 CXST_OFF = 0x0, 3062 CXST_B2W = 0x1, 3063 CXST_W1 = 0x2, 3064 CXST_W2 = 0x3, 3065 CXST_W2B = 0x4, 3066 CXST_B1 = 0x5, 3067 CXST_B2 = 0x6, 3068 CXST_B3 = 0x7, 3069 CXST_B4 = 0x8, 3070 CXST_LK = 0x9, 3071 CXST_BLK = 0xa, 3072 CXST_E2G = 0xb, 3073 CXST_E5G = 0xc, 3074 CXST_EBT = 0xd, 3075 CXST_ENULL = 0xe, 3076 CXST_WLK = 0xf, 3077 CXST_W1FDD = 0x10, 3078 CXST_B1FDD = 0x11, 3079 CXST_MAX = 0x12, 3080 }; 3081 3082 enum rtw89_btc_cxevnt { 3083 CXEVNT_TDMA_ENTRY = 0x0, 3084 CXEVNT_WL_TMR, 3085 CXEVNT_B1_TMR, 3086 CXEVNT_B2_TMR, 3087 CXEVNT_B3_TMR, 3088 CXEVNT_B4_TMR, 3089 CXEVNT_W2B_TMR, 3090 CXEVNT_B2W_TMR, 3091 CXEVNT_BCN_EARLY, 3092 CXEVNT_A2DP_EMPTY, 3093 CXEVNT_LK_END, 3094 CXEVNT_RX_ISR, 3095 CXEVNT_RX_FC0, 3096 CXEVNT_RX_FC1, 3097 CXEVNT_BT_RELINK, 3098 CXEVNT_BT_RETRY, 3099 CXEVNT_E2G, 3100 CXEVNT_E5G, 3101 CXEVNT_EBT, 3102 CXEVNT_ENULL, 3103 CXEVNT_DRV_WLK, 3104 CXEVNT_BCN_OK, 3105 CXEVNT_BT_CHANGE, 3106 CXEVNT_EBT_EXTEND, 3107 CXEVNT_E2G_NULL1, 3108 CXEVNT_B1FDD_TMR, 3109 CXEVNT_MAX 3110 }; 3111 3112 enum { 3113 CXBCN_ALL = 0x0, 3114 CXBCN_ALL_OK, 3115 CXBCN_BT_SLOT, 3116 CXBCN_BT_OK, 3117 CXBCN_MAX 3118 }; 3119 3120 enum btc_slot_type { 3121 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 3122 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 3123 CXSTYPE_NUM, 3124 }; 3125 3126 enum { /* TIME */ 3127 CXT_BT = 0x0, 3128 CXT_WL = 0x1, 3129 CXT_MAX 3130 }; 3131 3132 enum { /* TIME-A2DP */ 3133 CXT_FLCTRL_OFF = 0x0, 3134 CXT_FLCTRL_ON = 0x1, 3135 CXT_FLCTRL_MAX 3136 }; 3137 3138 enum { /* STEP TYPE */ 3139 CXSTEP_NONE = 0x0, 3140 CXSTEP_EVNT = 0x1, 3141 CXSTEP_SLOT = 0x2, 3142 CXSTEP_MAX, 3143 }; 3144 3145 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 3146 RPT_BT_AFH_SEQ_LEGACY = 0x10, 3147 RPT_BT_AFH_SEQ_LE = 0x20 3148 }; 3149 3150 enum btc_wl_gpio_debug { 3151 BTC_DBG_GNT_BT = 0, 3152 BTC_DBG_GNT_WL = 1, 3153 BTC_DBG_GNT_BT1 = 2, 3154 BTC_DBG_GNT_WL1 = 3, 3155 /* The following signals should 0-1 tiggle by each function-call */ 3156 BTC_DBG_BCN_EARLY = 4, 3157 BTC_DBG_WL_NULL0 = 5, 3158 BTC_DBG_WL_NULL1 = 6, 3159 BTC_DBG_WL_RXISR = 7, 3160 BTC_DBG_TDMA_ENTRY = 8, 3161 BTC_DBG_A2DP_EMPTY = 9, 3162 BTC_DBG_BT_RETRY = 10, 3163 /* The following signals should 0-1 tiggle by state L/H */ 3164 BTC_DBG_BT_RELINK = 11, 3165 BTC_DBG_SLOT_WL = 12, 3166 BTC_DBG_SLOT_BT = 13, 3167 /* The following signals should 0-1 tiggle by external*/ 3168 BTC_DBG_WL_ERR = 14, 3169 BTC_DBG_WL_OK = 15, 3170 /* The following signals appear only 1-active at same time*/ 3171 BTC_DBG_SLOT_B2W = 16, 3172 BTC_DBG_SLOT_W1 = 17, 3173 BTC_DBG_SLOT_W2 = 18, 3174 BTC_DBG_SLOT_W2B = 19, 3175 BTC_DBG_SLOT_B1 = 20, 3176 BTC_DBG_SLOT_B2 = 21, 3177 BTC_DBG_SLOT_B3 = 22, 3178 BTC_DBG_SLOT_B4 = 23, 3179 BTC_DBG_SLOT_LK = 24, 3180 BTC_DBG_SLOT_E2G = 25, 3181 BTC_DBG_SLOT_E5G = 26, 3182 BTC_DBG_SLOT_EBT = 27, 3183 BTC_DBG_SLOT_WLK = 28, 3184 BTC_DBG_SLOT_B1FDD = 29, 3185 BTC_DBG_BT_CHANGE = 30, 3186 /* The following signals should 0-1 tiggle by external*/ 3187 BTC_DBG_WL_CCA = 31, 3188 3189 BTC_DBG_NUM, 3190 }; 3191 3192 struct rtw89_btc_fbtc_gpio_dbg_v1 { 3193 u8 fver; /* btc_ver::fcxgpiodbg */ 3194 u8 rsvd; 3195 __le16 rsvd2; 3196 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 3197 __le32 pre_state; /* the debug signal is 1 or 0 */ 3198 u8 gpio_map[BTC_DBG_NUM]; /*the debug signals to GPIO-Position */ 3199 } __packed; 3200 3201 struct rtw89_btc_fbtc_gpio_dbg_v7 { 3202 u8 fver; 3203 u8 rsvd0; 3204 u8 rsvd1; 3205 u8 rsvd2; 3206 3207 u8 gpio_map[BTC_DBG_NUM]; 3208 3209 __le32 en_map; 3210 __le32 pre_state; 3211 } __packed; 3212 3213 union rtw89_btc_fbtc_gpio_dbg { 3214 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 3215 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 3216 }; 3217 3218 /* 3219 * SET_GPIO_CTRL payload (max len = 7 bytes) 3220 * 3221 * type = CXDGPIO_EN_MAP 3222 * data.val[31:0] = debug signal enable map 3223 * 3224 * type = CXDGPIO_MUX_MAP 3225 * data.mux.sig = debug signal id 3226 * data.mux.gpio = GPIO id 3227 * 3228 * type = CXDGPIO_EXT_HPTA / CXDGPIO_EXT_HMBX / CXDGPIO_EXT_SWOUT 3229 * data.map.map_low = GPIO 7~0 map 3230 * data.map.map_high = GPIO 15~8 map 3231 * 3232 * type = CXDGPIO_EXT_SWIN 3233 * data.swin.in_map_low = GPIO 7~0 input-en-map 3234 * data.swin.in_map_high = GPIO 15~8 input-en-map 3235 * data.swin.int_map_low = GPIO 7~0 interrupt source map 3236 * data.swin.int_map_high = GPIO 15~8 interrupt source map 3237 */ 3238 #define CXDGPIO_SET_L4 4 3239 #define CXDGPIO_SET_L2 2 3240 struct rtw89_fbtc_h2c_set_gpio_en_map { 3241 u8 type; /* gpio_type */ 3242 u8 fver; /* FCX_VER_GPIODBG */ 3243 u8 dlen; 3244 u32 en_map; 3245 }; 3246 3247 struct rtw89_fbtc_h2c_set_gpio_mux { 3248 u8 type; /* gpio_type */ 3249 u8 fver; /* FCX_VER_GPIODBG */ 3250 u8 dlen; 3251 u8 sig; 3252 u8 gpio; 3253 }; 3254 3255 struct rtw89_fbtc_h2c_set_gpio_ext_pta { 3256 u8 type; /* gpio_type */ 3257 u8 fver; /* FCX_VER_GPIODBG */ 3258 u8 dlen; 3259 u8 map_low; 3260 u8 map_high; 3261 }; 3262 3263 struct rtw89_fbtc_h2c_set_gpio_ext_mb { 3264 u8 type; /* gpio_type */ 3265 u8 fver; /* FCX_VER_GPIODBG */ 3266 u8 dlen; 3267 u8 map_low; 3268 u8 map_high; 3269 }; 3270 3271 struct rtw89_fbtc_h2c_set_gpio_ext_swout { 3272 u8 type; /* gpio_type */ 3273 u8 fver; /* FCX_VER_GPIODBG */ 3274 u8 dlen; 3275 u8 map_low; 3276 u8 map_high; 3277 }; 3278 3279 struct rtw89_fbtc_h2c_set_gpio_ext_swin { 3280 u8 type; /* gpio_type */ 3281 u8 fver; /* FCX_VER_GPIODBG */ 3282 u8 dlen; 3283 u8 in_map_low; 3284 u8 in_map_high; 3285 u8 int_map_low; 3286 u8 int_map_high; 3287 }; 3288 3289 struct rtw89_fbtc_h2c_set_gpio_2b { 3290 u8 type; /* gpio_type */ 3291 u8 fver; /* FCX_VER_GPIODBG */ 3292 u8 dlen; 3293 u8 data[CXDGPIO_SET_L2]; 3294 } __packed; 3295 3296 struct rtw89_fbtc_h2c_set_gpio_4b { 3297 u8 type; /* gpio_type */ 3298 u8 fver; /* FCX_VER_GPIODBG */ 3299 u8 dlen; 3300 u8 data[CXDGPIO_SET_L4]; 3301 } __packed; 3302 3303 union rtw89_fbtc_h2c_set_gpio_en_map_u { 3304 struct rtw89_fbtc_h2c_set_gpio_4b fmt; 3305 struct rtw89_fbtc_h2c_set_gpio_en_map data; 3306 }; 3307 3308 union rtw89_fbtc_h2c_set_gpio_mux_u { 3309 struct rtw89_fbtc_h2c_set_gpio_2b fmt; 3310 struct rtw89_fbtc_h2c_set_gpio_mux data; 3311 }; 3312 3313 union rtw89_fbtc_h2c_set_gpio_ext_pta_u { 3314 struct rtw89_fbtc_h2c_set_gpio_2b fmt; 3315 struct rtw89_fbtc_h2c_set_gpio_ext_pta data; 3316 }; 3317 3318 union rtw89_fbtc_h2c_set_gpio_ext_swin_u { 3319 struct rtw89_fbtc_h2c_set_gpio_4b fmt; 3320 struct rtw89_fbtc_h2c_set_gpio_ext_swin data; 3321 }; 3322 3323 struct rtw89_fbtc_h2c_set_gpio { 3324 union rtw89_fbtc_h2c_set_gpio_en_map_u en_map; 3325 union rtw89_fbtc_h2c_set_gpio_mux_u mux; 3326 union rtw89_fbtc_h2c_set_gpio_ext_pta_u ext_pta; 3327 union rtw89_fbtc_h2c_set_gpio_ext_pta_u ext_mb; 3328 union rtw89_fbtc_h2c_set_gpio_ext_pta_u ext_swout; 3329 union rtw89_fbtc_h2c_set_gpio_ext_swin_u ext_swin; 3330 }; 3331 3332 struct rtw89_btc_fbtc_mreg_val_v1 { 3333 u8 fver; /* btc_ver::fcxmreg */ 3334 u8 reg_num; 3335 __le16 rsvd; 3336 __le32 mreg_val[CXMREG_MAX]; 3337 } __packed; 3338 3339 struct rtw89_btc_fbtc_mreg_val_v2 { 3340 u8 fver; /* btc_ver::fcxmreg */ 3341 u8 reg_num; 3342 __le16 rsvd; 3343 __le32 mreg_val[CXMREG_MAX_V2]; 3344 } __packed; 3345 3346 struct rtw89_btc_fbtc_mreg_val_v7 { 3347 u8 fver; 3348 u8 reg_num; 3349 u8 rsvd0; 3350 u8 rsvd1; 3351 __le32 mreg_val[CXMREG_MAX_V2]; 3352 } __packed; 3353 3354 union rtw89_btc_fbtc_mreg_val { 3355 struct rtw89_btc_fbtc_mreg_val_v1 v1; 3356 struct rtw89_btc_fbtc_mreg_val_v2 v2; 3357 struct rtw89_btc_fbtc_mreg_val_v7 v7; 3358 }; 3359 3360 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 3361 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 3362 .offset = cpu_to_le32(__offset), } 3363 3364 struct rtw89_btc_fbtc_mreg { 3365 __le16 type; 3366 __le16 bytes; 3367 __le32 offset; 3368 } __packed; 3369 3370 struct rtw89_btc_fbtc_slot { 3371 __le16 dur; 3372 __le32 cxtbl; 3373 __le16 cxtype; 3374 } __packed; 3375 3376 struct rtw89_btc_fbtc_slots { 3377 u8 fver; /* btc_ver::fcxslots */ 3378 u8 tbl_num; 3379 __le16 rsvd; 3380 __le32 update_map; 3381 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 3382 } __packed; 3383 3384 struct rtw89_btc_fbtc_slot_v7 { 3385 __le16 dur; /* slot duration */ 3386 __le16 cxtype; 3387 __le32 cxtbl; 3388 } __packed; 3389 3390 struct rtw89_btc_fbtc_slots_v2 { 3391 u8 fver; /* btc_ver::fcxslots */ 3392 u8 tbl_num; 3393 __le16 rsvd; 3394 __le32 update_map; 3395 struct rtw89_btc_fbtc_slot_v7 slot[CXST_MAX]; 3396 } __packed; 3397 3398 struct rtw89_btc_fbtc_slot_u16 { 3399 __le16 dur; /* slot duration */ 3400 __le16 cxtype; 3401 __le16 cxtbl_l16; /* coex table [15:0] */ 3402 __le16 cxtbl_h16; /* coex table [31:16] */ 3403 } __packed; 3404 3405 struct rtw89_btc_fbtc_1slot_v7 { 3406 u8 fver; 3407 u8 sid; /* slot id */ 3408 __le16 rsvd; 3409 struct rtw89_btc_fbtc_slot_v7 slot; 3410 } __packed; 3411 3412 struct rtw89_btc_fbtc_slots_v7 { 3413 u8 fver; 3414 u8 slot_cnt; 3415 u8 rsvd0; 3416 u8 rsvd1; 3417 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 3418 __le32 update_map; 3419 } __packed; 3420 3421 union rtw89_btc_fbtc_slots_info { 3422 struct rtw89_btc_fbtc_slots v1; 3423 struct rtw89_btc_fbtc_slots_v2 v2; 3424 struct rtw89_btc_fbtc_slots_v7 v7; 3425 } __packed; 3426 3427 struct rtw89_btc_fbtc_step { 3428 u8 type; 3429 u8 val; 3430 __le16 difft; 3431 } __packed; 3432 3433 struct rtw89_btc_fbtc_steps_v2 { 3434 u8 fver; /* btc_ver::fcxstep */ 3435 u8 rsvd; 3436 __le16 cnt; 3437 __le16 pos_old; 3438 __le16 pos_new; 3439 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 3440 } __packed; 3441 3442 struct rtw89_btc_fbtc_steps_v3 { 3443 u8 fver; 3444 u8 en; 3445 __le16 rsvd; 3446 __le32 cnt; 3447 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 3448 } __packed; 3449 3450 union rtw89_btc_fbtc_steps_info { 3451 struct rtw89_btc_fbtc_steps_v2 v2; 3452 struct rtw89_btc_fbtc_steps_v3 v3; 3453 }; 3454 3455 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 3456 u8 fver; /* btc_ver::fcxcysta */ 3457 u8 rsvd; 3458 __le16 cycles; /* total cycle number */ 3459 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 3460 __le16 a2dpept; /* a2dp empty cnt */ 3461 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 3462 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 3463 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 3464 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 3465 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 3466 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 3467 __le16 tavg_a2dpept; /* avg a2dp empty time */ 3468 __le16 tmax_a2dpept; /* max a2dp empty time */ 3469 __le16 tavg_lk; /* avg leak-slot time */ 3470 __le16 tmax_lk; /* max leak-slot time */ 3471 __le32 slot_cnt[CXST_MAX]; /* slot count */ 3472 __le32 bcn_cnt[CXBCN_MAX]; 3473 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 3474 __le32 collision_cnt; /* counter for event/timer occur at same time */ 3475 __le32 skip_cnt; 3476 __le32 exception; 3477 __le32 except_cnt; 3478 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 3479 } __packed; 3480 3481 struct rtw89_btc_fbtc_fdd_try_info { 3482 __le16 cycles[CXT_FLCTRL_MAX]; 3483 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 3484 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 3485 } __packed; 3486 3487 struct rtw89_btc_fbtc_cycle_time_info { 3488 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 3489 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 3490 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 3491 } __packed; 3492 3493 struct rtw89_btc_fbtc_cycle_time_info_v5 { 3494 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 3495 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 3496 } __packed; 3497 3498 struct rtw89_btc_fbtc_a2dp_trx_stat { 3499 u8 empty_cnt; 3500 u8 retry_cnt; 3501 u8 tx_rate; 3502 u8 tx_cnt; 3503 u8 ack_cnt; 3504 u8 nack_cnt; 3505 u8 rsvd1; 3506 u8 rsvd2; 3507 } __packed; 3508 3509 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 3510 u8 empty_cnt; 3511 u8 retry_cnt; 3512 u8 tx_rate; 3513 u8 tx_cnt; 3514 u8 ack_cnt; 3515 u8 nack_cnt; 3516 u8 no_empty_cnt; 3517 u8 rsvd; 3518 } __packed; 3519 3520 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 3521 __le16 cnt; /* a2dp empty cnt */ 3522 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 3523 __le16 tavg; /* avg a2dp empty time */ 3524 __le16 tmax; /* max a2dp empty time */ 3525 } __packed; 3526 3527 struct rtw89_btc_fbtc_cycle_leak_info { 3528 __le32 cnt_rximr; /* the rximr occur at leak slot */ 3529 __le16 tavg; /* avg leak-slot time */ 3530 __le16 tmax; /* max leak-slot time */ 3531 } __packed; 3532 3533 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 3534 __le16 tavg; 3535 __le16 tamx; 3536 __le32 cnt_rximr; 3537 } __packed; 3538 3539 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 3540 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 3541 3542 struct rtw89_btc_fbtc_cycle_fddt_info { 3543 __le16 train_cycle; 3544 __le16 tp; 3545 3546 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 3547 s8 bt_tx_power; /* decrease Tx power (dB) */ 3548 s8 bt_rx_gain; /* LNA constrain level */ 3549 u8 no_empty_cnt; 3550 3551 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 3552 u8 cn; /* condition_num */ 3553 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 3554 u8 train_result; /* refer to enum btc_fddt_check_map */ 3555 } __packed; 3556 3557 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 3558 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 3559 3560 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 3561 __le16 train_cycle; 3562 __le16 tp; 3563 3564 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 3565 s8 bt_tx_power; /* decrease Tx power (dB) */ 3566 s8 bt_rx_gain; /* LNA constrain level */ 3567 u8 no_empty_cnt; 3568 3569 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 3570 u8 cn; /* condition_num */ 3571 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 3572 u8 train_result; /* refer to enum btc_fddt_check_map */ 3573 } __packed; 3574 3575 struct rtw89_btc_fbtc_fddt_cell_status { 3576 s8 wl_tx_pwr; 3577 s8 bt_tx_pwr; 3578 s8 bt_rx_gain; 3579 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 3580 } __packed; 3581 3582 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 3583 u8 fver; 3584 u8 rsvd; 3585 __le16 cycles; /* total cycle number */ 3586 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 3587 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 3588 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 3589 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3590 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3591 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 3592 __le32 slot_cnt[CXST_MAX]; /* slot count */ 3593 __le32 bcn_cnt[CXBCN_MAX]; 3594 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 3595 __le32 skip_cnt; 3596 __le32 except_cnt; 3597 __le32 except_map; 3598 } __packed; 3599 3600 #define FDD_TRAIN_WL_DIRECTION 2 3601 #define FDD_TRAIN_WL_RSSI_LEVEL 5 3602 #define FDD_TRAIN_BT_RSSI_LEVEL 5 3603 3604 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 3605 u8 fver; 3606 u8 rsvd; 3607 u8 collision_cnt; /* counter for event/timer occur at the same time */ 3608 u8 except_cnt; 3609 3610 __le16 skip_cnt; 3611 __le16 cycles; /* total cycle number */ 3612 3613 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 3614 __le16 slot_cnt[CXST_MAX]; /* slot count */ 3615 __le16 bcn_cnt[CXBCN_MAX]; 3616 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 3617 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 3618 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3619 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3620 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 3621 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 3622 [FDD_TRAIN_WL_RSSI_LEVEL] 3623 [FDD_TRAIN_BT_RSSI_LEVEL]; 3624 __le32 except_map; 3625 } __packed; 3626 3627 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 3628 u8 fver; 3629 u8 rsvd; 3630 u8 collision_cnt; /* counter for event/timer occur at the same time */ 3631 u8 except_cnt; 3632 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 3633 3634 __le16 skip_cnt; 3635 __le16 cycles; /* total cycle number */ 3636 3637 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 3638 __le16 slot_cnt[CXST_MAX]; /* slot count */ 3639 __le16 bcn_cnt[CXBCN_MAX]; 3640 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 3641 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 3642 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3643 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3644 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 3645 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 3646 [FDD_TRAIN_WL_RSSI_LEVEL] 3647 [FDD_TRAIN_BT_RSSI_LEVEL]; 3648 __le32 except_map; 3649 } __packed; 3650 3651 struct rtw89_btc_fbtc_cysta_v105 { 3652 u8 fver; 3653 u8 rsvd; 3654 u8 collision_cnt; 3655 u8 except_cnt; 3656 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 3657 3658 __le16 skip_cnt; 3659 __le16 cycles; 3660 3661 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 3662 __le16 slot_cnt[CXST_MAX]; 3663 __le16 bcn_cnt[CXBCN_MAX]; 3664 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 3665 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 3666 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3667 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3668 __le32 except_map; 3669 } __packed; 3670 3671 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 3672 u8 fver; 3673 u8 rsvd; 3674 u8 collision_cnt; /* counter for event/timer occur at the same time */ 3675 u8 except_cnt; 3676 3677 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 3678 3679 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3680 3681 __le16 skip_cnt; 3682 __le16 cycles; /* total cycle number */ 3683 3684 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 3685 __le16 slot_cnt[CXST_MAX]; /* slot count */ 3686 __le16 bcn_cnt[CXBCN_MAX]; 3687 3688 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 3689 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3690 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 3691 3692 __le32 except_map; 3693 } __packed; 3694 3695 struct rtw89_btc_fbtc_cysta_v8 { /* statistics for cycles */ 3696 u8 fver; 3697 u8 rsvd; 3698 u8 collision_cnt; /* counter for event/timer at the same time */ 3699 u8 except_cnt; 3700 3701 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 3702 3703 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3704 3705 __le16 skip_cnt; 3706 __le16 cycles; /* total cycle number */ 3707 __le16 rsvd1; 3708 3709 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 3710 __le16 slot_cnt[CXST_MAX]; /* slot count */ 3711 __le16 bcn_cnt[5]; /* CXBCN_BT_PROTECT_OK added in v8 */ 3712 3713 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 3714 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3715 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 3716 3717 __le32 except_map; 3718 } __packed; 3719 3720 union rtw89_btc_fbtc_cysta_info { 3721 struct rtw89_btc_fbtc_cysta_v2 v2; 3722 struct rtw89_btc_fbtc_cysta_v3 v3; 3723 struct rtw89_btc_fbtc_cysta_v4 v4; 3724 struct rtw89_btc_fbtc_cysta_v5 v5; 3725 struct rtw89_btc_fbtc_cysta_v105 v105; 3726 struct rtw89_btc_fbtc_cysta_v7 v7; 3727 struct rtw89_btc_fbtc_cysta_v8 v8; 3728 }; 3729 3730 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 3731 u8 fver; /* btc_ver::fcxnullsta */ 3732 u8 rsvd; 3733 __le16 rsvd2; 3734 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 3735 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 3736 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 3737 } __packed; 3738 3739 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 3740 u8 fver; /* btc_ver::fcxnullsta */ 3741 u8 rsvd; 3742 __le16 rsvd2; 3743 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 3744 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 3745 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 3746 } __packed; 3747 3748 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 3749 u8 fver; 3750 u8 rsvd0; 3751 u8 rsvd1; 3752 u8 rsvd2; 3753 3754 __le32 tmax[2]; 3755 __le32 tavg[2]; 3756 __le32 result[2][5]; 3757 } __packed; 3758 3759 union rtw89_btc_fbtc_cynullsta_info { 3760 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 3761 struct rtw89_btc_fbtc_cynullsta_v2 v2; 3762 struct rtw89_btc_fbtc_cynullsta_v7 v7; 3763 }; 3764 3765 struct rtw89_btc_fbtc_btver_v1 { 3766 u8 fver; /* btc_ver::fcxbtver */ 3767 u8 rsvd; 3768 __le16 rsvd2; 3769 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 3770 __le32 fw_ver; 3771 __le32 feature; 3772 } __packed; 3773 3774 struct rtw89_btc_fbtc_btver_v7 { 3775 u8 fver; 3776 u8 rsvd0; 3777 u8 rsvd1; 3778 u8 rsvd2; 3779 3780 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 3781 __le32 fw_ver; 3782 __le32 feature; 3783 } __packed; 3784 3785 struct rtw89_btc_fbtc_btver_v8 { 3786 u8 fver; 3787 u8 bt_id; /* 0:BT0, 1:BT1 */ 3788 u8 rsvd1; 3789 u8 rsvd2; 3790 3791 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 3792 __le32 fw_ver; 3793 __le32 feature; 3794 } __packed; 3795 3796 union rtw89_btc_fbtc_btver { 3797 struct rtw89_btc_fbtc_btver_v1 v1; 3798 struct rtw89_btc_fbtc_btver_v7 v7; 3799 struct rtw89_btc_fbtc_btver_v8 v8; 3800 } __packed; 3801 3802 struct rtw89_btc_fbtc_btafh { 3803 u8 fver; /* btc_ver::fcxbtafh */ 3804 u8 rsvd; 3805 __le16 rsvd2; 3806 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 3807 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 3808 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 3809 } __packed; 3810 3811 struct rtw89_btc_fbtc_btafh_v2 { 3812 u8 fver; /* btc_ver::fcxbtafh */ 3813 u8 rsvd; 3814 u8 rsvd2; 3815 u8 map_type; 3816 u8 afh_l[4]; 3817 u8 afh_m[4]; 3818 u8 afh_h[4]; 3819 u8 afh_le_a[4]; 3820 u8 afh_le_b[4]; 3821 } __packed; 3822 3823 struct rtw89_btc_fbtc_btafh_v7 { 3824 u8 fver; 3825 u8 map_type; 3826 u8 rsvd0; 3827 u8 rsvd1; 3828 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 3829 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 3830 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 3831 u8 afh_le_a[4]; 3832 u8 afh_le_b[4]; 3833 } __packed; 3834 3835 struct rtw89_btc_fbtc_btafh_v8 { 3836 u8 fver; 3837 u8 map_type; 3838 u8 bt_id; /* 0:BT0, 1:BT1 */ 3839 u8 rsvd1; 3840 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 3841 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 3842 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 3843 u8 afh_le_a[4]; 3844 u8 afh_le_b[4]; 3845 } __packed; 3846 3847 struct rtw89_btc_fbtc_btdevinfo { 3848 u8 fver; /* btc_ver::fcxbtdevinfo */ 3849 u8 rsvd; 3850 __le16 vendor_id; 3851 __le32 dev_name; /* only 24 bits valid */ 3852 __le32 flush_time; 3853 } __packed; 3854 3855 struct rtw89_btc_trx_info { 3856 u8 tx_lvl; 3857 u8 rx_lvl; 3858 u8 wl_rssi; 3859 u8 bt_rssi; 3860 3861 s8 wl_tx_power[RTW89_PHY_NUM]; /* absolute Tx power (dBm), 0xff-> no BTC control */ 3862 s8 wl_rx_gain[RTW89_PHY_NUM]; /* rx gain table index (TBD.) */ 3863 s8 bt_tx_power[BTC_ALL_BT]; /* decrease Tx power (dB) */ 3864 s8 bt_rx_gain[BTC_ALL_BT]; /* LNA constrain level */ 3865 s8 zb_tx_power[BTC_ALL_BT]; 3866 s8 zb_rx_gain[BTC_ALL_BT]; 3867 3868 u8 cn; /* condition_num */ 3869 s8 nhm; 3870 u8 bt0_profile; 3871 u8 bt1_profile; 3872 3873 u16 tx_rate; 3874 u16 rx_rate; 3875 3876 u32 tx_tp; 3877 u32 rx_tp; 3878 u32 rx_err_ratio; 3879 }; 3880 3881 enum btc_rf_path { 3882 BTC_RF_S0 = 0, 3883 BTC_RF_S1 = 1, 3884 BTC_RF_NUM, 3885 }; 3886 3887 struct rtw89_btc_fbtc_outsrc_set_info_v1 { 3888 u8 rf_band[BTC_RF_NUM]; 3889 u8 btg_rx[BTC_RF_NUM]; 3890 u8 nbtg_tx[BTC_RF_NUM]; 3891 3892 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; 3893 struct rtw89_mac_ax_wl_act wlact_set[BTC_ALL_BT]; 3894 3895 u8 pta_req_hw_band; 3896 u8 rf_gbt_source; 3897 u8 bt_enable_state; 3898 u8 wl_btg_standby_chg; 3899 3900 u8 fbd_group_en[RTW89_MAC_NUM][2]; 3901 __le16 rf_center_freq[RTW89_MAC_NUM]; 3902 __le16 fbd_group_bound[RTW89_MAC_NUM][2]; 3903 __le16 freq_diff_thres[RTW89_MAC_NUM][BTC_ALL_BT]; 3904 } __packed; 3905 3906 struct rtw89_btc_fbtc_outsrc_set_info_v6 { 3907 u8 rf_band[BTC_RF_NUM]; 3908 u8 btg_rx[BTC_RF_NUM]; 3909 u8 nbtg_tx[BTC_RF_NUM]; 3910 3911 struct rtw89_btc_gnt_ctrl gnt_set[RTW89_MAC_AX_COEX_GNT_NR]; 3912 struct rtw89_mac_ax_wl_act wlact_set[BTC_ALL_BT_EZL]; 3913 3914 u8 pta_req_hw_band; 3915 u8 rf_gbt_source; 3916 u8 bt_enable_state; 3917 u8 bt_plut_type; 3918 u8 wl_tx_limit_en; 3919 u8 fc_exec; 3920 u8 wl_btg_standby_chg; 3921 u8 rsvd; 3922 u8 bb_path_sel_bt[BTC_RF_NUM]; 3923 u8 bb_phy_sel_bt[RTW89_PHY_NUM]; 3924 u8 fbd_group_en[RTW89_MAC_NUM][2]; 3925 __le16 rf_center_freq[RTW89_MAC_NUM]; 3926 __le16 freq_diff_thres[RTW89_MAC_NUM][BTC_ALL_BT_EZL]; 3927 __le16 fbd_group_bound[RTW89_MAC_NUM][2]; 3928 __le32 wl_tx_limit_time; 3929 } __packed; 3930 3931 struct rtw89_btc_fbtc_outsrc_set_info_v7 { 3932 u8 rf_band[BTC_RF_NUM]; 3933 u8 btg_rx[BTC_RF_NUM]; 3934 u8 nbtg_tx[BTC_RF_NUM]; 3935 3936 struct rtw89_btc_gnt_ctrl gnt_set[RTW89_MAC_AX_COEX_GNT_NR]; 3937 struct rtw89_mac_ax_wl_act wlact_set[BTC_ALL_BT_EZL]; 3938 3939 u8 pta_req_hw_band; 3940 u8 rf_gbt_source; 3941 u8 bt_enable_state; 3942 u8 bt_plut_type; 3943 u8 wl_tx_limit_en; 3944 u8 fc_exec; 3945 u8 wl_btg_standby_chg; 3946 u8 option; 3947 #define OPTION_SPDT_BB BIT(0) 3948 u8 bb_path_sel_bt[BTC_RF_NUM]; 3949 u8 bb_phy_sel_bt[RTW89_PHY_NUM]; 3950 u8 fbd_group_en[RTW89_MAC_NUM][2]; 3951 __le16 rf_center_freq[RTW89_MAC_NUM]; 3952 __le16 freq_diff_thres[RTW89_MAC_NUM][BTC_ALL_BT_EZL]; 3953 __le16 fbd_group_bound[RTW89_MAC_NUM][2]; 3954 __le32 wl_tx_limit_time; 3955 } __packed; 3956 3957 struct rtw89_btc_fbtc_outsrc_set_info { 3958 u8 rf_band[BTC_RF_NUM]; /* 0:2GHz/1:5GHz for MPI_bb_hwsi_ignore_gnt_wl() */ 3959 u8 btg_rx[BTC_RF_NUM]; /* for MPI_bb_btg_bt_rx() */ 3960 u8 nbtg_tx[BTC_RF_NUM]; /* for MPI_bb_nbtg_bt_tx pre=AGC control */ 3961 3962 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */ 3963 struct rtw89_btc_gnt_ctrl gnt_set_be[RTW89_MAC_AX_COEX_GNT_NR]; 3964 struct rtw89_mac_ax_wl_act wlact_set[BTC_ALL_BT_EZL]; 3965 3966 u8 pta_req_hw_band; /* Bind PTA to HWB0 or HWB1, only for 8922a 1-PTA */ 3967 u8 rf_gbt_source; /* gbt from S0 or S1 for RF 0x2[9], only for 8922a */ 3968 3969 /* The followngs are for 8922c/d new Multi-PTA design */ 3970 /* 0:BT0/1:BT1/2:ZB on/off for MAC(0xe580[0]/0xe680[0])/ RF 0x4[3:2] */ 3971 u8 bt_enable_state; 3972 u8 bt_plut_type; /* BT polluted type, refer to enum btc_plt_map */ 3973 3974 u8 wl_tx_limit_en; 3975 u8 fc_exec; 3976 u8 wl_btg_standby_chg; /* keep RX-IQGen on in standby mode */ 3977 u8 is_spdt_bb; /* v7: BT shares an SPDT with WL at BB level */ 3978 3979 u8 bb_path_sel_bt[BTC_RF_NUM]; /* bb s0(1) select GNT_BT0 or BT1 */ 3980 u8 bb_phy_sel_bt[RTW89_PHY_NUM]; /* bb phy0(1) select GNT_BT0 or BT1 */ 3981 3982 /* forbidden group-> bit[1]:fbd rf-band, bit[0]: fbd enable */ 3983 u8 fbd_group_en[RTW89_MAC_NUM][2]; /* HWB0/1 +.Group0/1 */ 3984 3985 /* bit[15]-> 0:2G/1:5G,6G, bit[14:0]-> WL HWBx ch freq in MHz */ 3986 u16 rf_center_freq[RTW89_MAC_NUM]; /* HWB0/1 */ 3987 3988 /* 11-bit in MHz, freq diff threshold */ 3989 u16 freq_diff_thres[RTW89_MAC_NUM][BTC_ALL_BT_EZL]; /* HWB0/1 vs.BT0/1/2 */ 3990 3991 /* forbidden group boundary: [15:8]->UP, [7:0]->LO */ 3992 u16 fbd_group_bound[RTW89_MAC_NUM][2]; /* HWB0/1 +.Group0/1 */ 3993 3994 u32 wl_tx_limit_time; 3995 }; 3996 3997 union rtw89_btc_fbtc_slot_u { 3998 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 3999 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 4000 }; 4001 4002 struct rtw89_btc_fddr_cell { 4003 u8 en; 4004 u8 wl_rx_max; 4005 u8 wl_rx_min; 4006 }; 4007 4008 struct rtw89_btc_fddr_result { 4009 u8 wl_rx_limit; 4010 u8 wl_rx_limit_step[6]; /* record search process */ 4011 u8 search_cnt; /* the rx-limit search count */ 4012 u32 wl_tp; 4013 u32 wl_tp_step[6]; /* record search process */ 4014 }; 4015 4016 struct rtw89_btc_fddr_train_info { 4017 u8 rx_limit_pre; 4018 u8 rx_limit_now; 4019 4020 u32 tp_rec_cnt; 4021 u32 tp_avg_cnt; 4022 4023 u32 wl_tp_pre; 4024 u32 wl_tp_now; 4025 }; 4026 4027 struct rtw89_btc_fddr_info { 4028 u8 state; /* refer to enum btc_fddr_state */ 4029 u8 cell_now; /* wl rssi_level after filter LNA != 6 */ 4030 u8 cell_change; 4031 u8 wl_low_rate; 4032 4033 u8 tp_setup_time; /* calculate TP after this value (in second) */ 4034 u8 tp_hold_time; /* TP calculation period (in second) */ 4035 u8 wl_rssi_thres[BTC_WL_RSSI_THMAX]; /* index 0 -> Max RSSI */ 4036 4037 u8 search_mode; /* 0: search, 1:look-up */ 4038 u8 search_dir; /* 0: Max->Min, 1:Min->Max */ 4039 4040 struct rtw89_btc_fddr_train_info tctrl; /* train flag */ 4041 struct rtw89_btc_fddr_result cell_result[BTC_WL_RSSI_THMAX + 1]; 4042 struct rtw89_btc_fddr_cell cell[BTC_WL_RSSI_THMAX + 1]; /* parameters */ 4043 4044 u16 wl_rx_rate_thres; /* switch to TDD if rx_rate < this threshold */ 4045 4046 u32 nrsn_map; /* the reason map for no-run fdd-traing */ 4047 u32 wl_rx_rate_now; 4048 }; 4049 4050 struct rtw89_btc_rpt_ctrl_a2dp_empty { 4051 u32 cnt_empty; /* a2dp empty count */ 4052 u32 cnt_flowctrl; /* a2dp empty flow control counter */ 4053 u32 cnt_tx; 4054 u32 cnt_ack; 4055 u32 cnt_nack; 4056 }; 4057 4058 struct rtw89_btc_fddt_bt_stat { 4059 struct rtw89_btc_rpt_ctrl_a2dp_empty a2dp_last; 4060 u32 retry_last; 4061 }; 4062 4063 struct rtw89_btc_fddt_cell { 4064 s8 wl_pwr_min; 4065 s8 wl_pwr_max; 4066 s8 bt_pwr_dec_max; 4067 s8 bt_rx_gain; 4068 }; 4069 4070 struct rtw89_btc_fddt_fail_check { /* for cell stay in training */ 4071 u8 check_map; /* check pass condition if bit-map = 1 */ 4072 u8 bt_no_empty_cnt; /* 0-fail if no bt-empty >= th in train_cycle */ 4073 u8 wl_tp_ratio; /* 1-fail if wl tp rise ratio < th */ 4074 u8 wl_kpibtr_ratio; /* 2-fail if phase_now_tp < phase_last_tp * kpibtr_ratio */ 4075 }; 4076 4077 struct rtw89_btc_fddt_break_check { /* for cell stay in training or train-ok */ 4078 u8 check_map; /* check break condition if bit-map = 1 */ 4079 u8 bt_no_empty_cnt; /* 0-break if no empty count >= th */ 4080 u8 wl_tp_ratio; /* 1-break if wl tp ratio < th (%) */ 4081 u8 wl_tp_low_bound; /* 2-break if wl tp (in Mbps) < th */ 4082 4083 u8 cn; /* 3-break if (cn >= cn_limit) >= th cycle */ 4084 u8 cell_chg; /* 4-break if non-matched-RSSI >= th cycle */ 4085 s8 nhm_limit; /* 5-break if nhm >= th --> ill-condition */ 4086 u8 cn_limit; /* if condition number >= th --> ill-condition */ 4087 }; 4088 4089 struct rtw89_btc_fddt_time_ctrl { 4090 /* 1 TDD cycle = w1 + b1, FDD 1cycle = w1fdd-slot + b1fdd-slot */ 4091 u8 m_cycle; /* KPI Moving-Average-Cycle: 1~32 cycles */ 4092 u8 w_cycle; /* Start to calcul WKPI after this if train-phase change */ 4093 u8 k_cycle; /* Total kpi-estimate cycles for each training-step */ 4094 u8 rsvd; 4095 }; 4096 4097 struct rtw89_btc_fddt_train_info { 4098 struct rtw89_btc_fddt_time_ctrl t_ctrl; 4099 struct rtw89_btc_fddt_break_check b_chk; 4100 struct rtw89_btc_fddt_fail_check f_chk; 4101 struct rtw89_btc_fddt_cell cell_ul[5][5]; 4102 struct rtw89_btc_fddt_cell cell_dl[5][5]; 4103 }; 4104 4105 struct rtw89_btc_fddt_info { 4106 u8 type; /* refer to enum btc_fddt_type */ 4107 u8 result; /* fw send fdd-training status by c2h */ 4108 u8 state; /* refer to enum btc_fddt_state */ 4109 4110 u8 wl_iot[6]; /* wl bssid */ 4111 u16 bt_iot; /* bt vendor-id */ 4112 4113 u32 nrsn_map; /* the reason map for no-run fdd-traing */ 4114 struct rtw89_btc_fddt_bt_stat bt_stat; /* bt statistics */ 4115 struct rtw89_btc_fddt_train_info train; 4116 struct rtw89_btc_fddt_train_info train_now; 4117 }; 4118 4119 struct rtw89_btc_dm { 4120 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */ 4121 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */ 4122 union rtw89_btc_fbtc_slot_u slot; 4123 union rtw89_btc_fbtc_slot_u slot_now; 4124 struct rtw89_btc_fbtc_tdma tdma; 4125 struct rtw89_btc_fbtc_tdma tdma_now; 4126 struct rtw89_btc_gnt_ctrl gnt_set[RTW89_MAC_AX_COEX_GNT_NR]; 4127 struct rtw89_btc_gnt_ctrl gnt_val[RTW89_MAC_AX_COEX_GNT_NR]; 4128 struct rtw89_mac_ax_wl_act wlact_set[BTC_ALL_BT_EZL]; 4129 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 4130 struct rtw89_btc_rf_trx_para_v9 rf_trx_para; 4131 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 4132 struct rtw89_btc_dm_step dm_step; 4133 struct rtw89_btc_eslot_ctrl eslot_ctrl; 4134 struct rtw89_btc_trx_info trx_info; 4135 union rtw89_btc_dm_error_map error; 4136 struct rtw89_btc_bind_info tdd_bind; 4137 struct rtw89_btc_bind_info fdd_bind; 4138 struct rtw89_btc_fddt_info fddt_info; 4139 struct rtw89_btc_fddr_info fddr_info; 4140 struct rtw89_btc_wl_trx_nss_para wl_trx_nss; 4141 u32 cnt_dm[BTC_DCNT_NUM]; 4142 u32 cnt_notify[BTC_NCNT_NUM]; 4143 u8 ant_xmap[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT ANT interact-map */ 4144 u8 xtk_xmap[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* 1: If RSSI<(BT-Pin -SIR) */ 4145 u8 sit_xmap[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT space interact-map */ 4146 u8 fit_xmap[RTW89_PHY_NUM][BTC_ALL_BT_EZL]; /* HWB-BT freq interact-map */ 4147 u8 tdd_map[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT tdd-map */ 4148 u8 fdd_map[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT fdd-map */ 4149 u8 corx_map[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT Co-Rx */ 4150 /* RF-Sx view of fit_xmap, 1SS MIMO-PS applied */ 4151 u8 fit_map[BTC_RF_NUM][BTC_ALL_BT_EZL]; 4152 u8 fit_used_path; /* 1SS MIMO-PS Rx path, RF_PATH_AB if no limit */ 4153 4154 u8 sit_xmap_last[BTC_RF_NUM][BTC_ALL_BT_EZL]; 4155 u8 fit_xmap_last[RTW89_PHY_NUM][BTC_ALL_BT_EZL]; 4156 4157 u8 tdd_rssi_thres; /* The FDD/TDD switch RSSI (in %) */ 4158 u8 sir_thres; /* WL(Signal) to BT(interference Pin) ratio */ 4159 u8 sir_state[BTC_ALL_BT_EZL]; /* 1: WL RSSI > BTx-interference */ 4160 4161 u32 update_slot_map; 4162 u32 set_ant_path; 4163 u32 e2g_slot_limit; 4164 u32 e2g_slot_nulltx_time; 4165 4166 u32 wl_only: 1; 4167 u32 wl_fw_cx_offload: 1; 4168 u32 freerun: 1; 4169 u32 fddt_train: 1; 4170 u32 wl_ps_ctrl: 2; 4171 u32 wl_mimo_ps: 1; 4172 u32 leak_ap: 1; 4173 u32 noisy_level: 3; 4174 u32 coex_info_map: 8; 4175 u32 bt_only: 1; 4176 u32 wl_btg_rx: 2; 4177 u32 trx_para_level: 8; 4178 u32 wl_stb_chg: 1; 4179 u32 pta_owner: 1; 4180 4181 u32 tdma_instant_excute: 1; 4182 u32 wl_btg_rx_rb: 2; 4183 4184 u16 slot_dur[CXST_MAX]; 4185 u16 bt_slot_flood; 4186 4187 u8 run_reason; 4188 u8 run_action; 4189 u8 wl_tx_pwr_phy_map; 4190 u8 vid; 4191 u8 client_ps_tdma_on; 4192 u8 wl_trx_nss_en; 4193 u8 trx_nss_lps_done; /* 1SS re-setup done for this exit-LPS */ 4194 u8 bttrx_en_done; /* BT TRX enable last programmed to RF */ 4195 u8 bttrx_en_ack; /* which bttrx_en_done bits are trustworthy */ 4196 4197 u8 wl_pre_agc: 2; 4198 u8 wl_lna2: 1; 4199 u8 freerun_chk: 1; 4200 u8 wl_pre_agc_rb: 2; 4201 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 4202 4203 u8 slot_req_more: 1; 4204 u8 out_of_band: 1; 4205 u8 fdd_en: 1; 4206 u8 tdd_en: 1; 4207 u8 lps_ctrl_scbd: 1; 4208 u8 lps_ctrl_change: 1; 4209 u8 bis_tdma: 1; /* BIS TDMA mode active */ 4210 u8 scbd_write_instant; 4211 bool scbd_b2w_update; 4212 bool scbd_w2b_update; 4213 bool pre_agc_chg; 4214 }; 4215 4216 struct rtw89_fbtc_wl_ctrl_info { 4217 u8 rf_band_map[RTW89_MAC_NUM]; 4218 u8 rf_ch[RTW89_MAC_NUM]; 4219 4220 u8 client_pstdma_on; 4221 u8 fw_scan; 4222 u8 rfk_state; 4223 u8 rfk_type; 4224 4225 u32 smap_val; 4226 }; 4227 4228 struct rtw89_btc_ctrl { 4229 u32 manual; 4230 u32 igno_bt: 1; 4231 u32 always_freerun: 1; 4232 u32 trace_step: 16; 4233 4234 u8 wl_only; 4235 u8 bt_only; 4236 4237 u8 ntfy_type; 4238 struct rtw89_fbtc_wl_ctrl_info wl_ctrl_info; 4239 }; 4240 4241 struct rtw89_btc_ctrl_v0 { 4242 u32 manual: 1; 4243 u32 igno_bt: 1; 4244 u32 always_freerun: 1; 4245 u32 trace_step: 16; 4246 u32 rsvd: 12; 4247 } __packed; 4248 4249 struct rtw89_btc_ctrl_v7 { 4250 u8 manual; 4251 u8 igno_bt; 4252 u8 always_freerun; 4253 u8 rsvd; 4254 } __packed; 4255 4256 struct rtw89_fbtc_wl_ctrl_info_v9 { 4257 u8 rf_band_map[RTW89_MAC_NUM]; 4258 u8 rf_ch[RTW89_MAC_NUM]; 4259 4260 u8 client_pstdma_on; 4261 u8 fw_scan; 4262 u8 rfk_state; 4263 u8 rfk_type; 4264 4265 __le32 smap_val; 4266 } __packed; 4267 4268 struct rtw89_btc_ctrl_v9 { 4269 u8 manual; 4270 u8 always_freerun; 4271 u8 wl_only; 4272 u8 bt_only; 4273 4274 u8 ntfy_type; 4275 u8 rsvd0; 4276 u8 rsvd1; 4277 u8 rsvd2; 4278 4279 struct rtw89_fbtc_wl_ctrl_info_v9 wl_ctrl_info; 4280 } __packed; 4281 4282 struct rtw89_btc_dbg { 4283 /* cmd "rb" */ 4284 bool rb_done; 4285 u32 rb_val; 4286 }; 4287 4288 enum rtw89_btc_btf_fw_event { 4289 BTF_EVNT_RPT = 0, 4290 BTF_EVNT_BT_INFO = 1, 4291 BTF_EVNT_BT_SCBD = 2, 4292 BTF_EVNT_BT_REG = 3, 4293 BTF_EVNT_CX_RUNINFO = 4, 4294 BTF_EVNT_BT_PSD = 5, 4295 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 4296 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 4297 BTF_EVNT_BUF_OVERFLOW, 4298 BTF_EVNT_C2H_LOOPBACK, 4299 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */ 4300 BTF_EVNT_ZB_INFO = 11, 4301 BTF_EVNT_ZB_CH = 12, 4302 BTF_EVNT_ZB_QUERY_TXPWR = 13, 4303 BTF_EVNT_MAX, 4304 }; 4305 4306 enum btf_fw_event_report { 4307 BTC_RPT_TYPE_CTRL = 0x0, 4308 BTC_RPT_TYPE_TDMA, 4309 BTC_RPT_TYPE_SLOT, 4310 BTC_RPT_TYPE_CYSTA, 4311 BTC_RPT_TYPE_STEP, 4312 BTC_RPT_TYPE_NULLSTA, 4313 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 4314 BTC_RPT_TYPE_MREG, 4315 BTC_RPT_TYPE_GPIO_DBG, 4316 BTC_RPT_TYPE_BT_VER, 4317 BTC_RPT_TYPE_BT_SCAN, 4318 BTC_RPT_TYPE_BT_AFH, 4319 BTC_RPT_TYPE_BT_DEVICE, 4320 BTC_RPT_TYPE_TEST, 4321 BTC_RPT_TYPE_MAX = 31, 4322 4323 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 4324 __BTC_RPT_TYPE_V0_MAX = 12, 4325 }; 4326 4327 enum rtw_btc_btf_reg_type { 4328 REG_MAC = 0x0, 4329 REG_BB = 0x1, 4330 REG_RF = 0x2, 4331 REG_BT_RF = 0x3, 4332 REG_BT_MODEM = 0x4, 4333 REG_BT_BLUEWIZE = 0x5, 4334 REG_BT_VENDOR = 0x6, 4335 REG_BT_LE = 0x7, 4336 REG_MAX_TYPE, 4337 }; 4338 4339 struct rtw89_btc_rpt_cmn_info { 4340 u32 rx_cnt; 4341 u32 rx_len; 4342 u32 req_len; /* expected rsp len */ 4343 u8 req_fver; /* expected rsp fver */ 4344 u8 rsp_fver; /* fver from fw */ 4345 u8 valid; 4346 } __packed; 4347 4348 union rtw89_btc_fbtc_btafh_info { 4349 struct rtw89_btc_fbtc_btafh v1; 4350 struct rtw89_btc_fbtc_btafh_v2 v2; 4351 struct rtw89_btc_fbtc_btafh_v7 v7; 4352 struct rtw89_btc_fbtc_btafh_v8 v8; 4353 }; 4354 4355 struct rtw89_btc_report_ctrl_state { 4356 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4357 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 4358 }; 4359 4360 struct rtw89_btc_rpt_fbtc_tdma { 4361 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4362 union rtw89_btc_fbtc_tdma_le32 finfo; 4363 }; 4364 4365 struct rtw89_btc_rpt_fbtc_slots { 4366 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4367 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 4368 }; 4369 4370 struct rtw89_btc_rpt_fbtc_cysta { 4371 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4372 union rtw89_btc_fbtc_cysta_info finfo; 4373 }; 4374 4375 struct rtw89_btc_rpt_fbtc_step { 4376 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4377 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 4378 }; 4379 4380 struct rtw89_btc_rpt_fbtc_nullsta { 4381 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4382 union rtw89_btc_fbtc_cynullsta_info finfo; 4383 }; 4384 4385 struct rtw89_btc_rpt_fbtc_mreg { 4386 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4387 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 4388 }; 4389 4390 struct rtw89_btc_rpt_fbtc_gpio_dbg { 4391 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4392 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 4393 }; 4394 4395 struct rtw89_btc_rpt_fbtc_btver { 4396 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4397 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 4398 }; 4399 4400 struct rtw89_btc_rpt_fbtc_btscan { 4401 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4402 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 4403 }; 4404 4405 struct rtw89_btc_rpt_fbtc_btafh { 4406 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4407 union rtw89_btc_fbtc_btafh_info finfo; 4408 }; 4409 4410 struct rtw89_btc_rpt_fbtc_btdev { 4411 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4412 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 4413 }; 4414 4415 enum rtw89_btc_btfre_type { 4416 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 4417 BTFRE_UNDEF_TYPE, 4418 BTFRE_EXCEPTION, 4419 BTFRE_MAX, 4420 }; 4421 4422 struct rtw89_btc_ver { 4423 enum rtw89_core_chip_id chip_id; 4424 u32 fw_ver_code; 4425 4426 u8 fcxbtcrpt; 4427 u8 fcxtdma; 4428 u8 fcxslots; 4429 u8 fcxcysta; 4430 u8 fcxstep; 4431 u8 fcxnullsta; 4432 u8 fcxmreg; 4433 u8 fcxgpiodbg; 4434 u8 fcxbtver; 4435 u8 fcxbtscan; 4436 u8 fcxbtafh; 4437 u8 fcxbtdevinfo; 4438 u8 fwlrole; 4439 u8 frptmap; 4440 u8 fcxctrl; 4441 u8 fcxinit; 4442 4443 u8 fwevntrptl; 4444 u8 fwc2hfunc; 4445 u8 drvinfo_ver; 4446 u16 info_buf; 4447 u8 max_role_num; 4448 u8 fcxosi; 4449 u8 fcxmlo; 4450 u8 bt_desired; 4451 u8 fcxtrx; 4452 u8 fcxtxpwr; 4453 }; 4454 4455 struct rtw89_btc_btf_fwinfo { 4456 u32 cnt_c2h; 4457 u32 cnt_h2c; 4458 u32 cnt_h2c_fail; 4459 u32 event[BTF_EVNT_MAX]; 4460 4461 u32 err[BTFRE_MAX]; 4462 u32 len_mismch; 4463 u32 fver_mismch; 4464 u32 rpt_en_map; 4465 4466 struct rtw89_btc_ver fw_subver; 4467 struct rtw89_btc_report_ctrl_state rpt_ctrl; 4468 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 4469 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 4470 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 4471 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 4472 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 4473 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 4474 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 4475 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 4476 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 4477 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 4478 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 4479 }; 4480 4481 #define RTW89_BTC_POLICY_MAXLEN 512 4482 #define BTC_H2C_MAXLEN 2020 4483 4484 struct rtw89_btc { 4485 const struct rtw89_btc_ver *ver; 4486 4487 struct rtw89_btc_cx cx; 4488 struct rtw89_btc_dm dm; 4489 struct rtw89_btc_ctrl ctrl; 4490 struct rtw89_btc_module mdinfo; 4491 struct rtw89_btc_btf_fwinfo fwinfo; 4492 struct rtw89_btc_dbg dbg; 4493 struct rtw89_fbtc_h2c_set_gpio gpio; 4494 4495 struct wiphy_work eapol_notify_work; 4496 struct wiphy_work arp_notify_work; 4497 struct wiphy_work dhcp_notify_work; 4498 struct wiphy_work icmp_notify_work; 4499 4500 u32 bt_req_len[RTW89_PHY_NUM]; 4501 4502 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 4503 u8 hbuf[BTC_H2C_MAXLEN]; /* H2C Macro buffer */ 4504 u8 hbuf_cnt; /* H2C cmd count in buffer */ 4505 u8 ant_type; 4506 u8 btg_pos; 4507 u8 io_oflld_type; 4508 u16 policy_len; 4509 u16 policy_type; 4510 u16 hbuf_len; /* H2C used length, it sshould be <= BTC_H2C_MAXLEN */ 4511 u32 hubmsg_cnt; 4512 bool bt_req_en; 4513 bool update_policy_force; 4514 bool btc_ctrl_lps; 4515 bool manual_ctrl; 4516 bool cli_h2c_cmd; 4517 }; 4518 4519 enum rtw89_btc_hmsg { 4520 RTW89_BTC_HMSG_TMR_EN = 0x0, 4521 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 4522 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 4523 RTW89_BTC_HMSG_FW_EV = 0x3, 4524 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 4525 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 4526 4527 NUM_OF_RTW89_BTC_HMSG, 4528 }; 4529 4530 enum rtw89_ra_mode { 4531 RTW89_RA_MODE_CCK = BIT(0), 4532 RTW89_RA_MODE_OFDM = BIT(1), 4533 RTW89_RA_MODE_HT = BIT(2), 4534 RTW89_RA_MODE_VHT = BIT(3), 4535 RTW89_RA_MODE_HE = BIT(4), 4536 RTW89_RA_MODE_EHT = BIT(5), 4537 }; 4538 4539 enum rtw89_ra_report_mode { 4540 RTW89_RA_RPT_MODE_LEGACY, 4541 RTW89_RA_RPT_MODE_HT, 4542 RTW89_RA_RPT_MODE_VHT, 4543 RTW89_RA_RPT_MODE_HE, 4544 RTW89_RA_RPT_MODE_EHT, 4545 }; 4546 4547 enum rtw89_dig_noisy_level { 4548 RTW89_DIG_NOISY_LEVEL0 = -1, 4549 RTW89_DIG_NOISY_LEVEL1 = 0, 4550 RTW89_DIG_NOISY_LEVEL2 = 1, 4551 RTW89_DIG_NOISY_LEVEL3 = 2, 4552 RTW89_DIG_NOISY_LEVEL_MAX = 3, 4553 }; 4554 4555 enum rtw89_gi_ltf { 4556 RTW89_GILTF_LGI_4XHE32 = 0, 4557 RTW89_GILTF_SGI_4XHE08 = 1, 4558 RTW89_GILTF_2XHE16 = 2, 4559 RTW89_GILTF_2XHE08 = 3, 4560 RTW89_GILTF_1XHE16 = 4, 4561 RTW89_GILTF_1XHE08 = 5, 4562 RTW89_GILTF_MAX 4563 }; 4564 4565 enum rtw89_rx_frame_type { 4566 RTW89_RX_TYPE_MGNT = 0, 4567 RTW89_RX_TYPE_CTRL = 1, 4568 RTW89_RX_TYPE_DATA = 2, 4569 RTW89_RX_TYPE_RSVD = 3, 4570 }; 4571 4572 enum rtw89_efuse_block { 4573 RTW89_EFUSE_BLOCK_SYS = 0, 4574 RTW89_EFUSE_BLOCK_RF = 1, 4575 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 4576 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 4577 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 4578 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 4579 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 4580 RTW89_EFUSE_BLOCK_ADIE = 7, 4581 4582 RTW89_EFUSE_BLOCK_NUM, 4583 RTW89_EFUSE_BLOCK_IGNORE, 4584 }; 4585 4586 struct rtw89_ra_info { 4587 u8 is_dis_ra:1; 4588 /* Bit0 : CCK 4589 * Bit1 : OFDM 4590 * Bit2 : HT 4591 * Bit3 : VHT 4592 * Bit4 : HE 4593 * Bit5 : EHT 4594 */ 4595 u8 mode_ctrl:6; 4596 u8 bw_cap:3; /* enum rtw89_bandwidth */ 4597 u8 macid; 4598 u8 dcm_cap:1; 4599 u8 er_cap:1; 4600 u8 init_rate_lv:2; 4601 u8 upd_all:1; 4602 u8 en_sgi:1; 4603 u8 ldpc_cap:1; 4604 u8 stbc_cap:1; 4605 u8 ss_num:3; 4606 u8 giltf:3; 4607 u8 upd_bw_nss_mask:1; 4608 u8 upd_mask:1; 4609 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 4610 /* BFee CSI */ 4611 u8 band_num; 4612 u8 ra_csi_rate_en:1; 4613 u8 fixed_csi_rate_en:1; 4614 u8 cr_tbl_sel:1; 4615 u8 fix_giltf_en:1; 4616 u8 fix_giltf:3; 4617 u8 partial_bw_er:1; 4618 u8 csi_mcs_ss_idx; 4619 u8 csi_mode:2; 4620 u8 csi_gi_ltf:3; 4621 u8 csi_bw:3; 4622 /* after v1 */ 4623 u8 is_noisy:1; 4624 u8 psra_en:1; 4625 u8 rsvd0:1; 4626 u8 macid_msb:2; 4627 u8 band:2; /* enum rtw89_band */ 4628 u8 is_new_dbgreg:1; 4629 }; 4630 4631 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 4632 #define RTW89_PPDU_MAC_INFO_SIZE 8 4633 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 4634 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 4635 4636 struct rtw89_ampdu_params { 4637 u16 agg_num; 4638 bool amsdu; 4639 }; 4640 4641 struct rtw89_ra_report { 4642 struct rate_info txrate; 4643 u32 bit_rate; 4644 u16 hw_rate; 4645 u8 retry_ratio; 4646 bool might_fallback_legacy; 4647 }; 4648 4649 DECLARE_EWMA(rssi, 10, 16); 4650 DECLARE_EWMA(evm, 10, 16); 4651 DECLARE_EWMA(snr, 10, 16); 4652 4653 struct rtw89_ba_cam_entry { 4654 struct list_head list; 4655 u8 tid; 4656 }; 4657 4658 #define RTW89_MAX_ADDR_CAM_NUM 128 4659 #define RTW89_MAX_BSSID_CAM_NUM 20 4660 #define RTW89_MAX_SEC_CAM_NUM 128 4661 #define RTW89_MAX_BA_CAM_NUM 24 4662 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 4663 4664 struct rtw89_addr_cam_entry { 4665 u8 addr_cam_idx; 4666 u8 offset; 4667 u8 len; 4668 u8 valid : 1; 4669 u8 addr_mask : 6; 4670 u8 wapi : 1; 4671 u8 mask_sel : 2; 4672 u8 bssid_cam_idx: 6; 4673 4674 u8 sec_ent_mode; 4675 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 4676 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 4677 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 4678 }; 4679 4680 struct rtw89_bssid_cam_entry { 4681 u8 bssid[ETH_ALEN]; 4682 u8 phy_idx; 4683 u8 bssid_cam_idx; 4684 u8 offset; 4685 u8 len; 4686 u8 valid : 1; 4687 u8 num; 4688 }; 4689 4690 struct rtw89_sec_cam_entry { 4691 u8 sec_cam_idx; 4692 u8 offset; 4693 u8 len; 4694 u8 type : 4; 4695 u8 ext_key : 1; 4696 u8 spp_mode : 1; 4697 /* 256 bits */ 4698 u8 key[32]; 4699 4700 struct ieee80211_key_conf *key_conf; 4701 }; 4702 4703 struct rtw89_sta_link { 4704 struct rtw89_sta *rtwsta; 4705 struct list_head dlink_schd; 4706 unsigned int link_id; 4707 4708 u8 mac_id; 4709 u8 tx_retry; 4710 bool er_cap; 4711 struct rtw89_vif_link *rtwvif_link; 4712 struct rtw89_ra_info ra; 4713 struct rtw89_ra_report ra_report; 4714 int max_agg_wait; 4715 u8 prev_rssi; 4716 struct ewma_rssi avg_rssi; 4717 struct ewma_rssi rssi[RF_PATH_MAX]; 4718 struct ewma_snr avg_snr; 4719 struct ewma_evm evm_1ss; 4720 struct ewma_evm evm_min[RF_PATH_MAX]; 4721 struct ewma_evm evm_max[RF_PATH_MAX]; 4722 struct ieee80211_rx_status rx_status; 4723 u16 rx_hw_rate; 4724 __le32 htc_template; 4725 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 4726 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 4727 4728 bool use_cfg_mask; 4729 struct cfg80211_bitrate_mask mask; 4730 4731 bool cctl_tx_time; 4732 u32 ampdu_max_time:4; 4733 bool cctl_tx_retry_limit; 4734 u32 data_tx_cnt_lmt:6; 4735 }; 4736 4737 #define RTW89_EFUSE_SN_LEN 5 4738 #define RTW89_EFUSE_UUID_LEN 16 4739 4740 struct rtw89_efuse { 4741 bool valid; 4742 bool power_k_valid; 4743 bool vcore_valid; 4744 bool dswr_valid; 4745 u8 xtal_cap; 4746 u8 addr[ETH_ALEN]; 4747 u8 rfe_type; 4748 char country_code[2]; 4749 u8 adc_td; 4750 u8 bt_setting_2; 4751 u8 bt_setting_3; 4752 u8 sn[RTW89_EFUSE_SN_LEN]; 4753 u8 uuid[RTW89_EFUSE_UUID_LEN]; 4754 u8 vcore_vmax_reduce; 4755 u8 dswr_vmin; 4756 }; 4757 4758 struct rtw89_phy_rate_pattern { 4759 u64 ra_mask; 4760 u16 rate; 4761 u8 ra_mode; 4762 bool enable; 4763 }; 4764 4765 #define RTW89_TX_DONE 0x0 4766 #define RTW89_TX_RETRY_LIMIT 0x1 4767 #define RTW89_TX_LIFE_TIME 0x2 4768 #define RTW89_TX_MACID_DROP 0x3 4769 4770 #define RTW89_MAX_TX_RPTS 16 4771 #define RTW89_MAX_TX_RPTS_MASK (RTW89_MAX_TX_RPTS - 1) 4772 struct rtw89_tx_rpt { 4773 struct sk_buff *skbs[RTW89_MAX_TX_RPTS]; 4774 /* protect skbs array access/modification */ 4775 spinlock_t skb_lock; 4776 atomic_t sn; 4777 }; 4778 4779 #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500) 4780 struct rtw89_tx_wait_info { 4781 struct rcu_head rcu_head; 4782 struct list_head list; 4783 struct completion completion; 4784 struct sk_buff *skb; 4785 bool tx_done; 4786 }; 4787 4788 struct rtw89_tx_skb_data { 4789 struct rtw89_tx_wait_info __rcu *wait; 4790 u8 tx_rpt_sn; 4791 u8 tx_pkt_cnt_lmt; 4792 u8 hci_priv[]; 4793 }; 4794 4795 #define RTW89_SCAN_NULL_TIMEOUT 30 4796 4797 #define RTW89_ROC_IDLE_TIMEOUT 500 4798 #define RTW89_ROC_TX_TIMEOUT 30 4799 enum rtw89_roc_state { 4800 RTW89_ROC_IDLE, 4801 RTW89_ROC_NORMAL, 4802 RTW89_ROC_MGMT, 4803 }; 4804 4805 struct rtw89_roc { 4806 struct ieee80211_channel chan; 4807 struct wiphy_delayed_work roc_work; 4808 enum ieee80211_roc_type type; 4809 enum rtw89_roc_state state; 4810 int duration; 4811 unsigned int link_id; 4812 }; 4813 4814 #define RTW89_P2P_MAX_NOA_NUM 2 4815 4816 struct rtw89_p2p_ie_head { 4817 u8 eid; 4818 u8 ie_len; 4819 u8 oui[3]; 4820 u8 oui_type; 4821 } __packed; 4822 4823 struct rtw89_noa_attr_head { 4824 u8 attr_type; 4825 __le16 attr_len; 4826 u8 index; 4827 u8 oppps_ctwindow; 4828 } __packed; 4829 4830 struct rtw89_p2p_noa_ie { 4831 struct rtw89_p2p_ie_head p2p_head; 4832 struct rtw89_noa_attr_head noa_head; 4833 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 4834 } __packed; 4835 4836 struct rtw89_p2p_noa_setter { 4837 struct rtw89_p2p_noa_ie ie; 4838 u8 noa_count; 4839 u8 noa_index; 4840 }; 4841 4842 struct rtw89_ps_noa_once_handler { 4843 bool in_duration; 4844 u64 tsf_begin; 4845 u64 tsf_end; 4846 struct wiphy_delayed_work set_work; 4847 struct wiphy_delayed_work clr_work; 4848 }; 4849 4850 struct rtw89_vif_link { 4851 struct rtw89_vif *rtwvif; 4852 struct list_head dlink_schd; 4853 unsigned int link_id; 4854 4855 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 4856 enum rtw89_chanctx_idx chanctx_idx; 4857 enum rtw89_reg_6ghz_power reg_6ghz_power; 4858 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 4859 4860 u8 mac_id; 4861 u8 port; 4862 u8 mac_addr[ETH_ALEN]; 4863 u8 bssid[ETH_ALEN]; 4864 u8 phy_idx; 4865 u8 mac_idx; 4866 u8 net_type; 4867 u8 wifi_role; 4868 u8 self_role; 4869 u8 wmm; 4870 u8 bcn_hit_cond; 4871 u8 bcn_bw_idx; 4872 u8 hit_rule; 4873 u8 last_noa_nr; 4874 u64 sync_bcn_tsf; 4875 u64 last_sync_bcn_tsf; 4876 bool rand_tsf_done; 4877 bool trigger; 4878 bool lsig_txop; 4879 u8 tgt_ind; 4880 u8 frm_tgt_ind; 4881 bool wowlan_pattern; 4882 bool wowlan_uc; 4883 bool wowlan_magic; 4884 bool is_hesta; 4885 bool last_a_ctrl; 4886 bool dyn_tb_bedge_en; 4887 bool pre_pwr_diff_en; 4888 bool pwr_diff_en; 4889 u8 def_tri_idx; 4890 struct wiphy_work update_beacon_work; 4891 struct wiphy_delayed_work csa_beacon_work; 4892 struct rtw89_addr_cam_entry addr_cam; 4893 struct rtw89_bssid_cam_entry bssid_cam; 4894 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 4895 struct rtw89_phy_rate_pattern rate_pattern; 4896 struct list_head general_pkt_list; 4897 struct rtw89_p2p_noa_setter p2p_noa; 4898 struct rtw89_ps_noa_once_handler noa_once; 4899 struct wiphy_delayed_work mcc_gc_detect_beacon_work; 4900 u8 detect_bcn_count; 4901 }; 4902 4903 enum rtw89_lv1_rcvy_step { 4904 RTW89_LV1_RCVY_STEP_1, 4905 RTW89_LV1_RCVY_STEP_2, 4906 }; 4907 4908 struct rtw89_hci_ops { 4909 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 4910 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 4911 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 4912 void (*reset)(struct rtw89_dev *rtwdev); 4913 int (*start)(struct rtw89_dev *rtwdev); 4914 void (*stop)(struct rtw89_dev *rtwdev); 4915 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 4916 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 4917 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 4918 4919 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 4920 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 4921 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 4922 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 4923 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 4924 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 4925 4926 u32 (*read32_pci_cfg)(struct rtw89_dev *rtwdev, u32 addr); 4927 4928 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 4929 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 4930 int (*mac_post_init)(struct rtw89_dev *rtwdev); 4931 int (*deinit)(struct rtw89_dev *rtwdev); 4932 4933 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 4934 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 4935 void (*dump_err_status)(struct rtw89_dev *rtwdev); 4936 int (*napi_poll)(struct napi_struct *napi, int budget); 4937 4938 /* Deal with locks inside recovery_start and recovery_complete callbacks 4939 * by hci instance, and handle things which need to consider under SER. 4940 * e.g. turn on/off interrupts except for the one for halt notification. 4941 */ 4942 void (*recovery_start)(struct rtw89_dev *rtwdev); 4943 void (*recovery_complete)(struct rtw89_dev *rtwdev); 4944 4945 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 4946 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 4947 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 4948 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 4949 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 4950 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 4951 void (*disable_intr)(struct rtw89_dev *rtwdev); 4952 void (*enable_intr)(struct rtw89_dev *rtwdev); 4953 int (*rst_bdram)(struct rtw89_dev *rtwdev); 4954 }; 4955 4956 struct rtw89_hci_info { 4957 const struct rtw89_hci_ops *ops; 4958 enum rtw89_hci_type type; 4959 enum rtw89_hci_dle_type dle_type; 4960 u32 rpwm_addr; 4961 u32 cpwm_addr; 4962 bool paused; 4963 bool tx_rpt_enabled; 4964 }; 4965 4966 struct rtw89_chip_ops { 4967 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 4968 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 4969 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4970 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4971 void (*bb_reset)(struct rtw89_dev *rtwdev, 4972 enum rtw89_phy_idx phy_idx); 4973 void (*bb_sethw)(struct rtw89_dev *rtwdev); 4974 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4975 u32 addr, u32 mask); 4976 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4977 u32 addr, u32 mask, u32 data); 4978 void (*set_channel)(struct rtw89_dev *rtwdev, 4979 const struct rtw89_chan *chan, 4980 enum rtw89_mac_idx mac_idx, 4981 enum rtw89_phy_idx phy_idx); 4982 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 4983 struct rtw89_channel_help_params *p, 4984 const struct rtw89_chan *chan, 4985 enum rtw89_mac_idx mac_idx, 4986 enum rtw89_phy_idx phy_idx); 4987 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 4988 enum rtw89_efuse_block block); 4989 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 4990 void (*fem_setup)(struct rtw89_dev *rtwdev); 4991 int (*data_setup)(struct rtw89_dev *rtwdev); 4992 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 4993 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 4994 void (*rfk_init)(struct rtw89_dev *rtwdev); 4995 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 4996 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 4997 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 4998 enum rtw89_phy_idx phy_idx, 4999 const struct rtw89_chan *chan); 5000 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5001 bool start); 5002 void (*rfk_track)(struct rtw89_dev *rtwdev); 5003 void (*power_trim)(struct rtw89_dev *rtwdev); 5004 void (*set_txpwr)(struct rtw89_dev *rtwdev, 5005 const struct rtw89_chan *chan, 5006 enum rtw89_phy_idx phy_idx); 5007 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 5008 enum rtw89_phy_idx phy_idx); 5009 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 5010 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 5011 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev, 5012 const struct rtw89_chan *chan); 5013 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 5014 enum rtw89_phy_idx phy_idx); 5015 void (*query_ppdu)(struct rtw89_dev *rtwdev, 5016 struct rtw89_rx_phy_ppdu *phy_ppdu, 5017 struct ieee80211_rx_status *status); 5018 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 5019 struct rtw89_rx_phy_ppdu *phy_ppdu); 5020 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 5021 struct rtw89_rx_desc_info *desc_info, 5022 struct ieee80211_rx_status *rx_status); 5023 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 5024 enum rtw89_phy_idx phy_idx); 5025 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 5026 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 5027 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 5028 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 5029 enum rtw89_phy_idx phy_idx); 5030 void (*calc_rx_gain_normal)(struct rtw89_dev *rtwdev, 5031 const struct rtw89_chan *chan, 5032 enum rtw89_rf_path path, 5033 enum rtw89_phy_idx phy_idx, 5034 struct rtw89_phy_calc_efuse_gain *calc); 5035 void (*path_diff_update)(struct rtw89_dev *rtwdev, 5036 struct rtw89_bb_ctx *bb); 5037 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 5038 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 5039 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 5040 struct rtw89_rx_desc_info *desc_info, 5041 u8 *data, u32 data_offset); 5042 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 5043 struct rtw89_tx_desc_info *desc_info, 5044 void *txdesc); 5045 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 5046 struct rtw89_tx_desc_info *desc_info, 5047 void *txdesc); 5048 u8 (*get_ch_dma[RTW89_HCI_TYPE_NUM])(struct rtw89_dev *rtwdev, u8 qsel); 5049 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 5050 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 5051 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 5052 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 5053 u32 *tx_en, enum rtw89_sch_tx_sel sel); 5054 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 5055 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 5056 struct rtw89_vif_link *rtwvif_link, 5057 struct rtw89_sta_link *rtwsta_link); 5058 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 5059 struct rtw89_vif_link *rtwvif_link, 5060 struct rtw89_sta_link *rtwsta_link); 5061 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 5062 struct rtw89_vif_link *rtwvif_link, 5063 struct rtw89_sta_link *rtwsta_link); 5064 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 5065 struct rtw89_vif_link *rtwvif_link, 5066 struct rtw89_sta_link *rtwsta_link); 5067 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 5068 struct rtw89_sta_link *rtwsta_link); 5069 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev, 5070 struct rtw89_vif_link *rtwvif_link, 5071 u16 punctured); 5072 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 5073 struct rtw89_vif_link *rtwvif_link, 5074 struct rtw89_sta_link *rtwsta_link); 5075 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 5076 struct rtw89_vif_link *rtwvif_link); 5077 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5078 bool valid, struct ieee80211_ampdu_params *params); 5079 int (*h2c_wow_cam_update)(struct rtw89_dev *rtwdev, 5080 struct rtw89_wow_cam_info *cam_info); 5081 5082 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 5083 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 5084 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 5085 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 5086 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 5087 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 5088 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 5089 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 5090 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 5091 }; 5092 5093 enum rtw89_dma_ch { 5094 RTW89_DMA_ACH0 = 0, 5095 RTW89_DMA_ACH1 = 1, 5096 RTW89_DMA_ACH2 = 2, 5097 RTW89_DMA_ACH3 = 3, 5098 RTW89_DMA_ACH4 = 4, 5099 RTW89_DMA_ACH5 = 5, 5100 RTW89_DMA_ACH6 = 6, 5101 RTW89_DMA_ACH7 = 7, 5102 RTW89_DMA_B0MG = 8, 5103 RTW89_DMA_B0HI = 9, 5104 RTW89_DMA_B1MG = 10, 5105 RTW89_DMA_B1HI = 11, 5106 RTW89_DMA_H2C = 12, 5107 RTW89_DMA_CH_NUM = 13 5108 }; 5109 5110 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 5111 5112 enum rtw89_mlo_dbcc_mode { 5113 MLO_DBCC_NOT_SUPPORT = 1, 5114 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 5115 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 5116 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 5117 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 5118 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 5119 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 5120 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 5121 DBCC_LEGACY = 0xffffffff, 5122 }; 5123 5124 enum rtw89_scan_be_operation { 5125 RTW89_SCAN_OP_STOP, 5126 RTW89_SCAN_OP_START, 5127 RTW89_SCAN_OP_SETPARM, 5128 RTW89_SCAN_OP_GETRPT, 5129 RTW89_SCAN_OP_NUM 5130 }; 5131 5132 enum rtw89_scan_be_mode { 5133 RTW89_SCAN_MODE_SA, 5134 RTW89_SCAN_MODE_MACC, 5135 RTW89_SCAN_MODE_NUM 5136 }; 5137 5138 enum rtw89_scan_be_opmode { 5139 RTW89_SCAN_OPMODE_NONE, 5140 RTW89_SCAN_OPMODE_TBTT, 5141 RTW89_SCAN_OPMODE_INTV, 5142 RTW89_SCAN_OPMODE_CNT, 5143 RTW89_SCAN_OPMODE_NUM, 5144 }; 5145 5146 struct rtw89_scan_option { 5147 bool enable; 5148 bool target_ch_mode; 5149 u8 num_macc_role; 5150 u8 num_opch; 5151 u8 repeat; 5152 u16 norm_pd; 5153 u16 slow_pd; 5154 u16 norm_cy; 5155 u8 opch_end; 5156 u16 delay; /* in unit of ms */ 5157 u64 prohib_chan; 5158 enum rtw89_phy_idx band; 5159 enum rtw89_scan_be_operation operation; 5160 enum rtw89_scan_be_mode scan_mode; 5161 enum rtw89_mlo_dbcc_mode mlo_mode; 5162 }; 5163 5164 enum rtw89_qta_mode { 5165 RTW89_QTA_SCC, 5166 RTW89_QTA_DBCC, 5167 RTW89_QTA_DLFW, 5168 RTW89_QTA_WOW, 5169 5170 /* keep last */ 5171 RTW89_QTA_INVALID, 5172 }; 5173 5174 struct rtw89_hfc_ch_cfg { 5175 u16 min; 5176 u16 max; 5177 #define grp_0 0 5178 #define grp_1 1 5179 #define grp_num 2 5180 u8 grp; 5181 }; 5182 5183 struct rtw89_hfc_ch_info { 5184 u16 aval; 5185 u16 used; 5186 }; 5187 5188 struct rtw89_hfc_pub_cfg { 5189 u16 grp0; 5190 u16 grp1; 5191 u16 pub_max; 5192 u16 wp_thrd; 5193 }; 5194 5195 struct rtw89_hfc_pub_info { 5196 u16 g0_used; 5197 u16 g1_used; 5198 u16 g0_aval; 5199 u16 g1_aval; 5200 u16 pub_aval; 5201 u16 wp_aval; 5202 }; 5203 5204 struct rtw89_hfc_prec_cfg { 5205 u16 ch011_prec; 5206 u16 h2c_prec; 5207 u16 wp_ch07_prec; 5208 u16 wp_ch811_prec; 5209 u8 ch011_full_cond; 5210 u8 h2c_full_cond; 5211 u8 wp_ch07_full_cond; 5212 u8 wp_ch811_full_cond; 5213 /* for WiFi 7 chips after 8922D */ 5214 u16 ch011_full_page; 5215 u16 h2c_full_page; 5216 u16 wp_ch07_full_page; 5217 u16 wp_ch811_full_page; 5218 }; 5219 5220 struct rtw89_hfc_param { 5221 bool en; 5222 bool h2c_en; 5223 u8 mode; 5224 const struct rtw89_hfc_ch_cfg *ch_cfg; 5225 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 5226 struct rtw89_hfc_pub_cfg pub_cfg; 5227 struct rtw89_hfc_pub_info pub_info; 5228 struct rtw89_hfc_prec_cfg prec_cfg; 5229 }; 5230 5231 struct rtw89_hfc_param_ini { 5232 const struct rtw89_hfc_ch_cfg *ch_cfg; 5233 const struct rtw89_hfc_pub_cfg *pub_cfg; 5234 const struct rtw89_hfc_prec_cfg *prec_cfg; 5235 u8 mode; 5236 }; 5237 5238 struct rtw89_dle_size { 5239 u16 pge_size; 5240 u16 lnk_pge_num; 5241 u16 unlnk_pge_num; 5242 /* for WiFi 7 chips below (suffix v1) */ 5243 u32 srt_ofst; 5244 }; 5245 5246 struct rtw89_wde_quota { 5247 u16 hif; 5248 u16 wcpu; 5249 /* unused dcpu isn't listed */ 5250 u16 pkt_in; 5251 u16 cpu_io; 5252 }; 5253 5254 struct rtw89_ple_quota { 5255 u16 cma0_tx; 5256 u16 cma1_tx; 5257 u16 c2h; 5258 u16 h2c; 5259 u16 wcpu; 5260 u16 mpdu_proc; 5261 u16 cma0_dma; 5262 u16 cma1_dma; 5263 u16 bb_rpt; 5264 u16 wd_rel; 5265 u16 cpu_io; 5266 u16 tx_rpt; 5267 /* for WiFi 7 chips below (suffix v1) */ 5268 u16 h2d; 5269 /* for WiFi 7 chips after 8922D (suffix v2) */ 5270 u16 snrpt; 5271 }; 5272 5273 struct rtw89_rsvd_quota { 5274 u16 mpdu_info_tbl; 5275 u16 b0_csi; 5276 u16 b1_csi; 5277 u16 b0_lmr; 5278 u16 b1_lmr; 5279 u16 b0_ftm; 5280 u16 b1_ftm; 5281 u16 b0_smr; 5282 u16 b1_smr; 5283 u16 others; 5284 }; 5285 5286 struct rtw89_dle_rsvd_size { 5287 u32 srt_ofst; 5288 u32 size; 5289 }; 5290 5291 struct rtw89_dle_input { 5292 u32 tx_ampdu_num_b0; 5293 u32 tx_ampdu_num_b1; 5294 u32 tx_amsdu_size; /* unit: KB */ 5295 u32 h2c_max_size; 5296 u32 rx_amsdu_size; /* unit: KB */ 5297 u32 c2h_max_size; 5298 u32 rls_rpt_max_size; 5299 u32 mpdu_info_tbl_b0; 5300 u32 mpdu_info_tbl_b1; 5301 }; 5302 5303 struct rtw89_dle_mem { 5304 enum rtw89_qta_mode mode; 5305 const struct rtw89_dle_size *wde_size; 5306 const struct rtw89_dle_size *ple_size; 5307 const struct rtw89_wde_quota *wde_min_qt; 5308 const struct rtw89_wde_quota *wde_max_qt; 5309 const struct rtw89_ple_quota *ple_min_qt; 5310 const struct rtw89_ple_quota *ple_max_qt; 5311 /* for WiFi 7 chips below */ 5312 const struct rtw89_rsvd_quota *rsvd_qt; 5313 const struct rtw89_dle_rsvd_size *rsvd0_size; 5314 const struct rtw89_dle_rsvd_size *rsvd1_size; 5315 /* for WiFi 7 chips after 8922D */ 5316 const struct rtw89_dle_input *dle_input; 5317 }; 5318 5319 struct rtw89_reg_def { 5320 u32 addr; 5321 u32 mask; 5322 }; 5323 5324 struct rtw89_reg2_def { 5325 u32 addr; 5326 u32 data; 5327 }; 5328 5329 struct rtw89_reg3_def { 5330 u32 addr; 5331 u32 mask; 5332 u32 data; 5333 }; 5334 5335 struct rtw89_reg5_def { 5336 u8 flag; /* recognized by parsers */ 5337 u8 path; 5338 u32 addr; 5339 u32 mask; 5340 u32 data; 5341 }; 5342 5343 #define RTW89_REGS_DEF(x) {x, ARRAY_SIZE(x)} 5344 struct rtw89_regs_def { 5345 const u32 *regs; 5346 u32 reg_nr; 5347 }; 5348 5349 struct rtw89_reg_imr { 5350 u32 addr; 5351 u32 clr; 5352 u32 set; 5353 }; 5354 5355 #define RTW89_MODULE_FWNAME_PLACEHOLDER_0 0, 5356 #define __RTW89_GEN_MODULE_FWNAME_FMT(placeholder_or_ignored, strfmt) \ 5357 __take_second_arg(placeholder_or_ignored, strfmt) 5358 #define RTW89_GEN_MODULE_FWNAME_FMT(maxfmt) \ 5359 __RTW89_GEN_MODULE_FWNAME_FMT(RTW89_MODULE_FWNAME_PLACEHOLDER_ ## maxfmt, \ 5360 "-" __stringify(maxfmt)) 5361 #define RTW89_GEN_MODULE_FWNAME(basename, maxformat) \ 5362 basename RTW89_GEN_MODULE_FWNAME_FMT(maxformat) ".bin" 5363 5364 #define RTW89_FWNAME_BOARD_ELM "rtw89/board_elm.bin" 5365 5366 struct rtw89_fw_def { 5367 const char *fw_basename; 5368 u8 fw_format_max; 5369 u16 fw_b_aid; 5370 }; 5371 5372 struct rtw89_qta_def { 5373 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_DLE_TYPE_NUM]; 5374 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM]; 5375 }; 5376 5377 struct rtw89_phy_table { 5378 const struct rtw89_reg2_def *regs; 5379 u32 n_regs; 5380 enum rtw89_rf_path rf_path; 5381 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 5382 enum rtw89_rf_path rf_path, void *data); 5383 }; 5384 5385 struct rtw89_txpwr_table { 5386 const void *data; 5387 u32 size; 5388 void (*load)(struct rtw89_dev *rtwdev, 5389 const struct rtw89_txpwr_table *tbl); 5390 }; 5391 5392 struct rtw89_txpwr_rule_2ghz { 5393 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 5394 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5395 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 5396 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 5397 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 5398 }; 5399 5400 struct rtw89_txpwr_rule_5ghz { 5401 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 5402 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5403 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 5404 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 5405 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 5406 }; 5407 5408 struct rtw89_txpwr_rule_6ghz { 5409 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 5410 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5411 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 5412 [RTW89_6G_CH_NUM]; 5413 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 5414 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 5415 [RTW89_6G_CH_NUM]; 5416 }; 5417 5418 struct rtw89_tx_shape { 5419 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM] 5420 [NUM_OF_RTW89_REG_6GHZ_POWER]; 5421 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]; 5422 5423 const u8 (*lmt_v0)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 5424 const u8 (*lmt_ru_v0)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 5425 }; 5426 5427 struct rtw89_rfe_parms { 5428 const struct rtw89_txpwr_table *byr_tbl; 5429 struct rtw89_txpwr_rule_2ghz rule_2ghz; 5430 struct rtw89_txpwr_rule_5ghz rule_5ghz; 5431 struct rtw89_txpwr_rule_6ghz rule_6ghz; 5432 struct rtw89_txpwr_rule_2ghz rule_da_2ghz; 5433 struct rtw89_txpwr_rule_5ghz rule_da_5ghz; 5434 struct rtw89_txpwr_rule_6ghz rule_da_6ghz; 5435 struct rtw89_tx_shape tx_shape; 5436 bool has_da; 5437 }; 5438 5439 struct rtw89_rfe_parms_conf { 5440 const struct rtw89_rfe_parms *rfe_parms; 5441 u8 rfe_type; 5442 }; 5443 5444 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 5445 5446 struct rtw89_txpwr_conf { 5447 u8 rfe_type; 5448 u8 ent_sz; 5449 u32 num_ents; 5450 const void *data; 5451 }; 5452 5453 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 5454 const struct rtw89_txpwr_conf *conf) 5455 { 5456 u8 valid_size = min(size, conf->ent_sz); 5457 5458 memcpy(entry, cursor, valid_size); 5459 return true; 5460 } 5461 5462 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 5463 5464 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 5465 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 5466 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 5467 (cursor) += (conf)->ent_sz) \ 5468 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 5469 5470 struct rtw89_txpwr_byrate_data { 5471 struct rtw89_txpwr_conf conf; 5472 struct rtw89_txpwr_table tbl; 5473 }; 5474 5475 struct rtw89_txpwr_lmt_2ghz_data { 5476 struct rtw89_txpwr_conf conf; 5477 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 5478 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5479 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 5480 }; 5481 5482 struct rtw89_txpwr_lmt_5ghz_data { 5483 struct rtw89_txpwr_conf conf; 5484 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 5485 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5486 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 5487 }; 5488 5489 struct rtw89_txpwr_lmt_6ghz_data { 5490 struct rtw89_txpwr_conf conf; 5491 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 5492 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5493 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 5494 [RTW89_6G_CH_NUM]; 5495 }; 5496 5497 struct rtw89_txpwr_lmt_ru_2ghz_data { 5498 struct rtw89_txpwr_conf conf; 5499 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 5500 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 5501 }; 5502 5503 struct rtw89_txpwr_lmt_ru_5ghz_data { 5504 struct rtw89_txpwr_conf conf; 5505 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 5506 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 5507 }; 5508 5509 struct rtw89_txpwr_lmt_ru_6ghz_data { 5510 struct rtw89_txpwr_conf conf; 5511 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 5512 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 5513 [RTW89_6G_CH_NUM]; 5514 }; 5515 5516 struct rtw89_tx_shape_lmt_data { 5517 struct rtw89_txpwr_conf conf; 5518 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM] 5519 [NUM_OF_RTW89_REG_6GHZ_POWER]; 5520 }; 5521 5522 struct rtw89_tx_shape_lmt_ru_data { 5523 struct rtw89_txpwr_conf conf; 5524 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]; 5525 }; 5526 5527 struct rtw89_rfe_data { 5528 struct rtw89_txpwr_byrate_data byrate; 5529 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 5530 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 5531 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 5532 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz; 5533 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz; 5534 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz; 5535 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 5536 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 5537 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 5538 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz; 5539 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz; 5540 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz; 5541 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 5542 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 5543 struct rtw89_rfe_parms rfe_parms; 5544 }; 5545 5546 struct rtw89_page_regs { 5547 u32 hci_fc_ctrl; 5548 u32 ch_page_ctrl; 5549 u32 ach_page_ctrl; 5550 u32 ach_page_info; 5551 u32 pub_page_info3; 5552 u32 pub_page_ctrl1; 5553 u32 pub_page_ctrl2; 5554 u32 pub_page_info1; 5555 u32 pub_page_info2; 5556 u32 wp_page_ctrl1; 5557 u32 wp_page_ctrl2; 5558 u32 wp_page_info1; 5559 }; 5560 5561 struct rtw89_imr_info { 5562 u32 wdrls_imr_set; 5563 u32 wsec_imr_reg; 5564 u32 wsec_imr_set; 5565 u32 mpdu_tx_imr_set; 5566 u32 mpdu_rx_imr_set; 5567 u32 sta_sch_imr_set; 5568 u32 txpktctl_imr_b0_reg; 5569 u32 txpktctl_imr_b0_clr; 5570 u32 txpktctl_imr_b0_set; 5571 u32 txpktctl_imr_b1_reg; 5572 u32 txpktctl_imr_b1_clr; 5573 u32 txpktctl_imr_b1_set; 5574 u32 wde_imr_clr; 5575 u32 wde_imr_set; 5576 u32 ple_imr_clr; 5577 u32 ple_imr_set; 5578 u32 host_disp_imr_clr; 5579 u32 host_disp_imr_set; 5580 u32 cpu_disp_imr_clr; 5581 u32 cpu_disp_imr_set; 5582 u32 other_disp_imr_clr; 5583 u32 other_disp_imr_set; 5584 u32 bbrpt_com_err_imr_reg; 5585 u32 bbrpt_chinfo_err_imr_reg; 5586 u32 bbrpt_err_imr_set; 5587 u32 bbrpt_dfs_err_imr_reg; 5588 u32 ptcl_imr_clr; 5589 u32 ptcl_imr_set; 5590 u32 cdma_imr_0_reg; 5591 u32 cdma_imr_0_clr; 5592 u32 cdma_imr_0_set; 5593 u32 cdma_imr_1_reg; 5594 u32 cdma_imr_1_clr; 5595 u32 cdma_imr_1_set; 5596 u32 phy_intf_imr_reg; 5597 u32 phy_intf_imr_clr; 5598 u32 phy_intf_imr_set; 5599 u32 rmac_imr_reg; 5600 u32 rmac_imr_clr; 5601 u32 rmac_imr_set; 5602 u32 tmac_imr_reg; 5603 u32 tmac_imr_clr; 5604 u32 tmac_imr_set; 5605 }; 5606 5607 struct rtw89_imr_table { 5608 const struct rtw89_reg_imr *regs; 5609 u32 n_regs; 5610 }; 5611 5612 struct rtw89_xtal_info { 5613 u32 xcap_reg; 5614 u32 sc_xo_mask; 5615 u32 sc_xi_mask; 5616 }; 5617 5618 struct rtw89_rrsr_cfgs { 5619 struct rtw89_reg3_def ref_rate; 5620 struct rtw89_reg3_def rsc; 5621 }; 5622 5623 struct rtw89_rfkill_regs { 5624 struct rtw89_reg3_def pinmux; 5625 struct rtw89_reg3_def mode; 5626 }; 5627 5628 struct rtw89_sb_regs { 5629 struct { 5630 u32 cfg; 5631 u32 get; 5632 } n[2]; 5633 }; 5634 5635 struct rtw89_dig_regs { 5636 u32 seg0_pd_reg; 5637 u32 pd_lower_bound_mask; 5638 u32 pd_spatial_reuse_en; 5639 u32 bmode_pd_reg; 5640 u32 bmode_cca_rssi_limit_en; 5641 u32 bmode_pd_lower_bound_reg; 5642 u32 bmode_rssi_nocca_low_th_mask; 5643 struct rtw89_reg_def p0_lna_init; 5644 struct rtw89_reg_def p1_lna_init; 5645 struct rtw89_reg_def p0_tia_init; 5646 struct rtw89_reg_def p1_tia_init; 5647 struct rtw89_reg_def p0_rxb_init; 5648 struct rtw89_reg_def p1_rxb_init; 5649 struct rtw89_reg_def p0_p20_pagcugc_en; 5650 struct rtw89_reg_def p0_s20_pagcugc_en; 5651 struct rtw89_reg_def p1_p20_pagcugc_en; 5652 struct rtw89_reg_def p1_s20_pagcugc_en; 5653 }; 5654 5655 struct rtw89_edcca_regs { 5656 u32 edcca_level; 5657 u32 edcca_mask; 5658 u32 edcca_p_mask; 5659 u32 ppdu_level; 5660 u32 ppdu_mask; 5661 struct rtw89_edcca_p_regs { 5662 u32 rpt_a; 5663 u32 rpt_b; 5664 u32 rpt_sel; 5665 u32 rpt_sel_mask; 5666 } p[RTW89_PHY_NUM]; 5667 u32 rpt_sel_be; 5668 u32 rpt_sel_be_mask; 5669 u32 tx_collision_t2r_st; 5670 u32 tx_collision_t2r_st_mask; 5671 }; 5672 5673 struct rtw89_pmac_regs { 5674 struct rtw89_reg_def cck_txon; 5675 struct rtw89_reg_def cck_txen; 5676 struct rtw89_reg_def cck_cca; 5677 struct rtw89_reg_def cck_sfd_gg; 5678 struct rtw89_reg_def cck_sig_gg; 5679 struct rtw89_reg_def cck_spoofing; 5680 struct rtw89_reg_def cck_brk; 5681 struct rtw89_reg_def brk; 5682 struct rtw89_reg_def brk_option; 5683 struct rtw89_reg_def search_fail; 5684 struct rtw89_reg_def lsig_brk_s_th; 5685 struct rtw89_reg_def lsig_brk_l_th; 5686 struct rtw89_reg_def rxl_err_parity; 5687 struct rtw89_reg_def rxl_err_rate; 5688 struct rtw89_reg_def ofdm_cca; 5689 struct rtw89_reg_def cca_spoofing; 5690 struct rtw89_reg_def ampdu_miss; 5691 struct rtw89_reg_def r1b_rx_rpt_rst; 5692 struct rtw89_reg_def r1b_rr_sel; 5693 struct rtw89_reg_def enable_all_cnt; 5694 struct rtw89_reg_def rst_all_cnt; 5695 u32 cck_crc32; 5696 u32 cck_crc32_ok_mask; 5697 u32 cck_crc32_fail_mask; 5698 u32 ofdm_txon; 5699 u32 ofdm_txon_mask; 5700 u32 ofdm_txen_mask; 5701 u32 l_crc; 5702 u32 l_crc_ok_mask; 5703 u32 l_crc_err_mask; 5704 u32 ht_crc; 5705 u32 ht_crc_ok_mask; 5706 u32 ht_crc_err_mask; 5707 u32 vht_crc; 5708 u32 vht_crc_ok_mask; 5709 u32 vht_crc_err_mask; 5710 u32 he_crc; 5711 u32 he_crc_ok_mask; 5712 u32 he_crc_err_mask; 5713 u32 eht_crc; 5714 u32 eht_crc_ok_mask; 5715 u32 eht_crc_err_mask; 5716 u32 ampdu_crc; 5717 u32 ampdu_crc_ok_mask; 5718 u32 ampdu_crc_err_mask; 5719 }; 5720 5721 struct rtw89_phy_ul_tb_info { 5722 bool dyn_tb_tri_en; 5723 u8 def_if_bandedge; 5724 }; 5725 5726 struct rtw89_antdiv_stats { 5727 struct ewma_rssi cck_rssi_avg; 5728 struct ewma_rssi ofdm_rssi_avg; 5729 struct ewma_rssi non_legacy_rssi_avg; 5730 u16 pkt_cnt_cck; 5731 u16 pkt_cnt_ofdm; 5732 u16 pkt_cnt_non_legacy; 5733 u32 evm; 5734 }; 5735 5736 struct rtw89_antdiv_info { 5737 struct rtw89_antdiv_stats target_stats; 5738 struct rtw89_antdiv_stats main_stats; 5739 struct rtw89_antdiv_stats aux_stats; 5740 u8 training_count; 5741 u8 rssi_pre; 5742 bool get_stats; 5743 }; 5744 5745 struct rtw89_bb_stat_cfg { 5746 bool enable; 5747 u16 mac_id; 5748 }; 5749 5750 struct rtw89_phy_info { 5751 const struct rtw89_bb_wrap_data *bb_wrap_data; 5752 struct rtw89_bb_stat_cfg bb_stat_cfg; 5753 }; 5754 5755 enum rtw89_chanctx_state { 5756 RTW89_CHANCTX_STATE_MCC_START, 5757 RTW89_CHANCTX_STATE_MCC_STOP, 5758 }; 5759 5760 enum rtw89_chanctx_callbacks { 5761 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 5762 RTW89_CHANCTX_CALLBACK_RFK, 5763 RTW89_CHANCTX_CALLBACK_TAS, 5764 5765 NUM_OF_RTW89_CHANCTX_CALLBACKS, 5766 }; 5767 5768 struct rtw89_chanctx_listener { 5769 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 5770 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 5771 }; 5772 5773 #define RTW89_NHM_TH_NUM 11 5774 #define RTW89_NHM_RPT_NUM 12 5775 5776 #define RTW89_LED_MAX_NUM 4 5777 5778 struct rtw89_led_gpio_entry { 5779 u8 pin; 5780 unsigned int color; 5781 u8 intensity; 5782 struct rtw89_reg3_def pinmux; 5783 struct rtw89_reg2_def mode; 5784 struct rtw89_reg2_def out; 5785 }; 5786 5787 struct rtw89_led_desc { 5788 const struct rtw89_led_gpio_entry *gpios; 5789 u8 n_gpio; 5790 }; 5791 5792 struct rtw89_led { 5793 bool registered; 5794 const struct rtw89_led_desc *desc; 5795 struct led_classdev led; 5796 struct led_classdev_mc led_mc; 5797 struct mc_subled subled[RTW89_LED_MAX_NUM]; 5798 enum led_brightness brightness_cache[RTW89_LED_MAX_NUM]; 5799 char name[32]; 5800 }; 5801 5802 struct rtw89_chip_info { 5803 enum rtw89_core_chip_id chip_id; 5804 enum rtw89_chip_gen chip_gen; 5805 const struct rtw89_chip_ops *ops; 5806 const struct rtw89_mac_gen_def *mac_def; 5807 const struct rtw89_phy_gen_def *phy_def; 5808 struct rtw89_fw_def fw_def; 5809 bool try_ce_fw; 5810 u8 bbmcu_nr; 5811 u32 needed_fw_elms; 5812 const struct rtw89_fw_blacklist *fw_blacklist; 5813 u32 fifo_size; 5814 bool small_fifo_size; 5815 u32 dle_scc_rsvd_size; 5816 u16 max_amsdu_limit; 5817 u16 max_vht_mpdu_cap; 5818 u16 max_eht_mpdu_cap; 5819 u16 max_tx_agg_num; 5820 u16 max_rx_agg_num; 5821 bool dis_2g_40m_ul_ofdma; 5822 u32 rsvd_ple_ofst; 5823 struct rtw89_qta_def qta_def; 5824 u8 wde_qempty_acq_grpnum; 5825 u8 wde_qempty_mgq_grpsel; 5826 u32 rf_base_addr[2]; 5827 u8 thermal_th[2]; 5828 u8 support_macid_num; 5829 u8 support_link_num; 5830 u8 support_chanctx_num; 5831 u8 support_bands; 5832 u16 support_bandwidths; 5833 bool support_unii4; 5834 bool support_rnr; 5835 bool support_ant_gain; 5836 bool support_tas; 5837 bool support_sar_by_ant; 5838 bool support_noise; 5839 bool support_fw_cmd_ofld; 5840 bool ul_tb_waveform_ctrl; 5841 bool ul_tb_pwr_diff; 5842 bool rx_freq_from_ie; 5843 bool hw_sec_hdr; 5844 bool hw_mgmt_tx_encrypt; 5845 bool hw_tkip_crypto; 5846 bool hw_mlo_bmc_crypto; 5847 u8 rf_path_num; 5848 u8 tx_nss; 5849 u8 rx_nss; 5850 u8 acam_num; 5851 u8 bcam_num; 5852 u8 scam_num; 5853 u8 bacam_num; 5854 u8 bacam_dynamic_num; 5855 enum rtw89_bacam_ver bacam_ver; 5856 u8 addrcam_ver; 5857 u8 ppdu_max_usr; 5858 5859 u8 sec_ctrl_efuse_size; 5860 u32 physical_efuse_size; 5861 u32 logical_efuse_size; 5862 u32 limit_efuse_size; 5863 u32 dav_phy_efuse_size; 5864 u32 dav_log_efuse_size; 5865 u32 phycap_addr; 5866 u32 phycap_size; 5867 const struct rtw89_efuse_block_cfg *efuse_blocks; 5868 5869 const struct rtw89_pwr_cfg * const *pwr_on_seq; 5870 const struct rtw89_pwr_cfg * const *pwr_off_seq; 5871 const struct rtw89_phy_table *bb_table; 5872 const struct rtw89_phy_table *bb_gain_table; 5873 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 5874 const struct rtw89_phy_table *nctl_table; 5875 const struct rtw89_rfk_tbl *nctl_post_table; 5876 const struct rtw89_phy_dig_gain_table *dig_table; 5877 const struct rtw89_dig_regs *dig_regs; 5878 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 5879 5880 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 5881 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 5882 const struct rtw89_rfe_parms *dflt_parms; 5883 const struct rtw89_chanctx_listener *chanctx_listener; 5884 5885 u8 txpwr_factor_bb; 5886 u8 txpwr_factor_rf; 5887 u8 txpwr_factor_mac; 5888 5889 u32 para_ver; 5890 u32 wlcx_desired; 5891 u8 scbd; 5892 u8 mailbox; 5893 5894 u8 afh_guard_ch; 5895 u16 fdd_iso_freq; 5896 const u8 *wl_rssi_thres; 5897 const u8 *bt_rssi_thres; 5898 u8 rssi_tol; 5899 5900 u8 mon_reg_num; 5901 const struct rtw89_btc_fbtc_mreg *mon_reg; 5902 const struct rtw89_btc_rf_trx_para_v0 *rf_para_ulink_v0; 5903 const struct rtw89_btc_rf_trx_para_v0 *rf_para_dlink_v0; 5904 u8 rf_para_ulink_num_v0; 5905 u8 rf_para_dlink_num_v0; 5906 const struct rtw89_btc_rf_trx_para_v9 *rf_para_ulink_v9; 5907 const struct rtw89_btc_rf_trx_para_v9 *rf_para_dlink_v9; 5908 u8 rf_para_ulink_num_v9; 5909 u8 rf_para_dlink_num_v9; 5910 u8 ps_mode_supported; 5911 u8 low_power_hci_modes; 5912 5913 u32 h2c_cctl_func_id; 5914 u32 hci_func_en_addr; 5915 u32 h2c_desc_size; 5916 u32 txwd_body_size; 5917 u32 txwd_info_size; 5918 u32 h2c_ctrl_reg; 5919 const u32 *h2c_regs; 5920 struct rtw89_reg_def h2c_counter_reg; 5921 u32 c2h_ctrl_reg; 5922 const u32 *c2h_regs; 5923 struct rtw89_reg_def c2h_counter_reg; 5924 const struct rtw89_page_regs *page_regs; 5925 const u32 *wow_reason_reg; 5926 bool cfo_src_fd; 5927 bool cfo_hw_comp; 5928 const struct rtw89_reg_def *dcfo_comp; 5929 u8 dcfo_comp_sft; 5930 const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM]; 5931 const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM]; 5932 const struct rtw89_imr_info *imr_info; 5933 const struct rtw89_imr_table *imr_dmac_table; 5934 const struct rtw89_imr_table *imr_cmac_table; 5935 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 5936 struct rtw89_reg_def bss_clr_vld; 5937 u32 bss_clr_map_reg; 5938 const struct rtw89_rfkill_regs *rfkill_init; 5939 struct rtw89_reg_def rfkill_get; 5940 struct rtw89_sb_regs btc_sb; 5941 u32 dma_ch_mask; 5942 const struct rtw89_edcca_regs *edcca_regs; 5943 const struct rtw89_pmac_regs *pmac_regs; 5944 const struct wiphy_wowlan_support *wowlan_stub; 5945 const struct rtw89_xtal_info *xtal_info; 5946 unsigned long default_quirks; /* bitmap of rtw89_quirks */ 5947 u16 txtime_limit_2ghz; 5948 }; 5949 5950 struct rtw89_chip_variant { 5951 bool no_mcs_12_13: 1; 5952 u32 fw_min_ver_code; 5953 const struct rtw89_fw_def *fw_def_override; 5954 const struct rtw89_qta_def *qta_def_override; 5955 }; 5956 5957 /* @pid can have extra suffix to describe the variant if necessary */ 5958 #define RTW89_BOARD_ID(vid, pid) \ 5959 RTW89_BOARD_ID_##vid##_##pid 5960 5961 enum rtw89_board_id { 5962 RTW89_BOARD_ID(0000, 0000) = 0, /* reserve 0 for non-variant */ 5963 RTW89_BOARD_ID(28de, 2432) = 1, 5964 5965 NUM_OF_RTW89_BOARD_IDS, 5966 }; 5967 5968 struct rtw89_board_variant { 5969 enum rtw89_board_id id; 5970 const struct rtw89_led_desc *led_desc; 5971 }; 5972 5973 union rtw89_bus_info { 5974 const struct rtw89_pci_info *pci; 5975 const struct rtw89_usb_info *usb; 5976 }; 5977 5978 struct rtw89_driver_info { 5979 const struct rtw89_chip_info *chip; 5980 const struct rtw89_chip_variant *variant; 5981 const struct rtw89_board_variant *board; 5982 const struct dmi_system_id *quirks; 5983 unsigned long dev_id_quirks; /* bitmap of rtw89_quirks */ 5984 union rtw89_bus_info bus; 5985 }; 5986 5987 enum rtw89_hcifc_mode { 5988 RTW89_HCIFC_POH = 0, 5989 RTW89_HCIFC_STF = 1, 5990 RTW89_HCIFC_SDIO = 2, 5991 5992 /* keep last */ 5993 RTW89_HCIFC_MODE_INVALID, 5994 }; 5995 5996 struct rtw89_dle_info { 5997 const struct rtw89_rsvd_quota *rsvd_qt; 5998 const struct rtw89_dle_input *dle_input; 5999 enum rtw89_qta_mode qta_mode; 6000 u16 ple_pg_size; 6001 u16 ple_free_pg; 6002 u16 c0_rx_qta; 6003 u16 c1_rx_qta; 6004 }; 6005 6006 enum rtw89_host_rpr_mode { 6007 RTW89_RPR_MODE_POH = 0, 6008 RTW89_RPR_MODE_STF 6009 }; 6010 6011 #define RTW89_COMPLETION_BUF_SIZE 40 6012 #define RTW89_WAIT_COND_IDLE UINT_MAX 6013 6014 struct rtw89_completion_data { 6015 bool err; 6016 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 6017 }; 6018 6019 struct rtw89_wait_response { 6020 struct rcu_head rcu_head; 6021 struct completion completion; 6022 struct rtw89_completion_data data; 6023 }; 6024 6025 struct rtw89_wait_info { 6026 atomic_t cond; 6027 struct rtw89_completion_data data; 6028 struct rtw89_wait_response __rcu *resp; 6029 }; 6030 6031 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 6032 6033 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 6034 { 6035 rcu_assign_pointer(wait->resp, NULL); 6036 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 6037 } 6038 6039 struct rtw89_mac_info { 6040 struct rtw89_dle_info dle_info; 6041 struct rtw89_hfc_param hfc_param; 6042 enum rtw89_qta_mode qta_mode; 6043 u8 rpwm_seq_num; 6044 u8 cpwm_seq_num; 6045 6046 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 6047 struct rtw89_wait_info fw_ofld_wait; 6048 /* see RTW89_PS_WAIT_COND series for wait condition */ 6049 struct rtw89_wait_info ps_wait; 6050 }; 6051 6052 enum rtw89_fwdl_check_type { 6053 RTW89_FWDL_CHECK_FREERTOS_DONE, 6054 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 6055 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 6056 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 6057 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 6058 }; 6059 6060 enum rtw89_fw_type { 6061 RTW89_FW_NORMAL = 1, 6062 RTW89_FW_WOWLAN = 3, 6063 RTW89_FW_NORMAL_CE = 5, 6064 RTW89_FW_NORMAL_B = 14, 6065 RTW89_FW_WOWLAN_B = 15, 6066 RTW89_FW_BBMCU0 = 64, 6067 RTW89_FW_BBMCU1 = 65, 6068 RTW89_FW_LOGFMT = 255, 6069 }; 6070 6071 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \ 6072 RTW89_FW_FEATURE_##_grp##_MIN, \ 6073 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \ 6074 _features \ 6075 __RTW89_FW_FEATURE_##_grp##_E, \ 6076 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1 6077 6078 enum rtw89_fw_feature { 6079 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 6080 RTW89_FW_FEATURE_SCAN_OFFLOAD, 6081 RTW89_FW_FEATURE_TX_WAKE, 6082 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER, 6083 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0, 6084 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1, 6085 ), 6086 RTW89_FW_FEATURE_NO_PACKET_DROP, 6087 RTW89_FW_FEATURE_NO_DEEP_PS, 6088 RTW89_FW_FEATURE_NO_LPS_PG, 6089 RTW89_FW_FEATURE_BEACON_FILTER, 6090 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 6091 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 6092 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V1, 6093 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V2, 6094 RTW89_FW_FEATURE_WOW_REASON_V1, 6095 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, 6096 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 6097 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 6098 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V2, 6099 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V3, 6100 ), 6101 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY_MCC, 6102 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V0, 6103 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V1, 6104 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V2, 6105 ), 6106 RTW89_FW_FEATURE_RFK_RXDCK_V0, 6107 RTW89_FW_FEATURE_RFK_IQK_V0, 6108 RTW89_FW_FEATURE_RFK_TXIQK_V0, 6109 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 6110 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 6111 RTW89_FW_FEATURE_CH_INFO_BE_V0, 6112 RTW89_FW_FEATURE_CH_INFO_BE_V1, 6113 RTW89_FW_FEATURE_LPS_CH_INFO, 6114 RTW89_FW_FEATURE_NO_PHYCAP_P1, 6115 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 6116 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1, 6117 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP, 6118 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0, 6119 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG, 6120 RTW89_FW_FEATURE_BEACON_TRACKING, 6121 RTW89_FW_FEATURE_ADDR_CAM_V0, 6122 RTW89_FW_FEATURE_SER_L1_BY_EVENT, 6123 RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C, 6124 RTW89_FW_FEATURE_LPS_ML_INFO_V1, 6125 RTW89_FW_FEATURE_LPS_ML_INFO_V1_EXTRA, 6126 RTW89_FW_FEATURE_SER_POST_RECOVER_DMAC, 6127 RTW89_FW_FEATURE_TX_HISTORY_V1, 6128 RTW89_FW_FEATURE_NO_DRV_BT_TXRX_EN, 6129 6130 NUM_OF_RTW89_FW_FEATURES, 6131 }; 6132 6133 struct rtw89_fw_suit { 6134 enum rtw89_fw_type type; 6135 const u8 *data; 6136 struct list_head list; 6137 u32 size; 6138 u8 major_ver; 6139 u8 minor_ver; 6140 u8 sub_ver; 6141 u8 sub_idex; 6142 u16 build_year; 6143 u16 build_mon; 6144 u16 build_date; 6145 u16 build_hour; 6146 u16 build_min; 6147 u8 cmd_ver; 6148 u8 hdr_ver; 6149 u32 commitid; 6150 }; 6151 6152 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 6153 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 6154 #define RTW89_FW_SUIT_VER_CODE(s) \ 6155 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 6156 6157 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 6158 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 6159 (mfw_hdr)->ver.minor, \ 6160 (mfw_hdr)->ver.sub, \ 6161 (mfw_hdr)->ver.idx) 6162 6163 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 6164 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 6165 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 6166 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 6167 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 6168 6169 struct rtw89_fw_req_info { 6170 const struct firmware *firmware; 6171 const struct firmware *board_elm; 6172 struct completion completion; 6173 bool free_after_probe; 6174 }; 6175 6176 struct rtw89_fw_log { 6177 struct rtw89_fw_suit suit; 6178 bool enable; 6179 u32 last_fmt_id; 6180 u32 fmt_count; 6181 const __le32 *fmt_ids; 6182 const char *(*fmts)[]; 6183 }; 6184 6185 struct rtw89_fw_elm_info { 6186 struct rtw89_phy_table *bb_tbl; 6187 struct rtw89_phy_table *bb_gain; 6188 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 6189 struct rtw89_phy_table *rf_nctl; 6190 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 6191 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 6192 const struct rtw89_regd_data *regd; 6193 const struct rtw89_fw_element_hdr *afe; 6194 const struct rtw89_fw_element_hdr *diag_mac; 6195 const struct rtw89_fw_element_hdr *tx_comp; 6196 }; 6197 6198 enum rtw89_fw_mss_dev_type { 6199 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 6200 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 6201 }; 6202 6203 struct rtw89_fw_secure { 6204 bool secure_boot: 1; 6205 bool can_mss_v1: 1; 6206 bool can_mss_v0: 1; 6207 u32 sb_sel_mgn; 6208 u8 mss_dev_type; 6209 u8 mss_cust_idx; 6210 u8 mss_key_num; 6211 u8 mss_idx; /* v0 */ 6212 }; 6213 6214 struct rtw89_fw_info { 6215 struct rtw89_fw_req_info req; 6216 int fw_format; 6217 u8 h2c_seq; 6218 u8 rec_seq; 6219 u8 h2c_counter; 6220 u8 c2h_counter; 6221 struct rtw89_fw_suit normal; 6222 struct rtw89_fw_suit wowlan; 6223 struct rtw89_fw_suit bbmcu0; 6224 struct rtw89_fw_suit bbmcu1; 6225 struct rtw89_fw_log log; 6226 struct rtw89_fw_elm_info elm_info; 6227 struct rtw89_fw_secure sec; 6228 6229 struct list_head dup_data_list; 6230 6231 DECLARE_BITMAP(feature_map, NUM_OF_RTW89_FW_FEATURES); 6232 }; 6233 6234 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 6235 test_bit(RTW89_FW_FEATURE_ ## _feat, (_fw)->feature_map) 6236 6237 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \ 6238 ({ \ 6239 unsigned int bit = find_next_bit((_fw)->feature_map, \ 6240 NUM_OF_RTW89_FW_FEATURES, \ 6241 RTW89_FW_FEATURE_ ## _grp ## _MIN); \ 6242 bit <= RTW89_FW_FEATURE_ ## _grp ## _MAX; \ 6243 }) 6244 6245 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 6246 set_bit(_fw_feature, (_fw)->feature_map) 6247 6248 #define RTW89_CLR_FW_FEATURE(_fw_feature, _fw) \ 6249 clear_bit(_fw_feature, (_fw)->feature_map) 6250 6251 struct rtw89_cam_info { 6252 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 6253 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 6254 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 6255 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 6256 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 6257 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 6258 }; 6259 6260 enum rtw89_sar_sources { 6261 RTW89_SAR_SOURCE_NONE, 6262 RTW89_SAR_SOURCE_COMMON, 6263 RTW89_SAR_SOURCE_ACPI, 6264 6265 RTW89_SAR_SOURCE_NR, 6266 }; 6267 6268 enum rtw89_sar_subband { 6269 RTW89_SAR_2GHZ_SUBBAND, 6270 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 6271 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 6272 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 6273 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 6274 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 6275 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 6276 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 6277 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 6278 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 6279 6280 RTW89_SAR_SUBBAND_NR, 6281 }; 6282 6283 struct rtw89_sar_cfg_common { 6284 bool set[RTW89_SAR_SUBBAND_NR]; 6285 s32 cfg[RTW89_SAR_SUBBAND_NR]; 6286 }; 6287 6288 enum rtw89_acpi_sar_subband { 6289 RTW89_ACPI_SAR_2GHZ_SUBBAND, 6290 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */ 6291 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */ 6292 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 6293 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 6294 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 6295 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 6296 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 6297 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 6298 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 6299 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 6300 6301 NUM_OF_RTW89_ACPI_SAR_SUBBAND, 6302 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1, 6303 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1, 6304 }; 6305 6306 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */ 6307 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX 6308 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN 6309 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6 6310 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1) 6311 6312 struct rtw89_sar_entry_from_acpi { 6313 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 6314 }; 6315 6316 struct rtw89_sar_table_from_acpi { 6317 /* If this table is active, must fill all fields according to either 6318 * configuration in BIOS or some default values for SAR to work well. 6319 */ 6320 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM]; 6321 }; 6322 6323 struct rtw89_sar_indicator_from_acpi { 6324 bool enable_sync; 6325 unsigned int fields; 6326 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath); 6327 6328 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path. 6329 * Not design with pointers since addresses will be invalid after 6330 * sync content with local container instance. 6331 */ 6332 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 6333 }; 6334 6335 struct rtw89_sar_cfg_acpi { 6336 u8 downgrade_2tx; 6337 unsigned int valid_num; 6338 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL]; 6339 struct rtw89_sar_indicator_from_acpi indicator; 6340 }; 6341 6342 struct rtw89_sar_info { 6343 /* used to decide how to access SAR cfg union */ 6344 enum rtw89_sar_sources src; 6345 6346 /* reserved for different knids of SAR cfg struct. 6347 * supposed that a single cfg struct cannot handle various SAR sources. 6348 */ 6349 union { 6350 struct rtw89_sar_cfg_common cfg_common; 6351 struct rtw89_sar_cfg_acpi cfg_acpi; 6352 }; 6353 }; 6354 6355 enum rtw89_ant_gain_subband { 6356 RTW89_ANT_GAIN_2GHZ_SUBBAND, 6357 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 6358 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 6359 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 6360 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 6361 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 6362 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 6363 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 6364 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 6365 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 6366 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 6367 6368 RTW89_ANT_GAIN_SUBBAND_NR, 6369 }; 6370 6371 enum rtw89_ant_gain_domain_type { 6372 RTW89_ANT_GAIN_ETSI = 0, 6373 6374 RTW89_ANT_GAIN_DOMAIN_NUM, 6375 }; 6376 6377 #define RTW89_ANT_GAIN_CHAIN_NUM 2 6378 struct rtw89_ant_gain_info { 6379 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 6380 u32 regd_enabled; 6381 bool block_country; 6382 }; 6383 6384 struct rtw89_6ghz_span { 6385 enum rtw89_sar_subband sar_subband_low; 6386 enum rtw89_sar_subband sar_subband_high; 6387 enum rtw89_acpi_sar_subband acpi_sar_subband_low; 6388 enum rtw89_acpi_sar_subband acpi_sar_subband_high; 6389 enum rtw89_ant_gain_subband ant_gain_subband_low; 6390 enum rtw89_ant_gain_subband ant_gain_subband_high; 6391 }; 6392 6393 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 6394 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high) 6395 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 6396 6397 enum rtw89_tas_state { 6398 RTW89_TAS_STATE_DPR_OFF, 6399 RTW89_TAS_STATE_DPR_ON, 6400 RTW89_TAS_STATE_STATIC_SAR, 6401 }; 6402 6403 #define RTW89_TAS_TX_RATIO_WINDOW 6 6404 #define RTW89_TAS_TXPWR_WINDOW 180 6405 struct rtw89_tas_info { 6406 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 6407 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 6408 u8 enabled_countries; 6409 u8 txpwr_head_idx; 6410 u8 txpwr_tail_idx; 6411 u8 tx_ratio_idx; 6412 u16 total_tx_ratio; 6413 u64 total_txpwr; 6414 u64 instant_txpwr; 6415 u32 window_size; 6416 s8 dpr_on_threshold; 6417 s8 dpr_off_threshold; 6418 enum rtw89_tas_state backup_state; 6419 enum rtw89_tas_state state; 6420 bool keep_history; 6421 bool block_regd; 6422 bool enable; 6423 bool pause; 6424 }; 6425 6426 struct rtw89_chanctx_cfg { 6427 enum rtw89_chanctx_idx idx; 6428 int ref_count; 6429 }; 6430 6431 enum rtw89_chanctx_changes { 6432 RTW89_CHANCTX_REMOTE_STA_CHANGE, 6433 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 6434 RTW89_CHANCTX_P2P_PS_CHANGE, 6435 RTW89_CHANCTX_BT_SLOT_CHANGE, 6436 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 6437 6438 NUM_OF_RTW89_CHANCTX_CHANGES, 6439 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 6440 }; 6441 6442 enum rtw89_entity_mode { 6443 RTW89_ENTITY_MODE_SCC_OR_SMLD, 6444 RTW89_ENTITY_MODE_MCC_PREPARE, 6445 RTW89_ENTITY_MODE_MCC, 6446 6447 NUM_OF_RTW89_ENTITY_MODE, 6448 RTW89_ENTITY_MODE_INVALID = -EINVAL, 6449 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 6450 }; 6451 6452 #define RTW89_MAX_INTERFACE_NUM 3 6453 6454 /* only valid when running with chanctx_ops */ 6455 struct rtw89_entity_mgnt { 6456 struct list_head active_list; 6457 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 6458 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 6459 [__RTW89_MLD_MAX_LINK_NUM]; 6460 }; 6461 6462 struct rtw89_chanctx { 6463 struct cfg80211_chan_def chandef; 6464 struct rtw89_chan chan; 6465 struct rtw89_chan_rcd rcd; 6466 6467 /* only assigned when running with chanctx_ops */ 6468 struct rtw89_chanctx_cfg *cfg; 6469 }; 6470 6471 struct rtw89_edcca_bak { 6472 u8 a; 6473 u8 p; 6474 u8 ppdu; 6475 u8 th_old; 6476 }; 6477 6478 enum rtw89_dm_type { 6479 RTW89_DM_DYNAMIC_EDCCA, 6480 RTW89_DM_THERMAL_PROTECT, 6481 RTW89_DM_TAS, 6482 RTW89_DM_MLO, 6483 RTW89_DM_HW_SCAN, 6484 RTW89_DM_INACTIVE_PS, 6485 RTW89_DM_DIG_PD, 6486 RTW89_DM_VCORE, 6487 }; 6488 6489 #define RTW89_THERMAL_PROT_LV_MAX 5 6490 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 6491 #define RTW89_THERMAL_PROT_VLV_MAX 6 6492 #define RTW89_THERMAL_PROT_VLV_TH_OFFSET 20 6493 6494 struct rtw89_hal { 6495 u32 rx_fltr; 6496 u8 cv; 6497 u8 cid; /* enum rtw89_core_chip_cid */ 6498 u8 acv; 6499 u16 aid; /* enum rtw89_core_chip_aid */ 6500 u32 antenna_tx; 6501 u32 antenna_rx; 6502 u8 tx_nss; 6503 u8 rx_nss; 6504 bool tx_path_diversity; 6505 bool ant_diversity; 6506 bool ant_diversity_fixed; 6507 bool support_cckpd; 6508 bool support_igi; 6509 bool no_mcs_12_13; 6510 bool no_eht; 6511 6512 atomic_t roc_chanctx_idx; 6513 6514 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 6515 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 6516 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 6517 struct cfg80211_chan_def roc_chandef; 6518 6519 bool entity_active[RTW89_PHY_NUM]; 6520 bool entity_pause; 6521 enum rtw89_entity_mode entity_mode; 6522 struct rtw89_entity_mgnt entity_mgnt; 6523 6524 enum rtw89_phy_idx entity_force_hw; 6525 6526 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 6527 6528 u8 thermal_prot_th; 6529 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 6530 6531 u8 thermal_prot_vmax; 6532 u8 thermal_prot_vmin; 6533 u8 thermal_prot_vlv; /* 0 ~ RTW89_THERMAL_PROT_VLV_MAX (6) */ 6534 6535 u8 fixed_dig_pd_th; /* v = (X(dBm) + 102)/2 */ 6536 s8 fixed_dig_cck_pd_th; /* dBm */ 6537 }; 6538 6539 #define RTW89_MAX_MAC_ID_NUM 128 6540 #define RTW89_MAX_PKT_OFLD_NUM 255 6541 6542 enum rtw89_flags { 6543 RTW89_FLAG_POWERON, 6544 RTW89_FLAG_DMAC_FUNC, 6545 RTW89_FLAG_CMAC0_FUNC, 6546 RTW89_FLAG_CMAC1_FUNC, 6547 RTW89_FLAG_CMAC0_PWR, 6548 RTW89_FLAG_CMAC1_PWR, 6549 RTW89_FLAG_FW_RDY, 6550 RTW89_FLAG_RUNNING, 6551 RTW89_FLAG_PROBE_DONE, 6552 RTW89_FLAG_BFEE_MON, 6553 RTW89_FLAG_BFEE_EN, 6554 RTW89_FLAG_BFEE_TIMER_KEEP, 6555 RTW89_FLAG_NAPI_RUNNING, 6556 RTW89_FLAG_LEISURE_PS, 6557 RTW89_FLAG_LOW_POWER_MODE, 6558 RTW89_FLAG_INACTIVE_PS, 6559 RTW89_FLAG_CRASH_SIMULATING, 6560 RTW89_FLAG_SER_HANDLING, 6561 RTW89_FLAG_WOWLAN, 6562 RTW89_FLAG_FORBIDDEN_TRACK_WORK, 6563 RTW89_FLAG_CHANGING_INTERFACE, 6564 RTW89_FLAG_HW_RFKILL_STATE, 6565 RTW89_FLAG_UNPLUGGED, 6566 RTW89_FLAG_SHUTDOWN, 6567 6568 NUM_OF_RTW89_FLAGS, 6569 }; 6570 6571 enum rtw89_quirks { 6572 RTW89_QUIRK_PCI_BER, 6573 RTW89_QUIRK_THERMAL_PROT_120C, 6574 RTW89_QUIRK_THERMAL_PROT_110C, 6575 RTW89_QUIRK_THERMAL_PROT_VCORE, 6576 RTW89_QUIRK_HW_INFO_SYSFS, 6577 RTW89_QUIRK_DISABLE_2GHZ, 6578 RTW89_QUIRK_1ANT, 6579 6580 NUM_OF_RTW89_QUIRKS, 6581 }; 6582 6583 enum rtw89_custid { 6584 RTW89_CUSTID_NONE = 0, 6585 RTW89_CUSTID_HP = 1, 6586 RTW89_CUSTID_ASUS = 2, 6587 RTW89_CUSTID_ACER = 3, 6588 RTW89_CUSTID_LENOVO = 4, 6589 RTW89_CUSTID_NEC = 5, 6590 RTW89_CUSTID_AMD = 6, 6591 RTW89_CUSTID_FUJITSU = 7, 6592 RTW89_CUSTID_DELL = 8, 6593 }; 6594 6595 enum rtw89_pkt_drop_sel { 6596 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6597 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6598 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6599 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6600 RTW89_PKT_DROP_SEL_MACID_ALL, 6601 RTW89_PKT_DROP_SEL_MG0_ONCE, 6602 RTW89_PKT_DROP_SEL_HIQ_ONCE, 6603 RTW89_PKT_DROP_SEL_HIQ_PORT, 6604 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 6605 RTW89_PKT_DROP_SEL_BAND, 6606 RTW89_PKT_DROP_SEL_BAND_ONCE, 6607 RTW89_PKT_DROP_SEL_REL_MACID, 6608 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 6609 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 6610 }; 6611 6612 struct rtw89_pkt_drop_params { 6613 enum rtw89_pkt_drop_sel sel; 6614 enum rtw89_mac_idx mac_band; 6615 u8 macid; 6616 u8 port; 6617 u8 mbssid; 6618 bool tf_trs; 6619 u32 macid_band_sel[4]; 6620 }; 6621 6622 struct rtw89_pkt_stat { 6623 u16 beacon_nr; 6624 u8 beacon_rate; 6625 u32 beacon_len; 6626 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 6627 struct { 6628 u32 ldpc; 6629 u32 bcc; 6630 u32 stbc; 6631 u32 su_bf; 6632 u32 su_non_bf; 6633 u32 mu; 6634 } rx; 6635 }; 6636 6637 #define RTW89_BCN_TRACK_STAT_NR 32 6638 #define RTW89_BCN_TRACK_SCALE_FACTOR 10 6639 #define RTW89_BCN_TRACK_MAX_BIN_NUM 6 6640 #define RTW89_BCN_TRACK_BIN_WIDTH 5 6641 #define RTW89_BCN_TRACK_TARGET_BCN 80 6642 6643 struct rtw89_beacon_dist { 6644 u16 min; 6645 u16 max; 6646 u16 outlier_count; 6647 u16 lower_bound; 6648 u16 upper_bound; 6649 u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM]; 6650 }; 6651 6652 struct rtw89_beacon_stat { 6653 u8 num; 6654 u8 wp; 6655 u16 tbtt_tu_min; 6656 u16 tbtt_tu_max; 6657 u16 drift[RTW89_BCN_TRACK_STAT_NR]; 6658 u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR]; 6659 u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR]; 6660 struct rtw89_beacon_dist bcn_dist; 6661 }; 6662 6663 DECLARE_EWMA(thermal, 4, 4); 6664 DECLARE_EWMA(path_diff, 4, 2); 6665 6666 struct rtw89_phy_path_diff { 6667 struct ewma_path_diff avg; 6668 u8 raw; 6669 bool bf_smo_en; 6670 u8 link_mode; 6671 }; 6672 6673 #define RTW89_TX_RATE_NR 40 6674 struct rtw89_phy_stat { 6675 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 6676 u8 last_thermal_max; 6677 u32 tx_rate_cnt[RTW89_TX_RATE_NR]; 6678 struct rtw89_beacon_stat bcn_stat; 6679 }; 6680 6681 enum rtw89_rfk_report_state { 6682 RTW89_RFK_STATE_START = 0x0, 6683 RTW89_RFK_STATE_OK = 0x1, 6684 RTW89_RFK_STATE_FAIL = 0x2, 6685 RTW89_RFK_STATE_TIMEOUT = 0x3, 6686 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 6687 }; 6688 6689 enum rtw89_rfk_report_types { 6690 RTW89_RFK_REPORT_PRE_NTFY, 6691 RTW89_RFK_REPORT_TSSI, 6692 RTW89_RFK_REPORT_IQK, 6693 RTW89_RFK_REPORT_DPK, 6694 RTW89_RFK_REPORT_TXGAPK, 6695 RTW89_RFK_REPORT_DACK, 6696 RTW89_RFK_REPORT_RX_DCK, 6697 RTW89_RFK_REPORT_TX_IQK, 6698 RTW89_RFK_REPORT_CIM3k, 6699 6700 NUM_OF_RTW89_RFK_REPORT_TYPES, 6701 }; 6702 6703 #define RTW89_RFK_RECORD_PATH_NR 2 6704 #define RTW89_RFK_RECORD_HISTORY_NR 10 6705 6706 struct rtw89_rfk_record { 6707 u32 ch[RTW89_RFK_RECORD_PATH_NR]; 6708 u32 cv[RTW89_RFK_RECORD_PATH_NR]; 6709 u32 c5[RTW89_RFK_RECORD_PATH_NR]; 6710 enum rtw89_phy_idx phy_idx; 6711 enum rtw89_rfk_report_state states[NUM_OF_RTW89_RFK_REPORT_TYPES]; 6712 }; 6713 6714 struct rtw89_rfk_wait_info { 6715 struct completion completion; 6716 ktime_t start_time; 6717 enum rtw89_rfk_report_state state; 6718 u8 version; 6719 6720 int record_idx; 6721 struct rtw89_rfk_record *record_ptr; 6722 struct rtw89_rfk_record records[RTW89_RFK_RECORD_HISTORY_NR]; 6723 6724 int record_tssi_idx; 6725 u32 tssi_code[RTW89_RFK_RECORD_HISTORY_NR][RTW89_RFK_RECORD_PATH_NR]; 6726 }; 6727 6728 #define RTW89_DACK_PATH_NR 2 6729 #define RTW89_DACK_IDX_NR 2 6730 #define RTW89_DACK_MSBK_NR 16 6731 struct rtw89_dack_info { 6732 bool dack_done; 6733 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 6734 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 6735 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 6736 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 6737 u32 dack_cnt; 6738 bool addck_timeout[RTW89_DACK_PATH_NR]; 6739 bool dadck_timeout[RTW89_DACK_PATH_NR]; 6740 bool msbk_timeout[RTW89_DACK_PATH_NR]; 6741 }; 6742 6743 enum rtw89_rfk_chs_nrs { 6744 __RTW89_RFK_CHS_NR_V0 = 2, 6745 __RTW89_RFK_CHS_NR_V1 = 3, 6746 6747 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 6748 }; 6749 6750 struct rtw89_rfk_mcc_info_data { 6751 u8 ch[RTW89_RFK_CHS_NR]; 6752 u8 band[RTW89_RFK_CHS_NR]; 6753 u8 bw[RTW89_RFK_CHS_NR]; 6754 u32 rf18[RTW89_RFK_CHS_NR]; 6755 u8 table_idx; 6756 }; 6757 6758 struct rtw89_rfk_mcc_info { 6759 struct rtw89_rfk_mcc_info_data data[2]; 6760 }; 6761 6762 #define RTW89_IQK_CHS_NR 2 6763 #define RTW89_IQK_PATH_NR 4 6764 6765 struct rtw89_lck_info { 6766 u8 thermal[RF_PATH_MAX]; 6767 }; 6768 6769 struct rtw89_rx_dck_info { 6770 u8 thermal[RF_PATH_MAX]; 6771 }; 6772 6773 struct rtw89_iqk_info { 6774 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6775 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6776 bool lok_fail[RTW89_IQK_PATH_NR]; 6777 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6778 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6779 u32 iqk_fail_cnt; 6780 bool is_iqk_init; 6781 u32 iqk_channel[RTW89_IQK_CHS_NR]; 6782 u8 iqk_band[RTW89_IQK_PATH_NR]; 6783 u8 iqk_ch[RTW89_IQK_PATH_NR]; 6784 u8 iqk_bw[RTW89_IQK_PATH_NR]; 6785 u8 iqk_times; 6786 u8 version; 6787 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 6788 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 6789 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 6790 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 6791 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 6792 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 6793 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 6794 bool is_nbiqk; 6795 bool iqk_fft_en; 6796 bool iqk_xym_en; 6797 bool iqk_sram_en; 6798 bool iqk_cfir_en; 6799 u32 syn1to2; 6800 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6801 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 6802 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6803 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6804 u32 iqc_bak[2]; 6805 }; 6806 6807 #define RTW89_DPK_RF_PATH 2 6808 #define RTW89_DPK_AVG_THERMAL_NUM 8 6809 #define RTW89_DPK_BKUP_NUM 2 6810 struct rtw89_dpk_bkup_para { 6811 enum rtw89_band band; 6812 enum rtw89_bandwidth bw; 6813 u8 ch; 6814 u8 path_ok; 6815 u8 mdpd_en; 6816 u8 txagc_dpk; 6817 u8 ther_dpk; 6818 u8 gs; 6819 u16 pwsf; 6820 }; 6821 6822 struct rtw89_dpk_info { 6823 bool is_dpk_enable; 6824 bool is_dpk_reload_en; 6825 u8 dpk_gs[RTW89_PHY_NUM]; 6826 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6827 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6828 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6829 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6830 u8 cur_idx[RTW89_DPK_RF_PATH]; 6831 u8 cur_k_set; 6832 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6833 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 6834 u32 dpk_order[RTW89_DPK_RF_PATH]; 6835 }; 6836 6837 struct rtw89_fem_info { 6838 bool elna_2g; 6839 bool elna_5g; 6840 bool epa_2g; 6841 bool epa_5g; 6842 bool epa_6g; 6843 }; 6844 6845 struct rtw89_phy_ch_info { 6846 u8 rssi_min; 6847 u16 rssi_min_macid; 6848 u8 pre_rssi_min; 6849 u8 rssi_max; 6850 u16 rssi_max_macid; 6851 u8 rxsc_160; 6852 u8 rxsc_80; 6853 u8 rxsc_40; 6854 u8 rxsc_20; 6855 u8 rxsc_l; 6856 u8 is_noisy; 6857 }; 6858 6859 struct rtw89_pmac_stat_info { 6860 u32 cck_phy_txon; 6861 u32 cck_mac_txen; 6862 u32 ofdm_mac_txen; 6863 u32 ofdm_phy_txon; 6864 u32 cnt_ofdm_cca; 6865 u32 cnt_cck_cca; 6866 u32 cnt_cca_all; 6867 u32 cnt_cck_spoofing; 6868 u32 cnt_ofdm_spoofing; 6869 u32 cnt_ampdu_miss; 6870 u32 cnt_ampdu_crc_error; 6871 u32 cnt_ampdu_crc_ok; 6872 u32 cnt_cck_crc32_error; 6873 u32 cnt_cck_crc32_ok; 6874 u32 cnt_ofdm_crc32_error; 6875 u32 cnt_ofdm_crc32_ok; 6876 u32 cnt_ht_crc32_error; 6877 u32 cnt_ht_crc32_ok; 6878 u32 cnt_vht_crc32_error; 6879 u32 cnt_vht_crc32_ok; 6880 u32 cnt_he_crc32_ok; 6881 u32 cnt_he_crc32_error; 6882 u32 cnt_eht_crc32_ok; 6883 u32 cnt_eht_crc32_error; 6884 u32 cnt_crc32_error_all; 6885 u32 cnt_crc32_ok_all; 6886 u32 cnt_sfd_gg; 6887 u32 cnt_sig_gg; 6888 u32 cnt_cck_fail; 6889 u32 cnt_ofdm_fail; 6890 u32 cnt_fail_all; 6891 u32 cnt_lsig_brk_s_th; 6892 u32 cnt_lsig_brk_l_th; 6893 u32 cnt_parity_fail; 6894 u32 cnt_rate_illegal; 6895 u32 cnt_sb_search_fail; 6896 }; 6897 6898 struct rtw89_tx_stat_info { 6899 u32 info[6]; 6900 u32 common_ctrl[2]; 6901 u32 txpwr[2]; 6902 u8 type; 6903 u8 subtype; 6904 u8 txcmd; 6905 u8 txsc; 6906 u8 bw; 6907 u16 tmac_txpwr; 6908 u8 tx_path_en; 6909 u8 path_map; 6910 u8 max_mcs; 6911 bool stbc; 6912 }; 6913 6914 enum rtw89_diag_bb_type { 6915 RTW89_DIAG_BB_HANG, 6916 RTW89_DIAG_BB_PD, 6917 RTW89_DIAG_BB_NO_RX, 6918 RTW89_DIAG_BB_FA, 6919 RTW89_DIAG_BB_EDCCA, 6920 6921 RTW89_DIAG_BB_NR, 6922 }; 6923 6924 struct rtw89_diag_bb { 6925 u32 diag_bb_bitmap; /* bitmap of enum rtw89_diag_bb_type */ 6926 u32 diag_bb_cnt[RTW89_DIAG_BB_NR]; 6927 u16 consecutive_no_tx_cnt; 6928 u16 consecutive_no_rx_cnt; 6929 }; 6930 6931 struct rtw89_agc_gaincode_set { 6932 u8 lna_idx; 6933 u8 tia_idx; 6934 u8 rxb_idx; 6935 }; 6936 6937 #define IGI_RSSI_TH_NUM 5 6938 #define FA_TH_NUM 4 6939 #define TIA_LNA_OP1DB_NUM 8 6940 #define LNA_GAIN_NUM 7 6941 #define TIA_GAIN_NUM 2 6942 struct rtw89_dig_info { 6943 struct rtw89_agc_gaincode_set cur_gaincode; 6944 bool force_gaincode_idx_en; 6945 struct rtw89_agc_gaincode_set force_gaincode; 6946 enum rtw89_dig_noisy_level noisy_lv; 6947 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 6948 u16 fa_th[FA_TH_NUM]; 6949 u8 igi_rssi; 6950 u8 igi_fa_rssi; 6951 u8 fa_rssi_ofst; 6952 u8 dyn_igi_max; 6953 u8 dyn_igi_min; 6954 bool dyn_pd_th_en; 6955 u8 dyn_pd_th_max; 6956 u8 dyn_pd_max_cnt; 6957 u8 pd_low_th_ofst; 6958 u8 ib_pbk; 6959 s8 ib_pkpwr; 6960 s8 lna_gain_a[LNA_GAIN_NUM]; 6961 s8 lna_gain_g[LNA_GAIN_NUM]; 6962 s8 *lna_gain; 6963 s8 tia_gain_a[TIA_GAIN_NUM]; 6964 s8 tia_gain_g[TIA_GAIN_NUM]; 6965 s8 *tia_gain; 6966 u32 bak_dig; 6967 bool is_linked_pre; 6968 bool bypass_dig; 6969 bool pause_dig; 6970 }; 6971 6972 enum rtw89_multi_cfo_mode { 6973 RTW89_PKT_BASED_AVG_MODE = 0, 6974 RTW89_ENTRY_BASED_AVG_MODE = 1, 6975 RTW89_TP_BASED_AVG_MODE = 2, 6976 }; 6977 6978 enum rtw89_phy_cfo_status { 6979 RTW89_PHY_DCFO_STATE_NORMAL = 0, 6980 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 6981 RTW89_PHY_DCFO_STATE_HOLD = 2, 6982 RTW89_PHY_DCFO_STATE_MAX 6983 }; 6984 6985 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 6986 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 6987 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 6988 }; 6989 6990 struct rtw89_cfo_tracking_info { 6991 u16 cfo_timer_ms; 6992 bool cfo_trig_by_timer_en; 6993 enum rtw89_phy_cfo_status phy_cfo_status; 6994 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 6995 u8 phy_cfo_trk_cnt; 6996 bool is_adjust; 6997 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 6998 bool apply_compensation; 6999 u8 crystal_cap; 7000 u8 crystal_cap_default; 7001 u8 def_x_cap; 7002 s8 x_cap_ofst; 7003 u32 sta_cfo_tolerance; 7004 s32 cfo_tail[CFO_TRACK_MAX_USER]; 7005 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 7006 s32 cfo_avg_pre; 7007 s32 cfo_avg[CFO_TRACK_MAX_USER]; 7008 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 7009 s32 dcfo_avg; 7010 s32 dcfo_avg_pre; 7011 u32 packet_count; 7012 u32 packet_count_pre; 7013 s32 residual_cfo_acc; 7014 u8 phy_cfotrk_state; 7015 u8 phy_cfotrk_cnt; 7016 bool divergence_lock_en; 7017 u8 x_cap_lb; 7018 u8 x_cap_ub; 7019 u8 lock_cnt; 7020 }; 7021 7022 enum rtw89_tssi_mode { 7023 RTW89_TSSI_NORMAL = 0, 7024 RTW89_TSSI_SCAN = 1, 7025 }; 7026 7027 enum rtw89_tssi_alimk_band { 7028 TSSI_ALIMK_2G = 0, 7029 TSSI_ALIMK_5GL, 7030 TSSI_ALIMK_5GM, 7031 TSSI_ALIMK_5GH, 7032 TSSI_ALIMK_MAX 7033 }; 7034 7035 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 7036 #define TSSI_TRIM_CH_GROUP_NUM 8 7037 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 7038 7039 #define TSSI_CCK_CH_GROUP_NUM 6 7040 #define TSSI_MCS_2G_CH_GROUP_NUM 5 7041 #define TSSI_MCS_5G_CH_GROUP_NUM 14 7042 #define TSSI_MCS_6G_CH_GROUP_NUM 32 7043 #define TSSI_MCS_CH_GROUP_NUM \ 7044 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 7045 #define TSSI_MAX_CH_NUM 67 7046 #define TSSI_ALIMK_VALUE_NUM 8 7047 7048 struct rtw89_tssi_info { 7049 u8 thermal[RF_PATH_MAX]; 7050 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 7051 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 7052 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 7053 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 7054 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 7055 s8 extra_ofst[RF_PATH_MAX]; 7056 bool tssi_tracking_check[RF_PATH_MAX]; 7057 u8 default_txagc_offset[RF_PATH_MAX]; 7058 u32 base_thermal[RF_PATH_MAX]; 7059 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 7060 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 7061 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 7062 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 7063 u64 tssi_alimk_time; 7064 }; 7065 7066 struct rtw89_power_trim_info { 7067 bool pg_thermal_trim; 7068 bool pg_pa_bias_trim; 7069 bool pg_vco_trim; 7070 u8 thermal_trim[RF_PATH_MAX]; 7071 u8 pa_bias_trim[RF_PATH_MAX]; 7072 u8 pad_bias_trim[RF_PATH_MAX]; 7073 u8 vco_trim[RF_PATH_MAX]; 7074 7075 s16 thermal_k; 7076 }; 7077 7078 enum rtw89_regd_func { 7079 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 7080 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 7081 7082 NUM_OF_RTW89_REGD_FUNC, 7083 }; 7084 7085 struct rtw89_regd { 7086 char alpha2[3]; 7087 u8 txpwr_regd[RTW89_BAND_NUM]; 7088 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 7089 }; 7090 7091 struct rtw89_regd_data { 7092 unsigned int nr; 7093 struct rtw89_regd map[] __counted_by(nr); 7094 }; 7095 7096 struct rtw89_regd_ctrl { 7097 unsigned int nr; 7098 const struct rtw89_regd *map; 7099 }; 7100 7101 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 7102 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 7103 #define RTW89_5GHZ_UNII4_START_INDEX 25 7104 7105 struct rtw89_regulatory_info { 7106 struct rtw89_regd_ctrl ctrl; 7107 const struct rtw89_regd *regd; 7108 bool programmed; 7109 7110 enum rtw89_reg_6ghz_power reg_6ghz_power; 7111 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 7112 bool txpwr_uk_follow_etsi; 7113 7114 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 7115 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 7116 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 7117 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM); 7118 }; 7119 7120 enum rtw89_ifs_clm_application { 7121 RTW89_IFS_CLM_INIT = 0, 7122 RTW89_IFS_CLM_BACKGROUND = 1, 7123 RTW89_IFS_CLM_ACS = 2, 7124 RTW89_IFS_CLM_DIG = 3, 7125 RTW89_IFS_CLM_TDMA_DIG = 4, 7126 RTW89_IFS_CLM_DBG = 5, 7127 RTW89_IFS_CLM_DBG_MANUAL = 6 7128 }; 7129 7130 enum rtw89_env_racing_lv { 7131 RTW89_RAC_RELEASE = 0, 7132 RTW89_RAC_LV_1 = 1, 7133 RTW89_RAC_LV_2 = 2, 7134 RTW89_RAC_LV_3 = 3, 7135 RTW89_RAC_LV_4 = 4, 7136 RTW89_RAC_MAX_NUM = 5 7137 }; 7138 7139 struct rtw89_ccx_para_info { 7140 enum rtw89_env_racing_lv rac_lv; 7141 u16 mntr_time; 7142 bool nhm_incld_cca; 7143 u8 nhm_manual_th_ofst; 7144 u8 nhm_manual_th0; 7145 enum rtw89_ifs_clm_application ifs_clm_app; 7146 u32 ifs_clm_manual_th_times; 7147 u32 ifs_clm_manual_th0; 7148 u8 fahm_manual_th_ofst; 7149 u8 fahm_manual_th0; 7150 u8 fahm_numer_opt; 7151 u8 fahm_denom_opt; 7152 }; 7153 7154 enum rtw89_ccx_edcca_opt_sc_idx { 7155 RTW89_CCX_EDCCA_SEG0_P0 = 0, 7156 RTW89_CCX_EDCCA_SEG0_S1 = 1, 7157 RTW89_CCX_EDCCA_SEG0_S2 = 2, 7158 RTW89_CCX_EDCCA_SEG0_S3 = 3, 7159 RTW89_CCX_EDCCA_SEG1_P0 = 4, 7160 RTW89_CCX_EDCCA_SEG1_S1 = 5, 7161 RTW89_CCX_EDCCA_SEG1_S2 = 6, 7162 RTW89_CCX_EDCCA_SEG1_S3 = 7 7163 }; 7164 7165 enum rtw89_ccx_edcca_opt_bw_idx { 7166 RTW89_CCX_EDCCA_BW20_0 = 0, 7167 RTW89_CCX_EDCCA_BW20_1 = 1, 7168 RTW89_CCX_EDCCA_BW20_2 = 2, 7169 RTW89_CCX_EDCCA_BW20_3 = 3, 7170 RTW89_CCX_EDCCA_BW20_4 = 4, 7171 RTW89_CCX_EDCCA_BW20_5 = 5, 7172 RTW89_CCX_EDCCA_BW20_6 = 6, 7173 RTW89_CCX_EDCCA_BW20_7 = 7 7174 }; 7175 7176 struct rtw89_nhm_report { 7177 struct list_head list; 7178 struct ieee80211_channel *channel; 7179 u8 noise; 7180 }; 7181 7182 #define RTW89_FAHM_TH_NUM 11 7183 #define RTW89_FAHM_RPT_NUM 12 7184 #define RTW89_IFS_CLM_NUM 4 7185 struct rtw89_env_monitor_info { 7186 u8 ccx_watchdog_result; 7187 bool ccx_ongoing; 7188 u8 ccx_rac_lv; 7189 bool ccx_manual_ctrl; 7190 u16 ifs_clm_mntr_time; 7191 enum rtw89_ifs_clm_application ifs_clm_app; 7192 u16 ccx_period; 7193 u8 ccx_unit_idx; 7194 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 7195 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 7196 u16 ifs_clm_tx; 7197 u16 ifs_clm_edcca_excl_cca; 7198 u16 ifs_clm_ofdmfa; 7199 u16 ifs_clm_ofdmcca_excl_fa; 7200 u16 ifs_clm_cckfa; 7201 u16 ifs_clm_cckcca_excl_fa; 7202 u16 ifs_clm_total_ifs; 7203 u16 ifs_clm_his[RTW89_IFS_CLM_NUM]; 7204 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 7205 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 7206 u8 ifs_clm_tx_ratio; 7207 u8 ifs_clm_edcca_excl_cca_ratio; 7208 u8 ifs_clm_cck_fa_ratio; 7209 u8 ifs_clm_ofdm_fa_ratio; 7210 u8 ifs_clm_cck_cca_excl_fa_ratio; 7211 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 7212 u16 ifs_clm_cck_fa_permil; 7213 u16 ifs_clm_ofdm_fa_permil; 7214 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 7215 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 7216 bool nhm_include_cca; 7217 u32 nhm_sum; 7218 u32 nhm_mntr_time; 7219 u16 nhm_result[RTW89_NHM_RPT_NUM]; 7220 u8 nhm_th[RTW89_NHM_RPT_NUM]; 7221 struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM]; 7222 struct list_head nhm_rpt_list; 7223 u8 edcca_clm_ratio; 7224 }; 7225 7226 enum rtw89_ser_rcvy_step { 7227 RTW89_SER_DRV_STOP_TX, 7228 RTW89_SER_DRV_STOP_RX, 7229 RTW89_SER_DRV_STOP_RUN, 7230 RTW89_SER_HAL_STOP_DMA, 7231 RTW89_SER_SUPPRESS_LOG, 7232 RTW89_NUM_OF_SER_FLAGS 7233 }; 7234 7235 struct rtw89_ser_count { 7236 unsigned int l1; 7237 unsigned int l2; 7238 }; 7239 7240 struct rtw89_ser { 7241 u8 state; 7242 u8 alarm_event; 7243 bool prehandle_l1; 7244 7245 struct rtw89_ser_count sw_cnt; 7246 7247 struct work_struct ser_hdl_work; 7248 struct delayed_work ser_alarm_work; 7249 const struct state_ent *st_tbl; 7250 const struct event_ent *ev_tbl; 7251 struct list_head msg_q; 7252 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 7253 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 7254 }; 7255 7256 enum rtw89_mac_ax_ps_mode { 7257 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 7258 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 7259 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 7260 RTW89_MAC_AX_PS_MODE_MAX = 3, 7261 }; 7262 7263 enum rtw89_last_rpwm_mode { 7264 RTW89_LAST_RPWM_PS = 0x0, 7265 RTW89_LAST_RPWM_ACTIVE = 0x6, 7266 }; 7267 7268 struct rtw89_lps_parm { 7269 u8 macid; 7270 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 7271 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 7272 }; 7273 7274 struct rtw89_ppdu_sts_info { 7275 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 7276 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 7277 }; 7278 7279 struct rtw89_early_h2c { 7280 struct list_head list; 7281 u8 *h2c; 7282 u16 h2c_len; 7283 }; 7284 7285 struct rtw89_hw_scan_extra_op { 7286 bool set; 7287 u8 macid; 7288 u8 port; 7289 struct rtw89_chan chan; 7290 struct rtw89_vif_link *rtwvif_link; 7291 }; 7292 7293 struct rtw89_hw_scan_info { 7294 struct rtw89_vif_link *scanning_vif; 7295 struct list_head pkt_list[NUM_NL80211_BANDS]; 7296 struct list_head chan_list; 7297 struct rtw89_chan op_chan; 7298 struct rtw89_hw_scan_extra_op extra_op; 7299 u8 wildcard_pkt_id[NUM_NL80211_BANDS]; 7300 u16 ssid_total_len; 7301 int n_ssids; 7302 bool connected; 7303 bool abort; 7304 u16 delay; /* in unit of ms */ 7305 u8 seq: 2; 7306 }; 7307 7308 enum rtw89_phy_bb_gain_band { 7309 RTW89_BB_GAIN_BAND_2G = 0, 7310 RTW89_BB_GAIN_BAND_5G_L = 1, 7311 RTW89_BB_GAIN_BAND_5G_M = 2, 7312 RTW89_BB_GAIN_BAND_5G_H = 3, 7313 RTW89_BB_GAIN_BAND_6G_L = 4, 7314 RTW89_BB_GAIN_BAND_6G_M = 5, 7315 RTW89_BB_GAIN_BAND_6G_H = 6, 7316 RTW89_BB_GAIN_BAND_6G_UH = 7, 7317 7318 RTW89_BB_GAIN_BAND_NR, 7319 }; 7320 7321 enum rtw89_phy_gain_band_be { 7322 RTW89_BB_GAIN_BAND_2G_BE = 0, 7323 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 7324 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 7325 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 7326 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 7327 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 7328 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 7329 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 7330 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 7331 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 7332 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 7333 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 7334 7335 RTW89_BB_GAIN_BAND_NR_BE, 7336 }; 7337 7338 enum rtw89_phy_bb_bw_be { 7339 RTW89_BB_BW_20_40 = 0, 7340 RTW89_BB_BW_80_160_320 = 1, 7341 7342 RTW89_BB_BW_NR_BE, 7343 }; 7344 7345 enum rtw89_bw20_sc { 7346 RTW89_BW20_SC_20M = 1, 7347 RTW89_BW20_SC_40M = 2, 7348 RTW89_BW20_SC_80M = 4, 7349 RTW89_BW20_SC_160M = 8, 7350 RTW89_BW20_SC_320M = 16, 7351 }; 7352 7353 enum rtw89_cmac_table_bw { 7354 RTW89_CMAC_BW_20M = 0, 7355 RTW89_CMAC_BW_40M = 1, 7356 RTW89_CMAC_BW_80M = 2, 7357 RTW89_CMAC_BW_160M = 3, 7358 RTW89_CMAC_BW_320M = 4, 7359 7360 RTW89_CMAC_BW_NR, 7361 }; 7362 7363 enum rtw89_phy_bb_rxsc_num { 7364 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 7365 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 7366 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 7367 }; 7368 7369 struct rtw89_phy_bb_gain_info { 7370 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 7371 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 7372 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 7373 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 7374 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 7375 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 7376 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 7377 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 7378 [RTW89_BB_RXSC_NUM_40]; 7379 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 7380 [RTW89_BB_RXSC_NUM_80]; 7381 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 7382 [RTW89_BB_RXSC_NUM_160]; 7383 }; 7384 7385 struct rtw89_phy_bb_gain_info_be { 7386 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 7387 [LNA_GAIN_NUM]; 7388 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 7389 [TIA_GAIN_NUM]; 7390 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 7391 [RF_PATH_MAX][LNA_GAIN_NUM]; 7392 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 7393 [RF_PATH_MAX][LNA_GAIN_NUM]; 7394 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 7395 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 7396 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 7397 [RTW89_BW20_SC_20M]; 7398 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 7399 [RTW89_BW20_SC_40M]; 7400 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 7401 [RTW89_BW20_SC_80M]; 7402 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 7403 [RTW89_BW20_SC_160M]; 7404 }; 7405 7406 struct rtw89_phy_efuse_gain { 7407 bool offset_valid; 7408 bool comp_valid; 7409 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 7410 s8 offset2[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 7411 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 7412 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 7413 s8 ref_gain_base[RTW89_PHY_NUM]; /* S(8, 2) */ 7414 s8 cck_rpl_base[RTW89_PHY_NUM]; /* S(8, 0) */ 7415 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 7416 }; 7417 7418 struct rtw89_phy_calc_efuse_gain { 7419 s8 cck_mean_gain_bias; 7420 s8 cck_rpl_ofst; 7421 s8 rssi_ofst; 7422 }; 7423 7424 #define RTW89_MAX_PATTERN_NUM 18 7425 #define RTW89_MAX_PATTERN_MASK_SIZE 4 7426 #define RTW89_MAX_PATTERN_SIZE 128 7427 7428 struct rtw89_wow_cam_info { 7429 bool r_w; 7430 u8 idx; 7431 __le32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 7432 u16 crc; 7433 bool negative_pattern_match; 7434 bool skip_mac_hdr; 7435 bool uc; 7436 bool mc; 7437 bool bc; 7438 bool valid; 7439 }; 7440 7441 struct rtw89_wow_key_info { 7442 u8 ptk_tx_iv[8]; 7443 u8 valid_check; 7444 u8 symbol_check_en; 7445 u8 gtk_keyidx; 7446 u8 rsvd[5]; 7447 u8 ptk_rx_iv[8]; 7448 u8 gtk_rx_iv[4][8]; 7449 } __packed; 7450 7451 struct rtw89_wow_gtk_info { 7452 u8 kck[32]; 7453 u8 kek[32]; 7454 u8 tk1[16]; 7455 u8 rxmickey[8]; 7456 u8 txmickey[8]; 7457 __le32 igtk_keyid; 7458 __le64 ipn; 7459 u8 igtk[2][32]; 7460 u8 psk[32]; 7461 } __packed; 7462 7463 struct rtw89_wow_aoac_report { 7464 u8 rpt_ver; 7465 u8 sec_type; 7466 u8 key_idx; 7467 u8 pattern_idx; 7468 u8 rekey_ok; 7469 u8 ptk_tx_iv[8]; 7470 u8 eapol_key_replay_count[8]; 7471 u8 gtk[32]; 7472 u8 ptk_rx_iv[8]; 7473 u8 gtk_rx_iv[4][8]; 7474 u64 igtk_key_id; 7475 u64 igtk_ipn; 7476 u8 igtk[32]; 7477 u8 csa_pri_ch; 7478 u8 csa_bw; 7479 u8 csa_ch_offset; 7480 u8 csa_chsw_failed; 7481 u8 csa_ch_band; 7482 }; 7483 7484 struct rtw89_wow_param { 7485 struct rtw89_vif_link *rtwvif_link; 7486 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 7487 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 7488 struct rtw89_wow_key_info key_info; 7489 struct rtw89_wow_gtk_info gtk_info; 7490 struct rtw89_wow_aoac_report aoac_rpt; 7491 u8 pattern_cnt; 7492 u8 ptk_alg; 7493 u8 gtk_alg; 7494 u8 ptk_keyidx; 7495 u8 akm; 7496 7497 /* see RTW89_WOW_WAIT_COND series for wait condition */ 7498 struct rtw89_wait_info wait; 7499 7500 bool pno_inited; 7501 struct list_head pno_pkt_list; 7502 struct cfg80211_sched_scan_request *nd_config; 7503 }; 7504 7505 struct rtw89_mcc_limit { 7506 bool enable; 7507 u16 max_tob; /* TU; max time offset behind */ 7508 u16 max_toa; /* TU; max time offset ahead */ 7509 u16 max_dur; /* TU */ 7510 }; 7511 7512 struct rtw89_mcc_policy { 7513 u8 c2h_rpt; 7514 u8 tx_null_early; 7515 u8 dis_tx_null; 7516 u8 in_curr_ch; 7517 u8 dis_sw_retry; 7518 u8 sw_retry_count; 7519 }; 7520 7521 struct rtw89_mcc_role { 7522 struct rtw89_vif_link *rtwvif_link; 7523 struct rtw89_mcc_policy policy; 7524 struct rtw89_mcc_limit limit; 7525 7526 const struct rtw89_mcc_courtesy_cfg *crtz; 7527 7528 /* only valid when running with FW MRC mechanism */ 7529 u8 slot_idx; 7530 7531 /* byte-array in LE order for FW */ 7532 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 7533 u8 probe_count; 7534 7535 u16 duration; /* TU */ 7536 u16 beacon_interval; /* TU */ 7537 bool is_2ghz; 7538 bool is_go; 7539 bool is_gc; 7540 bool ignore_bcn; 7541 }; 7542 7543 struct rtw89_mcc_bt_role { 7544 u16 duration; /* TU */ 7545 }; 7546 7547 struct rtw89_mcc_courtesy_cfg { 7548 u8 slot_num; 7549 u8 macid_tgt; 7550 }; 7551 7552 struct rtw89_mcc_courtesy { 7553 struct rtw89_mcc_courtesy_cfg ref; 7554 struct rtw89_mcc_courtesy_cfg aux; 7555 }; 7556 7557 enum rtw89_mcc_plan { 7558 RTW89_MCC_PLAN_TAIL_BT, 7559 RTW89_MCC_PLAN_MID_BT, 7560 RTW89_MCC_PLAN_NO_BT, 7561 7562 NUM_OF_RTW89_MCC_PLAN, 7563 }; 7564 7565 struct rtw89_mcc_pattern { 7566 s16 tob_ref; /* TU; time offset behind of reference role */ 7567 s16 toa_ref; /* TU; time offset ahead of reference role */ 7568 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 7569 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 7570 7571 enum rtw89_mcc_plan plan; 7572 struct rtw89_mcc_courtesy courtesy; 7573 }; 7574 7575 struct rtw89_mcc_sync { 7576 bool enable; 7577 u16 offset; /* TU */ 7578 u8 macid_src; 7579 u8 band_src; 7580 u8 port_src; 7581 u8 macid_tgt; 7582 u8 band_tgt; 7583 u8 port_tgt; 7584 }; 7585 7586 struct rtw89_mcc_config { 7587 struct rtw89_mcc_pattern pattern; 7588 struct rtw89_mcc_sync sync; 7589 u64 start_tsf; 7590 u64 start_tsf_in_aux_domain; 7591 u64 prepare_delay; 7592 u16 mcc_interval; /* TU */ 7593 u16 beacon_offset; /* TU */ 7594 }; 7595 7596 enum rtw89_mcc_mode { 7597 RTW89_MCC_MODE_GO_STA, 7598 RTW89_MCC_MODE_GC_STA, 7599 }; 7600 7601 struct rtw89_mcc_info { 7602 struct rtw89_wait_info wait; 7603 7604 u8 group; 7605 enum rtw89_mcc_mode mode; 7606 struct rtw89_mcc_role role_ref; /* reference role */ 7607 struct rtw89_mcc_role role_aux; /* auxiliary role */ 7608 struct rtw89_mcc_bt_role bt_role; 7609 struct rtw89_mcc_config config; 7610 }; 7611 7612 enum rtw89_mlo_mode { 7613 RTW89_MLO_MODE_MLSR = 0, 7614 RTW89_MLO_MODE_EMLSR = 1, 7615 7616 NUM_OF_RTW89_MLO_MODE, 7617 }; 7618 7619 struct rtw89_mlo_info { 7620 struct rtw89_wait_info wait; 7621 }; 7622 7623 struct rtw89_beacon_track_info { 7624 bool is_data_ready; 7625 u32 tbtt_offset; /* in unit of microsecond */ 7626 u16 bcn_timeout; /* in unit of millisecond */ 7627 7628 /* The following are constant and set at association. */ 7629 u8 dtim; 7630 u16 beacon_int; 7631 u16 low_bcn_th; 7632 u16 med_bcn_th; 7633 u16 high_bcn_th; 7634 u16 target_bcn_th; 7635 u16 outlier_low_bcn_th; 7636 u16 outlier_high_bcn_th; 7637 u32 close_bcn_intvl_th; 7638 u32 tbtt_diff_th; 7639 }; 7640 7641 struct rtw89_tid_stats { 7642 s64 last_pn; 7643 u16 last_sn; 7644 bool started; 7645 }; 7646 7647 struct rtw89_io_ops { 7648 int (*pack)(struct rtw89_dev *rtwdev); 7649 int (*unpack)(struct rtw89_dev *rtwdev); 7650 void (*do_udelay)(struct rtw89_dev *rtwdev, u32 us); 7651 void (*do_mdelay)(struct rtw89_dev *rtwdev, u32 ms); 7652 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 7653 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 7654 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 7655 void (*phy_write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 7656 void (*phy_write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 7657 void (*phy_write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 7658 void (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 7659 u32 addr, u32 mask, u32 data); 7660 void (*write8_set)(struct rtw89_dev *rtwdev, u32 addr, u8 bit); 7661 void (*write16_set)(struct rtw89_dev *rtwdev, u32 addr, u16 bit); 7662 void (*write32_set)(struct rtw89_dev *rtwdev, u32 addr, u32 bit); 7663 void (*write8_clr)(struct rtw89_dev *rtwdev, u32 addr, u8 bit); 7664 void (*write16_clr)(struct rtw89_dev *rtwdev, u32 addr, u16 bit); 7665 void (*write32_clr)(struct rtw89_dev *rtwdev, u32 addr, u32 bit); 7666 void (*write8_mask)(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 7667 u8 data); 7668 void (*write16_mask)(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 7669 u16 data); 7670 void (*write32_mask)(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 7671 u32 data); 7672 }; 7673 7674 struct rtw89_dev { 7675 struct ieee80211_hw *hw; 7676 struct device *dev; 7677 const struct ieee80211_ops *ops; 7678 const struct rtw89_io_ops *io; 7679 7680 bool dbcc_en; 7681 bool support_mlo; 7682 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 7683 struct rtw89_hw_scan_info scan_info; 7684 const struct rtw89_chip_info *chip; 7685 const struct rtw89_chip_variant *variant; 7686 const struct rtw89_board_variant *board; 7687 const struct rtw89_pci_info *pci_info; 7688 const struct rtw89_rfe_parms *rfe_parms; 7689 struct rtw89_hal hal; 7690 struct rtw89_beacon_track_info bcn_track; 7691 struct rtw89_mcc_info mcc; 7692 struct rtw89_mlo_info mlo; 7693 struct rtw89_mac_info mac; 7694 struct rtw89_fw_info fw; 7695 struct rtw89_hci_info hci; 7696 struct rtw89_efuse efuse; 7697 struct rtw89_traffic_stats stats; 7698 struct rtw89_rfe_data *rfe_data; 7699 enum rtw89_custid custid; 7700 7701 struct rtw89_fw_cmd_ofld_info *fw_cmd_ofld_info; 7702 7703 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 7704 refcount_t refcount_ap_info; 7705 7706 struct list_head rtwvifs_list; 7707 struct workqueue_struct *txq_wq; 7708 struct work_struct txq_work; 7709 struct delayed_work txq_reinvoke_work; 7710 /* used to protect ba_list and forbid_ba_list */ 7711 spinlock_t ba_lock; 7712 /* txqs to setup ba session */ 7713 struct list_head ba_list; 7714 /* txqs to forbid ba session */ 7715 struct list_head forbid_ba_list; 7716 struct work_struct ba_work; 7717 /* used to protect rpwm */ 7718 spinlock_t rpwm_lock; 7719 7720 struct list_head tx_waits; 7721 struct wiphy_delayed_work tx_wait_work; 7722 7723 struct rtw89_tx_rpt tx_rpt; 7724 7725 struct rtw89_cam_info cam_info; 7726 7727 struct sk_buff_head c2h_queue; 7728 struct wiphy_work c2h_work; 7729 struct wiphy_work ips_work; 7730 struct wiphy_work cancel_6ghz_probe_work; 7731 struct work_struct load_firmware_work; 7732 7733 struct list_head early_h2c_list; 7734 7735 struct rtw89_ser ser; 7736 7737 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 7738 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 7739 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 7740 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 7741 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 7742 7743 struct rtw89_phy_stat phystat; 7744 struct rtw89_rfk_wait_info rfk_wait; 7745 struct rtw89_dack_info dack; 7746 struct rtw89_iqk_info iqk; 7747 struct rtw89_dpk_info dpk; 7748 struct rtw89_rfk_mcc_info rfk_mcc; 7749 struct rtw89_lck_info lck; 7750 struct rtw89_rx_dck_info rx_dck; 7751 bool is_tssi_mode[RF_PATH_MAX]; 7752 bool is_bt_iqk_timeout; 7753 7754 struct rtw89_fem_info fem; 7755 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 7756 struct rtw89_tssi_info tssi; 7757 struct rtw89_power_trim_info pwr_trim; 7758 7759 struct rtw89_cfo_tracking_info cfo_tracking; 7760 union { 7761 struct rtw89_phy_bb_gain_info ax; 7762 struct rtw89_phy_bb_gain_info_be be; 7763 } bb_gain; 7764 struct rtw89_phy_efuse_gain efuse_gain; 7765 struct rtw89_phy_ul_tb_info ul_tb_info; 7766 struct rtw89_antdiv_info antdiv; 7767 struct rtw89_phy_info phy_info; 7768 7769 struct rtw89_bb_ctx { 7770 enum rtw89_phy_idx phy_idx; 7771 struct rtw89_env_monitor_info env_monitor; 7772 struct rtw89_dig_info dig; 7773 struct rtw89_phy_ch_info ch_info; 7774 struct rtw89_edcca_bak edcca_bak; 7775 struct ewma_rssi bcn_rssi; 7776 struct rtw89_pkt_stat cur_pkt_stat; 7777 struct rtw89_pkt_stat last_pkt_stat; 7778 struct rtw89_pmac_stat_info pmac_stat; 7779 struct rtw89_tx_stat_info tx_stat; 7780 struct rtw89_diag_bb diag; 7781 struct rtw89_phy_path_diff path_diff; 7782 } bbs[RTW89_PHY_NUM]; 7783 7784 struct wiphy_delayed_work track_work; 7785 struct wiphy_delayed_work track_ps_work; 7786 struct wiphy_delayed_work chanctx_work; 7787 struct wiphy_delayed_work coex_act1_work; 7788 struct wiphy_delayed_work coex_bt_devinfo_work; 7789 struct wiphy_delayed_work coex_rfk_chk_work; 7790 struct wiphy_delayed_work cfo_track_work; 7791 struct wiphy_delayed_work mcc_prepare_done_work; 7792 struct delayed_work forbid_ba_work; 7793 struct wiphy_delayed_work antdiv_work; 7794 struct rtw89_ppdu_sts_info ppdu_sts; 7795 u8 total_sta_assoc; 7796 bool scanning; 7797 7798 struct rtw89_regulatory_info regulatory; 7799 struct rtw89_sar_info sar; 7800 struct rtw89_tas_info tas; 7801 struct rtw89_ant_gain_info ant_gain; 7802 7803 struct rtw89_btc btc; 7804 enum rtw89_ps_mode ps_mode; 7805 bool lps_enabled; 7806 u8 ps_hang_cnt; 7807 7808 struct rtw89_wow_param wow; 7809 7810 /* napi structure */ 7811 struct net_device *netdev; 7812 struct napi_struct napi; 7813 int napi_budget_countdown; 7814 7815 struct rtw89_debugfs *debugfs; 7816 struct rtw89_vif *pure_monitor_mode_vif; 7817 struct rtw89_led led; 7818 7819 /* HCI related data, keep last */ 7820 u8 priv[] __aligned(sizeof(void *)); 7821 }; 7822 7823 struct rtw89_link_conf_container { 7824 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 7825 }; 7826 7827 struct rtw89_vif_ml_trans { 7828 u16 mediate_links; 7829 u16 links_to_del; 7830 u16 links_to_add; 7831 }; 7832 7833 #define RTW89_VIF_IDLE_LINK_ID 0 7834 7835 struct rtw89_vif { 7836 struct rtw89_dev *rtwdev; 7837 struct list_head list; 7838 struct list_head mgnt_entry; 7839 struct rtw89_link_conf_container __rcu *snap_link_confs; 7840 7841 u8 mac_addr[ETH_ALEN]; 7842 __be32 ip_addr; 7843 7844 struct rtw89_traffic_stats stats; 7845 struct rtw89_traffic_stats stats_ps; 7846 u32 tdls_peer; 7847 7848 struct ieee80211_scan_ies *scan_ies; 7849 struct cfg80211_scan_request *scan_req; 7850 7851 struct rtw89_roc roc; 7852 bool offchan; 7853 bool burst_active; 7854 7855 enum rtw89_mlo_mode mlo_mode; 7856 struct rtw89_vif_ml_trans ml_trans; 7857 7858 struct list_head dlink_pool; 7859 u8 links_inst_valid_num; 7860 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 7861 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 7862 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 7863 }; 7864 7865 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 7866 const struct rtw89_vif *rtwvif, 7867 unsigned int link_id) 7868 { 7869 *rtwvif_link = rtwvif->links[link_id]; 7870 return !!*rtwvif_link; 7871 } 7872 7873 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 7874 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 7875 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 7876 7877 enum rtw89_sta_flags { 7878 RTW89_REMOTE_STA_IN_PS, 7879 7880 NUM_OF_RTW89_STA_FLAGS, 7881 }; 7882 7883 struct rtw89_sta { 7884 struct rtw89_dev *rtwdev; 7885 struct rtw89_vif *rtwvif; 7886 7887 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 7888 7889 bool disassoc; 7890 7891 struct sk_buff_head roc_queue; 7892 7893 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 7894 struct rtw89_tid_stats tid_rx_stats[IEEE80211_NUM_TIDS]; 7895 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 7896 7897 struct list_head ba_cam_list; 7898 7899 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 7900 7901 struct list_head dlink_pool; 7902 u8 links_inst_valid_num; 7903 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 7904 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 7905 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 7906 }; 7907 7908 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 7909 const struct rtw89_sta *rtwsta, 7910 unsigned int link_id) 7911 { 7912 *rtwsta_link = rtwsta->links[link_id]; 7913 return !!*rtwsta_link; 7914 } 7915 7916 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 7917 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 7918 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 7919 7920 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 7921 { 7922 /* const after init, so no need to check if active first */ 7923 return rtwvif->links_inst[0].mac_id; 7924 } 7925 7926 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 7927 { 7928 /* const after init, so no need to check if active first */ 7929 return rtwvif->links_inst[0].port; 7930 } 7931 7932 static inline struct rtw89_vif_link * 7933 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 7934 { 7935 if (index >= rtwvif->links_inst_valid_num || 7936 !test_bit(index, rtwvif->links_inst_map)) 7937 return NULL; 7938 return &rtwvif->links_inst[index]; 7939 } 7940 7941 static inline 7942 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 7943 { 7944 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 7945 7946 return rtwvif_link - rtwvif->links_inst; 7947 } 7948 7949 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 7950 { 7951 /* const after init, so no need to check if active first */ 7952 return rtwsta->links_inst[0].mac_id; 7953 } 7954 7955 static inline struct rtw89_sta_link * 7956 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 7957 { 7958 if (index >= rtwsta->links_inst_valid_num || 7959 !test_bit(index, rtwsta->links_inst_map)) 7960 return NULL; 7961 return &rtwsta->links_inst[index]; 7962 } 7963 7964 static inline 7965 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 7966 { 7967 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 7968 7969 return rtwsta_link - rtwsta->links_inst; 7970 } 7971 7972 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 7973 { 7974 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 7975 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 7976 7977 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 7978 rtwsta_link); 7979 } 7980 7981 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 7982 { 7983 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 7984 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 7985 7986 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 7987 NULL); 7988 synchronize_rcu(); 7989 } 7990 7991 static inline struct rtw89_sta_link * 7992 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 7993 { 7994 if (unlikely(macid >= RTW89_MAX_MAC_ID_NUM)) 7995 return NULL; 7996 7997 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 7998 } 7999 8000 #define rtw89_get_designated_link(links_holder) \ 8001 ({ \ 8002 typeof(links_holder) p = links_holder; \ 8003 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 8004 }) 8005 8006 static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait) 8007 { 8008 dev_kfree_skb_any(wait->skb); 8009 kfree_rcu(wait, rcu_head); 8010 } 8011 8012 static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev) 8013 { 8014 struct rtw89_tx_wait_info *wait, *tmp; 8015 8016 lockdep_assert_wiphy(rtwdev->hw->wiphy); 8017 8018 list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) { 8019 if (!completion_done(&wait->completion)) 8020 continue; 8021 list_del(&wait->list); 8022 rtw89_tx_wait_release(wait); 8023 } 8024 } 8025 8026 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 8027 struct rtw89_core_tx_request *tx_req) 8028 { 8029 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 8030 } 8031 8032 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 8033 { 8034 rtwdev->hci.ops->reset(rtwdev); 8035 /* hci.ops->reset must complete all pending TX wait SKBs */ 8036 rtw89_tx_wait_list_clear(rtwdev); 8037 } 8038 8039 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 8040 { 8041 return rtwdev->hci.ops->start(rtwdev); 8042 } 8043 8044 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 8045 { 8046 rtwdev->hci.ops->stop(rtwdev); 8047 } 8048 8049 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 8050 { 8051 return rtwdev->hci.ops->deinit(rtwdev); 8052 } 8053 8054 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 8055 { 8056 rtwdev->hci.ops->pause(rtwdev, pause); 8057 } 8058 8059 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 8060 { 8061 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 8062 } 8063 8064 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 8065 { 8066 rtwdev->hci.ops->recalc_int_mit(rtwdev); 8067 } 8068 8069 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 8070 { 8071 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 8072 } 8073 8074 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 8075 { 8076 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 8077 } 8078 8079 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 8080 { 8081 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 8082 } 8083 8084 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 8085 bool drop) 8086 { 8087 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 8088 return; 8089 8090 if (rtwdev->hci.ops->flush_queues) 8091 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 8092 } 8093 8094 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 8095 { 8096 if (rtwdev->hci.ops->recovery_start) 8097 rtwdev->hci.ops->recovery_start(rtwdev); 8098 } 8099 8100 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 8101 { 8102 if (rtwdev->hci.ops->recovery_complete) 8103 rtwdev->hci.ops->recovery_complete(rtwdev); 8104 } 8105 8106 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 8107 { 8108 if (rtwdev->hci.ops->enable_intr) 8109 rtwdev->hci.ops->enable_intr(rtwdev); 8110 } 8111 8112 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 8113 { 8114 if (rtwdev->hci.ops->disable_intr) 8115 rtwdev->hci.ops->disable_intr(rtwdev); 8116 } 8117 8118 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 8119 { 8120 if (rtwdev->hci.ops->ctrl_txdma_ch) 8121 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 8122 } 8123 8124 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 8125 { 8126 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 8127 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 8128 } 8129 8130 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 8131 { 8132 if (rtwdev->hci.ops->ctrl_trxhci) 8133 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 8134 } 8135 8136 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 8137 { 8138 int ret = 0; 8139 8140 if (rtwdev->hci.ops->poll_txdma_ch_idle) 8141 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 8142 return ret; 8143 } 8144 8145 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 8146 { 8147 if (rtwdev->hci.ops->clr_idx_all) 8148 rtwdev->hci.ops->clr_idx_all(rtwdev); 8149 } 8150 8151 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 8152 { 8153 int ret = 0; 8154 8155 if (rtwdev->hci.ops->rst_bdram) 8156 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 8157 return ret; 8158 } 8159 8160 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 8161 { 8162 if (rtwdev->hci.ops->clear) 8163 rtwdev->hci.ops->clear(rtwdev, pdev); 8164 } 8165 8166 static inline 8167 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 8168 { 8169 /* 8170 * This should be used by/after rtw89_hci_tx_write() and before doing 8171 * ieee80211_tx_info_clear_status(). 8172 */ 8173 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 8174 8175 return (struct rtw89_tx_skb_data *)info->driver_data; 8176 } 8177 8178 static inline int rtw89_raw_io_pack(struct rtw89_dev *rtwdev) 8179 { 8180 return 0; 8181 } 8182 8183 static inline int rtw89_raw_io_unpack(struct rtw89_dev *rtwdev) 8184 { 8185 return 0; 8186 } 8187 8188 static inline void rtw89_raw_io_udelay(struct rtw89_dev *rtwdev, u32 us) 8189 { 8190 udelay(us); 8191 } 8192 8193 static inline void rtw89_raw_io_mdelay(struct rtw89_dev *rtwdev, u32 ms) 8194 { 8195 mdelay(ms); 8196 } 8197 8198 static inline int rtw89_io_pack(struct rtw89_dev *rtwdev) 8199 { 8200 return rtwdev->io->pack(rtwdev); 8201 } 8202 8203 static inline int rtw89_io_unpack(struct rtw89_dev *rtwdev) 8204 { 8205 return rtwdev->io->unpack(rtwdev); 8206 } 8207 8208 static inline void rtw89_io_udelay(struct rtw89_dev *rtwdev, u32 us) 8209 { 8210 rtwdev->io->do_udelay(rtwdev, us); 8211 } 8212 8213 static inline void rtw89_io_mdelay(struct rtw89_dev *rtwdev, u32 ms) 8214 { 8215 rtwdev->io->do_mdelay(rtwdev, ms); 8216 } 8217 8218 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 8219 { 8220 return rtwdev->hci.ops->read8(rtwdev, addr); 8221 } 8222 8223 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 8224 { 8225 return rtwdev->hci.ops->read16(rtwdev, addr); 8226 } 8227 8228 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 8229 { 8230 return rtwdev->hci.ops->read32(rtwdev, addr); 8231 } 8232 8233 static inline void rtw89_raw_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 8234 { 8235 rtwdev->hci.ops->write8(rtwdev, addr, data); 8236 } 8237 8238 static inline void rtw89_raw_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 8239 { 8240 rtwdev->hci.ops->write16(rtwdev, addr, data); 8241 } 8242 8243 static inline void rtw89_raw_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 8244 { 8245 rtwdev->hci.ops->write32(rtwdev, addr, data); 8246 } 8247 8248 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 8249 { 8250 rtwdev->io->write8(rtwdev, addr, data); 8251 } 8252 8253 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 8254 { 8255 rtwdev->io->write16(rtwdev, addr, data); 8256 } 8257 8258 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 8259 { 8260 rtwdev->io->write32(rtwdev, addr, data); 8261 } 8262 8263 static inline void 8264 rtw89_raw_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 8265 { 8266 u8 val; 8267 8268 val = rtw89_read8(rtwdev, addr); 8269 rtw89_raw_write8(rtwdev, addr, val | bit); 8270 } 8271 8272 static inline void 8273 rtw89_raw_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 8274 { 8275 u16 val; 8276 8277 val = rtw89_read16(rtwdev, addr); 8278 rtw89_raw_write16(rtwdev, addr, val | bit); 8279 } 8280 8281 static inline void 8282 rtw89_raw_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 8283 { 8284 u32 val; 8285 8286 val = rtw89_read32(rtwdev, addr); 8287 rtw89_raw_write32(rtwdev, addr, val | bit); 8288 } 8289 8290 static inline void 8291 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 8292 { 8293 rtwdev->io->write8_set(rtwdev, addr, bit); 8294 } 8295 8296 static inline void 8297 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 8298 { 8299 rtwdev->io->write16_set(rtwdev, addr, bit); 8300 } 8301 8302 static inline void 8303 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 8304 { 8305 rtwdev->io->write32_set(rtwdev, addr, bit); 8306 } 8307 8308 static inline void 8309 rtw89_raw_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 8310 { 8311 u8 val; 8312 8313 val = rtw89_read8(rtwdev, addr); 8314 rtw89_raw_write8(rtwdev, addr, val & ~bit); 8315 } 8316 8317 static inline void 8318 rtw89_raw_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 8319 { 8320 u16 val; 8321 8322 val = rtw89_read16(rtwdev, addr); 8323 rtw89_raw_write16(rtwdev, addr, val & ~bit); 8324 } 8325 8326 static inline void 8327 rtw89_raw_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 8328 { 8329 u32 val; 8330 8331 val = rtw89_read32(rtwdev, addr); 8332 rtw89_raw_write32(rtwdev, addr, val & ~bit); 8333 } 8334 8335 static inline void 8336 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 8337 { 8338 rtwdev->io->write8_clr(rtwdev, addr, bit); 8339 } 8340 8341 static inline void 8342 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 8343 { 8344 rtwdev->io->write16_clr(rtwdev, addr, bit); 8345 } 8346 8347 static inline void 8348 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 8349 { 8350 rtwdev->io->write32_clr(rtwdev, addr, bit); 8351 } 8352 8353 static inline u32 8354 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 8355 { 8356 u32 shift = __ffs(mask); 8357 u32 orig; 8358 u32 ret; 8359 8360 orig = rtw89_read32(rtwdev, addr); 8361 ret = (orig & mask) >> shift; 8362 8363 return ret; 8364 } 8365 8366 static inline u16 8367 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 8368 { 8369 u32 shift = __ffs(mask); 8370 u32 orig; 8371 u32 ret; 8372 8373 orig = rtw89_read16(rtwdev, addr); 8374 ret = (orig & mask) >> shift; 8375 8376 return ret; 8377 } 8378 8379 static inline u8 8380 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 8381 { 8382 u32 shift = __ffs(mask); 8383 u32 orig; 8384 u32 ret; 8385 8386 orig = rtw89_read8(rtwdev, addr); 8387 ret = (orig & mask) >> shift; 8388 8389 return ret; 8390 } 8391 8392 static inline void 8393 rtw89_raw_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 8394 { 8395 u8 orig, set; 8396 8397 orig = rtw89_read8(rtwdev, addr); 8398 set = (orig & ~mask) | (data & mask); 8399 rtw89_raw_write8(rtwdev, addr, set); 8400 } 8401 8402 static inline void 8403 rtw89_raw_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 8404 { 8405 u16 orig, set; 8406 8407 orig = rtw89_read16(rtwdev, addr); 8408 set = (orig & ~mask) | (data & mask); 8409 rtw89_raw_write16(rtwdev, addr, set); 8410 } 8411 8412 static inline void 8413 rtw89_raw_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 8414 { 8415 u32 orig, set; 8416 8417 orig = rtw89_read32(rtwdev, addr); 8418 set = (orig & ~mask) | (data & mask); 8419 rtw89_raw_write32(rtwdev, addr, set); 8420 } 8421 8422 static inline void 8423 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 8424 { 8425 u32 shift = __ffs(mask); 8426 8427 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 8428 8429 rtwdev->io->write32_mask(rtwdev, addr, mask, (data << shift) & mask); 8430 } 8431 8432 static inline void 8433 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 8434 { 8435 u32 shift; 8436 8437 mask &= 0xffff; 8438 shift = __ffs(mask); 8439 8440 rtwdev->io->write16_mask(rtwdev, addr, mask, (data << shift) & mask); 8441 } 8442 8443 static inline void 8444 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 8445 { 8446 u32 shift; 8447 8448 mask &= 0xff; 8449 shift = __ffs(mask); 8450 8451 rtwdev->io->write8_mask(rtwdev, addr, mask, (data << shift) & mask); 8452 } 8453 8454 static inline u32 8455 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 8456 u32 addr, u32 mask) 8457 { 8458 lockdep_assert_wiphy(rtwdev->hw->wiphy); 8459 8460 return rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 8461 } 8462 8463 static inline void 8464 rtw89_raw_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 8465 u32 addr, u32 mask, u32 data) 8466 { 8467 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 8468 } 8469 8470 static inline void 8471 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 8472 u32 addr, u32 mask, u32 data) 8473 { 8474 lockdep_assert_wiphy(rtwdev->hw->wiphy); 8475 8476 rtwdev->io->write_rf(rtwdev, rf_path, addr, mask, data); 8477 } 8478 8479 static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr) 8480 { 8481 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE || 8482 !rtwdev->hci.ops->read32_pci_cfg) 8483 return RTW89_R32_EA; 8484 8485 return rtwdev->hci.ops->read32_pci_cfg(rtwdev, addr); 8486 } 8487 8488 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 8489 { 8490 void *p = rtwtxq; 8491 8492 return container_of(p, struct ieee80211_txq, drv_priv); 8493 } 8494 8495 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 8496 struct ieee80211_txq *txq) 8497 { 8498 struct rtw89_txq *rtwtxq; 8499 8500 if (!txq) 8501 return; 8502 8503 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 8504 INIT_LIST_HEAD(&rtwtxq->list); 8505 } 8506 8507 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 8508 { 8509 void *p = rtwvif; 8510 8511 return container_of(p, struct ieee80211_vif, drv_priv); 8512 } 8513 8514 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 8515 { 8516 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 8517 } 8518 8519 static inline 8520 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 8521 { 8522 return rtwvif_to_vif(rtwvif_link->rtwvif); 8523 } 8524 8525 static inline 8526 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 8527 { 8528 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 8529 } 8530 8531 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 8532 { 8533 return (struct rtw89_vif *)vif->drv_priv; 8534 } 8535 8536 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 8537 { 8538 return vif ? vif_to_rtwvif(vif) : NULL; 8539 } 8540 8541 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 8542 { 8543 void *p = rtwsta; 8544 8545 return container_of(p, struct ieee80211_sta, drv_priv); 8546 } 8547 8548 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 8549 { 8550 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 8551 } 8552 8553 static inline 8554 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 8555 { 8556 return rtwsta_to_sta(rtwsta_link->rtwsta); 8557 } 8558 8559 static inline 8560 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 8561 { 8562 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 8563 } 8564 8565 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 8566 { 8567 return (struct rtw89_sta *)sta->drv_priv; 8568 } 8569 8570 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 8571 { 8572 return sta ? sta_to_rtwsta(sta) : NULL; 8573 } 8574 8575 static inline struct ieee80211_bss_conf * 8576 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 8577 { 8578 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 8579 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 8580 struct rtw89_link_conf_container *snap; 8581 struct ieee80211_bss_conf *bss_conf; 8582 8583 snap = rcu_dereference(rtwvif->snap_link_confs); 8584 if (snap) { 8585 bss_conf = snap->link_conf[rtwvif_link->link_id]; 8586 goto out; 8587 } 8588 8589 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 8590 8591 out: 8592 if (unlikely(!bss_conf)) { 8593 *nolink = true; 8594 return &vif->bss_conf; 8595 } 8596 8597 *nolink = false; 8598 return bss_conf; 8599 } 8600 8601 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 8602 ({ \ 8603 typeof(rtwvif_link) p = rtwvif_link; \ 8604 struct ieee80211_bss_conf *bss_conf; \ 8605 bool nolink; \ 8606 \ 8607 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 8608 if (unlikely(nolink) && (assert)) \ 8609 rtw89_err(p->rtwvif->rtwdev, \ 8610 "%s: cannot find exact bss_conf for link_id %u\n",\ 8611 __func__, p->link_id); \ 8612 bss_conf; \ 8613 }) 8614 8615 static inline struct ieee80211_link_sta * 8616 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 8617 { 8618 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 8619 struct ieee80211_link_sta *link_sta; 8620 8621 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 8622 if (unlikely(!link_sta)) { 8623 *nolink = true; 8624 return &sta->deflink; 8625 } 8626 8627 *nolink = false; 8628 return link_sta; 8629 } 8630 8631 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 8632 ({ \ 8633 typeof(rtwsta_link) p = rtwsta_link; \ 8634 struct ieee80211_link_sta *link_sta; \ 8635 bool nolink; \ 8636 \ 8637 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 8638 if (unlikely(nolink) && (assert)) \ 8639 rtw89_err(p->rtwsta->rtwdev, \ 8640 "%s: cannot find exact link_sta for link_id %u\n",\ 8641 __func__, p->link_id); \ 8642 link_sta; \ 8643 }) 8644 8645 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 8646 { 8647 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 8648 return RATE_INFO_BW_160; 8649 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 8650 return RATE_INFO_BW_80; 8651 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 8652 return RATE_INFO_BW_40; 8653 else 8654 return RATE_INFO_BW_20; 8655 } 8656 8657 static inline 8658 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 8659 { 8660 switch (hw_band) { 8661 default: 8662 case RTW89_BAND_2G: 8663 return NL80211_BAND_2GHZ; 8664 case RTW89_BAND_5G: 8665 return NL80211_BAND_5GHZ; 8666 case RTW89_BAND_6G: 8667 return NL80211_BAND_6GHZ; 8668 } 8669 } 8670 8671 static inline 8672 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 8673 { 8674 switch (nl_band) { 8675 default: 8676 case NL80211_BAND_2GHZ: 8677 return RTW89_BAND_2G; 8678 case NL80211_BAND_5GHZ: 8679 return RTW89_BAND_5G; 8680 case NL80211_BAND_6GHZ: 8681 return RTW89_BAND_6G; 8682 } 8683 } 8684 8685 static inline 8686 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 8687 { 8688 switch (width) { 8689 default: 8690 WARN(1, "Not support bandwidth %d\n", width); 8691 fallthrough; 8692 case NL80211_CHAN_WIDTH_20_NOHT: 8693 case NL80211_CHAN_WIDTH_20: 8694 return RTW89_CHANNEL_WIDTH_20; 8695 case NL80211_CHAN_WIDTH_40: 8696 return RTW89_CHANNEL_WIDTH_40; 8697 case NL80211_CHAN_WIDTH_80: 8698 return RTW89_CHANNEL_WIDTH_80; 8699 case NL80211_CHAN_WIDTH_160: 8700 return RTW89_CHANNEL_WIDTH_160; 8701 } 8702 } 8703 8704 static inline 8705 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 8706 { 8707 switch (rua) { 8708 default: 8709 WARN(1, "Invalid RU allocation: %d\n", rua); 8710 fallthrough; 8711 case 0 ... 36: 8712 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 8713 case 37 ... 52: 8714 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 8715 case 53 ... 60: 8716 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 8717 case 61 ... 64: 8718 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 8719 case 65 ... 66: 8720 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 8721 case 67: 8722 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 8723 case 68: 8724 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 8725 } 8726 } 8727 8728 static inline 8729 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 8730 struct rtw89_sta_link *rtwsta_link) 8731 { 8732 if (rtwsta_link) { 8733 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 8734 8735 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 8736 return &rtwsta_link->addr_cam; 8737 } 8738 return &rtwvif_link->addr_cam; 8739 } 8740 8741 static inline 8742 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 8743 struct rtw89_sta_link *rtwsta_link) 8744 { 8745 if (rtwsta_link) { 8746 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 8747 8748 if (sta->tdls) 8749 return &rtwsta_link->bssid_cam; 8750 } 8751 return &rtwvif_link->bssid_cam; 8752 } 8753 8754 static inline 8755 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 8756 struct rtw89_channel_help_params *p, 8757 const struct rtw89_chan *chan, 8758 enum rtw89_mac_idx mac_idx, 8759 enum rtw89_phy_idx phy_idx) 8760 { 8761 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 8762 mac_idx, phy_idx); 8763 } 8764 8765 static inline 8766 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 8767 struct rtw89_channel_help_params *p, 8768 const struct rtw89_chan *chan, 8769 enum rtw89_mac_idx mac_idx, 8770 enum rtw89_phy_idx phy_idx) 8771 { 8772 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 8773 mac_idx, phy_idx); 8774 } 8775 8776 static inline 8777 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 8778 enum rtw89_chanctx_idx idx) 8779 { 8780 struct rtw89_hal *hal = &rtwdev->hal; 8781 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 8782 8783 if (roc_idx == idx) 8784 return &hal->roc_chandef; 8785 8786 return &hal->chanctx[idx].chandef; 8787 } 8788 8789 static inline 8790 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 8791 enum rtw89_chanctx_idx idx) 8792 { 8793 struct rtw89_hal *hal = &rtwdev->hal; 8794 8795 return &hal->chanctx[idx].chan; 8796 } 8797 8798 static inline 8799 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 8800 enum rtw89_chanctx_idx idx) 8801 { 8802 struct rtw89_hal *hal = &rtwdev->hal; 8803 8804 return &hal->chanctx[idx].rcd; 8805 } 8806 8807 static inline 8808 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 8809 { 8810 const struct rtw89_chanctx *chanctx = 8811 container_of_const(chan, struct rtw89_chanctx, chan); 8812 8813 return &chanctx->rcd; 8814 } 8815 8816 static inline 8817 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 8818 { 8819 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 8820 8821 if (rtwvif_link) 8822 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 8823 else 8824 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 8825 } 8826 8827 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 8828 { 8829 const struct rtw89_chip_info *chip = rtwdev->chip; 8830 8831 if (chip->ops->fem_setup) 8832 chip->ops->fem_setup(rtwdev); 8833 } 8834 8835 static inline int rtw89_chip_data_setup(struct rtw89_dev *rtwdev) 8836 { 8837 const struct rtw89_chip_info *chip = rtwdev->chip; 8838 8839 if (!chip->ops->data_setup) 8840 return 0; 8841 8842 return chip->ops->data_setup(rtwdev); 8843 } 8844 8845 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 8846 { 8847 const struct rtw89_chip_info *chip = rtwdev->chip; 8848 8849 if (chip->ops->rfe_gpio) 8850 chip->ops->rfe_gpio(rtwdev); 8851 } 8852 8853 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 8854 { 8855 const struct rtw89_chip_info *chip = rtwdev->chip; 8856 8857 if (chip->ops->rfk_hw_init) 8858 chip->ops->rfk_hw_init(rtwdev); 8859 } 8860 8861 static inline 8862 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev) 8863 { 8864 const struct rtw89_chip_info *chip = rtwdev->chip; 8865 8866 if (!chip->ops->bb_preinit) 8867 return; 8868 8869 chip->ops->bb_preinit(rtwdev, RTW89_PHY_0); 8870 8871 if (rtwdev->dbcc_en) 8872 chip->ops->bb_preinit(rtwdev, RTW89_PHY_1); 8873 } 8874 8875 static inline 8876 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 8877 { 8878 const struct rtw89_chip_info *chip = rtwdev->chip; 8879 8880 if (!chip->ops->bb_postinit) 8881 return; 8882 8883 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 8884 8885 if (rtwdev->dbcc_en) 8886 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 8887 } 8888 8889 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 8890 { 8891 const struct rtw89_chip_info *chip = rtwdev->chip; 8892 8893 rtw89_io_pack(rtwdev); 8894 8895 if (chip->ops->bb_sethw) 8896 chip->ops->bb_sethw(rtwdev); 8897 8898 rtw89_io_unpack(rtwdev); 8899 } 8900 8901 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 8902 { 8903 const struct rtw89_chip_info *chip = rtwdev->chip; 8904 8905 if (chip->ops->rfk_init) 8906 chip->ops->rfk_init(rtwdev); 8907 } 8908 8909 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 8910 { 8911 const struct rtw89_chip_info *chip = rtwdev->chip; 8912 8913 if (chip->ops->rfk_init_late) 8914 chip->ops->rfk_init_late(rtwdev); 8915 } 8916 8917 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 8918 enum rtw89_phy_idx phy_idx, 8919 const struct rtw89_chan *chan) 8920 { 8921 const struct rtw89_chip_info *chip = rtwdev->chip; 8922 8923 if (chip->ops->rfk_band_changed) 8924 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 8925 } 8926 8927 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 8928 struct rtw89_vif_link *rtwvif_link, bool start) 8929 { 8930 const struct rtw89_chip_info *chip = rtwdev->chip; 8931 8932 if (chip->ops->rfk_scan) 8933 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 8934 } 8935 8936 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 8937 { 8938 const struct rtw89_chip_info *chip = rtwdev->chip; 8939 8940 if (chip->ops->rfk_track) 8941 chip->ops->rfk_track(rtwdev); 8942 } 8943 8944 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 8945 { 8946 const struct rtw89_chip_info *chip = rtwdev->chip; 8947 8948 if (!chip->ops->set_txpwr_ctrl) 8949 return; 8950 8951 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 8952 if (rtwdev->dbcc_en) 8953 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 8954 } 8955 8956 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 8957 { 8958 const struct rtw89_chip_info *chip = rtwdev->chip; 8959 8960 if (chip->ops->power_trim) 8961 chip->ops->power_trim(rtwdev); 8962 } 8963 8964 static inline void rtw89_chip_path_diff_update(struct rtw89_dev *rtwdev, 8965 struct rtw89_bb_ctx *bb) 8966 { 8967 const struct rtw89_chip_info *chip = rtwdev->chip; 8968 8969 if (chip->ops->path_diff_update) 8970 chip->ops->path_diff_update(rtwdev, bb); 8971 } 8972 8973 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 8974 enum rtw89_phy_idx phy_idx) 8975 { 8976 const struct rtw89_chip_info *chip = rtwdev->chip; 8977 8978 if (chip->ops->init_txpwr_unit) 8979 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 8980 } 8981 8982 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 8983 { 8984 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 8985 if (rtwdev->dbcc_en) 8986 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 8987 } 8988 8989 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 8990 enum rtw89_rf_path rf_path) 8991 { 8992 const struct rtw89_chip_info *chip = rtwdev->chip; 8993 8994 if (!chip->ops->get_thermal) 8995 return 0x10; 8996 8997 return chip->ops->get_thermal(rtwdev, rf_path); 8998 } 8999 9000 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev, 9001 const struct rtw89_chan *chan) 9002 { 9003 const struct rtw89_chip_info *chip = rtwdev->chip; 9004 9005 if (!chip->ops->chan_to_rf18_val) 9006 return 0; 9007 9008 return chip->ops->chan_to_rf18_val(rtwdev, chan); 9009 } 9010 9011 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 9012 struct rtw89_rx_phy_ppdu *phy_ppdu, 9013 struct ieee80211_rx_status *status) 9014 { 9015 const struct rtw89_chip_info *chip = rtwdev->chip; 9016 9017 if (chip->ops->query_ppdu) 9018 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 9019 } 9020 9021 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 9022 struct rtw89_rx_phy_ppdu *phy_ppdu) 9023 { 9024 const struct rtw89_chip_info *chip = rtwdev->chip; 9025 9026 if (chip->ops->convert_rpl_to_rssi) 9027 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 9028 } 9029 9030 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 9031 struct rtw89_rx_desc_info *desc_info, 9032 struct ieee80211_rx_status *rx_status) 9033 { 9034 const struct rtw89_chip_info *chip = rtwdev->chip; 9035 9036 if (chip->ops->phy_rpt_to_rssi) 9037 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 9038 } 9039 9040 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 9041 enum rtw89_phy_idx phy_idx) 9042 { 9043 const struct rtw89_chip_info *chip = rtwdev->chip; 9044 9045 if (chip->ops->ctrl_nbtg_bt_tx) 9046 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 9047 } 9048 9049 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 9050 { 9051 const struct rtw89_chip_info *chip = rtwdev->chip; 9052 9053 if (chip->ops->cfg_txrx_path) 9054 chip->ops->cfg_txrx_path(rtwdev); 9055 } 9056 9057 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 9058 enum rtw89_phy_idx phy_idx) 9059 { 9060 const struct rtw89_chip_info *chip = rtwdev->chip; 9061 9062 if (chip->ops->digital_pwr_comp) 9063 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 9064 } 9065 9066 static inline 9067 void rtw89_chip_calc_rx_gain_normal(struct rtw89_dev *rtwdev, 9068 const struct rtw89_chan *chan, 9069 enum rtw89_rf_path path, 9070 enum rtw89_phy_idx phy_idx, 9071 struct rtw89_phy_calc_efuse_gain *calc) 9072 { 9073 const struct rtw89_chip_info *chip = rtwdev->chip; 9074 9075 if (chip->ops->calc_rx_gain_normal) 9076 chip->ops->calc_rx_gain_normal(rtwdev, chan, path, phy_idx, calc); 9077 } 9078 9079 static inline const struct rtw89_fw_def * 9080 __rtw89_chip_get_fw_def(const struct rtw89_chip_info *chip, 9081 const struct rtw89_chip_variant *variant) 9082 { 9083 if (variant && variant->fw_def_override) 9084 return variant->fw_def_override; 9085 9086 return &chip->fw_def; 9087 } 9088 9089 static inline 9090 const struct rtw89_fw_def *rtw89_chip_get_fw_def(struct rtw89_dev *rtwdev) 9091 { 9092 return __rtw89_chip_get_fw_def(rtwdev->chip, rtwdev->variant); 9093 } 9094 9095 static inline 9096 const struct rtw89_qta_def *rtw89_chip_get_qta_def(struct rtw89_dev *rtwdev) 9097 { 9098 const struct rtw89_chip_variant *variant = rtwdev->variant; 9099 9100 if (variant && variant->qta_def_override) 9101 return variant->qta_def_override; 9102 9103 return &rtwdev->chip->qta_def; 9104 } 9105 9106 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 9107 const struct rtw89_txpwr_table *tbl) 9108 { 9109 tbl->load(rtwdev, tbl); 9110 } 9111 9112 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 9113 { 9114 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 9115 const struct rtw89_regd *regd = regulatory->regd; 9116 u8 txpwr_regd = regd->txpwr_regd[band]; 9117 9118 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK) 9119 return RTW89_ETSI; 9120 9121 return txpwr_regd; 9122 } 9123 9124 static inline u8 rtw89_get_tx_shape_idx(struct rtw89_dev *rtwdev, u8 band, 9125 enum rtw89_rate_section rs) 9126 { 9127 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 9128 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 9129 const struct rtw89_tx_shape *tx_shape = &rfe_parms->tx_shape; 9130 u8 reg6_pwr = regulatory->reg_6ghz_power; 9131 u8 regd = rtw89_regd_get(rtwdev, band); 9132 9133 if (unlikely(rs >= RTW89_RS_TX_SHAPE_NUM)) 9134 rs = RTW89_RS_OFDM; 9135 9136 if (!tx_shape->lmt) 9137 goto v0; 9138 9139 if (band != RTW89_BAND_6G) 9140 reg6_pwr = RTW89_REG_6GHZ_POWER_DFLT; 9141 9142 return (*tx_shape->lmt)[band][rs][regd][reg6_pwr]; 9143 9144 v0: 9145 return (*tx_shape->lmt_v0)[band][rs][regd]; 9146 } 9147 9148 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 9149 enum rtw89_phy_idx phy_idx) 9150 { 9151 const struct rtw89_chip_info *chip = rtwdev->chip; 9152 9153 if (chip->ops->ctrl_btg_bt_rx) 9154 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 9155 } 9156 9157 static inline 9158 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 9159 struct rtw89_rx_desc_info *desc_info, 9160 u8 *data, u32 data_offset) 9161 { 9162 const struct rtw89_chip_info *chip = rtwdev->chip; 9163 9164 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 9165 } 9166 9167 static inline 9168 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 9169 struct rtw89_tx_desc_info *desc_info, 9170 void *txdesc) 9171 { 9172 const struct rtw89_chip_info *chip = rtwdev->chip; 9173 9174 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 9175 } 9176 9177 static inline 9178 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 9179 struct rtw89_tx_desc_info *desc_info, 9180 void *txdesc) 9181 { 9182 const struct rtw89_chip_info *chip = rtwdev->chip; 9183 9184 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 9185 } 9186 9187 static inline 9188 u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 9189 { 9190 const struct rtw89_chip_info *chip = rtwdev->chip; 9191 9192 return chip->ops->get_ch_dma[rtwdev->hci.type](rtwdev, qsel); 9193 } 9194 9195 static inline 9196 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 9197 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 9198 { 9199 const struct rtw89_chip_info *chip = rtwdev->chip; 9200 9201 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 9202 } 9203 9204 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 9205 { 9206 const struct rtw89_chip_info *chip = rtwdev->chip; 9207 9208 chip->ops->cfg_ctrl_path(rtwdev, wl); 9209 } 9210 9211 static inline 9212 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 9213 u32 *tx_en, enum rtw89_sch_tx_sel sel) 9214 { 9215 const struct rtw89_chip_info *chip = rtwdev->chip; 9216 9217 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 9218 } 9219 9220 static inline 9221 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 9222 { 9223 const struct rtw89_chip_info *chip = rtwdev->chip; 9224 9225 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 9226 } 9227 9228 static inline 9229 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 9230 struct rtw89_vif_link *rtwvif_link, 9231 struct rtw89_sta_link *rtwsta_link) 9232 { 9233 const struct rtw89_chip_info *chip = rtwdev->chip; 9234 9235 if (!chip->ops->h2c_dctl_sec_cam) 9236 return 0; 9237 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 9238 } 9239 9240 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 9241 { 9242 __le16 fc = hdr->frame_control; 9243 9244 if (ieee80211_has_tods(fc)) 9245 return hdr->addr1; 9246 else if (ieee80211_has_fromds(fc)) 9247 return hdr->addr2; 9248 else 9249 return hdr->addr3; 9250 } 9251 9252 static inline 9253 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 9254 { 9255 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 9256 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 9257 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 9258 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 9259 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 9260 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 9261 return true; 9262 return false; 9263 } 9264 9265 static inline 9266 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 9267 { 9268 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 9269 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 9270 return true; 9271 9272 return false; 9273 } 9274 9275 static inline 9276 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 9277 { 9278 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 9279 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 9280 return true; 9281 9282 return false; 9283 } 9284 9285 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 9286 enum rtw89_fw_type type) 9287 { 9288 struct rtw89_fw_info *fw_info = &rtwdev->fw; 9289 9290 switch (type) { 9291 case RTW89_FW_WOWLAN: 9292 case RTW89_FW_WOWLAN_B: 9293 return &fw_info->wowlan; 9294 case RTW89_FW_LOGFMT: 9295 return &fw_info->log.suit; 9296 case RTW89_FW_BBMCU0: 9297 return &fw_info->bbmcu0; 9298 case RTW89_FW_BBMCU1: 9299 return &fw_info->bbmcu1; 9300 default: 9301 break; 9302 } 9303 9304 return &fw_info->normal; 9305 } 9306 9307 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 9308 unsigned int length) 9309 { 9310 struct sk_buff *skb; 9311 9312 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 9313 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 9314 if (!skb) 9315 return NULL; 9316 9317 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 9318 return skb; 9319 } 9320 9321 return dev_alloc_skb(length); 9322 } 9323 9324 static inline bool rtw89_core_is_tx_wait(struct rtw89_dev *rtwdev, 9325 struct rtw89_tx_skb_data *skb_data) 9326 { 9327 return rcu_access_pointer(skb_data->wait); 9328 } 9329 9330 static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 9331 struct rtw89_tx_skb_data *skb_data, 9332 u8 tx_status) 9333 { 9334 struct rtw89_tx_wait_info *wait; 9335 9336 guard(rcu)(); 9337 9338 wait = rcu_dereference(skb_data->wait); 9339 if (!wait) 9340 return false; 9341 9342 wait->tx_done = tx_status == RTW89_TX_DONE; 9343 /* Don't access skb anymore after completion */ 9344 complete_all(&wait->completion); 9345 return true; 9346 } 9347 9348 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 9349 { 9350 switch (rtwdev->mlo_dbcc_mode) { 9351 case MLO_1_PLUS_1_1RF: 9352 case MLO_1_PLUS_1_2RF: 9353 case DBCC_LEGACY: 9354 return true; 9355 default: 9356 return false; 9357 } 9358 } 9359 9360 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 9361 { 9362 if (!rtwdev->dbcc_en) 9363 return BIT(RTW89_PHY_0); 9364 9365 switch (rtwdev->mlo_dbcc_mode) { 9366 case MLO_0_PLUS_2_1RF: 9367 case MLO_0_PLUS_2_2RF: 9368 return BIT(RTW89_PHY_1); 9369 case MLO_1_PLUS_1_1RF: 9370 case MLO_1_PLUS_1_2RF: 9371 case MLO_2_PLUS_2_2RF: 9372 case DBCC_LEGACY: 9373 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 9374 case MLO_2_PLUS_0_1RF: 9375 case MLO_2_PLUS_0_2RF: 9376 default: 9377 return BIT(RTW89_PHY_0); 9378 } 9379 } 9380 9381 #define rtw89_for_each_active_bb(rtwdev, bb) \ 9382 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 9383 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 9384 if (__active_bb_bitmap & BIT(__phy_idx) && \ 9385 (bb = &rtwdev->bbs[__phy_idx])) 9386 9387 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 9388 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 9389 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 9390 if ((bb = &rtwdev->bbs[__phy_idx])) 9391 9392 static inline 9393 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 9394 enum rtw89_phy_idx phy_idx) 9395 { 9396 if (phy_idx >= RTW89_PHY_NUM) 9397 return &rtwdev->bbs[RTW89_PHY_0]; 9398 9399 return &rtwdev->bbs[phy_idx]; 9400 } 9401 9402 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 9403 { 9404 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 9405 9406 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 9407 return true; 9408 9409 return false; 9410 } 9411 9412 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval) 9413 { 9414 switch (interval) { 9415 default: 9416 case RTW89_TFC_INTERVAL_2SEC: 9417 return bytes >> 18; /* bytes/2s --> Mbps */; 9418 case RTW89_TFC_INTERVAL_100MS: 9419 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */ 9420 } 9421 } 9422 9423 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 9424 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 9425 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 9426 struct sk_buff *skb, bool fwdl); 9427 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 9428 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 9429 struct rtw89_tx_wait_info *wait, int qsel, 9430 unsigned int timeout); 9431 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 9432 struct rtw89_tx_desc_info *desc_info, 9433 void *txdesc); 9434 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 9435 struct rtw89_tx_desc_info *desc_info, 9436 void *txdesc); 9437 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 9438 struct rtw89_tx_desc_info *desc_info, 9439 void *txdesc); 9440 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev, 9441 struct rtw89_tx_desc_info *desc_info, 9442 void *txdesc); 9443 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 9444 struct rtw89_tx_desc_info *desc_info, 9445 void *txdesc); 9446 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 9447 struct rtw89_tx_desc_info *desc_info, 9448 void *txdesc); 9449 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel); 9450 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel); 9451 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel); 9452 void rtw89_core_rx(struct rtw89_dev *rtwdev, 9453 struct rtw89_rx_desc_info *desc_info, 9454 struct sk_buff *skb); 9455 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 9456 struct rtw89_rx_desc_info *desc_info, 9457 u8 *data, u32 data_offset); 9458 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 9459 struct rtw89_rx_desc_info *desc_info, 9460 u8 *data, u32 data_offset); 9461 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev, 9462 struct rtw89_rx_desc_info *desc_info, 9463 u8 *data, u32 data_offset); 9464 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 9465 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 9466 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 9467 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 9468 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 9469 struct rtw89_vif_link *rtwvif_link, 9470 struct rtw89_sta_link *rtwsta_link); 9471 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 9472 struct rtw89_vif_link *rtwvif_link, 9473 struct rtw89_sta_link *rtwsta_link); 9474 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 9475 struct rtw89_vif_link *rtwvif_link, 9476 struct rtw89_sta_link *rtwsta_link); 9477 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 9478 struct rtw89_vif_link *rtwvif_link, 9479 struct rtw89_sta_link *rtwsta_link); 9480 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 9481 struct rtw89_vif_link *rtwvif_link, 9482 struct rtw89_sta_link *rtwsta_link); 9483 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 9484 struct ieee80211_sta *sta, 9485 struct cfg80211_tid_config *tid_config); 9486 void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 9487 struct ieee80211_ampdu_params *params, bool enable); 9488 void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev); 9489 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 9490 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 9491 int rtw89_core_init(struct rtw89_dev *rtwdev); 9492 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 9493 int rtw89_core_register(struct rtw89_dev *rtwdev); 9494 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 9495 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 9496 u32 bus_data_size, 9497 const struct rtw89_driver_info *info); 9498 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 9499 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 9500 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 9501 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 9502 u8 mac_id, u8 port); 9503 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 9504 struct rtw89_sta *rtwsta, u8 mac_id); 9505 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 9506 unsigned int link_id); 9507 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 9508 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 9509 unsigned int link_id); 9510 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 9511 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 9512 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 9513 struct rtw89_vif_link *rtwvif_link); 9514 const struct rtw89_6ghz_span * 9515 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 9516 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 9517 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 9518 struct rtw89_chan *chan); 9519 int rtw89_set_channel(struct rtw89_dev *rtwdev); 9520 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 9521 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 9522 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 9523 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 9524 struct rtw89_sta *rtwsta, u8 tid, 9525 u8 *cam_idx); 9526 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 9527 struct rtw89_sta *rtwsta, u8 tid, 9528 u8 *cam_idx); 9529 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 9530 struct ieee80211_sta *sta); 9531 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 9532 struct ieee80211_sta *sta); 9533 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 9534 struct ieee80211_sta *sta); 9535 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 9536 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 9537 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 9538 struct rtw89_vif_link *rtwvif_link); 9539 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate); 9540 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 9541 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 9542 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 9543 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 9544 struct rtw89_traffic_stats *stats); 9545 struct rtw89_wait_response * 9546 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 9547 __acquires(rtw89_wait); 9548 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 9549 struct rtw89_wait_response *prep, int err) 9550 __releases(rtw89_wait); 9551 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 9552 const struct rtw89_completion_data *data); 9553 int rtw89_core_start(struct rtw89_dev *rtwdev); 9554 void rtw89_core_stop(struct rtw89_dev *rtwdev); 9555 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 9556 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 9557 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 9558 bool qos, bool ps, int timeout); 9559 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 9560 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 9561 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 9562 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 9563 const u8 *mac_addr, bool hw_scan); 9564 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 9565 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 9566 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 9567 bool active); 9568 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 9569 struct rtw89_vif_link *rtwvif_link, 9570 struct ieee80211_bss_conf *bss_conf); 9571 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, 9572 enum rtw89_btc_hmsg event, 9573 enum rtw89_phy_idx phy_idx); 9574 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 9575 unsigned int link_id); 9576 void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new); 9577 void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type); 9578 void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type); 9579 9580 #endif 9581