xref: /linux/include/misc/cxllib.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright 2017 IBM Corp.
4  */
5 
6 #ifndef _MISC_CXLLIB_H
7 #define _MISC_CXLLIB_H
8 
9 #include <linux/pci.h>
10 #include <asm/reg.h>
11 
12 /*
13  * cxl driver exports a in-kernel 'library' API which can be called by
14  * other drivers to help interacting with an IBM XSL.
15  */
16 
17 /*
18  * tells whether capi is supported on the PCIe slot where the
19  * device is seated
20  *
21  * Input:
22  *	dev: device whose slot needs to be checked
23  *	flags: 0 for the time being
24  */
25 bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags);
26 
27 
28 /*
29  * Returns the configuration parameters to be used by the XSL or device
30  *
31  * Input:
32  *	dev: device, used to find PHB
33  * Output:
34  *	struct cxllib_xsl_config:
35  *		version
36  *		capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF
37  *		capi BAR size
38  *		data send control (XSL_DSNCTL)
39  *		dummy read address (XSL_DRA)
40  */
41 #define CXL_XSL_CONFIG_VERSION1		1
42 struct cxllib_xsl_config {
43 	u32	version;     /* format version for register encoding */
44 	u32	log_bar_size;/* log size of the capi_window */
45 	u64	bar_addr;    /* address of the start of capi window */
46 	u64	dsnctl;      /* matches definition of XSL_DSNCTL */
47 	u64	dra;         /* real address that can be used for dummy read */
48 };
49 
50 int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg);
51 
52 
53 /*
54  * Activate capi for the pci host bridge associated with the device.
55  * Can be extended to deactivate once we know how to do it.
56  * Device must be ready to accept messages from the CAPP unit and
57  * respond accordingly (TLB invalidates, ...)
58  *
59  * PHB is switched to capi mode through calls to skiboot.
60  * CAPP snooping is activated
61  *
62  * Input:
63  *	dev: device whose PHB should switch mode
64  *	mode: mode to switch to i.e. CAPI or PCI
65  *	flags: options related to the mode
66  */
67 enum cxllib_mode {
68 	CXL_MODE_CXL,
69 	CXL_MODE_PCI,
70 };
71 
72 #define CXL_MODE_NO_DMA       0
73 #define CXL_MODE_DMA_TVT0     1
74 #define CXL_MODE_DMA_TVT1     2
75 
76 int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
77 			unsigned long flags);
78 
79 
80 /*
81  * Set the device for capi DMA.
82  * Define its dma_ops and dma offset so that allocations will be using TVT#1
83  *
84  * Input:
85  *	dev: device to set
86  *	flags: options. CXL_MODE_DMA_TVT1 should be used
87  */
88 int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags);
89 
90 
91 /*
92  * Get the Process Element structure for the given thread
93  *
94  * Input:
95  *    task: task_struct for the context of the translation
96  *    translation_mode: whether addresses should be translated
97  * Output:
98  *    attr: attributes to fill up the Process Element structure from CAIA
99  */
100 struct cxllib_pe_attributes {
101 	u64 sr;
102 	u32 lpid;
103 	u32 tid;
104 	u32 pid;
105 };
106 #define CXL_TRANSLATED_MODE 0
107 #define CXL_REAL_MODE 1
108 
109 int cxllib_get_PE_attributes(struct task_struct *task,
110 	     unsigned long translation_mode, struct cxllib_pe_attributes *attr);
111 
112 
113 /*
114  * Handle memory fault.
115  * Fault in all the pages of the specified buffer for the permissions
116  * provided in ‘flags’
117  *
118  * Shouldn't be called from interrupt context
119  *
120  * Input:
121  *	mm: struct mm for the thread faulting the pages
122  *	addr: base address of the buffer to page in
123  *	size: size of the buffer to page in
124  *	flags: permission requested (DSISR_ISSTORE...)
125  */
126 int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags);
127 
128 
129 #endif /* _MISC_CXLLIB_H */
130