1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_CORE_H__ 5 #define __CXL_CORE_H__ 6 7 #include <cxl/mailbox.h> 8 #include <linux/rwsem.h> 9 10 extern const struct device_type cxl_nvdimm_bridge_type; 11 extern const struct device_type cxl_nvdimm_type; 12 extern const struct device_type cxl_pmu_type; 13 14 extern struct attribute_group cxl_base_attribute_group; 15 16 enum cxl_detach_mode { 17 DETACH_ONLY, 18 DETACH_INVALIDATE, 19 }; 20 21 #ifdef CONFIG_CXL_REGION 22 23 struct cxl_region_context { 24 struct cxl_endpoint_decoder *cxled; 25 struct range hpa_range; 26 int interleave_ways; 27 int interleave_granularity; 28 }; 29 30 extern struct device_attribute dev_attr_create_pmem_region; 31 extern struct device_attribute dev_attr_create_ram_region; 32 extern struct device_attribute dev_attr_delete_region; 33 extern struct device_attribute dev_attr_region; 34 extern const struct device_type cxl_pmem_region_type; 35 extern const struct device_type cxl_dax_region_type; 36 extern const struct device_type cxl_region_type; 37 38 int cxl_decoder_detach(struct cxl_region *cxlr, 39 struct cxl_endpoint_decoder *cxled, int pos, 40 enum cxl_detach_mode mode); 41 42 #define CXL_REGION_ATTR(x) (&dev_attr_##x.attr) 43 #define CXL_REGION_TYPE(x) (&cxl_region_type) 44 #define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr), 45 #define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type) 46 #define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type) 47 int cxl_region_init(void); 48 void cxl_region_exit(void); 49 int cxl_get_poison_by_endpoint(struct cxl_port *port); 50 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa); 51 u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, 52 u64 dpa); 53 int devm_cxl_add_dax_region(struct cxl_region *cxlr); 54 int devm_cxl_add_pmem_region(struct cxl_region *cxlr); 55 void kill_regions(struct cxl_root_decoder *cxlrd); 56 57 #else 58 static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, 59 const struct cxl_memdev *cxlmd, u64 dpa) 60 { 61 return ULLONG_MAX; 62 } 63 static inline 64 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa) 65 { 66 return NULL; 67 } 68 static inline int cxl_get_poison_by_endpoint(struct cxl_port *port) 69 { 70 return 0; 71 } 72 static inline int cxl_decoder_detach(struct cxl_region *cxlr, 73 struct cxl_endpoint_decoder *cxled, 74 int pos, enum cxl_detach_mode mode) 75 { 76 return 0; 77 } 78 static inline int cxl_region_init(void) 79 { 80 return 0; 81 } 82 static inline void cxl_region_exit(void) 83 { 84 } 85 static inline void kill_regions(struct cxl_root_decoder *cxlrd) { }; 86 #define CXL_REGION_ATTR(x) NULL 87 #define CXL_REGION_TYPE(x) NULL 88 #define SET_CXL_REGION_ATTR(x) 89 #define CXL_PMEM_REGION_TYPE(x) NULL 90 #define CXL_DAX_REGION_TYPE(x) NULL 91 #endif 92 93 struct cxl_send_command; 94 struct cxl_mem_query_commands; 95 int cxl_query_cmd(struct cxl_mailbox *cxl_mbox, 96 struct cxl_mem_query_commands __user *q); 97 int cxl_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_send_command __user *s); 98 void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, 99 resource_size_t length); 100 101 struct dentry *cxl_debugfs_create_dir(const char *dir); 102 int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled, 103 enum cxl_partition_mode mode); 104 int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, u64 size); 105 int cxl_dpa_free(struct cxl_endpoint_decoder *cxled); 106 resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled); 107 resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled); 108 bool cxl_resource_contains_addr(const struct resource *res, const resource_size_t addr); 109 110 enum cxl_rcrb { 111 CXL_RCRB_DOWNSTREAM, 112 CXL_RCRB_UPSTREAM, 113 }; 114 struct cxl_rcrb_info; 115 resource_size_t __rcrb_to_component(struct device *dev, 116 struct cxl_rcrb_info *ri, 117 enum cxl_rcrb which); 118 u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb); 119 120 #define PCI_RCRB_CAP_LIST_ID_MASK GENMASK(7, 0) 121 #define PCI_RCRB_CAP_HDR_ID_MASK GENMASK(7, 0) 122 #define PCI_RCRB_CAP_HDR_NEXT_MASK GENMASK(15, 8) 123 #define PCI_CAP_EXP_SIZEOF 0x3c 124 125 struct cxl_rwsem { 126 /* 127 * All changes to HPA (interleave configuration) occur with this 128 * lock held for write. 129 */ 130 struct rw_semaphore region; 131 /* 132 * All changes to a device DPA space occur with this lock held 133 * for write. 134 */ 135 struct rw_semaphore dpa; 136 }; 137 138 extern struct cxl_rwsem cxl_rwsem; 139 140 int cxl_memdev_init(void); 141 void cxl_memdev_exit(void); 142 void cxl_mbox_init(void); 143 144 enum cxl_poison_trace_type { 145 CXL_POISON_TRACE_LIST, 146 CXL_POISON_TRACE_INJECT, 147 CXL_POISON_TRACE_CLEAR, 148 }; 149 150 enum poison_cmd_enabled_bits; 151 bool cxl_memdev_has_poison_cmd(struct cxl_memdev *cxlmd, 152 enum poison_cmd_enabled_bits cmd); 153 154 long cxl_pci_get_latency(struct pci_dev *pdev); 155 int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c); 156 int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, 157 struct access_coordinate *c); 158 159 static inline struct device *port_to_host(struct cxl_port *port) 160 { 161 struct cxl_port *parent = is_cxl_root(port) ? NULL : 162 to_cxl_port(port->dev.parent); 163 164 /* 165 * The host of CXL root port and the first level of ports is 166 * the platform firmware device, the host of all other ports 167 * is their parent port. 168 */ 169 if (!parent) 170 return port->uport_dev; 171 else if (is_cxl_root(parent)) 172 return parent->uport_dev; 173 else 174 return &parent->dev; 175 } 176 177 static inline struct device *dport_to_host(struct cxl_dport *dport) 178 { 179 struct cxl_port *port = dport->port; 180 181 if (is_cxl_root(port)) 182 return port->uport_dev; 183 return &port->dev; 184 } 185 #ifdef CONFIG_CXL_RAS 186 int cxl_ras_init(void); 187 void cxl_ras_exit(void); 188 bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); 189 void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); 190 void cxl_dport_map_rch_aer(struct cxl_dport *dport); 191 void cxl_disable_rch_root_ints(struct cxl_dport *dport); 192 void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); 193 void devm_cxl_dport_ras_setup(struct cxl_dport *dport); 194 #else 195 static inline int cxl_ras_init(void) 196 { 197 return 0; 198 } 199 static inline void cxl_ras_exit(void) { } 200 static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) 201 { 202 return false; 203 } 204 static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { } 205 static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } 206 static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } 207 static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { } 208 static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { } 209 #endif /* CONFIG_CXL_RAS */ 210 211 int cxl_gpf_port_setup(struct cxl_dport *dport); 212 213 struct cxl_hdm; 214 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, 215 struct cxl_endpoint_dvsec_info *info); 216 int cxl_port_get_possible_dports(struct cxl_port *port); 217 218 #ifdef CONFIG_CXL_FEATURES 219 struct cxl_feat_entry * 220 cxl_feature_info(struct cxl_features_state *cxlfs, const uuid_t *uuid); 221 size_t cxl_get_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid, 222 enum cxl_get_feat_selection selection, 223 void *feat_out, size_t feat_out_size, u16 offset, 224 u16 *return_code); 225 int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid, 226 u8 feat_version, const void *feat_data, 227 size_t feat_data_size, u32 feat_flag, u16 offset, 228 u16 *return_code); 229 #endif 230 231 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 232 struct cxl_dport *dport); 233 #endif /* __CXL_CORE_H__ */ 234