1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3 #undef TRACE_SYSTEM 4 #define TRACE_SYSTEM cxl 5 6 #if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ) 7 #define _CXL_EVENTS_H 8 9 #include <linux/tracepoint.h> 10 #include <linux/pci.h> 11 #include <linux/unaligned.h> 12 13 #include <cxl.h> 14 #include <cxlmem.h> 15 #include "core.h" 16 17 #define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0) 18 #define CXL_RAS_UC_CACHE_ADDR_PARITY BIT(1) 19 #define CXL_RAS_UC_CACHE_BE_PARITY BIT(2) 20 #define CXL_RAS_UC_CACHE_DATA_ECC BIT(3) 21 #define CXL_RAS_UC_MEM_DATA_PARITY BIT(4) 22 #define CXL_RAS_UC_MEM_ADDR_PARITY BIT(5) 23 #define CXL_RAS_UC_MEM_BE_PARITY BIT(6) 24 #define CXL_RAS_UC_MEM_DATA_ECC BIT(7) 25 #define CXL_RAS_UC_REINIT_THRESH BIT(8) 26 #define CXL_RAS_UC_RSVD_ENCODE BIT(9) 27 #define CXL_RAS_UC_POISON BIT(10) 28 #define CXL_RAS_UC_RECV_OVERFLOW BIT(11) 29 #define CXL_RAS_UC_INTERNAL_ERR BIT(14) 30 #define CXL_RAS_UC_IDE_TX_ERR BIT(15) 31 #define CXL_RAS_UC_IDE_RX_ERR BIT(16) 32 33 #define show_uc_errs(status) __print_flags(status, " | ", \ 34 { CXL_RAS_UC_CACHE_DATA_PARITY, "Cache Data Parity Error" }, \ 35 { CXL_RAS_UC_CACHE_ADDR_PARITY, "Cache Address Parity Error" }, \ 36 { CXL_RAS_UC_CACHE_BE_PARITY, "Cache Byte Enable Parity Error" }, \ 37 { CXL_RAS_UC_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 38 { CXL_RAS_UC_MEM_DATA_PARITY, "Memory Data Parity Error" }, \ 39 { CXL_RAS_UC_MEM_ADDR_PARITY, "Memory Address Parity Error" }, \ 40 { CXL_RAS_UC_MEM_BE_PARITY, "Memory Byte Enable Parity Error" }, \ 41 { CXL_RAS_UC_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 42 { CXL_RAS_UC_REINIT_THRESH, "REINIT Threshold Hit" }, \ 43 { CXL_RAS_UC_RSVD_ENCODE, "Received Unrecognized Encoding" }, \ 44 { CXL_RAS_UC_POISON, "Received Poison From Peer" }, \ 45 { CXL_RAS_UC_RECV_OVERFLOW, "Receiver Overflow" }, \ 46 { CXL_RAS_UC_INTERNAL_ERR, "Component Specific Error" }, \ 47 { CXL_RAS_UC_IDE_TX_ERR, "IDE Tx Error" }, \ 48 { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ 49 ) 50 51 TRACE_EVENT(cxl_port_aer_uncorrectable_error, 52 TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), 53 TP_ARGS(dev, status, fe, hl), 54 TP_STRUCT__entry( 55 __string(device, dev_name(dev)) 56 __string(host, dev_name(dev->parent)) 57 __field(u32, status) 58 __field(u32, first_error) 59 __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) 60 ), 61 TP_fast_assign( 62 __assign_str(device); 63 __assign_str(host); 64 __entry->status = status; 65 __entry->first_error = fe; 66 /* 67 * Embed the 512B headerlog data for user app retrieval and 68 * parsing, but no need to print this in the trace buffer. 69 */ 70 memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); 71 ), 72 TP_printk("device=%s host=%s status: '%s' first_error: '%s'", 73 __get_str(device), __get_str(host), 74 show_uc_errs(__entry->status), 75 show_uc_errs(__entry->first_error) 76 ) 77 ); 78 79 TRACE_EVENT(cxl_aer_uncorrectable_error, 80 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), 81 TP_ARGS(cxlmd, status, fe, hl), 82 TP_STRUCT__entry( 83 __string(memdev, dev_name(&cxlmd->dev)) 84 __string(host, dev_name(cxlmd->dev.parent)) 85 __field(u64, serial) 86 __field(u32, status) 87 __field(u32, first_error) 88 __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) 89 ), 90 TP_fast_assign( 91 __assign_str(memdev); 92 __assign_str(host); 93 __entry->serial = cxlmd->cxlds->serial; 94 __entry->status = status; 95 __entry->first_error = fe; 96 /* 97 * Embed the 512B headerlog data for user app retrieval and 98 * parsing, but no need to print this in the trace buffer. 99 */ 100 memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); 101 ), 102 TP_printk("memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'", 103 __get_str(memdev), __get_str(host), __entry->serial, 104 show_uc_errs(__entry->status), 105 show_uc_errs(__entry->first_error) 106 ) 107 ); 108 109 #define CXL_RAS_CE_CACHE_DATA_ECC BIT(0) 110 #define CXL_RAS_CE_MEM_DATA_ECC BIT(1) 111 #define CXL_RAS_CE_CRC_THRESH BIT(2) 112 #define CLX_RAS_CE_RETRY_THRESH BIT(3) 113 #define CXL_RAS_CE_CACHE_POISON BIT(4) 114 #define CXL_RAS_CE_MEM_POISON BIT(5) 115 #define CXL_RAS_CE_PHYS_LAYER_ERR BIT(6) 116 117 #define show_ce_errs(status) __print_flags(status, " | ", \ 118 { CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 119 { CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 120 { CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" }, \ 121 { CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" }, \ 122 { CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" }, \ 123 { CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" }, \ 124 { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ 125 ) 126 127 TRACE_EVENT(cxl_port_aer_correctable_error, 128 TP_PROTO(struct device *dev, u32 status), 129 TP_ARGS(dev, status), 130 TP_STRUCT__entry( 131 __string(device, dev_name(dev)) 132 __string(host, dev_name(dev->parent)) 133 __field(u32, status) 134 ), 135 TP_fast_assign( 136 __assign_str(device); 137 __assign_str(host); 138 __entry->status = status; 139 ), 140 TP_printk("device=%s host=%s status='%s'", 141 __get_str(device), __get_str(host), 142 show_ce_errs(__entry->status) 143 ) 144 ); 145 146 TRACE_EVENT(cxl_aer_correctable_error, 147 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), 148 TP_ARGS(cxlmd, status), 149 TP_STRUCT__entry( 150 __string(memdev, dev_name(&cxlmd->dev)) 151 __string(host, dev_name(cxlmd->dev.parent)) 152 __field(u64, serial) 153 __field(u32, status) 154 ), 155 TP_fast_assign( 156 __assign_str(memdev); 157 __assign_str(host); 158 __entry->serial = cxlmd->cxlds->serial; 159 __entry->status = status; 160 ), 161 TP_printk("memdev=%s host=%s serial=%lld: status: '%s'", 162 __get_str(memdev), __get_str(host), __entry->serial, 163 show_ce_errs(__entry->status) 164 ) 165 ); 166 167 #define cxl_event_log_type_str(type) \ 168 __print_symbolic(type, \ 169 { CXL_EVENT_TYPE_INFO, "Informational" }, \ 170 { CXL_EVENT_TYPE_WARN, "Warning" }, \ 171 { CXL_EVENT_TYPE_FAIL, "Failure" }, \ 172 { CXL_EVENT_TYPE_FATAL, "Fatal" }) 173 174 TRACE_EVENT(cxl_overflow, 175 176 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 177 struct cxl_get_event_payload *payload), 178 179 TP_ARGS(cxlmd, log, payload), 180 181 TP_STRUCT__entry( 182 __string(memdev, dev_name(&cxlmd->dev)) 183 __string(host, dev_name(cxlmd->dev.parent)) 184 __field(int, log) 185 __field(u64, serial) 186 __field(u64, first_ts) 187 __field(u64, last_ts) 188 __field(u16, count) 189 ), 190 191 TP_fast_assign( 192 __assign_str(memdev); 193 __assign_str(host); 194 __entry->serial = cxlmd->cxlds->serial; 195 __entry->log = log; 196 __entry->count = le16_to_cpu(payload->overflow_err_count); 197 __entry->first_ts = le64_to_cpu(payload->first_overflow_timestamp); 198 __entry->last_ts = le64_to_cpu(payload->last_overflow_timestamp); 199 ), 200 201 TP_printk("memdev=%s host=%s serial=%lld: log=%s : %u records from %llu to %llu", 202 __get_str(memdev), __get_str(host), __entry->serial, 203 cxl_event_log_type_str(__entry->log), __entry->count, 204 __entry->first_ts, __entry->last_ts) 205 206 ); 207 208 /* 209 * Common Event Record Format 210 * CXL 3.0 section 8.2.9.2.1; Table 8-42 211 */ 212 #define CXL_EVENT_RECORD_FLAG_PERMANENT BIT(2) 213 #define CXL_EVENT_RECORD_FLAG_MAINT_NEEDED BIT(3) 214 #define CXL_EVENT_RECORD_FLAG_PERF_DEGRADED BIT(4) 215 #define CXL_EVENT_RECORD_FLAG_HW_REPLACE BIT(5) 216 #define CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID BIT(6) 217 #define show_hdr_flags(flags) __print_flags(flags, " | ", \ 218 { CXL_EVENT_RECORD_FLAG_PERMANENT, "PERMANENT_CONDITION" }, \ 219 { CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, "MAINTENANCE_NEEDED" }, \ 220 { CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, "PERFORMANCE_DEGRADED" }, \ 221 { CXL_EVENT_RECORD_FLAG_HW_REPLACE, "HARDWARE_REPLACEMENT_NEEDED" }, \ 222 { CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID, "MAINT_OP_SUB_CLASS_VALID" } \ 223 ) 224 225 /* 226 * Define macros for the common header of each CXL event. 227 * 228 * Tracepoints using these macros must do 3 things: 229 * 230 * 1) Add CXL_EVT_TP_entry to TP_STRUCT__entry 231 * 2) Use CXL_EVT_TP_fast_assign within TP_fast_assign; 232 * pass the dev, log, and CXL event header 233 * NOTE: The uuid must be assigned by the specific trace event 234 * 3) Use CXL_EVT_TP_printk() instead of TP_printk() 235 * 236 * See the generic_event tracepoint as an example. 237 */ 238 #define CXL_EVT_TP_entry \ 239 __string(memdev, dev_name(&cxlmd->dev)) \ 240 __string(host, dev_name(cxlmd->dev.parent)) \ 241 __field(int, log) \ 242 __field_struct(uuid_t, hdr_uuid) \ 243 __field(u64, serial) \ 244 __field(u32, hdr_flags) \ 245 __field(u16, hdr_handle) \ 246 __field(u16, hdr_related_handle) \ 247 __field(u64, hdr_timestamp) \ 248 __field(u8, hdr_length) \ 249 __field(u8, hdr_maint_op_class) \ 250 __field(u8, hdr_maint_op_sub_class) 251 252 #define CXL_EVT_TP_fast_assign(cxlmd, l, hdr) \ 253 __assign_str(memdev); \ 254 __assign_str(host); \ 255 __entry->log = (l); \ 256 __entry->serial = (cxlmd)->cxlds->serial; \ 257 __entry->hdr_length = (hdr).length; \ 258 __entry->hdr_flags = get_unaligned_le24((hdr).flags); \ 259 __entry->hdr_handle = le16_to_cpu((hdr).handle); \ 260 __entry->hdr_related_handle = le16_to_cpu((hdr).related_handle); \ 261 __entry->hdr_timestamp = le64_to_cpu((hdr).timestamp); \ 262 __entry->hdr_maint_op_class = (hdr).maint_op_class; \ 263 __entry->hdr_maint_op_sub_class = (hdr).maint_op_sub_class 264 265 #define CXL_EVT_TP_printk(fmt, ...) \ 266 TP_printk("memdev=%s host=%s serial=%lld log=%s : time=%llu uuid=%pUb " \ 267 "len=%d flags='%s' handle=%x related_handle=%x " \ 268 "maint_op_class=%u maint_op_sub_class=%u : " fmt, \ 269 __get_str(memdev), __get_str(host), __entry->serial, \ 270 cxl_event_log_type_str(__entry->log), \ 271 __entry->hdr_timestamp, &__entry->hdr_uuid, __entry->hdr_length,\ 272 show_hdr_flags(__entry->hdr_flags), __entry->hdr_handle, \ 273 __entry->hdr_related_handle, __entry->hdr_maint_op_class, \ 274 __entry->hdr_maint_op_sub_class, \ 275 ##__VA_ARGS__) 276 277 TRACE_EVENT(cxl_generic_event, 278 279 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 280 const uuid_t *uuid, struct cxl_event_generic *gen_rec), 281 282 TP_ARGS(cxlmd, log, uuid, gen_rec), 283 284 TP_STRUCT__entry( 285 CXL_EVT_TP_entry 286 __array(u8, data, CXL_EVENT_RECORD_DATA_LENGTH) 287 ), 288 289 TP_fast_assign( 290 CXL_EVT_TP_fast_assign(cxlmd, log, gen_rec->hdr); 291 memcpy(&__entry->hdr_uuid, uuid, sizeof(uuid_t)); 292 memcpy(__entry->data, gen_rec->data, CXL_EVENT_RECORD_DATA_LENGTH); 293 ), 294 295 CXL_EVT_TP_printk("%s", 296 __print_hex(__entry->data, CXL_EVENT_RECORD_DATA_LENGTH)) 297 ); 298 299 /* 300 * Physical Address field masks 301 * 302 * General Media Event Record 303 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 304 * 305 * DRAM Event Record 306 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 307 */ 308 #define CXL_DPA_FLAGS_MASK GENMASK(1, 0) 309 #define CXL_DPA_MASK GENMASK_ULL(63, 6) 310 311 #define CXL_DPA_VOLATILE BIT(0) 312 #define CXL_DPA_NOT_REPAIRABLE BIT(1) 313 #define show_dpa_flags(flags) __print_flags(flags, "|", \ 314 { CXL_DPA_VOLATILE, "VOLATILE" }, \ 315 { CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \ 316 ) 317 318 /* 319 * Component ID Format 320 * CXL 3.1 section 8.2.9.2.1; Table 8-44 321 */ 322 #define CXL_PLDM_COMPONENT_ID_ENTITY_VALID BIT(0) 323 #define CXL_PLDM_COMPONENT_ID_RES_VALID BIT(1) 324 325 #define show_comp_id_pldm_flags(flags) __print_flags(flags, " | ", \ 326 { CXL_PLDM_COMPONENT_ID_ENTITY_VALID, "PLDM Entity ID" }, \ 327 { CXL_PLDM_COMPONENT_ID_RES_VALID, "Resource ID" } \ 328 ) 329 330 #define show_pldm_entity_id(flags, valid_comp_id, valid_id_format, comp_id) \ 331 (flags & valid_comp_id && flags & valid_id_format) ? \ 332 (comp_id[0] & CXL_PLDM_COMPONENT_ID_ENTITY_VALID) ? \ 333 __print_hex(&comp_id[1], 6) : "0x00" : "0x00" 334 335 #define show_pldm_resource_id(flags, valid_comp_id, valid_id_format, comp_id) \ 336 (flags & valid_comp_id && flags & valid_id_format) ? \ 337 (comp_id[0] & CXL_PLDM_COMPONENT_ID_RES_VALID) ? \ 338 __print_hex(&comp_id[7], 4) : "0x00" : "0x00" 339 340 /* 341 * General Media Event Record - GMER 342 * CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45 343 */ 344 #define CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT BIT(0) 345 #define CXL_GMER_EVT_DESC_THRESHOLD_EVENT BIT(1) 346 #define CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW BIT(2) 347 #define show_event_desc_flags(flags) __print_flags(flags, "|", \ 348 { CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT, "UNCORRECTABLE_EVENT" }, \ 349 { CXL_GMER_EVT_DESC_THRESHOLD_EVENT, "THRESHOLD_EVENT" }, \ 350 { CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW, "POISON_LIST_OVERFLOW" } \ 351 ) 352 353 #define CXL_GMER_MEM_EVT_TYPE_ECC_ERROR 0x00 354 #define CXL_GMER_MEM_EVT_TYPE_INV_ADDR 0x01 355 #define CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x02 356 #define CXL_GMER_MEM_EVT_TYPE_TE_STATE_VIOLATION 0x03 357 #define CXL_GMER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x04 358 #define CXL_GMER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE 0x05 359 #define CXL_GMER_MEM_EVT_TYPE_CKID_VIOLATION 0x06 360 #define show_gmer_mem_event_type(type) __print_symbolic(type, \ 361 { CXL_GMER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \ 362 { CXL_GMER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \ 363 { CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" }, \ 364 { CXL_GMER_MEM_EVT_TYPE_TE_STATE_VIOLATION, "TE State Violation" }, \ 365 { CXL_GMER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \ 366 { CXL_GMER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE, "Adv Prog CME Counter Expiration" }, \ 367 { CXL_GMER_MEM_EVT_TYPE_CKID_VIOLATION, "CKID Violation" } \ 368 ) 369 370 #define CXL_GMER_TRANS_UNKNOWN 0x00 371 #define CXL_GMER_TRANS_HOST_READ 0x01 372 #define CXL_GMER_TRANS_HOST_WRITE 0x02 373 #define CXL_GMER_TRANS_HOST_SCAN_MEDIA 0x03 374 #define CXL_GMER_TRANS_HOST_INJECT_POISON 0x04 375 #define CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB 0x05 376 #define CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT 0x06 377 #define CXL_GMER_TRANS_INTERNAL_MEDIA_ECS 0x07 378 #define CXL_GMER_TRANS_MEDIA_INITIALIZATION 0x08 379 #define show_trans_type(type) __print_symbolic(type, \ 380 { CXL_GMER_TRANS_UNKNOWN, "Unknown" }, \ 381 { CXL_GMER_TRANS_HOST_READ, "Host Read" }, \ 382 { CXL_GMER_TRANS_HOST_WRITE, "Host Write" }, \ 383 { CXL_GMER_TRANS_HOST_SCAN_MEDIA, "Host Scan Media" }, \ 384 { CXL_GMER_TRANS_HOST_INJECT_POISON, "Host Inject Poison" }, \ 385 { CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, "Internal Media Scrub" }, \ 386 { CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT, "Internal Media Management" }, \ 387 { CXL_GMER_TRANS_INTERNAL_MEDIA_ECS, "Internal Media Error Check Scrub" }, \ 388 { CXL_GMER_TRANS_MEDIA_INITIALIZATION, "Media Initialization" } \ 389 ) 390 391 #define CXL_GMER_VALID_CHANNEL BIT(0) 392 #define CXL_GMER_VALID_RANK BIT(1) 393 #define CXL_GMER_VALID_DEVICE BIT(2) 394 #define CXL_GMER_VALID_COMPONENT BIT(3) 395 #define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4) 396 #define show_valid_flags(flags) __print_flags(flags, "|", \ 397 { CXL_GMER_VALID_CHANNEL, "CHANNEL" }, \ 398 { CXL_GMER_VALID_RANK, "RANK" }, \ 399 { CXL_GMER_VALID_DEVICE, "DEVICE" }, \ 400 { CXL_GMER_VALID_COMPONENT, "COMPONENT" }, \ 401 { CXL_GMER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" } \ 402 ) 403 404 #define CXL_GMER_CME_EV_FLAG_CME_MULTIPLE_MEDIA BIT(0) 405 #define CXL_GMER_CME_EV_FLAG_THRESHOLD_EXCEEDED BIT(1) 406 #define show_cme_threshold_ev_flags(flags) __print_flags(flags, "|", \ 407 { \ 408 CXL_GMER_CME_EV_FLAG_CME_MULTIPLE_MEDIA, \ 409 "Corrected Memory Errors in Multiple Media Components" \ 410 }, { \ 411 CXL_GMER_CME_EV_FLAG_THRESHOLD_EXCEEDED, \ 412 "Exceeded Programmable Threshold" \ 413 } \ 414 ) 415 416 #define CXL_GMER_MEM_EVT_SUB_TYPE_NOT_REPORTED 0x00 417 #define CXL_GMER_MEM_EVT_SUB_TYPE_INTERNAL_DATAPATH_ERROR 0x01 418 #define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_COMMAND_TRAINING_ERROR 0x02 419 #define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CONTROL_TRAINING_ERROR 0x03 420 #define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_DATA_TRAINING_ERROR 0x04 421 #define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CRC_ERROR 0x05 422 #define show_mem_event_sub_type(sub_type) __print_symbolic(sub_type, \ 423 { CXL_GMER_MEM_EVT_SUB_TYPE_NOT_REPORTED, "Not Reported" }, \ 424 { CXL_GMER_MEM_EVT_SUB_TYPE_INTERNAL_DATAPATH_ERROR, "Internal Datapath Error" }, \ 425 { \ 426 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_COMMAND_TRAINING_ERROR, \ 427 "Media Link Command Training Error" \ 428 }, { \ 429 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CONTROL_TRAINING_ERROR, \ 430 "Media Link Control Training Error" \ 431 }, { \ 432 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_DATA_TRAINING_ERROR, \ 433 "Media Link Data Training Error" \ 434 }, { \ 435 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CRC_ERROR, "Media Link CRC Error" \ 436 } \ 437 ) 438 439 TRACE_EVENT(cxl_general_media, 440 441 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 442 struct cxl_region *cxlr, u64 hpa, u64 hpa_alias0, 443 struct cxl_event_gen_media *rec), 444 445 TP_ARGS(cxlmd, log, cxlr, hpa, hpa_alias0, rec), 446 447 TP_STRUCT__entry( 448 CXL_EVT_TP_entry 449 /* General Media */ 450 __field(u64, dpa) 451 __field(u8, descriptor) 452 __field(u8, type) 453 __field(u8, transaction_type) 454 __field(u8, channel) 455 __field(u32, device) 456 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 457 /* Following are out of order to pack trace record */ 458 __field(u64, hpa) 459 __field(u64, hpa_alias0) 460 __field_struct(uuid_t, region_uuid) 461 __field(u16, validity_flags) 462 __field(u8, rank) 463 __field(u8, dpa_flags) 464 __field(u32, cme_count) 465 __field(u8, sub_type) 466 __field(u8, cme_threshold_ev_flags) 467 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "") 468 ), 469 470 TP_fast_assign( 471 CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr); 472 __entry->hdr_uuid = CXL_EVENT_GEN_MEDIA_UUID; 473 474 /* General Media */ 475 __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr); 476 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; 477 /* Mask after flags have been parsed */ 478 __entry->dpa &= CXL_DPA_MASK; 479 __entry->descriptor = rec->media_hdr.descriptor; 480 __entry->type = rec->media_hdr.type; 481 __entry->sub_type = rec->sub_type; 482 __entry->transaction_type = rec->media_hdr.transaction_type; 483 __entry->channel = rec->media_hdr.channel; 484 __entry->rank = rec->media_hdr.rank; 485 __entry->device = get_unaligned_le24(rec->device); 486 memcpy(__entry->comp_id, &rec->component_id, 487 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 488 __entry->validity_flags = get_unaligned_le16(&rec->media_hdr.validity_flags); 489 __entry->hpa = hpa; 490 __entry->hpa_alias0 = hpa_alias0; 491 if (cxlr) { 492 __assign_str(region_name); 493 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); 494 } else { 495 __assign_str(region_name); 496 uuid_copy(&__entry->region_uuid, &uuid_null); 497 } 498 __entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags; 499 __entry->cme_count = get_unaligned_le24(rec->cme_count); 500 ), 501 502 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \ 503 "descriptor='%s' type='%s' sub_type='%s' " \ 504 "transaction_type='%s' channel=%u rank=%u " \ 505 "device=%x validity_flags='%s' " \ 506 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 507 "pldm_entity_id=%s pldm_resource_id=%s " \ 508 "hpa=%llx hpa_alias0=%llx region=%s region_uuid=%pUb " \ 509 "cme_threshold_ev_flags='%s' cme_count=%u", 510 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 511 show_event_desc_flags(__entry->descriptor), 512 show_gmer_mem_event_type(__entry->type), 513 show_mem_event_sub_type(__entry->sub_type), 514 show_trans_type(__entry->transaction_type), 515 __entry->channel, __entry->rank, __entry->device, 516 show_valid_flags(__entry->validity_flags), 517 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 518 show_comp_id_pldm_flags(__entry->comp_id[0]), 519 show_pldm_entity_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT, 520 CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 521 show_pldm_resource_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT, 522 CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 523 __entry->hpa, __entry->hpa_alias0, __get_str(region_name), &__entry->region_uuid, 524 show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags), __entry->cme_count 525 ) 526 ); 527 528 /* 529 * DRAM Event Record - DER 530 * 531 * CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46 532 */ 533 /* 534 * DRAM Event Record defines many fields the same as the General Media Event 535 * Record. Reuse those definitions as appropriate. 536 */ 537 #define CXL_DER_MEM_EVT_TYPE_ECC_ERROR 0x00 538 #define CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x01 539 #define CXL_DER_MEM_EVT_TYPE_INV_ADDR 0x02 540 #define CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x03 541 #define CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION 0x04 542 #define CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE 0x05 543 #define CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION 0x06 544 #define show_dram_mem_event_type(type) __print_symbolic(type, \ 545 { CXL_DER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \ 546 { CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \ 547 { CXL_DER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \ 548 { CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" }, \ 549 { CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION, "TE State Violation" }, \ 550 { CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE, "Adv Prog CME Counter Expiration" }, \ 551 { CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION, "CKID Violation" } \ 552 ) 553 554 #define CXL_DER_VALID_CHANNEL BIT(0) 555 #define CXL_DER_VALID_RANK BIT(1) 556 #define CXL_DER_VALID_NIBBLE BIT(2) 557 #define CXL_DER_VALID_BANK_GROUP BIT(3) 558 #define CXL_DER_VALID_BANK BIT(4) 559 #define CXL_DER_VALID_ROW BIT(5) 560 #define CXL_DER_VALID_COLUMN BIT(6) 561 #define CXL_DER_VALID_CORRECTION_MASK BIT(7) 562 #define CXL_DER_VALID_COMPONENT BIT(8) 563 #define CXL_DER_VALID_COMPONENT_ID_FORMAT BIT(9) 564 #define CXL_DER_VALID_SUB_CHANNEL BIT(10) 565 #define show_dram_valid_flags(flags) __print_flags(flags, "|", \ 566 { CXL_DER_VALID_CHANNEL, "CHANNEL" }, \ 567 { CXL_DER_VALID_RANK, "RANK" }, \ 568 { CXL_DER_VALID_NIBBLE, "NIBBLE" }, \ 569 { CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \ 570 { CXL_DER_VALID_BANK, "BANK" }, \ 571 { CXL_DER_VALID_ROW, "ROW" }, \ 572 { CXL_DER_VALID_COLUMN, "COLUMN" }, \ 573 { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" }, \ 574 { CXL_DER_VALID_COMPONENT, "COMPONENT" }, \ 575 { CXL_DER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" }, \ 576 { CXL_DER_VALID_SUB_CHANNEL, "SUB CHANNEL" } \ 577 ) 578 579 TRACE_EVENT(cxl_dram, 580 581 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 582 struct cxl_region *cxlr, u64 hpa, u64 hpa_alias0, 583 struct cxl_event_dram *rec), 584 585 TP_ARGS(cxlmd, log, cxlr, hpa, hpa_alias0, rec), 586 587 TP_STRUCT__entry( 588 CXL_EVT_TP_entry 589 /* DRAM */ 590 __field(u64, dpa) 591 __field(u8, descriptor) 592 __field(u8, type) 593 __field(u8, transaction_type) 594 __field(u8, channel) 595 __field(u16, validity_flags) 596 __field(u16, column) /* Out of order to pack trace record */ 597 __field(u32, nibble_mask) 598 __field(u32, row) 599 __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE) 600 __field(u64, hpa) 601 __field(u64, hpa_alias0) 602 __field_struct(uuid_t, region_uuid) 603 __field(u8, rank) /* Out of order to pack trace record */ 604 __field(u8, bank_group) /* Out of order to pack trace record */ 605 __field(u8, bank) /* Out of order to pack trace record */ 606 __field(u8, dpa_flags) /* Out of order to pack trace record */ 607 /* Following are out of order to pack trace record */ 608 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 609 __field(u32, cvme_count) 610 __field(u8, sub_type) 611 __field(u8, sub_channel) 612 __field(u8, cme_threshold_ev_flags) 613 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "") 614 ), 615 616 TP_fast_assign( 617 CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr); 618 __entry->hdr_uuid = CXL_EVENT_DRAM_UUID; 619 620 /* DRAM */ 621 __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr); 622 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; 623 __entry->dpa &= CXL_DPA_MASK; 624 __entry->descriptor = rec->media_hdr.descriptor; 625 __entry->type = rec->media_hdr.type; 626 __entry->sub_type = rec->sub_type; 627 __entry->transaction_type = rec->media_hdr.transaction_type; 628 __entry->validity_flags = get_unaligned_le16(rec->media_hdr.validity_flags); 629 __entry->channel = rec->media_hdr.channel; 630 __entry->rank = rec->media_hdr.rank; 631 __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); 632 __entry->bank_group = rec->bank_group; 633 __entry->bank = rec->bank; 634 __entry->row = get_unaligned_le24(rec->row); 635 __entry->column = get_unaligned_le16(rec->column); 636 memcpy(__entry->cor_mask, &rec->correction_mask, 637 CXL_EVENT_DER_CORRECTION_MASK_SIZE); 638 __entry->hpa = hpa; 639 __entry->hpa_alias0 = hpa_alias0; 640 if (cxlr) { 641 __assign_str(region_name); 642 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); 643 } else { 644 __assign_str(region_name); 645 uuid_copy(&__entry->region_uuid, &uuid_null); 646 } 647 memcpy(__entry->comp_id, &rec->component_id, 648 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 649 __entry->sub_channel = rec->sub_channel; 650 __entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags; 651 __entry->cvme_count = get_unaligned_le24(rec->cvme_count); 652 ), 653 654 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' sub_type='%s' " \ 655 "transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \ 656 "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \ 657 "validity_flags='%s' " \ 658 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 659 "pldm_entity_id=%s pldm_resource_id=%s " \ 660 "hpa=%llx hpa_alias0=%llx region=%s region_uuid=%pUb " \ 661 "sub_channel=%u cme_threshold_ev_flags='%s' cvme_count=%u", 662 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 663 show_event_desc_flags(__entry->descriptor), 664 show_dram_mem_event_type(__entry->type), 665 show_mem_event_sub_type(__entry->sub_type), 666 show_trans_type(__entry->transaction_type), 667 __entry->channel, __entry->rank, __entry->nibble_mask, 668 __entry->bank_group, __entry->bank, 669 __entry->row, __entry->column, 670 __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE), 671 show_dram_valid_flags(__entry->validity_flags), 672 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 673 show_comp_id_pldm_flags(__entry->comp_id[0]), 674 show_pldm_entity_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT, 675 CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 676 show_pldm_resource_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT, 677 CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 678 __entry->hpa, __entry->hpa_alias0, __get_str(region_name), &__entry->region_uuid, 679 __entry->sub_channel, show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags), 680 __entry->cvme_count 681 ) 682 ); 683 684 /* 685 * Memory Module Event Record - MMER 686 * 687 * CXL res 3.1 section 8.2.9.2.1.3; Table 8-47 688 */ 689 #define CXL_MMER_HEALTH_STATUS_CHANGE 0x00 690 #define CXL_MMER_MEDIA_STATUS_CHANGE 0x01 691 #define CXL_MMER_LIFE_USED_CHANGE 0x02 692 #define CXL_MMER_TEMP_CHANGE 0x03 693 #define CXL_MMER_DATA_PATH_ERROR 0x04 694 #define CXL_MMER_LSA_ERROR 0x05 695 #define CXL_MMER_UNRECOV_SIDEBAND_BUS_ERROR 0x06 696 #define CXL_MMER_MEMORY_MEDIA_FRU_ERROR 0x07 697 #define CXL_MMER_POWER_MANAGEMENT_FAULT 0x08 698 #define show_dev_evt_type(type) __print_symbolic(type, \ 699 { CXL_MMER_HEALTH_STATUS_CHANGE, "Health Status Change" }, \ 700 { CXL_MMER_MEDIA_STATUS_CHANGE, "Media Status Change" }, \ 701 { CXL_MMER_LIFE_USED_CHANGE, "Life Used Change" }, \ 702 { CXL_MMER_TEMP_CHANGE, "Temperature Change" }, \ 703 { CXL_MMER_DATA_PATH_ERROR, "Data Path Error" }, \ 704 { CXL_MMER_LSA_ERROR, "LSA Error" }, \ 705 { CXL_MMER_UNRECOV_SIDEBAND_BUS_ERROR, "Unrecoverable Internal Sideband Bus Error" }, \ 706 { CXL_MMER_MEMORY_MEDIA_FRU_ERROR, "Memory Media FRU Error" }, \ 707 { CXL_MMER_POWER_MANAGEMENT_FAULT, "Power Management Fault" } \ 708 ) 709 710 /* 711 * Device Health Information - DHI 712 * 713 * CXL res 3.1 section 8.2.9.9.3.1; Table 8-133 714 */ 715 #define CXL_DHI_HS_MAINTENANCE_NEEDED BIT(0) 716 #define CXL_DHI_HS_PERFORMANCE_DEGRADED BIT(1) 717 #define CXL_DHI_HS_HW_REPLACEMENT_NEEDED BIT(2) 718 #define CXL_DHI_HS_MEM_CAPACITY_DEGRADED BIT(3) 719 #define show_health_status_flags(flags) __print_flags(flags, "|", \ 720 { CXL_DHI_HS_MAINTENANCE_NEEDED, "MAINTENANCE_NEEDED" }, \ 721 { CXL_DHI_HS_PERFORMANCE_DEGRADED, "PERFORMANCE_DEGRADED" }, \ 722 { CXL_DHI_HS_HW_REPLACEMENT_NEEDED, "REPLACEMENT_NEEDED" }, \ 723 { CXL_DHI_HS_MEM_CAPACITY_DEGRADED, "MEM_CAPACITY_DEGRADED" } \ 724 ) 725 726 #define CXL_DHI_MS_NORMAL 0x00 727 #define CXL_DHI_MS_NOT_READY 0x01 728 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOST 0x02 729 #define CXL_DHI_MS_ALL_DATA_LOST 0x03 730 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS 0x04 731 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN 0x05 732 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT 0x06 733 #define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS 0x07 734 #define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN 0x08 735 #define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT 0x09 736 #define show_media_status(ms) __print_symbolic(ms, \ 737 { CXL_DHI_MS_NORMAL, \ 738 "Normal" }, \ 739 { CXL_DHI_MS_NOT_READY, \ 740 "Not Ready" }, \ 741 { CXL_DHI_MS_WRITE_PERSISTENCY_LOST, \ 742 "Write Persistency Lost" }, \ 743 { CXL_DHI_MS_ALL_DATA_LOST, \ 744 "All Data Lost" }, \ 745 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS, \ 746 "Write Persistency Loss in the Event of Power Loss" }, \ 747 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN, \ 748 "Write Persistency Loss in Event of Shutdown" }, \ 749 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT, \ 750 "Write Persistency Loss Imminent" }, \ 751 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS, \ 752 "All Data Loss in Event of Power Loss" }, \ 753 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN, \ 754 "All Data loss in the Event of Shutdown" }, \ 755 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT, \ 756 "All Data Loss Imminent" } \ 757 ) 758 759 #define CXL_DHI_AS_NORMAL 0x0 760 #define CXL_DHI_AS_WARNING 0x1 761 #define CXL_DHI_AS_CRITICAL 0x2 762 #define show_two_bit_status(as) __print_symbolic(as, \ 763 { CXL_DHI_AS_NORMAL, "Normal" }, \ 764 { CXL_DHI_AS_WARNING, "Warning" }, \ 765 { CXL_DHI_AS_CRITICAL, "Critical" } \ 766 ) 767 #define show_one_bit_status(as) __print_symbolic(as, \ 768 { CXL_DHI_AS_NORMAL, "Normal" }, \ 769 { CXL_DHI_AS_WARNING, "Warning" } \ 770 ) 771 772 #define CXL_DHI_AS_LIFE_USED(as) (as & 0x3) 773 #define CXL_DHI_AS_DEV_TEMP(as) ((as & 0xC) >> 2) 774 #define CXL_DHI_AS_COR_VOL_ERR_CNT(as) ((as & 0x10) >> 4) 775 #define CXL_DHI_AS_COR_PER_ERR_CNT(as) ((as & 0x20) >> 5) 776 777 #define CXL_MMER_VALID_COMPONENT BIT(0) 778 #define CXL_MMER_VALID_COMPONENT_ID_FORMAT BIT(1) 779 #define show_mem_module_valid_flags(flags) __print_flags(flags, "|", \ 780 { CXL_MMER_VALID_COMPONENT, "COMPONENT" }, \ 781 { CXL_MMER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" } \ 782 ) 783 #define CXL_MMER_DEV_EVT_SUB_TYPE_NOT_REPORTED 0x00 784 #define CXL_MMER_DEV_EVT_SUB_TYPE_INVALID_CONFIG_DATA 0x01 785 #define CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_CONFIG_DATA 0x02 786 #define CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_MEM_MEDIA_FRU 0x03 787 #define show_dev_event_sub_type(sub_type) __print_symbolic(sub_type, \ 788 { CXL_MMER_DEV_EVT_SUB_TYPE_NOT_REPORTED, "Not Reported" }, \ 789 { CXL_MMER_DEV_EVT_SUB_TYPE_INVALID_CONFIG_DATA, "Invalid Config Data" }, \ 790 { CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_CONFIG_DATA, "Unsupported Config Data" }, \ 791 { \ 792 CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_MEM_MEDIA_FRU, \ 793 "Unsupported Memory Media FRU" \ 794 } \ 795 ) 796 797 TRACE_EVENT(cxl_memory_module, 798 799 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 800 struct cxl_event_mem_module *rec), 801 802 TP_ARGS(cxlmd, log, rec), 803 804 TP_STRUCT__entry( 805 CXL_EVT_TP_entry 806 807 /* Memory Module Event */ 808 __field(u8, event_type) 809 810 /* Device Health Info */ 811 __field(u8, health_status) 812 __field(u8, media_status) 813 __field(u8, life_used) 814 __field(u32, dirty_shutdown_cnt) 815 __field(u32, cor_vol_err_cnt) 816 __field(u32, cor_per_err_cnt) 817 __field(s16, device_temp) 818 __field(u8, add_status) 819 __field(u8, event_sub_type) 820 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 821 __field(u16, validity_flags) 822 ), 823 824 TP_fast_assign( 825 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 826 __entry->hdr_uuid = CXL_EVENT_MEM_MODULE_UUID; 827 828 /* Memory Module Event */ 829 __entry->event_type = rec->event_type; 830 __entry->event_sub_type = rec->event_sub_type; 831 832 /* Device Health Info */ 833 __entry->health_status = rec->info.health_status; 834 __entry->media_status = rec->info.media_status; 835 __entry->life_used = rec->info.life_used; 836 __entry->dirty_shutdown_cnt = get_unaligned_le32(rec->info.dirty_shutdown_cnt); 837 __entry->cor_vol_err_cnt = get_unaligned_le32(rec->info.cor_vol_err_cnt); 838 __entry->cor_per_err_cnt = get_unaligned_le32(rec->info.cor_per_err_cnt); 839 __entry->device_temp = get_unaligned_le16(rec->info.device_temp); 840 __entry->add_status = rec->info.add_status; 841 __entry->validity_flags = get_unaligned_le16(rec->validity_flags); 842 memcpy(__entry->comp_id, &rec->component_id, 843 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 844 ), 845 846 CXL_EVT_TP_printk("event_type='%s' event_sub_type='%s' health_status='%s' " \ 847 "media_status='%s' as_life_used=%s as_dev_temp=%s as_cor_vol_err_cnt=%s " \ 848 "as_cor_per_err_cnt=%s life_used=%u device_temp=%d " \ 849 "dirty_shutdown_cnt=%u cor_vol_err_cnt=%u cor_per_err_cnt=%u " \ 850 "validity_flags='%s' " \ 851 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 852 "pldm_entity_id=%s pldm_resource_id=%s", 853 show_dev_evt_type(__entry->event_type), 854 show_dev_event_sub_type(__entry->event_sub_type), 855 show_health_status_flags(__entry->health_status), 856 show_media_status(__entry->media_status), 857 show_two_bit_status(CXL_DHI_AS_LIFE_USED(__entry->add_status)), 858 show_two_bit_status(CXL_DHI_AS_DEV_TEMP(__entry->add_status)), 859 show_one_bit_status(CXL_DHI_AS_COR_VOL_ERR_CNT(__entry->add_status)), 860 show_one_bit_status(CXL_DHI_AS_COR_PER_ERR_CNT(__entry->add_status)), 861 __entry->life_used, __entry->device_temp, 862 __entry->dirty_shutdown_cnt, __entry->cor_vol_err_cnt, 863 __entry->cor_per_err_cnt, 864 show_mem_module_valid_flags(__entry->validity_flags), 865 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 866 show_comp_id_pldm_flags(__entry->comp_id[0]), 867 show_pldm_entity_id(__entry->validity_flags, CXL_MMER_VALID_COMPONENT, 868 CXL_MMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 869 show_pldm_resource_id(__entry->validity_flags, CXL_MMER_VALID_COMPONENT, 870 CXL_MMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id) 871 ) 872 ); 873 874 #define show_poison_trace_type(type) \ 875 __print_symbolic(type, \ 876 { CXL_POISON_TRACE_LIST, "List" }, \ 877 { CXL_POISON_TRACE_INJECT, "Inject" }, \ 878 { CXL_POISON_TRACE_CLEAR, "Clear" }) 879 880 #define __show_poison_source(source) \ 881 __print_symbolic(source, \ 882 { CXL_POISON_SOURCE_UNKNOWN, "Unknown" }, \ 883 { CXL_POISON_SOURCE_EXTERNAL, "External" }, \ 884 { CXL_POISON_SOURCE_INTERNAL, "Internal" }, \ 885 { CXL_POISON_SOURCE_INJECTED, "Injected" }, \ 886 { CXL_POISON_SOURCE_VENDOR, "Vendor" }) 887 888 #define show_poison_source(source) \ 889 (((source > CXL_POISON_SOURCE_INJECTED) && \ 890 (source != CXL_POISON_SOURCE_VENDOR)) ? "Reserved" \ 891 : __show_poison_source(source)) 892 893 #define show_poison_flags(flags) \ 894 __print_flags(flags, "|", \ 895 { CXL_POISON_FLAG_MORE, "More" }, \ 896 { CXL_POISON_FLAG_OVERFLOW, "Overflow" }, \ 897 { CXL_POISON_FLAG_SCANNING, "Scanning" }) 898 899 #define __cxl_poison_addr(record) \ 900 (le64_to_cpu(record->address)) 901 #define cxl_poison_record_dpa(record) \ 902 (__cxl_poison_addr(record) & CXL_POISON_START_MASK) 903 #define cxl_poison_record_source(record) \ 904 (__cxl_poison_addr(record) & CXL_POISON_SOURCE_MASK) 905 #define cxl_poison_record_dpa_length(record) \ 906 (le32_to_cpu(record->length) * CXL_POISON_LEN_MULT) 907 #define cxl_poison_overflow(flags, time) \ 908 (flags & CXL_POISON_FLAG_OVERFLOW ? le64_to_cpu(time) : 0) 909 910 TRACE_EVENT(cxl_poison, 911 912 TP_PROTO(struct cxl_memdev *cxlmd, struct cxl_region *cxlr, 913 const struct cxl_poison_record *record, u8 flags, 914 __le64 overflow_ts, enum cxl_poison_trace_type trace_type), 915 916 TP_ARGS(cxlmd, cxlr, record, flags, overflow_ts, trace_type), 917 918 TP_STRUCT__entry( 919 __string(memdev, dev_name(&cxlmd->dev)) 920 __string(host, dev_name(cxlmd->dev.parent)) 921 __field(u64, serial) 922 __field(u8, trace_type) 923 __string(region, cxlr ? dev_name(&cxlr->dev) : "") 924 __field(u64, overflow_ts) 925 __field(u64, hpa) 926 __field(u64, hpa_alias0) 927 __field(u64, dpa) 928 __field(u32, dpa_length) 929 __array(char, uuid, 16) 930 __field(u8, source) 931 __field(u8, flags) 932 ), 933 934 TP_fast_assign( 935 __assign_str(memdev); 936 __assign_str(host); 937 __entry->serial = cxlmd->cxlds->serial; 938 __entry->overflow_ts = cxl_poison_overflow(flags, overflow_ts); 939 __entry->dpa = cxl_poison_record_dpa(record); 940 __entry->dpa_length = cxl_poison_record_dpa_length(record); 941 __entry->source = cxl_poison_record_source(record); 942 __entry->trace_type = trace_type; 943 __entry->flags = flags; 944 if (cxlr) { 945 __assign_str(region); 946 memcpy(__entry->uuid, &cxlr->params.uuid, 16); 947 __entry->hpa = cxl_dpa_to_hpa(cxlr, cxlmd, 948 __entry->dpa); 949 if (__entry->hpa != ULLONG_MAX && cxlr->params.cache_size) 950 __entry->hpa_alias0 = __entry->hpa + 951 cxlr->params.cache_size; 952 else 953 __entry->hpa_alias0 = ULLONG_MAX; 954 } else { 955 __assign_str(region); 956 memset(__entry->uuid, 0, 16); 957 __entry->hpa = ULLONG_MAX; 958 __entry->hpa_alias0 = ULLONG_MAX; 959 } 960 ), 961 962 TP_printk("memdev=%s host=%s serial=%lld trace_type=%s region=%s " \ 963 "region_uuid=%pU hpa=0x%llx hpa_alias0=0x%llx dpa=0x%llx " \ 964 "dpa_length=0x%x source=%s flags=%s overflow_time=%llu", 965 __get_str(memdev), 966 __get_str(host), 967 __entry->serial, 968 show_poison_trace_type(__entry->trace_type), 969 __get_str(region), 970 __entry->uuid, 971 __entry->hpa, 972 __entry->hpa_alias0, 973 __entry->dpa, 974 __entry->dpa_length, 975 show_poison_source(__entry->source), 976 show_poison_flags(__entry->flags), 977 __entry->overflow_ts 978 ) 979 ); 980 981 #endif /* _CXL_EVENTS_H */ 982 983 #define TRACE_INCLUDE_FILE trace 984 #include <trace/define_trace.h> 985