1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/pci.h> 7 #include <linux/cdev.h> 8 #include <linux/uuid.h> 9 #include <linux/node.h> 10 #include <cxl/event.h> 11 #include <cxl/mailbox.h> 12 #include "cxl.h" 13 14 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 15 #define CXLMDEV_STATUS_OFFSET 0x0 16 #define CXLMDEV_DEV_FATAL BIT(0) 17 #define CXLMDEV_FW_HALT BIT(1) 18 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 19 #define CXLMDEV_MS_NOT_READY 0 20 #define CXLMDEV_MS_READY 1 21 #define CXLMDEV_MS_ERROR 2 22 #define CXLMDEV_MS_DISABLED 3 23 #define CXLMDEV_READY(status) \ 24 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 25 CXLMDEV_MS_READY) 26 #define CXLMDEV_MBOX_IF_READY BIT(4) 27 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 28 #define CXLMDEV_RESET_NEEDED_NOT 0 29 #define CXLMDEV_RESET_NEEDED_COLD 1 30 #define CXLMDEV_RESET_NEEDED_WARM 2 31 #define CXLMDEV_RESET_NEEDED_HOT 3 32 #define CXLMDEV_RESET_NEEDED_CXL 4 33 #define CXLMDEV_RESET_NEEDED(status) \ 34 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 35 CXLMDEV_RESET_NEEDED_NOT) 36 37 /** 38 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 39 * @dev: driver core device object 40 * @cdev: char dev core object for ioctl operations 41 * @cxlds: The device state backing this device 42 * @detach_work: active memdev lost a port in its ancestry 43 * @cxl_nvb: coordinate removal of @cxl_nvd if present 44 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 45 * @endpoint: connection to the CXL port topology for this memory device 46 * @id: id number of this memdev instance. 47 * @depth: endpoint port depth 48 */ 49 struct cxl_memdev { 50 struct device dev; 51 struct cdev cdev; 52 struct cxl_dev_state *cxlds; 53 struct work_struct detach_work; 54 struct cxl_nvdimm_bridge *cxl_nvb; 55 struct cxl_nvdimm *cxl_nvd; 56 struct cxl_port *endpoint; 57 int id; 58 int depth; 59 }; 60 61 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 62 { 63 return container_of(dev, struct cxl_memdev, dev); 64 } 65 66 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 67 { 68 return to_cxl_port(cxled->cxld.dev.parent); 69 } 70 71 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 72 { 73 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 74 } 75 76 static inline struct cxl_memdev * 77 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 78 { 79 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 80 81 return to_cxl_memdev(port->uport_dev); 82 } 83 84 bool is_cxl_memdev(const struct device *dev); 85 static inline bool is_cxl_endpoint(struct cxl_port *port) 86 { 87 return is_cxl_memdev(port->uport_dev); 88 } 89 90 struct cxl_memdev *devm_cxl_add_memdev(struct device *host, 91 struct cxl_dev_state *cxlds); 92 int devm_cxl_sanitize_setup_notifier(struct device *host, 93 struct cxl_memdev *cxlmd); 94 struct cxl_memdev_state; 95 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds); 96 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 97 resource_size_t base, resource_size_t len, 98 resource_size_t skipped); 99 100 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 101 struct cxl_memdev *cxlmd) 102 { 103 if (!port) 104 return NULL; 105 106 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 107 } 108 109 /* 110 * Per CXL 3.0 Section 8.2.8.4.5.1 111 */ 112 #define CMD_CMD_RC_TABLE \ 113 C(SUCCESS, 0, NULL), \ 114 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 115 C(INPUT, -ENXIO, "cmd input was invalid"), \ 116 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 117 C(INTERNAL, -ENXIO, "internal device error"), \ 118 C(RETRY, -ENXIO, "temporary error, retry once"), \ 119 C(BUSY, -ENXIO, "ongoing background operation"), \ 120 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 121 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 122 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 123 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 124 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 125 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 126 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 127 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 128 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 129 C(POISONLMT, -EBUSY, "poison injection limit has been reached"), \ 130 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 131 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 132 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 133 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 134 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 135 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 136 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 137 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \ 138 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 139 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 140 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 141 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 142 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 143 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 144 145 #undef C 146 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 147 enum { CMD_CMD_RC_TABLE }; 148 #undef C 149 #define C(a, b, c) { b, c } 150 struct cxl_mbox_cmd_rc { 151 int err; 152 const char *desc; 153 }; 154 155 static const 156 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 157 #undef C 158 159 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 160 { 161 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 162 } 163 164 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 165 { 166 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 167 } 168 169 /* 170 * CXL 2.0 - Memory capacity multiplier 171 * See Section 8.2.9.5 172 * 173 * Volatile, Persistent, and Partition capacities are specified to be in 174 * multiples of 256MB - define a multiplier to convert to/from bytes. 175 */ 176 #define CXL_CAPACITY_MULTIPLIER SZ_256M 177 178 /* 179 * Event Interrupt Policy 180 * 181 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 182 */ 183 enum cxl_event_int_mode { 184 CXL_INT_NONE = 0x00, 185 CXL_INT_MSI_MSIX = 0x01, 186 CXL_INT_FW = 0x02 187 }; 188 struct cxl_event_interrupt_policy { 189 u8 info_settings; 190 u8 warn_settings; 191 u8 failure_settings; 192 u8 fatal_settings; 193 } __packed; 194 195 /** 196 * struct cxl_event_state - Event log driver state 197 * 198 * @buf: Buffer to receive event data 199 * @log_lock: Serialize event_buf and log use 200 */ 201 struct cxl_event_state { 202 struct cxl_get_event_payload *buf; 203 struct mutex log_lock; 204 }; 205 206 /* Device enabled poison commands */ 207 enum poison_cmd_enabled_bits { 208 CXL_POISON_ENABLED_LIST, 209 CXL_POISON_ENABLED_INJECT, 210 CXL_POISON_ENABLED_CLEAR, 211 CXL_POISON_ENABLED_SCAN_CAPS, 212 CXL_POISON_ENABLED_SCAN_MEDIA, 213 CXL_POISON_ENABLED_SCAN_RESULTS, 214 CXL_POISON_ENABLED_MAX 215 }; 216 217 /* Device enabled security commands */ 218 enum security_cmd_enabled_bits { 219 CXL_SEC_ENABLED_SANITIZE, 220 CXL_SEC_ENABLED_SECURE_ERASE, 221 CXL_SEC_ENABLED_GET_SECURITY_STATE, 222 CXL_SEC_ENABLED_SET_PASSPHRASE, 223 CXL_SEC_ENABLED_DISABLE_PASSPHRASE, 224 CXL_SEC_ENABLED_UNLOCK, 225 CXL_SEC_ENABLED_FREEZE_SECURITY, 226 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE, 227 CXL_SEC_ENABLED_MAX 228 }; 229 230 /** 231 * struct cxl_poison_state - Driver poison state info 232 * 233 * @max_errors: Maximum media error records held in device cache 234 * @enabled_cmds: All poison commands enabled in the CEL 235 * @list_out: The poison list payload returned by device 236 * @lock: Protect reads of the poison list 237 * 238 * Reads of the poison list are synchronized to ensure that a reader 239 * does not get an incomplete list because their request overlapped 240 * (was interrupted or preceded by) another read request of the same 241 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 242 */ 243 struct cxl_poison_state { 244 u32 max_errors; 245 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 246 struct cxl_mbox_poison_out *list_out; 247 struct mutex lock; /* Protect reads of poison list */ 248 }; 249 250 /* 251 * Get FW Info 252 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56 253 */ 254 struct cxl_mbox_get_fw_info { 255 u8 num_slots; 256 u8 slot_info; 257 u8 activation_cap; 258 u8 reserved[13]; 259 char slot_1_revision[16]; 260 char slot_2_revision[16]; 261 char slot_3_revision[16]; 262 char slot_4_revision[16]; 263 } __packed; 264 265 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0) 266 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3) 267 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3 268 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0) 269 270 /* 271 * Transfer FW Input Payload 272 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57 273 */ 274 struct cxl_mbox_transfer_fw { 275 u8 action; 276 u8 slot; 277 u8 reserved[2]; 278 __le32 offset; 279 u8 reserved2[0x78]; 280 u8 data[]; 281 } __packed; 282 283 #define CXL_FW_TRANSFER_ACTION_FULL 0x0 284 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1 285 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2 286 #define CXL_FW_TRANSFER_ACTION_END 0x3 287 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4 288 289 /* 290 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages 291 * and for each part transferred in a Transfer FW command. 292 */ 293 #define CXL_FW_TRANSFER_ALIGNMENT 128 294 295 /* 296 * Activate FW Input Payload 297 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58 298 */ 299 struct cxl_mbox_activate_fw { 300 u8 action; 301 u8 slot; 302 } __packed; 303 304 #define CXL_FW_ACTIVATE_ONLINE 0x0 305 #define CXL_FW_ACTIVATE_OFFLINE 0x1 306 307 /* FW state bits */ 308 #define CXL_FW_STATE_BITS 32 309 #define CXL_FW_CANCEL 0 310 311 /** 312 * struct cxl_fw_state - Firmware upload / activation state 313 * 314 * @state: fw_uploader state bitmask 315 * @oneshot: whether the fw upload fits in a single transfer 316 * @num_slots: Number of FW slots available 317 * @cur_slot: Slot number currently active 318 * @next_slot: Slot number for the new firmware 319 */ 320 struct cxl_fw_state { 321 DECLARE_BITMAP(state, CXL_FW_STATE_BITS); 322 bool oneshot; 323 int num_slots; 324 int cur_slot; 325 int next_slot; 326 }; 327 328 /** 329 * struct cxl_security_state - Device security state 330 * 331 * @state: state of last security operation 332 * @enabled_cmds: All security commands enabled in the CEL 333 * @poll_tmo_secs: polling timeout 334 * @sanitize_active: sanitize completion pending 335 * @poll_dwork: polling work item 336 * @sanitize_node: sanitation sysfs file to notify 337 */ 338 struct cxl_security_state { 339 unsigned long state; 340 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX); 341 int poll_tmo_secs; 342 bool sanitize_active; 343 struct delayed_work poll_dwork; 344 struct kernfs_node *sanitize_node; 345 }; 346 347 /* 348 * enum cxl_devtype - delineate type-2 from a generic type-3 device 349 * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or 350 * HDM-DB, no requirement that this device implements a 351 * mailbox, or other memory-device-standard manageability 352 * flows. 353 * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with 354 * HDM-H and class-mandatory memory device registers 355 */ 356 enum cxl_devtype { 357 CXL_DEVTYPE_DEVMEM, 358 CXL_DEVTYPE_CLASSMEM, 359 }; 360 361 /** 362 * struct cxl_dpa_perf - DPA performance property entry 363 * @dpa_range: range for DPA address 364 * @coord: QoS performance data (i.e. latency, bandwidth) 365 * @cdat_coord: raw QoS performance data from CDAT 366 * @qos_class: QoS Class cookies 367 */ 368 struct cxl_dpa_perf { 369 struct range dpa_range; 370 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 371 struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX]; 372 int qos_class; 373 }; 374 375 /** 376 * struct cxl_dev_state - The driver device state 377 * 378 * cxl_dev_state represents the CXL driver/device state. It provides an 379 * interface to mailbox commands as well as some cached data about the device. 380 * Currently only memory devices are represented. 381 * 382 * @dev: The device associated with this CXL state 383 * @cxlmd: The device representing the CXL.mem capabilities of @dev 384 * @reg_map: component and ras register mapping parameters 385 * @regs: Parsed register blocks 386 * @cxl_dvsec: Offset to the PCIe device DVSEC 387 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 388 * @media_ready: Indicate whether the device media is usable 389 * @dpa_res: Overall DPA resource tree for the device 390 * @pmem_res: Active Persistent memory capacity configuration 391 * @ram_res: Active Volatile memory capacity configuration 392 * @serial: PCIe Device Serial Number 393 * @type: Generic Memory Class device or Vendor Specific Memory device 394 * @cxl_mbox: CXL mailbox context 395 * @cxlfs: CXL features context 396 */ 397 struct cxl_dev_state { 398 struct device *dev; 399 struct cxl_memdev *cxlmd; 400 struct cxl_register_map reg_map; 401 struct cxl_regs regs; 402 int cxl_dvsec; 403 bool rcd; 404 bool media_ready; 405 struct resource dpa_res; 406 struct resource pmem_res; 407 struct resource ram_res; 408 u64 serial; 409 enum cxl_devtype type; 410 struct cxl_mailbox cxl_mbox; 411 #ifdef CONFIG_CXL_FEATURES 412 struct cxl_features_state *cxlfs; 413 #endif 414 }; 415 416 static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox) 417 { 418 return dev_get_drvdata(cxl_mbox->host); 419 } 420 421 /** 422 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data 423 * 424 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines 425 * common memory device functionality like the presence of a mailbox and 426 * the functionality related to that like Identify Memory Device and Get 427 * Partition Info 428 * @cxlds: Core driver state common across Type-2 and Type-3 devices 429 * @lsa_size: Size of Label Storage Area 430 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 431 * @firmware_version: Firmware version for the memory device. 432 * @total_bytes: sum of all possible capacities 433 * @volatile_only_bytes: hard volatile capacity 434 * @persistent_only_bytes: hard persistent capacity 435 * @partition_align_bytes: alignment size for partition-able capacity 436 * @active_volatile_bytes: sum of hard + soft volatile 437 * @active_persistent_bytes: sum of hard + soft persistent 438 * @next_volatile_bytes: volatile capacity change pending device reset 439 * @next_persistent_bytes: persistent capacity change pending device reset 440 * @ram_perf: performance data entry matched to RAM partition 441 * @pmem_perf: performance data entry matched to PMEM partition 442 * @event: event log driver state 443 * @poison: poison driver state info 444 * @security: security driver state info 445 * @fw: firmware upload / activation state 446 * 447 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for 448 * details on capacity parameters. 449 */ 450 struct cxl_memdev_state { 451 struct cxl_dev_state cxlds; 452 size_t lsa_size; 453 char firmware_version[0x10]; 454 u64 total_bytes; 455 u64 volatile_only_bytes; 456 u64 persistent_only_bytes; 457 u64 partition_align_bytes; 458 u64 active_volatile_bytes; 459 u64 active_persistent_bytes; 460 u64 next_volatile_bytes; 461 u64 next_persistent_bytes; 462 463 struct cxl_dpa_perf ram_perf; 464 struct cxl_dpa_perf pmem_perf; 465 466 struct cxl_event_state event; 467 struct cxl_poison_state poison; 468 struct cxl_security_state security; 469 struct cxl_fw_state fw; 470 }; 471 472 static inline struct cxl_memdev_state * 473 to_cxl_memdev_state(struct cxl_dev_state *cxlds) 474 { 475 if (cxlds->type != CXL_DEVTYPE_CLASSMEM) 476 return NULL; 477 return container_of(cxlds, struct cxl_memdev_state, cxlds); 478 } 479 480 enum cxl_opcode { 481 CXL_MBOX_OP_INVALID = 0x0000, 482 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 483 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 484 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 485 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 486 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 487 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 488 CXL_MBOX_OP_TRANSFER_FW = 0x0201, 489 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 490 CXL_MBOX_OP_GET_TIMESTAMP = 0x0300, 491 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 492 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 493 CXL_MBOX_OP_GET_LOG = 0x0401, 494 CXL_MBOX_OP_GET_LOG_CAPS = 0x0402, 495 CXL_MBOX_OP_CLEAR_LOG = 0x0403, 496 CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405, 497 CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500, 498 CXL_MBOX_OP_GET_FEATURE = 0x0501, 499 CXL_MBOX_OP_SET_FEATURE = 0x0502, 500 CXL_MBOX_OP_IDENTIFY = 0x4000, 501 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 502 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 503 CXL_MBOX_OP_GET_LSA = 0x4102, 504 CXL_MBOX_OP_SET_LSA = 0x4103, 505 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 506 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 507 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 508 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 509 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 510 CXL_MBOX_OP_GET_POISON = 0x4300, 511 CXL_MBOX_OP_INJECT_POISON = 0x4301, 512 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 513 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 514 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 515 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 516 CXL_MBOX_OP_SANITIZE = 0x4400, 517 CXL_MBOX_OP_SECURE_ERASE = 0x4401, 518 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 519 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 520 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 521 CXL_MBOX_OP_UNLOCK = 0x4503, 522 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 523 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 524 CXL_MBOX_OP_MAX = 0x10000 525 }; 526 527 #define DEFINE_CXL_CEL_UUID \ 528 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 529 0x3b, 0x3f, 0x17) 530 531 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 532 UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 533 0x40, 0x3d, 0x86) 534 535 struct cxl_mbox_get_supported_logs { 536 __le16 entries; 537 u8 rsvd[6]; 538 struct cxl_gsl_entry { 539 uuid_t uuid; 540 __le32 size; 541 } __packed entry[]; 542 } __packed; 543 544 struct cxl_cel_entry { 545 __le16 opcode; 546 __le16 effect; 547 } __packed; 548 549 struct cxl_mbox_get_log { 550 uuid_t uuid; 551 __le32 offset; 552 __le32 length; 553 } __packed; 554 555 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 556 struct cxl_mbox_identify { 557 char fw_revision[0x10]; 558 __le64 total_capacity; 559 __le64 volatile_capacity; 560 __le64 persistent_capacity; 561 __le64 partition_align; 562 __le16 info_event_log_size; 563 __le16 warning_event_log_size; 564 __le16 failure_event_log_size; 565 __le16 fatal_event_log_size; 566 __le32 lsa_size; 567 u8 poison_list_max_mer[3]; 568 __le16 inject_poison_limit; 569 u8 poison_caps; 570 u8 qos_telemetry_caps; 571 } __packed; 572 573 /* 574 * General Media Event Record UUID 575 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 576 */ 577 #define CXL_EVENT_GEN_MEDIA_UUID \ 578 UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \ 579 0x21, 0xeb, 0xa6) 580 581 /* 582 * DRAM Event Record UUID 583 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 584 */ 585 #define CXL_EVENT_DRAM_UUID \ 586 UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \ 587 0x5c, 0x96, 0x24) 588 589 /* 590 * Memory Module Event Record UUID 591 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 592 */ 593 #define CXL_EVENT_MEM_MODULE_UUID \ 594 UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \ 595 0x13, 0xb7, 0x74) 596 597 /* 598 * Get Event Records output payload 599 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 600 */ 601 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 602 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 603 struct cxl_get_event_payload { 604 u8 flags; 605 u8 reserved1; 606 __le16 overflow_err_count; 607 __le64 first_overflow_timestamp; 608 __le64 last_overflow_timestamp; 609 __le16 record_count; 610 u8 reserved2[10]; 611 struct cxl_event_record_raw records[]; 612 } __packed; 613 614 /* 615 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 616 */ 617 enum cxl_event_log_type { 618 CXL_EVENT_TYPE_INFO = 0x00, 619 CXL_EVENT_TYPE_WARN, 620 CXL_EVENT_TYPE_FAIL, 621 CXL_EVENT_TYPE_FATAL, 622 CXL_EVENT_TYPE_MAX 623 }; 624 625 /* 626 * Clear Event Records input payload 627 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 628 */ 629 struct cxl_mbox_clear_event_payload { 630 u8 event_log; /* enum cxl_event_log_type */ 631 u8 clear_flags; 632 u8 nr_recs; 633 u8 reserved[3]; 634 __le16 handles[]; 635 } __packed; 636 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 637 638 struct cxl_mbox_get_partition_info { 639 __le64 active_volatile_cap; 640 __le64 active_persistent_cap; 641 __le64 next_volatile_cap; 642 __le64 next_persistent_cap; 643 } __packed; 644 645 struct cxl_mbox_get_lsa { 646 __le32 offset; 647 __le32 length; 648 } __packed; 649 650 struct cxl_mbox_set_lsa { 651 __le32 offset; 652 __le32 reserved; 653 u8 data[]; 654 } __packed; 655 656 struct cxl_mbox_set_partition_info { 657 __le64 volatile_capacity; 658 u8 flags; 659 } __packed; 660 661 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 662 663 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 664 struct cxl_mbox_set_timestamp_in { 665 __le64 timestamp; 666 667 } __packed; 668 669 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 670 struct cxl_mbox_poison_in { 671 __le64 offset; 672 __le64 length; 673 } __packed; 674 675 struct cxl_mbox_poison_out { 676 u8 flags; 677 u8 rsvd1; 678 __le64 overflow_ts; 679 __le16 count; 680 u8 rsvd2[20]; 681 struct cxl_poison_record { 682 __le64 address; 683 __le32 length; 684 __le32 rsvd; 685 } __packed record[]; 686 } __packed; 687 688 /* 689 * Get Poison List address field encodes the starting 690 * address of poison, and the source of the poison. 691 */ 692 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 693 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 694 695 /* Get Poison List record length is in units of 64 bytes */ 696 #define CXL_POISON_LEN_MULT 64 697 698 /* Kernel defined maximum for a list of poison errors */ 699 #define CXL_POISON_LIST_MAX 1024 700 701 /* Get Poison List: Payload out flags */ 702 #define CXL_POISON_FLAG_MORE BIT(0) 703 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 704 #define CXL_POISON_FLAG_SCANNING BIT(2) 705 706 /* Get Poison List: Poison Source */ 707 #define CXL_POISON_SOURCE_UNKNOWN 0 708 #define CXL_POISON_SOURCE_EXTERNAL 1 709 #define CXL_POISON_SOURCE_INTERNAL 2 710 #define CXL_POISON_SOURCE_INJECTED 3 711 #define CXL_POISON_SOURCE_VENDOR 7 712 713 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 714 struct cxl_mbox_inject_poison { 715 __le64 address; 716 }; 717 718 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 719 struct cxl_mbox_clear_poison { 720 __le64 address; 721 u8 write_data[CXL_POISON_LEN_MULT]; 722 } __packed; 723 724 /** 725 * struct cxl_mem_command - Driver representation of a memory device command 726 * @info: Command information as it exists for the UAPI 727 * @opcode: The actual bits used for the mailbox protocol 728 * @flags: Set of flags effecting driver behavior. 729 * 730 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 731 * will be enabled by the driver regardless of what hardware may have 732 * advertised. 733 * 734 * The cxl_mem_command is the driver's internal representation of commands that 735 * are supported by the driver. Some of these commands may not be supported by 736 * the hardware. The driver will use @info to validate the fields passed in by 737 * the user then submit the @opcode to the hardware. 738 * 739 * See struct cxl_command_info. 740 */ 741 struct cxl_mem_command { 742 struct cxl_command_info info; 743 enum cxl_opcode opcode; 744 u32 flags; 745 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 746 }; 747 748 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 749 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 750 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 751 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 752 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 753 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 754 755 /* set passphrase input payload */ 756 struct cxl_set_pass { 757 u8 type; 758 u8 reserved[31]; 759 /* CXL field using NVDIMM define, same length */ 760 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 761 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 762 } __packed; 763 764 /* disable passphrase input payload */ 765 struct cxl_disable_pass { 766 u8 type; 767 u8 reserved[31]; 768 u8 pass[NVDIMM_PASSPHRASE_LEN]; 769 } __packed; 770 771 /* passphrase secure erase payload */ 772 struct cxl_pass_erase { 773 u8 type; 774 u8 reserved[31]; 775 u8 pass[NVDIMM_PASSPHRASE_LEN]; 776 } __packed; 777 778 enum { 779 CXL_PMEM_SEC_PASS_MASTER = 0, 780 CXL_PMEM_SEC_PASS_USER, 781 }; 782 783 int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, 784 struct cxl_mbox_cmd *cmd); 785 int cxl_dev_state_identify(struct cxl_memdev_state *mds); 786 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 787 int cxl_enumerate_cmds(struct cxl_memdev_state *mds); 788 int cxl_mem_create_range_info(struct cxl_memdev_state *mds); 789 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev); 790 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, 791 unsigned long *cmds); 792 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, 793 unsigned long *cmds); 794 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status); 795 void cxl_event_trace_record(const struct cxl_memdev *cxlmd, 796 enum cxl_event_log_type type, 797 enum cxl_event_type event_type, 798 const uuid_t *uuid, union cxl_event *evt); 799 int cxl_set_timestamp(struct cxl_memdev_state *mds); 800 int cxl_poison_state_init(struct cxl_memdev_state *mds); 801 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 802 struct cxl_region *cxlr); 803 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 804 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 805 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 806 807 #ifdef CONFIG_CXL_SUSPEND 808 void cxl_mem_active_inc(void); 809 void cxl_mem_active_dec(void); 810 #else 811 static inline void cxl_mem_active_inc(void) 812 { 813 } 814 static inline void cxl_mem_active_dec(void) 815 { 816 } 817 #endif 818 819 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd); 820 821 /** 822 * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities 823 * @regs: mapped registers, see devm_cxl_setup_hdm() 824 * @decoder_count: number of decoders for this port 825 * @target_count: for switch decoders, max downstream port targets 826 * @interleave_mask: interleave granularity capability, see check_interleave_cap() 827 * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap() 828 * @port: mapped cxl_port, see devm_cxl_setup_hdm() 829 */ 830 struct cxl_hdm { 831 struct cxl_component_regs regs; 832 unsigned int decoder_count; 833 unsigned int target_count; 834 unsigned int interleave_mask; 835 unsigned long iw_cap_mask; 836 struct cxl_port *port; 837 }; 838 839 struct seq_file; 840 struct dentry *cxl_debugfs_create_dir(const char *dir); 841 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 842 #endif /* __CXL_MEM_H__ */ 843