1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/notifier.h> 10 #include <linux/bitops.h> 11 #include <linux/log2.h> 12 #include <linux/node.h> 13 #include <linux/io.h> 14 #include <linux/range.h> 15 #include <cxl/cxl.h> 16 17 extern const struct nvdimm_security_ops *cxl_security_ops; 18 19 /** 20 * DOC: cxl objects 21 * 22 * The CXL core objects like ports, decoders, and regions are shared 23 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 24 * (port-driver, region-driver, nvdimm object-drivers... etc). 25 */ 26 27 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 28 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 29 30 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 31 #define CXL_CM_OFFSET 0x1000 32 #define CXL_CM_CAP_HDR_OFFSET 0x0 33 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 34 #define CM_CAP_HDR_CAP_ID 1 35 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 36 #define CM_CAP_HDR_CAP_VERSION 1 37 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 38 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 39 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 40 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 41 42 #define CXL_CM_CAP_CAP_ID_RAS 0x2 43 #define CXL_CM_CAP_CAP_ID_HDM 0x5 44 #define CXL_CM_CAP_CAP_HDM_VERSION 1 45 46 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 47 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 48 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 49 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 50 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 51 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 52 #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) 53 #define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) 54 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 55 #define CXL_HDM_DECODER_ENABLE BIT(1) 56 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 57 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 58 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 59 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 60 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 61 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 62 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 63 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 64 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 65 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 66 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 67 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 68 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 69 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 70 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 71 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 72 73 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 74 #define CXL_DECODER_MIN_GRANULARITY 256 75 #define CXL_DECODER_MAX_ENCODED_IG 6 76 77 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 78 { 79 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 80 81 switch (val) { 82 case 0: 83 return 1; 84 case 1 ... 8: 85 return val * 2; 86 case 9 ... 12: 87 return (val - 4) * 4; 88 default: 89 return -ENXIO; 90 } 91 } 92 93 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 94 static inline int eig_to_granularity(u16 eig, int *granularity) 95 { 96 if (eig > CXL_DECODER_MAX_ENCODED_IG) 97 return -EINVAL; 98 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 99 return 0; 100 } 101 102 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 103 static inline int eiw_to_ways(u8 eiw, int *ways) 104 { 105 switch (eiw) { 106 case 0 ... 4: 107 *ways = 1 << eiw; 108 break; 109 case 8 ... 10: 110 *ways = 3 << (eiw - 8); 111 break; 112 default: 113 return -EINVAL; 114 } 115 116 return 0; 117 } 118 119 static inline int granularity_to_eig(int granularity, u16 *eig) 120 { 121 *eig = 0; 122 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 123 !is_power_of_2(granularity)) 124 return -EINVAL; 125 *eig = ilog2(granularity) - 8; 126 return 0; 127 } 128 129 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 130 { 131 *eiw = 0; 132 if (ways > 16) 133 return -EINVAL; 134 if (is_power_of_2(ways)) { 135 *eiw = ilog2(ways); 136 return 0; 137 } 138 if (ways % 3) 139 return -EINVAL; 140 ways /= 3; 141 if (!is_power_of_2(ways)) 142 return -EINVAL; 143 *eiw = ilog2(ways) + 8; 144 return 0; 145 } 146 147 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 148 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 149 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 150 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 151 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 152 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 153 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 154 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 155 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 156 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 157 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 158 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 159 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 160 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 161 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 162 #define CXL_RAS_CAPABILITY_LENGTH 0x58 163 #define CXL_HEADERLOG_SIZE SZ_64 164 #define CXL_HEADERLOG_SIZE_U32 (CXL_HEADERLOG_SIZE / sizeof(u32)) 165 166 /* 167 * The RAS UCE trace event header array was originally sized at SZ_512/sizeof(u32) 168 * = 128 u32s due to a bug. Userspace tools (rasdaemon) have grown a dependency 169 * on that 512-byte layout. Keep the trace array at 128 u32s to preserve the 170 * ABI; only CXL_HEADERLOG_SIZE_U32 (16) dwords are valid hardware data, the 171 * remainder are zero-filled. 172 */ 173 #define CXL_HEADERLOG_TRACE_SIZE SZ_512 174 #define CXL_HEADERLOG_TRACE_SIZE_U32 (CXL_HEADERLOG_TRACE_SIZE / sizeof(u32)) 175 176 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 177 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 178 #define CXLDEV_CAP_ARRAY_CAP_ID 0 179 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 180 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 181 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 182 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 183 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 184 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 185 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 186 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 187 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 188 189 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 190 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 191 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 192 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 193 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 194 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 195 196 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 197 CXLDEV_EVENT_STATUS_WARN | \ 198 CXLDEV_EVENT_STATUS_FAIL | \ 199 CXLDEV_EVENT_STATUS_FATAL) 200 201 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 202 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 203 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 204 205 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 206 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 207 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 208 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 209 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 210 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 211 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 212 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 213 #define CXLDEV_MBOX_CMD_OFFSET 0x08 214 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 215 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 216 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 217 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 218 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 219 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 220 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 221 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 222 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 223 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 224 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 225 226 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 227 struct cxl_component_reg_map *map); 228 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 229 struct cxl_device_reg_map *map); 230 int cxl_map_component_regs(const struct cxl_register_map *map, 231 struct cxl_component_regs *regs, 232 unsigned long map_mask); 233 int cxl_map_device_regs(const struct cxl_register_map *map, 234 struct cxl_device_regs *regs); 235 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); 236 237 #define CXL_INSTANCES_COUNT -1 238 enum cxl_regloc_type; 239 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 240 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 241 struct cxl_register_map *map, unsigned int index); 242 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 243 struct cxl_register_map *map); 244 int cxl_setup_regs(struct cxl_register_map *map); 245 struct cxl_dport; 246 int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); 247 248 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 249 #define CXL_TARGET_STRLEN 20 250 251 /* 252 * cxl_decoder flags that define the type of memory / devices this 253 * decoder supports as well as configuration lock status See "CXL 2.0 254 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 255 * Additionally indicate whether decoder settings were autodetected, 256 * user customized. 257 */ 258 #define CXL_DECODER_F_RAM BIT(0) 259 #define CXL_DECODER_F_PMEM BIT(1) 260 #define CXL_DECODER_F_TYPE2 BIT(2) 261 #define CXL_DECODER_F_TYPE3 BIT(3) 262 #define CXL_DECODER_F_LOCK BIT(4) 263 #define CXL_DECODER_F_ENABLE BIT(5) 264 #define CXL_DECODER_F_NORMALIZED_ADDRESSING BIT(6) 265 #define CXL_DECODER_F_RESET_MASK (CXL_DECODER_F_ENABLE | CXL_DECODER_F_LOCK) 266 267 enum cxl_decoder_type { 268 CXL_DECODER_DEVMEM = 2, 269 CXL_DECODER_HOSTONLYMEM = 3, 270 }; 271 272 /* 273 * Current specification goes up to 8, double that seems a reasonable 274 * software max for the foreseeable future 275 */ 276 #define CXL_DECODER_MAX_INTERLEAVE 16 277 278 #define CXL_QOS_CLASS_INVALID -1 279 280 /** 281 * struct cxl_decoder - Common CXL HDM Decoder Attributes 282 * @dev: this decoder's device 283 * @id: kernel device name id 284 * @hpa_range: Host physical address range mapped by this decoder 285 * @interleave_ways: number of cxl_dports in this decode 286 * @interleave_granularity: data stride per dport 287 * @target_type: accelerator vs expander (type2 vs type3) selector 288 * @region: currently assigned region for this decoder 289 * @flags: memory type capabilities and locking 290 * @target_map: cached copy of hardware port-id list, available at init 291 * before all @dport objects have been instantiated. While 292 * dport id is 8bit, CFMWS interleave targets are 32bits. 293 * @commit: device/decoder-type specific callback to commit settings to hw 294 * @reset: device/decoder-type specific callback to reset hw settings 295 */ 296 struct cxl_decoder { 297 struct device dev; 298 int id; 299 struct range hpa_range; 300 int interleave_ways; 301 int interleave_granularity; 302 enum cxl_decoder_type target_type; 303 struct cxl_region *region; 304 unsigned long flags; 305 u32 target_map[CXL_DECODER_MAX_INTERLEAVE]; 306 int (*commit)(struct cxl_decoder *cxld); 307 void (*reset)(struct cxl_decoder *cxld); 308 }; 309 310 /* 311 * Track whether this decoder is free for userspace provisioning, reserved for 312 * region autodiscovery, whether it is started connecting (awaiting other 313 * peers), or has completed auto assembly. 314 */ 315 enum cxl_decoder_state { 316 CXL_DECODER_STATE_MANUAL, 317 CXL_DECODER_STATE_AUTO, 318 CXL_DECODER_STATE_AUTO_STAGED, 319 }; 320 321 /** 322 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 323 * @cxld: base cxl_decoder_object 324 * @dpa_res: actively claimed DPA span of this decoder 325 * @skip: offset into @dpa_res where @cxld.hpa_range maps 326 * @state: autodiscovery state 327 * @part: partition index this decoder maps 328 * @pos: interleave position in @cxld.region 329 */ 330 struct cxl_endpoint_decoder { 331 struct cxl_decoder cxld; 332 struct resource *dpa_res; 333 resource_size_t skip; 334 enum cxl_decoder_state state; 335 int part; 336 int pos; 337 }; 338 339 /** 340 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 341 * @cxld: base cxl_decoder object 342 * @nr_targets: number of elements in @target 343 * @target: active ordered target list in current decoder configuration 344 * 345 * The 'switch' decoder type represents the decoder instances of cxl_port's that 346 * route from the root of a CXL memory decode topology to the endpoints. They 347 * come in two flavors, root-level decoders, statically defined by platform 348 * firmware, and mid-level decoders, where interleave-granularity, 349 * interleave-width, and the target list are mutable. 350 */ 351 struct cxl_switch_decoder { 352 struct cxl_decoder cxld; 353 int nr_targets; 354 struct cxl_dport *target[]; 355 }; 356 357 struct cxl_root_decoder; 358 /** 359 * struct cxl_rd_ops - CXL root decoder callback operations 360 * @hpa_to_spa: Convert host physical address to system physical address 361 * @spa_to_hpa: Convert system physical address to host physical address 362 */ 363 struct cxl_rd_ops { 364 u64 (*hpa_to_spa)(struct cxl_root_decoder *cxlrd, u64 hpa); 365 u64 (*spa_to_hpa)(struct cxl_root_decoder *cxlrd, u64 spa); 366 }; 367 368 /** 369 * struct cxl_root_decoder - Static platform CXL address decoder 370 * @res: host / parent resource for region allocations 371 * @cache_size: extended linear cache size if exists, otherwise zero. 372 * @region_id: region id for next region provisioning event 373 * @platform_data: platform specific configuration data 374 * @regions_lock: sync region discovery, construction, and deletion 375 * @regions: regions to remove at root decoder destruct time 376 * @dead: root decoder dead to region creation 377 * @qos_class: QoS performance class cookie 378 * @ops: CXL root decoder operations 379 * @cxlsd: base cxl switch decoder 380 */ 381 struct cxl_root_decoder { 382 struct resource *res; 383 resource_size_t cache_size; 384 atomic_t region_id; 385 void *platform_data; 386 struct mutex regions_lock; 387 struct xarray regions; 388 bool dead; 389 int qos_class; 390 struct cxl_rd_ops ops; 391 struct cxl_switch_decoder cxlsd; 392 }; 393 394 /* 395 * enum cxl_config_state - State machine for region configuration 396 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 397 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 398 * changes to interleave_ways or interleave_granularity 399 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 400 * active 401 * @CXL_CONFIG_RESET_PENDING: see commit_store() 402 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 403 */ 404 enum cxl_config_state { 405 CXL_CONFIG_IDLE, 406 CXL_CONFIG_INTERLEAVE_ACTIVE, 407 CXL_CONFIG_ACTIVE, 408 CXL_CONFIG_RESET_PENDING, 409 CXL_CONFIG_COMMIT, 410 }; 411 412 /** 413 * struct cxl_region_params - region settings 414 * @state: allow the driver to lockdown further parameter changes 415 * @uuid: unique id for persistent regions 416 * @interleave_ways: number of endpoints in the region 417 * @interleave_granularity: capacity each endpoint contributes to a stripe 418 * @res: allocated iomem capacity for this region 419 * @targets: active ordered targets in current decoder configuration 420 * @nr_targets: number of targets 421 * @cache_size: extended linear cache size if exists, otherwise zero. 422 * 423 * State transitions are protected by cxl_rwsem.region 424 */ 425 struct cxl_region_params { 426 enum cxl_config_state state; 427 uuid_t uuid; 428 int interleave_ways; 429 int interleave_granularity; 430 struct resource *res; 431 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 432 int nr_targets; 433 resource_size_t cache_size; 434 }; 435 436 /* 437 * Indicate whether this region has been assembled by autodetection or 438 * userspace assembly. Prevent endpoint decoders outside of automatic 439 * detection from being added to the region. 440 */ 441 #define CXL_REGION_F_AUTO 0 442 443 /* 444 * Require that a committed region successfully complete a teardown once 445 * any of its associated decoders have been torn down. This maintains 446 * the commit state for the region since there are committed decoders, 447 * but blocks cxl_region_probe(). 448 */ 449 #define CXL_REGION_F_NEEDS_RESET 1 450 451 /* 452 * Indicate whether this region is locked due to 1 or more decoders that have 453 * been locked. The approach of all or nothing is taken with regard to the 454 * locked attribute. CXL_REGION_F_NEEDS_RESET should not be set if this flag is 455 * set. 456 */ 457 #define CXL_REGION_F_LOCK 2 458 459 /* 460 * Indicate Normalized Addressing. Use it to disable SPA conversion if 461 * HPA != SPA and an address translation callback handler does not 462 * exist. Flag is needed by AMD Zen5 platforms. 463 */ 464 #define CXL_REGION_F_NORMALIZED_ADDRESSING 3 465 466 /** 467 * struct cxl_region - CXL region 468 * @dev: This region's device 469 * @id: This region's id. Id is globally unique across all regions 470 * @cxlrd: Region's root decoder 471 * @hpa_range: Address range occupied by the region 472 * @mode: Operational mode of the mapped capacity 473 * @type: Endpoint decoder target type 474 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 475 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 476 * @flags: Region state flags 477 * @params: active + config params for the region 478 * @coord: QoS access coordinates for the region 479 * @node_notifier: notifier for setting the access coordinates to node 480 * @adist_notifier: notifier for calculating the abstract distance of node 481 */ 482 struct cxl_region { 483 struct device dev; 484 int id; 485 struct cxl_root_decoder *cxlrd; 486 struct range hpa_range; 487 enum cxl_partition_mode mode; 488 enum cxl_decoder_type type; 489 struct cxl_nvdimm_bridge *cxl_nvb; 490 struct cxl_pmem_region *cxlr_pmem; 491 unsigned long flags; 492 struct cxl_region_params params; 493 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 494 struct notifier_block node_notifier; 495 struct notifier_block adist_notifier; 496 }; 497 498 struct cxl_nvdimm_bridge { 499 int id; 500 struct device dev; 501 struct cxl_port *port; 502 struct nvdimm_bus *nvdimm_bus; 503 struct nvdimm_bus_descriptor nd_desc; 504 }; 505 506 #define CXL_DEV_ID_LEN 19 507 508 enum { 509 CXL_NVD_F_INVALIDATED = 0, 510 }; 511 512 struct cxl_nvdimm { 513 struct device dev; 514 struct cxl_memdev *cxlmd; 515 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 516 u64 dirty_shutdowns; 517 unsigned long flags; 518 }; 519 520 struct cxl_pmem_region_mapping { 521 struct cxl_memdev *cxlmd; 522 struct cxl_nvdimm *cxl_nvd; 523 u64 start; 524 u64 size; 525 int position; 526 }; 527 528 struct cxl_pmem_region { 529 struct device dev; 530 struct cxl_region *cxlr; 531 struct nd_region *nd_region; 532 struct range hpa_range; 533 int nr_mappings; 534 struct cxl_pmem_region_mapping mapping[]; 535 }; 536 537 struct cxl_dax_region { 538 struct device dev; 539 struct cxl_region *cxlr; 540 struct range hpa_range; 541 }; 542 543 /** 544 * struct cxl_port - logical collection of upstream port devices and 545 * downstream port devices to construct a CXL memory 546 * decode hierarchy. 547 * @dev: this port's device 548 * @uport_dev: PCI or platform device implementing the upstream port capability 549 * @host_bridge: Shortcut to the platform attach point for this port 550 * @id: id for port device-name 551 * @dports: cxl_dport instances referenced by decoders 552 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 553 * @regions: cxl_region_ref instances, regions mapped by this port 554 * @parent_dport: dport that points to this port in the parent 555 * @decoder_ida: allocator for decoder ids 556 * @reg_map: component and ras register mapping parameters 557 * @regs: mapped component registers 558 * @nr_dports: number of entries in @dports 559 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 560 * @commit_end: cursor to track highest committed decoder for commit ordering 561 * @dead: last ep has been removed, force port re-creation 562 * @depth: How deep this port is relative to the root. depth 0 is the root. 563 * @cdat: Cached CDAT data 564 * @cdat_available: Should a CDAT attribute be available in sysfs 565 * @pci_latency: Upstream latency in picoseconds 566 * @component_reg_phys: Physical address of component register 567 */ 568 struct cxl_port { 569 struct device dev; 570 struct device *uport_dev; 571 struct device *host_bridge; 572 int id; 573 struct xarray dports; 574 struct xarray endpoints; 575 struct xarray regions; 576 struct cxl_dport *parent_dport; 577 struct ida decoder_ida; 578 struct cxl_register_map reg_map; 579 struct cxl_component_regs regs; 580 int nr_dports; 581 int hdm_end; 582 int commit_end; 583 bool dead; 584 unsigned int depth; 585 struct cxl_cdat { 586 void *table; 587 size_t length; 588 } cdat; 589 bool cdat_available; 590 long pci_latency; 591 resource_size_t component_reg_phys; 592 }; 593 594 struct cxl_root; 595 596 struct cxl_root_ops { 597 int (*qos_class)(struct cxl_root *cxl_root, 598 struct access_coordinate *coord, int entries, 599 int *qos_class); 600 int (*translation_setup_root)(struct cxl_root *cxl_root, void *data); 601 }; 602 603 /** 604 * struct cxl_root - logical collection of root cxl_port items 605 * 606 * @port: cxl_port member 607 * @ops: cxl root operations 608 */ 609 struct cxl_root { 610 struct cxl_port port; 611 struct cxl_root_ops ops; 612 }; 613 614 static inline struct cxl_root * 615 to_cxl_root(const struct cxl_port *port) 616 { 617 return container_of(port, struct cxl_root, port); 618 } 619 620 static inline struct cxl_dport * 621 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 622 { 623 return xa_load(&port->dports, (unsigned long)dport_dev); 624 } 625 626 struct cxl_rcrb_info { 627 resource_size_t base; 628 u16 aer_cap; 629 }; 630 631 /** 632 * struct cxl_dport - CXL downstream port 633 * @dport_dev: PCI bridge or firmware device representing the downstream link 634 * @reg_map: component and ras register mapping parameters 635 * @port_id: unique hardware identifier for dport in decoder target list 636 * @rcrb: Data about the Root Complex Register Block layout 637 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 638 * @port: reference to cxl_port that contains this downstream port 639 * @regs: Dport parsed register blocks 640 * @coord: access coordinates (bandwidth and latency performance attributes) 641 * @link_latency: calculated PCIe downstream latency 642 * @gpf_dvsec: Cached GPF port DVSEC 643 */ 644 struct cxl_dport { 645 struct device *dport_dev; 646 struct cxl_register_map reg_map; 647 int port_id; 648 struct cxl_rcrb_info rcrb; 649 bool rch; 650 struct cxl_port *port; 651 struct cxl_regs regs; 652 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 653 long link_latency; 654 int gpf_dvsec; 655 }; 656 657 /** 658 * struct cxl_ep - track an endpoint's interest in a port 659 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 660 * @dport: which dport routes to this endpoint on @port 661 * @next: cxl switch port across the link attached to @dport NULL if 662 * attached to an endpoint 663 */ 664 struct cxl_ep { 665 struct device *ep; 666 struct cxl_dport *dport; 667 struct cxl_port *next; 668 }; 669 670 /** 671 * struct cxl_region_ref - track a region's interest in a port 672 * @port: point in topology to install this reference 673 * @decoder: decoder assigned for @region in @port 674 * @region: region for this reference 675 * @endpoints: cxl_ep references for region members beneath @port 676 * @nr_targets_set: track how many targets have been programmed during setup 677 * @nr_eps: number of endpoints beneath @port 678 * @nr_targets: number of distinct targets needed to reach @nr_eps 679 */ 680 struct cxl_region_ref { 681 struct cxl_port *port; 682 struct cxl_decoder *decoder; 683 struct cxl_region *region; 684 struct xarray endpoints; 685 int nr_targets_set; 686 int nr_eps; 687 int nr_targets; 688 }; 689 690 /* 691 * The platform firmware device hosting the root is also the top of the 692 * CXL port topology. All other CXL ports have another CXL port as their 693 * parent and their ->uport_dev / host device is out-of-line of the port 694 * ancestry. 695 */ 696 static inline bool is_cxl_root(struct cxl_port *port) 697 { 698 return port->uport_dev == port->dev.parent; 699 } 700 701 /* Address translation functions exported to cxl_translate test module only */ 702 int cxl_validate_translation_params(u8 eiw, u16 eig, int pos); 703 u64 cxl_calculate_hpa_offset(u64 dpa_offset, int pos, u8 eiw, u16 eig); 704 u64 cxl_calculate_dpa_offset(u64 hpa_offset, u8 eiw, u16 eig); 705 int cxl_calculate_position(u64 hpa_offset, u8 eiw, u16 eig); 706 struct cxl_cxims_data { 707 int nr_maps; 708 u64 xormaps[] __counted_by(nr_maps); 709 }; 710 711 #if IS_ENABLED(CONFIG_CXL_ACPI) 712 u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw); 713 #else 714 static inline u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw) 715 { 716 return ULLONG_MAX; 717 } 718 #endif 719 720 int cxl_num_decoders_committed(struct cxl_port *port); 721 bool is_cxl_port(const struct device *dev); 722 struct cxl_port *to_cxl_port(const struct device *dev); 723 struct cxl_port *parent_port_of(struct cxl_port *port); 724 void cxl_port_commit_reap(struct cxl_decoder *cxld); 725 struct pci_bus; 726 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 727 struct pci_bus *bus); 728 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 729 struct cxl_port *devm_cxl_add_port(struct device *host, 730 struct device *uport_dev, 731 resource_size_t component_reg_phys, 732 struct cxl_dport *parent_dport); 733 struct cxl_root *devm_cxl_add_root(struct device *host); 734 int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, 735 struct cxl_dport *parent_dport); 736 struct cxl_root *find_cxl_root(struct cxl_port *port); 737 738 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev)) 739 DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 740 DEFINE_FREE(put_cxl_root_decoder, struct cxl_root_decoder *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev)) 741 DEFINE_FREE(put_cxl_region, struct cxl_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 742 DEFINE_FREE(put_cxl_dax_region, struct cxl_dax_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 743 744 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 745 void cxl_bus_rescan(void); 746 void cxl_bus_drain(void); 747 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 748 struct cxl_dport **dport); 749 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 750 struct cxl_dport **dport); 751 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 752 753 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 754 struct device *dport, int port_id, 755 resource_size_t component_reg_phys); 756 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 757 struct device *dport_dev, int port_id, 758 resource_size_t rcrb); 759 760 #ifdef CONFIG_CXL_ATL 761 void cxl_setup_prm_address_translation(struct cxl_root *cxl_root); 762 #else 763 static inline 764 void cxl_setup_prm_address_translation(struct cxl_root *cxl_root) {} 765 #endif 766 767 struct cxl_decoder *to_cxl_decoder(struct device *dev); 768 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 769 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 770 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 771 bool is_root_decoder(struct device *dev); 772 bool is_switch_decoder(struct device *dev); 773 bool is_endpoint_decoder(struct device *dev); 774 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 775 unsigned int nr_targets); 776 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 777 unsigned int nr_targets); 778 int cxl_decoder_add(struct cxl_decoder *cxld); 779 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 780 int cxl_decoder_add_locked(struct cxl_decoder *cxld); 781 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 782 static inline int cxl_root_decoder_autoremove(struct device *host, 783 struct cxl_root_decoder *cxlrd) 784 { 785 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld); 786 } 787 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 788 789 /** 790 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 791 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 792 * @ranges: Number of active HDM ranges this device uses. 793 * @port: endpoint port associated with this info instance 794 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 795 */ 796 struct cxl_endpoint_dvsec_info { 797 bool mem_enabled; 798 int ranges; 799 struct cxl_port *port; 800 struct range dvsec_range[2]; 801 }; 802 803 int devm_cxl_switch_port_decoders_setup(struct cxl_port *port); 804 int devm_cxl_endpoint_decoders_setup(struct cxl_port *port); 805 void cxl_port_update_decoder_targets(struct cxl_port *port, 806 struct cxl_dport *dport); 807 int cxl_port_setup_regs(struct cxl_port *port, 808 resource_size_t component_reg_phys); 809 810 struct cxl_dev_state; 811 int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, 812 struct cxl_endpoint_dvsec_info *info); 813 814 bool is_cxl_region(struct device *dev); 815 816 extern const struct bus_type cxl_bus_type; 817 818 /* 819 * Note, add_dport() is expressly for the cxl_port driver. TODO: investigate a 820 * type-safe driver model where probe()/remove() take the type of object implied 821 * by @id and the add_dport() op only defined for the CXL_DEVICE_PORT driver 822 * template. 823 */ 824 struct cxl_driver { 825 const char *name; 826 int (*probe)(struct device *dev); 827 void (*remove)(struct device *dev); 828 struct cxl_dport *(*add_dport)(struct cxl_port *port, 829 struct device *dport_dev); 830 struct device_driver drv; 831 int id; 832 }; 833 834 #define to_cxl_drv(__drv) container_of_const(__drv, struct cxl_driver, drv) 835 836 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 837 const char *modname); 838 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 839 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 840 841 #define module_cxl_driver(__cxl_driver) \ 842 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 843 844 #define CXL_DEVICE_NVDIMM_BRIDGE 1 845 #define CXL_DEVICE_NVDIMM 2 846 #define CXL_DEVICE_PORT 3 847 #define CXL_DEVICE_ROOT 4 848 #define CXL_DEVICE_MEMORY_EXPANDER 5 849 #define CXL_DEVICE_REGION 6 850 #define CXL_DEVICE_PMEM_REGION 7 851 #define CXL_DEVICE_DAX_REGION 8 852 #define CXL_DEVICE_PMU 9 853 854 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 855 #define CXL_MODALIAS_FMT "cxl:t%d" 856 857 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 858 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 859 struct cxl_port *port); 860 struct cxl_nvdimm_bridge *__devm_cxl_add_nvdimm_bridge(struct device *host, 861 struct cxl_port *port); 862 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 863 bool is_cxl_nvdimm(struct device *dev); 864 int devm_cxl_add_nvdimm(struct device *host, struct cxl_port *port, 865 struct cxl_memdev *cxlmd); 866 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); 867 868 #ifdef CONFIG_CXL_REGION 869 bool is_cxl_pmem_region(struct device *dev); 870 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 871 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled); 872 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 873 u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa); 874 bool cxl_region_contains_resource(const struct resource *res); 875 #else 876 static inline bool is_cxl_pmem_region(struct device *dev) 877 { 878 return false; 879 } 880 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 881 { 882 return NULL; 883 } 884 static inline int cxl_add_to_region(struct cxl_endpoint_decoder *cxled) 885 { 886 return 0; 887 } 888 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 889 { 890 return NULL; 891 } 892 static inline u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, 893 u64 spa) 894 { 895 return 0; 896 } 897 static inline bool cxl_region_contains_resource(const struct resource *res) 898 { 899 return false; 900 } 901 #endif 902 903 void cxl_endpoint_parse_cdat(struct cxl_port *port); 904 void cxl_switch_parse_cdat(struct cxl_dport *dport); 905 906 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 907 struct access_coordinate *coord); 908 void cxl_region_perf_data_calculate(struct cxl_region *cxlr, 909 struct cxl_endpoint_decoder *cxled); 910 void cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr); 911 912 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd); 913 914 void cxl_coordinates_combine(struct access_coordinate *out, 915 struct access_coordinate *c1, 916 struct access_coordinate *c2); 917 918 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); 919 struct cxl_dport *devm_cxl_add_dport_by_dev(struct cxl_port *port, 920 struct device *dport_dev); 921 922 /* 923 * Unit test builds overrides this to __weak, find the 'strong' version 924 * of these symbols in tools/testing/cxl/. 925 */ 926 #ifndef __mock 927 #define __mock static 928 #endif 929 930 u16 cxl_gpf_get_dvsec(struct device *dev); 931 932 #endif /* __CXL_H__ */ 933