1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/notifier.h> 10 #include <linux/bitops.h> 11 #include <linux/log2.h> 12 #include <linux/node.h> 13 #include <linux/io.h> 14 #include <linux/range.h> 15 16 extern const struct nvdimm_security_ops *cxl_security_ops; 17 18 /** 19 * DOC: cxl objects 20 * 21 * The CXL core objects like ports, decoders, and regions are shared 22 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 23 * (port-driver, region-driver, nvdimm object-drivers... etc). 24 */ 25 26 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 27 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 28 29 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 30 #define CXL_CM_OFFSET 0x1000 31 #define CXL_CM_CAP_HDR_OFFSET 0x0 32 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 33 #define CM_CAP_HDR_CAP_ID 1 34 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 35 #define CM_CAP_HDR_CAP_VERSION 1 36 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 37 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 38 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 39 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 40 41 #define CXL_CM_CAP_CAP_ID_RAS 0x2 42 #define CXL_CM_CAP_CAP_ID_HDM 0x5 43 #define CXL_CM_CAP_CAP_HDM_VERSION 1 44 45 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 46 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 47 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 48 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 49 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 50 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 51 #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) 52 #define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) 53 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 54 #define CXL_HDM_DECODER_ENABLE BIT(1) 55 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 56 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 57 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 58 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 59 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 60 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 61 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 62 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 63 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 64 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 65 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 66 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 67 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 68 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 69 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 70 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 71 72 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 73 #define CXL_DECODER_MIN_GRANULARITY 256 74 #define CXL_DECODER_MAX_ENCODED_IG 6 75 76 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 77 { 78 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 79 80 return val ? val * 2 : 1; 81 } 82 83 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 84 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 85 { 86 if (eig > CXL_DECODER_MAX_ENCODED_IG) 87 return -EINVAL; 88 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 89 return 0; 90 } 91 92 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 93 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 94 { 95 switch (eiw) { 96 case 0 ... 4: 97 *ways = 1 << eiw; 98 break; 99 case 8 ... 10: 100 *ways = 3 << (eiw - 8); 101 break; 102 default: 103 return -EINVAL; 104 } 105 106 return 0; 107 } 108 109 static inline int granularity_to_eig(int granularity, u16 *eig) 110 { 111 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 112 !is_power_of_2(granularity)) 113 return -EINVAL; 114 *eig = ilog2(granularity) - 8; 115 return 0; 116 } 117 118 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 119 { 120 if (ways > 16) 121 return -EINVAL; 122 if (is_power_of_2(ways)) { 123 *eiw = ilog2(ways); 124 return 0; 125 } 126 if (ways % 3) 127 return -EINVAL; 128 ways /= 3; 129 if (!is_power_of_2(ways)) 130 return -EINVAL; 131 *eiw = ilog2(ways) + 8; 132 return 0; 133 } 134 135 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 136 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 137 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 138 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 139 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 140 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 141 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 142 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 143 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 144 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 145 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 146 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 147 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 148 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 149 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 150 #define CXL_RAS_CAPABILITY_LENGTH 0x58 151 #define CXL_HEADERLOG_SIZE SZ_512 152 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 153 154 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 155 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 156 #define CXLDEV_CAP_ARRAY_CAP_ID 0 157 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 158 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 159 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 160 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 161 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 162 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 163 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 164 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 165 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 166 167 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 168 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 169 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 170 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 171 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 172 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 173 174 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 175 CXLDEV_EVENT_STATUS_WARN | \ 176 CXLDEV_EVENT_STATUS_FAIL | \ 177 CXLDEV_EVENT_STATUS_FATAL) 178 179 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 180 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 181 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 182 183 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 184 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 185 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 186 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 187 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 188 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 189 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 190 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 191 #define CXLDEV_MBOX_CMD_OFFSET 0x08 192 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 193 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 194 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 195 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 196 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 197 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 198 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 199 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 200 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 201 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 202 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 203 204 /* 205 * Using struct_group() allows for per register-block-type helper routines, 206 * without requiring block-type agnostic code to include the prefix. 207 */ 208 struct cxl_regs { 209 /* 210 * Common set of CXL Component register block base pointers 211 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 212 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 213 */ 214 struct_group_tagged(cxl_component_regs, component, 215 void __iomem *hdm_decoder; 216 void __iomem *ras; 217 ); 218 /* 219 * Common set of CXL Device register block base pointers 220 * @status: CXL 2.0 8.2.8.3 Device Status Registers 221 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 222 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 223 */ 224 struct_group_tagged(cxl_device_regs, device_regs, 225 void __iomem *status, *mbox, *memdev; 226 ); 227 228 struct_group_tagged(cxl_pmu_regs, pmu_regs, 229 void __iomem *pmu; 230 ); 231 232 /* 233 * RCH downstream port specific RAS register 234 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB 235 */ 236 struct_group_tagged(cxl_rch_regs, rch_regs, 237 void __iomem *dport_aer; 238 ); 239 240 /* 241 * RCD upstream port specific PCIe cap register 242 * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB 243 */ 244 struct_group_tagged(cxl_rcd_regs, rcd_regs, 245 void __iomem *rcd_pcie_cap; 246 ); 247 }; 248 249 struct cxl_reg_map { 250 bool valid; 251 int id; 252 unsigned long offset; 253 unsigned long size; 254 }; 255 256 struct cxl_component_reg_map { 257 struct cxl_reg_map hdm_decoder; 258 struct cxl_reg_map ras; 259 }; 260 261 struct cxl_device_reg_map { 262 struct cxl_reg_map status; 263 struct cxl_reg_map mbox; 264 struct cxl_reg_map memdev; 265 }; 266 267 struct cxl_pmu_reg_map { 268 struct cxl_reg_map pmu; 269 }; 270 271 /** 272 * struct cxl_register_map - DVSEC harvested register block mapping parameters 273 * @host: device for devm operations and logging 274 * @base: virtual base of the register-block-BAR + @block_offset 275 * @resource: physical resource base of the register block 276 * @max_size: maximum mapping size to perform register search 277 * @reg_type: see enum cxl_regloc_type 278 * @component_map: cxl_reg_map for component registers 279 * @device_map: cxl_reg_maps for device registers 280 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units 281 */ 282 struct cxl_register_map { 283 struct device *host; 284 void __iomem *base; 285 resource_size_t resource; 286 resource_size_t max_size; 287 u8 reg_type; 288 union { 289 struct cxl_component_reg_map component_map; 290 struct cxl_device_reg_map device_map; 291 struct cxl_pmu_reg_map pmu_map; 292 }; 293 }; 294 295 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 296 struct cxl_component_reg_map *map); 297 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 298 struct cxl_device_reg_map *map); 299 int cxl_map_component_regs(const struct cxl_register_map *map, 300 struct cxl_component_regs *regs, 301 unsigned long map_mask); 302 int cxl_map_device_regs(const struct cxl_register_map *map, 303 struct cxl_device_regs *regs); 304 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); 305 306 #define CXL_INSTANCES_COUNT -1 307 enum cxl_regloc_type; 308 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 309 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 310 struct cxl_register_map *map, unsigned int index); 311 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 312 struct cxl_register_map *map); 313 int cxl_setup_regs(struct cxl_register_map *map); 314 struct cxl_dport; 315 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 316 struct cxl_dport *dport); 317 int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); 318 319 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 320 #define CXL_TARGET_STRLEN 20 321 322 /* 323 * cxl_decoder flags that define the type of memory / devices this 324 * decoder supports as well as configuration lock status See "CXL 2.0 325 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 326 * Additionally indicate whether decoder settings were autodetected, 327 * user customized. 328 */ 329 #define CXL_DECODER_F_RAM BIT(0) 330 #define CXL_DECODER_F_PMEM BIT(1) 331 #define CXL_DECODER_F_TYPE2 BIT(2) 332 #define CXL_DECODER_F_TYPE3 BIT(3) 333 #define CXL_DECODER_F_LOCK BIT(4) 334 #define CXL_DECODER_F_ENABLE BIT(5) 335 #define CXL_DECODER_F_NORMALIZED_ADDRESSING BIT(6) 336 337 enum cxl_decoder_type { 338 CXL_DECODER_DEVMEM = 2, 339 CXL_DECODER_HOSTONLYMEM = 3, 340 }; 341 342 /* 343 * Current specification goes up to 8, double that seems a reasonable 344 * software max for the foreseeable future 345 */ 346 #define CXL_DECODER_MAX_INTERLEAVE 16 347 348 #define CXL_QOS_CLASS_INVALID -1 349 350 /** 351 * struct cxl_decoder - Common CXL HDM Decoder Attributes 352 * @dev: this decoder's device 353 * @id: kernel device name id 354 * @hpa_range: Host physical address range mapped by this decoder 355 * @interleave_ways: number of cxl_dports in this decode 356 * @interleave_granularity: data stride per dport 357 * @target_type: accelerator vs expander (type2 vs type3) selector 358 * @region: currently assigned region for this decoder 359 * @flags: memory type capabilities and locking 360 * @target_map: cached copy of hardware port-id list, available at init 361 * before all @dport objects have been instantiated. While 362 * dport id is 8bit, CFMWS interleave targets are 32bits. 363 * @commit: device/decoder-type specific callback to commit settings to hw 364 * @reset: device/decoder-type specific callback to reset hw settings 365 */ 366 struct cxl_decoder { 367 struct device dev; 368 int id; 369 struct range hpa_range; 370 int interleave_ways; 371 int interleave_granularity; 372 enum cxl_decoder_type target_type; 373 struct cxl_region *region; 374 unsigned long flags; 375 u32 target_map[CXL_DECODER_MAX_INTERLEAVE]; 376 int (*commit)(struct cxl_decoder *cxld); 377 void (*reset)(struct cxl_decoder *cxld); 378 }; 379 380 /* 381 * Track whether this decoder is reserved for region autodiscovery, or 382 * free for userspace provisioning. 383 */ 384 enum cxl_decoder_state { 385 CXL_DECODER_STATE_MANUAL, 386 CXL_DECODER_STATE_AUTO, 387 }; 388 389 /** 390 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 391 * @cxld: base cxl_decoder_object 392 * @dpa_res: actively claimed DPA span of this decoder 393 * @skip: offset into @dpa_res where @cxld.hpa_range maps 394 * @state: autodiscovery state 395 * @part: partition index this decoder maps 396 * @pos: interleave position in @cxld.region 397 */ 398 struct cxl_endpoint_decoder { 399 struct cxl_decoder cxld; 400 struct resource *dpa_res; 401 resource_size_t skip; 402 enum cxl_decoder_state state; 403 int part; 404 int pos; 405 }; 406 407 /** 408 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 409 * @cxld: base cxl_decoder object 410 * @nr_targets: number of elements in @target 411 * @target: active ordered target list in current decoder configuration 412 * 413 * The 'switch' decoder type represents the decoder instances of cxl_port's that 414 * route from the root of a CXL memory decode topology to the endpoints. They 415 * come in two flavors, root-level decoders, statically defined by platform 416 * firmware, and mid-level decoders, where interleave-granularity, 417 * interleave-width, and the target list are mutable. 418 */ 419 struct cxl_switch_decoder { 420 struct cxl_decoder cxld; 421 int nr_targets; 422 struct cxl_dport *target[]; 423 }; 424 425 struct cxl_root_decoder; 426 /** 427 * struct cxl_rd_ops - CXL root decoder callback operations 428 * @hpa_to_spa: Convert host physical address to system physical address 429 * @spa_to_hpa: Convert system physical address to host physical address 430 */ 431 struct cxl_rd_ops { 432 u64 (*hpa_to_spa)(struct cxl_root_decoder *cxlrd, u64 hpa); 433 u64 (*spa_to_hpa)(struct cxl_root_decoder *cxlrd, u64 spa); 434 }; 435 436 /** 437 * struct cxl_root_decoder - Static platform CXL address decoder 438 * @res: host / parent resource for region allocations 439 * @cache_size: extended linear cache size if exists, otherwise zero. 440 * @region_id: region id for next region provisioning event 441 * @platform_data: platform specific configuration data 442 * @range_lock: sync region autodiscovery by address range 443 * @qos_class: QoS performance class cookie 444 * @ops: CXL root decoder operations 445 * @cxlsd: base cxl switch decoder 446 */ 447 struct cxl_root_decoder { 448 struct resource *res; 449 resource_size_t cache_size; 450 atomic_t region_id; 451 void *platform_data; 452 struct mutex range_lock; 453 int qos_class; 454 struct cxl_rd_ops ops; 455 struct cxl_switch_decoder cxlsd; 456 }; 457 458 /* 459 * enum cxl_config_state - State machine for region configuration 460 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 461 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 462 * changes to interleave_ways or interleave_granularity 463 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 464 * active 465 * @CXL_CONFIG_RESET_PENDING: see commit_store() 466 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 467 */ 468 enum cxl_config_state { 469 CXL_CONFIG_IDLE, 470 CXL_CONFIG_INTERLEAVE_ACTIVE, 471 CXL_CONFIG_ACTIVE, 472 CXL_CONFIG_RESET_PENDING, 473 CXL_CONFIG_COMMIT, 474 }; 475 476 /** 477 * struct cxl_region_params - region settings 478 * @state: allow the driver to lockdown further parameter changes 479 * @uuid: unique id for persistent regions 480 * @interleave_ways: number of endpoints in the region 481 * @interleave_granularity: capacity each endpoint contributes to a stripe 482 * @res: allocated iomem capacity for this region 483 * @targets: active ordered targets in current decoder configuration 484 * @nr_targets: number of targets 485 * @cache_size: extended linear cache size if exists, otherwise zero. 486 * 487 * State transitions are protected by cxl_rwsem.region 488 */ 489 struct cxl_region_params { 490 enum cxl_config_state state; 491 uuid_t uuid; 492 int interleave_ways; 493 int interleave_granularity; 494 struct resource *res; 495 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 496 int nr_targets; 497 resource_size_t cache_size; 498 }; 499 500 enum cxl_partition_mode { 501 CXL_PARTMODE_RAM, 502 CXL_PARTMODE_PMEM, 503 }; 504 505 /* 506 * Indicate whether this region has been assembled by autodetection or 507 * userspace assembly. Prevent endpoint decoders outside of automatic 508 * detection from being added to the region. 509 */ 510 #define CXL_REGION_F_AUTO 0 511 512 /* 513 * Require that a committed region successfully complete a teardown once 514 * any of its associated decoders have been torn down. This maintains 515 * the commit state for the region since there are committed decoders, 516 * but blocks cxl_region_probe(). 517 */ 518 #define CXL_REGION_F_NEEDS_RESET 1 519 520 /* 521 * Indicate whether this region is locked due to 1 or more decoders that have 522 * been locked. The approach of all or nothing is taken with regard to the 523 * locked attribute. CXL_REGION_F_NEEDS_RESET should not be set if this flag is 524 * set. 525 */ 526 #define CXL_REGION_F_LOCK 2 527 528 /* 529 * Indicate Normalized Addressing. Use it to disable SPA conversion if 530 * HPA != SPA and an address translation callback handler does not 531 * exist. Flag is needed by AMD Zen5 platforms. 532 */ 533 #define CXL_REGION_F_NORMALIZED_ADDRESSING 3 534 535 /** 536 * struct cxl_region - CXL region 537 * @dev: This region's device 538 * @id: This region's id. Id is globally unique across all regions 539 * @cxlrd: Region's root decoder 540 * @hpa_range: Address range occupied by the region 541 * @mode: Operational mode of the mapped capacity 542 * @type: Endpoint decoder target type 543 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 544 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 545 * @flags: Region state flags 546 * @params: active + config params for the region 547 * @coord: QoS access coordinates for the region 548 * @node_notifier: notifier for setting the access coordinates to node 549 * @adist_notifier: notifier for calculating the abstract distance of node 550 */ 551 struct cxl_region { 552 struct device dev; 553 int id; 554 struct cxl_root_decoder *cxlrd; 555 struct range hpa_range; 556 enum cxl_partition_mode mode; 557 enum cxl_decoder_type type; 558 struct cxl_nvdimm_bridge *cxl_nvb; 559 struct cxl_pmem_region *cxlr_pmem; 560 unsigned long flags; 561 struct cxl_region_params params; 562 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 563 struct notifier_block node_notifier; 564 struct notifier_block adist_notifier; 565 }; 566 567 struct cxl_nvdimm_bridge { 568 int id; 569 struct device dev; 570 struct cxl_port *port; 571 struct nvdimm_bus *nvdimm_bus; 572 struct nvdimm_bus_descriptor nd_desc; 573 }; 574 575 #define CXL_DEV_ID_LEN 19 576 577 struct cxl_nvdimm { 578 struct device dev; 579 struct cxl_memdev *cxlmd; 580 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 581 u64 dirty_shutdowns; 582 }; 583 584 struct cxl_pmem_region_mapping { 585 struct cxl_memdev *cxlmd; 586 struct cxl_nvdimm *cxl_nvd; 587 u64 start; 588 u64 size; 589 int position; 590 }; 591 592 struct cxl_pmem_region { 593 struct device dev; 594 struct cxl_region *cxlr; 595 struct nd_region *nd_region; 596 struct range hpa_range; 597 int nr_mappings; 598 struct cxl_pmem_region_mapping mapping[]; 599 }; 600 601 struct cxl_dax_region { 602 struct device dev; 603 struct cxl_region *cxlr; 604 struct range hpa_range; 605 }; 606 607 /** 608 * struct cxl_port - logical collection of upstream port devices and 609 * downstream port devices to construct a CXL memory 610 * decode hierarchy. 611 * @dev: this port's device 612 * @uport_dev: PCI or platform device implementing the upstream port capability 613 * @host_bridge: Shortcut to the platform attach point for this port 614 * @id: id for port device-name 615 * @dports: cxl_dport instances referenced by decoders 616 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 617 * @regions: cxl_region_ref instances, regions mapped by this port 618 * @parent_dport: dport that points to this port in the parent 619 * @decoder_ida: allocator for decoder ids 620 * @reg_map: component and ras register mapping parameters 621 * @regs: mapped component registers 622 * @nr_dports: number of entries in @dports 623 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 624 * @commit_end: cursor to track highest committed decoder for commit ordering 625 * @dead: last ep has been removed, force port re-creation 626 * @depth: How deep this port is relative to the root. depth 0 is the root. 627 * @cdat: Cached CDAT data 628 * @cdat_available: Should a CDAT attribute be available in sysfs 629 * @pci_latency: Upstream latency in picoseconds 630 * @component_reg_phys: Physical address of component register 631 */ 632 struct cxl_port { 633 struct device dev; 634 struct device *uport_dev; 635 struct device *host_bridge; 636 int id; 637 struct xarray dports; 638 struct xarray endpoints; 639 struct xarray regions; 640 struct cxl_dport *parent_dport; 641 struct ida decoder_ida; 642 struct cxl_register_map reg_map; 643 struct cxl_component_regs regs; 644 int nr_dports; 645 int hdm_end; 646 int commit_end; 647 bool dead; 648 unsigned int depth; 649 struct cxl_cdat { 650 void *table; 651 size_t length; 652 } cdat; 653 bool cdat_available; 654 long pci_latency; 655 resource_size_t component_reg_phys; 656 }; 657 658 struct cxl_root; 659 660 struct cxl_root_ops { 661 int (*qos_class)(struct cxl_root *cxl_root, 662 struct access_coordinate *coord, int entries, 663 int *qos_class); 664 int (*translation_setup_root)(struct cxl_root *cxl_root, void *data); 665 }; 666 667 /** 668 * struct cxl_root - logical collection of root cxl_port items 669 * 670 * @port: cxl_port member 671 * @ops: cxl root operations 672 */ 673 struct cxl_root { 674 struct cxl_port port; 675 struct cxl_root_ops ops; 676 }; 677 678 static inline struct cxl_root * 679 to_cxl_root(const struct cxl_port *port) 680 { 681 return container_of(port, struct cxl_root, port); 682 } 683 684 static inline struct cxl_dport * 685 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 686 { 687 return xa_load(&port->dports, (unsigned long)dport_dev); 688 } 689 690 struct cxl_rcrb_info { 691 resource_size_t base; 692 u16 aer_cap; 693 }; 694 695 /** 696 * struct cxl_dport - CXL downstream port 697 * @dport_dev: PCI bridge or firmware device representing the downstream link 698 * @reg_map: component and ras register mapping parameters 699 * @port_id: unique hardware identifier for dport in decoder target list 700 * @rcrb: Data about the Root Complex Register Block layout 701 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 702 * @port: reference to cxl_port that contains this downstream port 703 * @regs: Dport parsed register blocks 704 * @coord: access coordinates (bandwidth and latency performance attributes) 705 * @link_latency: calculated PCIe downstream latency 706 * @gpf_dvsec: Cached GPF port DVSEC 707 */ 708 struct cxl_dport { 709 struct device *dport_dev; 710 struct cxl_register_map reg_map; 711 int port_id; 712 struct cxl_rcrb_info rcrb; 713 bool rch; 714 struct cxl_port *port; 715 struct cxl_regs regs; 716 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 717 long link_latency; 718 int gpf_dvsec; 719 }; 720 721 /** 722 * struct cxl_ep - track an endpoint's interest in a port 723 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 724 * @dport: which dport routes to this endpoint on @port 725 * @next: cxl switch port across the link attached to @dport NULL if 726 * attached to an endpoint 727 */ 728 struct cxl_ep { 729 struct device *ep; 730 struct cxl_dport *dport; 731 struct cxl_port *next; 732 }; 733 734 /** 735 * struct cxl_region_ref - track a region's interest in a port 736 * @port: point in topology to install this reference 737 * @decoder: decoder assigned for @region in @port 738 * @region: region for this reference 739 * @endpoints: cxl_ep references for region members beneath @port 740 * @nr_targets_set: track how many targets have been programmed during setup 741 * @nr_eps: number of endpoints beneath @port 742 * @nr_targets: number of distinct targets needed to reach @nr_eps 743 */ 744 struct cxl_region_ref { 745 struct cxl_port *port; 746 struct cxl_decoder *decoder; 747 struct cxl_region *region; 748 struct xarray endpoints; 749 int nr_targets_set; 750 int nr_eps; 751 int nr_targets; 752 }; 753 754 /* 755 * The platform firmware device hosting the root is also the top of the 756 * CXL port topology. All other CXL ports have another CXL port as their 757 * parent and their ->uport_dev / host device is out-of-line of the port 758 * ancestry. 759 */ 760 static inline bool is_cxl_root(struct cxl_port *port) 761 { 762 return port->uport_dev == port->dev.parent; 763 } 764 765 /* Address translation functions exported to cxl_translate test module only */ 766 int cxl_validate_translation_params(u8 eiw, u16 eig, int pos); 767 u64 cxl_calculate_hpa_offset(u64 dpa_offset, int pos, u8 eiw, u16 eig); 768 u64 cxl_calculate_dpa_offset(u64 hpa_offset, u8 eiw, u16 eig); 769 int cxl_calculate_position(u64 hpa_offset, u8 eiw, u16 eig); 770 struct cxl_cxims_data { 771 int nr_maps; 772 u64 xormaps[] __counted_by(nr_maps); 773 }; 774 775 #if IS_ENABLED(CONFIG_CXL_ACPI) 776 u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw); 777 #else 778 static inline u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw) 779 { 780 return ULLONG_MAX; 781 } 782 #endif 783 784 int cxl_num_decoders_committed(struct cxl_port *port); 785 bool is_cxl_port(const struct device *dev); 786 struct cxl_port *to_cxl_port(const struct device *dev); 787 struct cxl_port *parent_port_of(struct cxl_port *port); 788 void cxl_port_commit_reap(struct cxl_decoder *cxld); 789 struct pci_bus; 790 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 791 struct pci_bus *bus); 792 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 793 struct cxl_port *devm_cxl_add_port(struct device *host, 794 struct device *uport_dev, 795 resource_size_t component_reg_phys, 796 struct cxl_dport *parent_dport); 797 struct cxl_root *devm_cxl_add_root(struct device *host); 798 int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, 799 struct cxl_dport *parent_dport); 800 struct cxl_root *find_cxl_root(struct cxl_port *port); 801 802 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev)) 803 DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 804 DEFINE_FREE(put_cxl_root_decoder, struct cxl_root_decoder *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev)) 805 DEFINE_FREE(put_cxl_region, struct cxl_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 806 807 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 808 void cxl_bus_rescan(void); 809 void cxl_bus_drain(void); 810 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 811 struct cxl_dport **dport); 812 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 813 struct cxl_dport **dport); 814 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 815 816 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 817 struct device *dport, int port_id, 818 resource_size_t component_reg_phys); 819 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 820 struct device *dport_dev, int port_id, 821 resource_size_t rcrb); 822 823 #ifdef CONFIG_CXL_ATL 824 void cxl_setup_prm_address_translation(struct cxl_root *cxl_root); 825 #else 826 static inline 827 void cxl_setup_prm_address_translation(struct cxl_root *cxl_root) {} 828 #endif 829 830 struct cxl_decoder *to_cxl_decoder(struct device *dev); 831 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 832 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 833 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 834 bool is_root_decoder(struct device *dev); 835 bool is_switch_decoder(struct device *dev); 836 bool is_endpoint_decoder(struct device *dev); 837 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 838 unsigned int nr_targets); 839 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 840 unsigned int nr_targets); 841 int cxl_decoder_add(struct cxl_decoder *cxld); 842 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 843 int cxl_decoder_add_locked(struct cxl_decoder *cxld); 844 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 845 static inline int cxl_root_decoder_autoremove(struct device *host, 846 struct cxl_root_decoder *cxlrd) 847 { 848 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld); 849 } 850 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 851 852 /** 853 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 854 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 855 * @ranges: Number of active HDM ranges this device uses. 856 * @port: endpoint port associated with this info instance 857 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 858 */ 859 struct cxl_endpoint_dvsec_info { 860 bool mem_enabled; 861 int ranges; 862 struct cxl_port *port; 863 struct range dvsec_range[2]; 864 }; 865 866 int devm_cxl_switch_port_decoders_setup(struct cxl_port *port); 867 int devm_cxl_endpoint_decoders_setup(struct cxl_port *port); 868 void cxl_port_update_decoder_targets(struct cxl_port *port, 869 struct cxl_dport *dport); 870 int cxl_port_setup_regs(struct cxl_port *port, 871 resource_size_t component_reg_phys); 872 873 struct cxl_dev_state; 874 int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, 875 struct cxl_endpoint_dvsec_info *info); 876 877 bool is_cxl_region(struct device *dev); 878 879 extern const struct bus_type cxl_bus_type; 880 881 /* 882 * Note, add_dport() is expressly for the cxl_port driver. TODO: investigate a 883 * type-safe driver model where probe()/remove() take the type of object implied 884 * by @id and the add_dport() op only defined for the CXL_DEVICE_PORT driver 885 * template. 886 */ 887 struct cxl_driver { 888 const char *name; 889 int (*probe)(struct device *dev); 890 void (*remove)(struct device *dev); 891 struct cxl_dport *(*add_dport)(struct cxl_port *port, 892 struct device *dport_dev); 893 struct device_driver drv; 894 int id; 895 }; 896 897 #define to_cxl_drv(__drv) container_of_const(__drv, struct cxl_driver, drv) 898 899 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 900 const char *modname); 901 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 902 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 903 904 #define module_cxl_driver(__cxl_driver) \ 905 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 906 907 #define CXL_DEVICE_NVDIMM_BRIDGE 1 908 #define CXL_DEVICE_NVDIMM 2 909 #define CXL_DEVICE_PORT 3 910 #define CXL_DEVICE_ROOT 4 911 #define CXL_DEVICE_MEMORY_EXPANDER 5 912 #define CXL_DEVICE_REGION 6 913 #define CXL_DEVICE_PMEM_REGION 7 914 #define CXL_DEVICE_DAX_REGION 8 915 #define CXL_DEVICE_PMU 9 916 917 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 918 #define CXL_MODALIAS_FMT "cxl:t%d" 919 920 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 921 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 922 struct cxl_port *port); 923 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 924 bool is_cxl_nvdimm(struct device *dev); 925 int devm_cxl_add_nvdimm(struct device *host, struct cxl_port *port, 926 struct cxl_memdev *cxlmd); 927 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); 928 929 #ifdef CONFIG_CXL_REGION 930 bool is_cxl_pmem_region(struct device *dev); 931 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 932 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled); 933 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 934 u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa); 935 #else 936 static inline bool is_cxl_pmem_region(struct device *dev) 937 { 938 return false; 939 } 940 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 941 { 942 return NULL; 943 } 944 static inline int cxl_add_to_region(struct cxl_endpoint_decoder *cxled) 945 { 946 return 0; 947 } 948 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 949 { 950 return NULL; 951 } 952 static inline u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, 953 u64 spa) 954 { 955 return 0; 956 } 957 #endif 958 959 void cxl_endpoint_parse_cdat(struct cxl_port *port); 960 void cxl_switch_parse_cdat(struct cxl_dport *dport); 961 962 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 963 struct access_coordinate *coord); 964 void cxl_region_perf_data_calculate(struct cxl_region *cxlr, 965 struct cxl_endpoint_decoder *cxled); 966 void cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr); 967 968 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd); 969 970 void cxl_coordinates_combine(struct access_coordinate *out, 971 struct access_coordinate *c1, 972 struct access_coordinate *c2); 973 974 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); 975 struct cxl_dport *devm_cxl_add_dport_by_dev(struct cxl_port *port, 976 struct device *dport_dev); 977 978 /* 979 * Unit test builds overrides this to __weak, find the 'strong' version 980 * of these symbols in tools/testing/cxl/. 981 */ 982 #ifndef __mock 983 #define __mock static 984 #endif 985 986 u16 cxl_gpf_get_dvsec(struct device *dev); 987 988 #endif /* __CXL_H__ */ 989