1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved
4 */
5
6 #include <drm/drm_managed.h>
7 #include "dpu_hw_cwb.h"
8
9 #include <linux/bitfield.h>
10
11 #define CWB_MUX 0x000
12 #define CWB_MODE 0x004
13
14 /* CWB mux block bit definitions */
15 #define CWB_MUX_MASK GENMASK(3, 0)
16 #define CWB_MODE_MASK GENMASK(2, 0)
17
dpu_hw_cwb_config(struct dpu_hw_cwb * ctx,struct dpu_hw_cwb_setup_cfg * cwb_cfg)18 static void dpu_hw_cwb_config(struct dpu_hw_cwb *ctx,
19 struct dpu_hw_cwb_setup_cfg *cwb_cfg)
20 {
21 struct dpu_hw_blk_reg_map *c = &ctx->hw;
22 int cwb_mux_cfg = 0xF;
23 enum dpu_pingpong pp;
24 enum cwb_mode_input input;
25
26 if (!cwb_cfg)
27 return;
28
29 input = cwb_cfg->input;
30 pp = cwb_cfg->pp_idx;
31
32 if (input >= INPUT_MODE_MAX)
33 return;
34
35 /*
36 * The CWB_MUX register takes the pingpong index for the real-time
37 * display
38 */
39 if ((pp != PINGPONG_NONE) && (pp < PINGPONG_MAX))
40 cwb_mux_cfg = FIELD_PREP(CWB_MUX_MASK, pp - PINGPONG_0);
41
42 input = FIELD_PREP(CWB_MODE_MASK, input);
43
44 DPU_REG_WRITE(c, CWB_MUX, cwb_mux_cfg);
45 DPU_REG_WRITE(c, CWB_MODE, input);
46 }
47
48 /**
49 * dpu_hw_cwb_init() - Initializes the writeback hw driver object with cwb.
50 * @dev: Corresponding device for devres management
51 * @cfg: wb_path catalog entry for which driver object is required
52 * @addr: mapped register io address of MDP
53 * Return: Error code or allocated dpu_hw_wb context
54 */
dpu_hw_cwb_init(struct drm_device * dev,const struct dpu_cwb_cfg * cfg,void __iomem * addr)55 struct dpu_hw_cwb *dpu_hw_cwb_init(struct drm_device *dev,
56 const struct dpu_cwb_cfg *cfg,
57 void __iomem *addr)
58 {
59 struct dpu_hw_cwb *c;
60
61 if (!addr)
62 return ERR_PTR(-EINVAL);
63
64 c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);
65 if (!c)
66 return ERR_PTR(-ENOMEM);
67
68 c->hw.blk_addr = addr + cfg->base;
69 c->hw.log_mask = DPU_DBG_MASK_CWB;
70
71 c->idx = cfg->id;
72 c->ops.config_cwb = dpu_hw_cwb_config;
73
74 return c;
75 }
76