1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CSR_H 7 #define _ASM_RISCV_CSR_H 8 9 #include <asm/asm.h> 10 #include <linux/bits.h> 11 12 /* Status register flags */ 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21 /* zicfilp landing pad status bit */ 22 #define SR_SPELP _AC(0x00800000, UL) 23 #define SR_MPELP _AC(0x020000000000, UL) 24 #ifdef CONFIG_RISCV_M_MODE 25 #define SR_ELP SR_MPELP 26 #else 27 #define SR_ELP SR_SPELP 28 #endif 29 30 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 31 #define SR_FS_OFF _AC(0x00000000, UL) 32 #define SR_FS_INITIAL _AC(0x00002000, UL) 33 #define SR_FS_CLEAN _AC(0x00004000, UL) 34 #define SR_FS_DIRTY _AC(0x00006000, UL) 35 36 #define SR_VS _AC(0x00000600, UL) /* Vector Status */ 37 #define SR_VS_OFF _AC(0x00000000, UL) 38 #define SR_VS_INITIAL _AC(0x00000200, UL) 39 #define SR_VS_CLEAN _AC(0x00000400, UL) 40 #define SR_VS_DIRTY _AC(0x00000600, UL) 41 42 #define SR_VS_THEAD _AC(0x01800000, UL) /* xtheadvector Status */ 43 #define SR_VS_OFF_THEAD _AC(0x00000000, UL) 44 #define SR_VS_INITIAL_THEAD _AC(0x00800000, UL) 45 #define SR_VS_CLEAN_THEAD _AC(0x01000000, UL) 46 #define SR_VS_DIRTY_THEAD _AC(0x01800000, UL) 47 48 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 49 #define SR_XS_OFF _AC(0x00000000, UL) 50 #define SR_XS_INITIAL _AC(0x00008000, UL) 51 #define SR_XS_CLEAN _AC(0x00010000, UL) 52 #define SR_XS_DIRTY _AC(0x00018000, UL) 53 54 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */ 55 56 #ifndef CONFIG_64BIT 57 #define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ 58 #else 59 #define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ 60 #endif 61 62 #ifdef CONFIG_64BIT 63 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ 64 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ 65 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ 66 #endif 67 68 /* SATP flags */ 69 #ifndef CONFIG_64BIT 70 #define SATP_PPN _AC(0x003FFFFF, UL) 71 #define SATP_MODE_32 _AC(0x80000000, UL) 72 #define SATP_MODE_SHIFT 31 73 #define SATP_ASID_BITS 9 74 #define SATP_ASID_SHIFT 22 75 #define SATP_ASID_MASK _AC(0x1FF, UL) 76 #else 77 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 78 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 79 #define SATP_MODE_48 _AC(0x9000000000000000, UL) 80 #define SATP_MODE_57 _AC(0xa000000000000000, UL) 81 #define SATP_MODE_SHIFT 60 82 #define SATP_ASID_BITS 16 83 #define SATP_ASID_SHIFT 44 84 #define SATP_ASID_MASK _AC(0xFFFF, UL) 85 #endif 86 87 /* Exception cause high bit - is an interrupt if set */ 88 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 89 90 /* Interrupt causes (minus the high bit) */ 91 #define IRQ_S_SOFT 1 92 #define IRQ_VS_SOFT 2 93 #define IRQ_M_SOFT 3 94 #define IRQ_S_TIMER 5 95 #define IRQ_VS_TIMER 6 96 #define IRQ_M_TIMER 7 97 #define IRQ_S_EXT 9 98 #define IRQ_VS_EXT 10 99 #define IRQ_M_EXT 11 100 #define IRQ_S_GEXT 12 101 #define IRQ_PMU_OVF 13 102 #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) 103 #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) 104 105 /* Exception causes */ 106 #define EXC_INST_MISALIGNED 0 107 #define EXC_INST_ACCESS 1 108 #define EXC_INST_ILLEGAL 2 109 #define EXC_BREAKPOINT 3 110 #define EXC_LOAD_MISALIGNED 4 111 #define EXC_LOAD_ACCESS 5 112 #define EXC_STORE_MISALIGNED 6 113 #define EXC_STORE_ACCESS 7 114 #define EXC_SYSCALL 8 115 #define EXC_HYPERVISOR_SYSCALL 9 116 #define EXC_SUPERVISOR_SYSCALL 10 117 #define EXC_INST_PAGE_FAULT 12 118 #define EXC_LOAD_PAGE_FAULT 13 119 #define EXC_STORE_PAGE_FAULT 15 120 #define EXC_INST_GUEST_PAGE_FAULT 20 121 #define EXC_LOAD_GUEST_PAGE_FAULT 21 122 #define EXC_VIRTUAL_INST_FAULT 22 123 #define EXC_STORE_GUEST_PAGE_FAULT 23 124 125 /* PMP configuration */ 126 #define PMP_R 0x01 127 #define PMP_W 0x02 128 #define PMP_X 0x04 129 #define PMP_A 0x18 130 #define PMP_A_TOR 0x08 131 #define PMP_A_NA4 0x10 132 #define PMP_A_NAPOT 0x18 133 #define PMP_L 0x80 134 135 /* HSTATUS flags */ 136 #ifdef CONFIG_64BIT 137 #define HSTATUS_HUPMM _AC(0x3000000000000, UL) 138 #define HSTATUS_HUPMM_PMLEN_0 _AC(0x0000000000000, UL) 139 #define HSTATUS_HUPMM_PMLEN_7 _AC(0x2000000000000, UL) 140 #define HSTATUS_HUPMM_PMLEN_16 _AC(0x3000000000000, UL) 141 #define HSTATUS_VSXL _AC(0x300000000, UL) 142 #define HSTATUS_VSXL_SHIFT 32 143 #endif 144 #define HSTATUS_VTSR _AC(0x00400000, UL) 145 #define HSTATUS_VTW _AC(0x00200000, UL) 146 #define HSTATUS_VTVM _AC(0x00100000, UL) 147 #define HSTATUS_VGEIN _AC(0x0003f000, UL) 148 #define HSTATUS_VGEIN_SHIFT 12 149 #define HSTATUS_HU _AC(0x00000200, UL) 150 #define HSTATUS_SPVP _AC(0x00000100, UL) 151 #define HSTATUS_SPV _AC(0x00000080, UL) 152 #define HSTATUS_GVA _AC(0x00000040, UL) 153 #define HSTATUS_VSBE _AC(0x00000020, UL) 154 155 /* HGATP flags */ 156 #define HGATP_MODE_OFF _AC(0, UL) 157 #define HGATP_MODE_SV32X4 _AC(1, UL) 158 #define HGATP_MODE_SV39X4 _AC(8, UL) 159 #define HGATP_MODE_SV48X4 _AC(9, UL) 160 #define HGATP_MODE_SV57X4 _AC(10, UL) 161 162 #define HGATP32_MODE_SHIFT 31 163 #define HGATP32_VMID_SHIFT 22 164 #define HGATP32_VMID GENMASK(28, 22) 165 #define HGATP32_PPN GENMASK(21, 0) 166 167 #define HGATP64_MODE_SHIFT 60 168 #define HGATP64_VMID_SHIFT 44 169 #define HGATP64_VMID GENMASK(57, 44) 170 #define HGATP64_PPN GENMASK(43, 0) 171 172 #define HGATP_PAGE_SHIFT 12 173 174 #ifdef CONFIG_64BIT 175 #define HGATP_PPN HGATP64_PPN 176 #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT 177 #define HGATP_VMID HGATP64_VMID 178 #define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT 179 #else 180 #define HGATP_PPN HGATP32_PPN 181 #define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT 182 #define HGATP_VMID HGATP32_VMID 183 #define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT 184 #endif 185 186 /* VSIP & HVIP relation */ 187 #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) 188 #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ 189 (_AC(1, UL) << IRQ_S_TIMER) | \ 190 (_AC(1, UL) << IRQ_S_EXT) | \ 191 (_AC(1, UL) << IRQ_PMU_OVF)) 192 193 /* AIA CSR bits */ 194 #define TOPI_IID_SHIFT 16 195 #define TOPI_IID_MASK GENMASK(11, 0) 196 #define TOPI_IPRIO_MASK GENMASK(7, 0) 197 #define TOPI_IPRIO_BITS 8 198 199 #define TOPEI_ID_SHIFT 16 200 #define TOPEI_ID_MASK GENMASK(10, 0) 201 #define TOPEI_PRIO_MASK GENMASK(10, 0) 202 203 #define ISELECT_IPRIO0 0x30 204 #define ISELECT_IPRIO15 0x3f 205 #define ISELECT_MASK GENMASK(8, 0) 206 207 #define HVICTL_VTI BIT(30) 208 #define HVICTL_IID GENMASK(27, 16) 209 #define HVICTL_IID_SHIFT 16 210 #define HVICTL_DPR BIT(9) 211 #define HVICTL_IPRIOM BIT(8) 212 #define HVICTL_IPRIO GENMASK(7, 0) 213 214 /* xENVCFG flags */ 215 #define ENVCFG_STCE (_AC(1, ULL) << 63) 216 #define ENVCFG_PBMTE (_AC(1, ULL) << 62) 217 #define ENVCFG_ADUE (_AC(1, ULL) << 61) 218 #define ENVCFG_PMM (_AC(0x3, ULL) << 32) 219 #define ENVCFG_PMM_PMLEN_0 (_AC(0x0, ULL) << 32) 220 #define ENVCFG_PMM_PMLEN_7 (_AC(0x2, ULL) << 32) 221 #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) 222 #define ENVCFG_CBZE (_AC(1, UL) << 7) 223 #define ENVCFG_CBCFE (_AC(1, UL) << 6) 224 #define ENVCFG_LPE (_AC(1, UL) << 2) 225 #define ENVCFG_SSE (_AC(1, UL) << 3) 226 #define ENVCFG_CBIE_SHIFT 4 227 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) 228 #define ENVCFG_CBIE_ILL _AC(0x0, UL) 229 #define ENVCFG_CBIE_FLUSH _AC(0x1, UL) 230 #define ENVCFG_CBIE_INV _AC(0x3, UL) 231 #define ENVCFG_FIOM _AC(0x1, UL) 232 233 /* Smstateen bits */ 234 #define SMSTATEEN0_AIA_IMSIC_SHIFT 58 235 #define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT) 236 #define SMSTATEEN0_AIA_SHIFT 59 237 #define SMSTATEEN0_AIA (_ULL(1) << SMSTATEEN0_AIA_SHIFT) 238 #define SMSTATEEN0_AIA_ISEL_SHIFT 60 239 #define SMSTATEEN0_AIA_ISEL (_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT) 240 #define SMSTATEEN0_HSENVCFG_SHIFT 62 241 #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) 242 #define SMSTATEEN0_SSTATEEN0_SHIFT 63 243 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) 244 245 /* mseccfg bits */ 246 #define MSECCFG_PMM ENVCFG_PMM 247 #define MSECCFG_PMM_PMLEN_0 ENVCFG_PMM_PMLEN_0 248 #define MSECCFG_PMM_PMLEN_7 ENVCFG_PMM_PMLEN_7 249 #define MSECCFG_PMM_PMLEN_16 ENVCFG_PMM_PMLEN_16 250 251 /* symbolic CSR names: */ 252 #define CSR_CYCLE 0xc00 253 #define CSR_TIME 0xc01 254 #define CSR_INSTRET 0xc02 255 #define CSR_HPMCOUNTER3 0xc03 256 #define CSR_HPMCOUNTER4 0xc04 257 #define CSR_HPMCOUNTER5 0xc05 258 #define CSR_HPMCOUNTER6 0xc06 259 #define CSR_HPMCOUNTER7 0xc07 260 #define CSR_HPMCOUNTER8 0xc08 261 #define CSR_HPMCOUNTER9 0xc09 262 #define CSR_HPMCOUNTER10 0xc0a 263 #define CSR_HPMCOUNTER11 0xc0b 264 #define CSR_HPMCOUNTER12 0xc0c 265 #define CSR_HPMCOUNTER13 0xc0d 266 #define CSR_HPMCOUNTER14 0xc0e 267 #define CSR_HPMCOUNTER15 0xc0f 268 #define CSR_HPMCOUNTER16 0xc10 269 #define CSR_HPMCOUNTER17 0xc11 270 #define CSR_HPMCOUNTER18 0xc12 271 #define CSR_HPMCOUNTER19 0xc13 272 #define CSR_HPMCOUNTER20 0xc14 273 #define CSR_HPMCOUNTER21 0xc15 274 #define CSR_HPMCOUNTER22 0xc16 275 #define CSR_HPMCOUNTER23 0xc17 276 #define CSR_HPMCOUNTER24 0xc18 277 #define CSR_HPMCOUNTER25 0xc19 278 #define CSR_HPMCOUNTER26 0xc1a 279 #define CSR_HPMCOUNTER27 0xc1b 280 #define CSR_HPMCOUNTER28 0xc1c 281 #define CSR_HPMCOUNTER29 0xc1d 282 #define CSR_HPMCOUNTER30 0xc1e 283 #define CSR_HPMCOUNTER31 0xc1f 284 #define CSR_CYCLEH 0xc80 285 #define CSR_TIMEH 0xc81 286 #define CSR_INSTRETH 0xc82 287 #define CSR_HPMCOUNTER3H 0xc83 288 #define CSR_HPMCOUNTER4H 0xc84 289 #define CSR_HPMCOUNTER5H 0xc85 290 #define CSR_HPMCOUNTER6H 0xc86 291 #define CSR_HPMCOUNTER7H 0xc87 292 #define CSR_HPMCOUNTER8H 0xc88 293 #define CSR_HPMCOUNTER9H 0xc89 294 #define CSR_HPMCOUNTER10H 0xc8a 295 #define CSR_HPMCOUNTER11H 0xc8b 296 #define CSR_HPMCOUNTER12H 0xc8c 297 #define CSR_HPMCOUNTER13H 0xc8d 298 #define CSR_HPMCOUNTER14H 0xc8e 299 #define CSR_HPMCOUNTER15H 0xc8f 300 #define CSR_HPMCOUNTER16H 0xc90 301 #define CSR_HPMCOUNTER17H 0xc91 302 #define CSR_HPMCOUNTER18H 0xc92 303 #define CSR_HPMCOUNTER19H 0xc93 304 #define CSR_HPMCOUNTER20H 0xc94 305 #define CSR_HPMCOUNTER21H 0xc95 306 #define CSR_HPMCOUNTER22H 0xc96 307 #define CSR_HPMCOUNTER23H 0xc97 308 #define CSR_HPMCOUNTER24H 0xc98 309 #define CSR_HPMCOUNTER25H 0xc99 310 #define CSR_HPMCOUNTER26H 0xc9a 311 #define CSR_HPMCOUNTER27H 0xc9b 312 #define CSR_HPMCOUNTER28H 0xc9c 313 #define CSR_HPMCOUNTER29H 0xc9d 314 #define CSR_HPMCOUNTER30H 0xc9e 315 #define CSR_HPMCOUNTER31H 0xc9f 316 317 #define CSR_SCOUNTOVF 0xda0 318 319 #define CSR_SSTATUS 0x100 320 #define CSR_SIE 0x104 321 #define CSR_STVEC 0x105 322 #define CSR_SCOUNTEREN 0x106 323 #define CSR_SENVCFG 0x10a 324 #define CSR_SSTATEEN0 0x10c 325 #define CSR_SSCRATCH 0x140 326 #define CSR_SEPC 0x141 327 #define CSR_SCAUSE 0x142 328 #define CSR_STVAL 0x143 329 #define CSR_SIP 0x144 330 #define CSR_SATP 0x180 331 332 #define CSR_STIMECMP 0x14D 333 #define CSR_STIMECMPH 0x15D 334 335 /* zicfiss user mode csr. CSR_SSP holds current shadow stack pointer */ 336 #define CSR_SSP 0x011 337 338 /* xtheadvector symbolic CSR names */ 339 #define CSR_VXSAT 0x9 340 #define CSR_VXRM 0xa 341 342 /* xtheadvector CSR masks */ 343 #define CSR_VXRM_MASK 3 344 #define CSR_VXRM_SHIFT 1 345 #define CSR_VXSAT_MASK 1 346 347 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 348 #define CSR_SISELECT 0x150 349 #define CSR_SIREG 0x151 350 351 /* Supervisor-Level Interrupts (AIA) */ 352 #define CSR_STOPEI 0x15c 353 #define CSR_STOPI 0xdb0 354 355 /* Supervisor-Level High-Half CSRs (AIA) */ 356 #define CSR_SIEH 0x114 357 #define CSR_SIPH 0x154 358 359 #define CSR_VSSTATUS 0x200 360 #define CSR_VSIE 0x204 361 #define CSR_VSTVEC 0x205 362 #define CSR_VSSCRATCH 0x240 363 #define CSR_VSEPC 0x241 364 #define CSR_VSCAUSE 0x242 365 #define CSR_VSTVAL 0x243 366 #define CSR_VSIP 0x244 367 #define CSR_VSATP 0x280 368 #define CSR_VSTIMECMP 0x24D 369 #define CSR_VSTIMECMPH 0x25D 370 371 #define CSR_HSTATUS 0x600 372 #define CSR_HEDELEG 0x602 373 #define CSR_HIDELEG 0x603 374 #define CSR_HIE 0x604 375 #define CSR_HTIMEDELTA 0x605 376 #define CSR_HCOUNTEREN 0x606 377 #define CSR_HGEIE 0x607 378 #define CSR_HENVCFG 0x60a 379 #define CSR_HTIMEDELTAH 0x615 380 #define CSR_HENVCFGH 0x61a 381 #define CSR_HTVAL 0x643 382 #define CSR_HIP 0x644 383 #define CSR_HVIP 0x645 384 #define CSR_HTINST 0x64a 385 #define CSR_HGATP 0x680 386 #define CSR_HGEIP 0xe12 387 388 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 389 #define CSR_HVIEN 0x608 390 #define CSR_HVICTL 0x609 391 #define CSR_HVIPRIO1 0x646 392 #define CSR_HVIPRIO2 0x647 393 394 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 395 #define CSR_VSISELECT 0x250 396 #define CSR_VSIREG 0x251 397 398 /* VS-Level Interrupts (H-extension with AIA) */ 399 #define CSR_VSTOPEI 0x25c 400 #define CSR_VSTOPI 0xeb0 401 402 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 403 #define CSR_HIDELEGH 0x613 404 #define CSR_HVIENH 0x618 405 #define CSR_HVIPH 0x655 406 #define CSR_HVIPRIO1H 0x656 407 #define CSR_HVIPRIO2H 0x657 408 #define CSR_VSIEH 0x214 409 #define CSR_VSIPH 0x254 410 411 /* Hypervisor stateen CSRs */ 412 #define CSR_HSTATEEN0 0x60c 413 #define CSR_HSTATEEN0H 0x61c 414 415 #define CSR_MSTATUS 0x300 416 #define CSR_MISA 0x301 417 #define CSR_MIDELEG 0x303 418 #define CSR_MIE 0x304 419 #define CSR_MTVEC 0x305 420 #define CSR_MENVCFG 0x30a 421 #define CSR_MENVCFGH 0x31a 422 #define CSR_MSCRATCH 0x340 423 #define CSR_MEPC 0x341 424 #define CSR_MCAUSE 0x342 425 #define CSR_MTVAL 0x343 426 #define CSR_MIP 0x344 427 #define CSR_PMPCFG0 0x3a0 428 #define CSR_PMPADDR0 0x3b0 429 #define CSR_MSECCFG 0x747 430 #define CSR_MSECCFGH 0x757 431 #define CSR_MVENDORID 0xf11 432 #define CSR_MARCHID 0xf12 433 #define CSR_MIMPID 0xf13 434 #define CSR_MHARTID 0xf14 435 436 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 437 #define CSR_MISELECT 0x350 438 #define CSR_MIREG 0x351 439 440 /* Machine-Level Interrupts (AIA) */ 441 #define CSR_MTOPEI 0x35c 442 #define CSR_MTOPI 0xfb0 443 444 /* Virtual Interrupts for Supervisor Level (AIA) */ 445 #define CSR_MVIEN 0x308 446 #define CSR_MVIP 0x309 447 448 /* Machine-Level High-Half CSRs (AIA) */ 449 #define CSR_MIDELEGH 0x313 450 #define CSR_MIEH 0x314 451 #define CSR_MVIENH 0x318 452 #define CSR_MVIPH 0x319 453 #define CSR_MIPH 0x354 454 455 #define CSR_VSTART 0x8 456 #define CSR_VCSR 0xf 457 #define CSR_VL 0xc20 458 #define CSR_VTYPE 0xc21 459 #define CSR_VLENB 0xc22 460 461 #define VTYPE_VLMUL _AC(7, UL) 462 #define VTYPE_VLMUL_FRAC _AC(4, UL) 463 #define VTYPE_VSEW_SHIFT 3 464 #define VTYPE_VSEW (_AC(7, UL) << VTYPE_VSEW_SHIFT) 465 #define VTYPE_VTA_SHIFT 6 466 #define VTYPE_VTA (_AC(1, UL) << VTYPE_VTA_SHIFT) 467 #define VTYPE_VMA_SHIFT 7 468 #define VTYPE_VMA (_AC(1, UL) << VTYPE_VMA_SHIFT) 469 #define VTYPE_VILL_SHIFT (__riscv_xlen - 1) 470 #define VTYPE_VILL (_AC(1, UL) << VTYPE_VILL_SHIFT) 471 472 #define VTYPE_VLMUL_THEAD _AC(3, UL) 473 #define VTYPE_VSEW_THEAD_SHIFT 2 474 #define VTYPE_VSEW_THEAD (_AC(7, UL) << VTYPE_VSEW_THEAD_SHIFT) 475 #define VTYPE_VEDIV_THEAD_SHIFT 5 476 #define VTYPE_VEDIV_THEAD (_AC(3, UL) << VTYPE_VEDIV_THEAD_SHIFT) 477 478 /* Scalar Crypto Extension - Entropy */ 479 #define CSR_SEED 0x015 480 #define SEED_OPST_MASK _AC(0xC0000000, UL) 481 #define SEED_OPST_BIST _AC(0x00000000, UL) 482 #define SEED_OPST_WAIT _AC(0x40000000, UL) 483 #define SEED_OPST_ES16 _AC(0x80000000, UL) 484 #define SEED_OPST_DEAD _AC(0xC0000000, UL) 485 #define SEED_ENTROPY_MASK _AC(0xFFFF, UL) 486 487 #ifdef CONFIG_RISCV_M_MODE 488 # define CSR_STATUS CSR_MSTATUS 489 # define CSR_IE CSR_MIE 490 # define CSR_TVEC CSR_MTVEC 491 # define CSR_ENVCFG CSR_MENVCFG 492 # define CSR_SCRATCH CSR_MSCRATCH 493 # define CSR_EPC CSR_MEPC 494 # define CSR_CAUSE CSR_MCAUSE 495 # define CSR_TVAL CSR_MTVAL 496 # define CSR_IP CSR_MIP 497 498 # define CSR_IEH CSR_MIEH 499 # define CSR_ISELECT CSR_MISELECT 500 # define CSR_IREG CSR_MIREG 501 # define CSR_IPH CSR_MIPH 502 # define CSR_TOPEI CSR_MTOPEI 503 # define CSR_TOPI CSR_MTOPI 504 505 # define SR_IE SR_MIE 506 # define SR_PIE SR_MPIE 507 # define SR_PP SR_MPP 508 509 # define RV_IRQ_SOFT IRQ_M_SOFT 510 # define RV_IRQ_TIMER IRQ_M_TIMER 511 # define RV_IRQ_EXT IRQ_M_EXT 512 #else /* CONFIG_RISCV_M_MODE */ 513 # define CSR_STATUS CSR_SSTATUS 514 # define CSR_IE CSR_SIE 515 # define CSR_TVEC CSR_STVEC 516 # define CSR_ENVCFG CSR_SENVCFG 517 # define CSR_SCRATCH CSR_SSCRATCH 518 # define CSR_EPC CSR_SEPC 519 # define CSR_CAUSE CSR_SCAUSE 520 # define CSR_TVAL CSR_STVAL 521 # define CSR_IP CSR_SIP 522 523 # define CSR_IEH CSR_SIEH 524 # define CSR_ISELECT CSR_SISELECT 525 # define CSR_IREG CSR_SIREG 526 # define CSR_IPH CSR_SIPH 527 # define CSR_TOPEI CSR_STOPEI 528 # define CSR_TOPI CSR_STOPI 529 530 # define SR_IE SR_SIE 531 # define SR_PIE SR_SPIE 532 # define SR_PP SR_SPP 533 534 # define RV_IRQ_SOFT IRQ_S_SOFT 535 # define RV_IRQ_TIMER IRQ_S_TIMER 536 # define RV_IRQ_EXT IRQ_S_EXT 537 # define RV_IRQ_PMU IRQ_PMU_OVF 538 # define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF) 539 540 #endif /* !CONFIG_RISCV_M_MODE */ 541 542 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 543 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 544 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 545 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 546 547 #ifndef __ASSEMBLER__ 548 549 #define csr_swap(csr, val) \ 550 ({ \ 551 unsigned long __v = (unsigned long)(val); \ 552 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 553 : "=r" (__v) : "rK" (__v) \ 554 : "memory"); \ 555 __v; \ 556 }) 557 558 #define csr_read(csr) \ 559 ({ \ 560 register unsigned long __v; \ 561 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 562 : "=r" (__v) : \ 563 : "memory"); \ 564 __v; \ 565 }) 566 567 #define csr_write(csr, val) \ 568 ({ \ 569 unsigned long __v = (unsigned long)(val); \ 570 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 571 : : "rK" (__v) \ 572 : "memory"); \ 573 }) 574 575 #define csr_read_set(csr, val) \ 576 ({ \ 577 unsigned long __v = (unsigned long)(val); \ 578 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 579 : "=r" (__v) : "rK" (__v) \ 580 : "memory"); \ 581 __v; \ 582 }) 583 584 #define csr_set(csr, val) \ 585 ({ \ 586 unsigned long __v = (unsigned long)(val); \ 587 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 588 : : "rK" (__v) \ 589 : "memory"); \ 590 }) 591 592 #define csr_read_clear(csr, val) \ 593 ({ \ 594 unsigned long __v = (unsigned long)(val); \ 595 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 596 : "=r" (__v) : "rK" (__v) \ 597 : "memory"); \ 598 __v; \ 599 }) 600 601 #define csr_clear(csr, val) \ 602 ({ \ 603 unsigned long __v = (unsigned long)(val); \ 604 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 605 : : "rK" (__v) \ 606 : "memory"); \ 607 }) 608 609 #endif /* __ASSEMBLER__ */ 610 611 #endif /* _ASM_RISCV_CSR_H */ 612