1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * CS530x CODEC driver internal data 4 * 5 * Copyright (C) 2023-2025 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 9 #ifndef _CS530X_H 10 #define _CS530X_H 11 12 #include <linux/device.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/regmap.h> 15 #include <linux/regulator/consumer.h> 16 17 /* Devices */ 18 #define CS530X_2CH_CODEC_DEV_ID 0x4282 19 #define CS530X_2CH_DAC_DEV_ID 0x4302 20 #define CS530X_4CH_DAC_DEV_ID 0x4304 21 #define CS530X_8CH_DAC_DEV_ID 0x4308 22 #define CS530X_2CH_ADC_DEV_ID 0x5302 23 #define CS530X_4CH_ADC_DEV_ID 0x5304 24 #define CS530X_8CH_ADC_DEV_ID 0x5308 25 26 /* Registers */ 27 28 #define CS530X_DEVID 0x0000000 29 #define CS530X_REVID 0x0000004 30 #define CS530X_SW_RESET 0x0000022 31 32 #define CS530X_CLK_CFG_0 0x0000040 33 #define CS530X_CLK_CFG_1 0x0000042 34 #define CS530X_CHIP_ENABLE 0x0000044 35 #define CS530X_ASP_CFG 0x0000048 36 #define CS530X_SIGNAL_PATH_CFG 0x0000050 37 #define CS530X_IN_ENABLES 0x0000080 38 #define CS530X_IN_RAMP_SUM 0x0000082 39 #define CS530X_IN_FILTER 0x0000086 40 #define CS530X_IN_HIZ 0x0000088 41 #define CS530X_IN_INV 0x000008A 42 #define CS530X_IN_VOL_CTRL1_0 0x0000090 43 #define CS530X_IN_VOL_CTRL1_1 0x0000092 44 #define CS530X_IN_VOL_CTRL2_0 0x0000094 45 #define CS530X_IN_VOL_CTRL2_1 0x0000096 46 #define CS530X_IN_VOL_CTRL3_0 0x0000098 47 #define CS530X_IN_VOL_CTRL3_1 0x000009A 48 #define CS530X_IN_VOL_CTRL4_0 0x000009C 49 #define CS530X_IN_VOL_CTRL4_1 0x000009E 50 #define CS530X_IN_VOL_CTRL5 0x00000A0 51 52 #define CS530X_OUT_ENABLES 0x00000C0 53 #define CS530X_OUT_RAMP_SUM 0x00000C2 54 #define CS530X_OUT_DEEMPH 0x00000C4 55 #define CS530X_OUT_FILTER 0x00000C6 56 #define CS530X_OUT_INV 0x00000CA 57 #define CS530X_OUT_VOL_CTRL1_0 0x00000D0 58 #define CS530X_OUT_VOL_CTRL1_1 0x00000D2 59 #define CS530X_OUT_VOL_CTRL2_0 0x00000D4 60 #define CS530X_OUT_VOL_CTRL2_1 0x00000D6 61 #define CS530X_OUT_VOL_CTRL3_0 0x00000D8 62 #define CS530X_OUT_VOL_CTRL3_1 0x00000DA 63 #define CS530X_OUT_VOL_CTRL4_0 0x00000DC 64 #define CS530X_OUT_VOL_CTRL4_1 0x00000DE 65 #define CS530X_OUT_VOL_CTRL5 0x00000E0 66 67 #define CS530X_PAD_FN 0x0003D24 68 #define CS530X_PAD_LVL 0x0003D28 69 70 #define CS530X_MAX_REGISTER CS530X_PAD_LVL 71 72 /* Register Fields */ 73 74 /* REVID */ 75 #define CS530X_MTLREVID GENMASK(3, 0) 76 #define CS530X_AREVID GENMASK(7, 4) 77 78 /* SW_RESET */ 79 #define CS530X_SW_RST_SHIFT 8 80 #define CS530X_SW_RST_VAL (0x5A << CS530X_SW_RST_SHIFT) 81 82 /* CLK_CFG_0 */ 83 #define CS530X_PLL_REFCLK_SRC_MASK BIT(0) 84 #define CS530X_PLL_REFCLK_FREQ_MASK GENMASK(5, 4) 85 #define CS530X_SYSCLK_SRC_MASK BIT(12) 86 #define CS530X_SYSCLK_SRC_SHIFT 12 87 #define CS530X_REFCLK_2P822_3P072 0 88 #define CS530X_REFCLK_5P6448_6P144 0x10 89 #define CS530X_REFCLK_11P2896_12P288 0x20 90 #define CS530X_REFCLK_24P5792_24P576 0x30 91 92 /* CLK_CFG_1 */ 93 #define CS530X_SAMPLE_RATE_MASK GENMASK(2, 0) 94 #define CS530X_FS_32K 0 95 #define CS530X_FS_44P1K_48K 1 96 #define CS530X_FS_88P2K_96K 2 97 #define CS530X_FS_176P4K_192K 3 98 #define CS530X_FS_356P8K_384K 4 99 #define CS530X_FS_705P6K_768K 5 100 101 /* CHIP_ENABLE */ 102 #define CS530X_GLOBAL_EN BIT(0) 103 104 /* ASP_CFG */ 105 #define CS530X_ASP_BCLK_FREQ_MASK GENMASK(1, 0) 106 #define CS530X_ASP_PRIMARY BIT(5) 107 #define CS530X_ASP_BCLK_INV BIT(6) 108 #define CS530X_BCLK_2P822_3P072 0 109 #define CS530X_BCLK_5P6448_6P144 1 110 #define CS530X_BCLK_11P2896_12P288 2 111 #define CS530X_BCLK_24P5792_24P576 3 112 113 /* SIGNAL_PATH_CFG */ 114 #define CS530X_ASP_FMT_MASK GENMASK(2, 0) 115 #define CS530X_ASP_TDM_SLOT_MASK GENMASK(5, 3) 116 #define CS530X_ASP_TDM_SLOT_SHIFT 3 117 #define CS530X_ASP_CH_REVERSE BIT(9) 118 #define CS530X_TDM_EN_MASK BIT(2) 119 #define CS530X_ASP_FMT_I2S 0 120 #define CS530X_ASP_FMT_LJ 1 121 #define CS530X_ASP_FMT_DSP_A 6 122 123 /* TDM Slots */ 124 #define CS530X_0_1_TDM_SLOT_MASK GENMASK(1, 0) 125 #define CS530X_0_3_TDM_SLOT_MASK GENMASK(3, 0) 126 #define CS530X_0_7_TDM_SLOT_MASK GENMASK(7, 0) 127 #define CS530X_0_7_TDM_SLOT_VAL 0 128 129 #define CS530X_2_3_TDM_SLOT_MASK GENMASK(3, 2) 130 #define CS530X_2_3_TDM_SLOT_VAL 1 131 132 #define CS530X_4_5_TDM_SLOT_MASK GENMASK(5, 4) 133 #define CS530X_4_7_TDM_SLOT_MASK GENMASK(7, 4) 134 #define CS530X_4_7_TDM_SLOT_VAL 2 135 136 #define CS530X_6_7_TDM_SLOT_MASK GENMASK(7, 6) 137 #define CS530X_6_7_TDM_SLOT_VAL 3 138 139 #define CS530X_8_9_TDM_SLOT_MASK GENMASK(9, 8) 140 #define CS530X_8_11_TDM_SLOT_MASK GENMASK(11, 8) 141 #define CS530X_8_15_TDM_SLOT_MASK GENMASK(15, 8) 142 #define CS530X_8_15_TDM_SLOT_VAL 4 143 144 #define CS530X_10_11_TDM_SLOT_MASK GENMASK(11, 10) 145 #define CS530X_10_11_TDM_SLOT_VAL 5 146 147 #define CS530X_12_13_TDM_SLOT_MASK GENMASK(13, 12) 148 #define CS530X_12_15_TDM_SLOT_MASK GENMASK(15, 12) 149 #define CS530X_12_15_TDM_SLOT_VAL 6 150 151 #define CS530X_14_15_TDM_SLOT_MASK GENMASK(15, 14) 152 #define CS530X_14_15_TDM_SLOT_VAL 7 153 154 /* IN_RAMP_SUM and OUT_RAMP_SUM */ 155 #define CS530X_RAMP_RATE_INC_SHIFT 0 156 #define CS530X_RAMP_RATE_DEC_SHIFT 4 157 #define CS530X_INOUT_SUM_MODE_SHIFT 13 158 159 /* IN_FILTER and OUT_FILTER */ 160 #define CS530X_INOUT_FILTER_SHIFT 8 161 #define CS530X_INOUT_HPF_EN_SHIFT 12 162 163 /* IN_HIZ */ 164 #define CS530X_IN12_HIZ BIT(0) 165 #define CS530X_IN34_HIZ BIT(1) 166 #define CS530X_IN56_HIZ BIT(2) 167 #define CS530X_IN78_HIZ BIT(3) 168 169 /* IN_INV and OUT_INV */ 170 #define CS530X_INOUT1_INV_SHIFT 0 171 #define CS530X_INOUT2_INV_SHIFT 1 172 #define CS530X_INOUT3_INV_SHIFT 2 173 #define CS530X_INOUT4_INV_SHIFT 3 174 #define CS530X_INOUT5_INV_SHIFT 4 175 #define CS530X_INOUT6_INV_SHIFT 5 176 #define CS530X_INOUT7_INV_SHIFT 6 177 #define CS530X_INOUT8_INV_SHIFT 7 178 179 /* IN_VOL_CTLy_z and OUT_VOL_CTLy_z */ 180 #define CS530X_INOUT_MUTE BIT(15) 181 182 /* IN_VOL_CTL5 */ 183 #define CS530X_IN_VU BIT(0) 184 185 /* PAD_FN */ 186 #define CS530X_DOUT2_FN BIT(0) 187 #define CS530X_DOUT3_FN BIT(1) 188 #define CS530X_DOUT4_FN BIT(2) 189 #define CS530X_SPI_CS_FN BIT(3) 190 #define CS530X_CONFIG2_FN BIT(6) 191 #define CS530X_CONFIG3_FN BIT(7) 192 #define CS530X_CONFIG4_FN BIT(8) 193 #define CS530X_CONFIG5_FN BIT(9) 194 195 /* PAD_LVL */ 196 #define CS530X_CONFIG2_LVL BIT(6) 197 #define CS530X_CONFIG3_LVL BIT(7) 198 #define CS530X_CONFIG4_LVL BIT(8) 199 #define CS530X_CONFIG5_LVL BIT(9) 200 /* IN_VOL_CTL5 and OUT_VOL_CTL5 */ 201 #define CS530X_INOUT_VU BIT(0) 202 203 /* MCLK Reference Source Frequency */ 204 /* 41KHz related */ 205 #define CS530X_SYSCLK_REF_45_1MHZ 45158400 206 /* 48KHz related */ 207 #define CS530X_SYSCLK_REF_49_1MHZ 49152000 208 209 /* System Clock Source */ 210 #define CS530X_SYSCLK_SRC_MCLK 0 211 #define CS530X_SYSCLK_SRC_PLL 1 212 213 /* PLL Reference Clock Source */ 214 #define CS530X_PLL_SRC_BCLK 0 215 #define CS530X_PLL_SRC_MCLK 1 216 217 #define CS530X_NUM_SUPPLIES 2 218 219 enum cs530x_type { 220 CS4282 = CS530X_2CH_CODEC_DEV_ID, 221 CS4302 = CS530X_2CH_DAC_DEV_ID, 222 CS4304 = CS530X_4CH_DAC_DEV_ID, 223 CS4308 = CS530X_8CH_DAC_DEV_ID, 224 CS5302 = CS530X_2CH_ADC_DEV_ID, 225 CS5304 = CS530X_4CH_ADC_DEV_ID, 226 CS5308 = CS530X_8CH_ADC_DEV_ID, 227 }; 228 229 /* codec private data */ 230 struct cs530x_priv { 231 struct regmap *regmap; 232 struct device *dev; 233 struct snd_soc_dai_driver *dev_dai; 234 235 enum cs530x_type devtype; 236 int num_adcs; 237 int num_dacs; 238 239 struct regulator_bulk_data supplies[CS530X_NUM_SUPPLIES]; 240 241 int tdm_width; 242 int tdm_slots; 243 int adc_pairs_count; 244 int dac_pairs_count; 245 246 struct gpio_desc *reset_gpio; 247 }; 248 249 extern const struct regmap_config cs530x_regmap_i2c; 250 extern const struct regmap_config cs530x_regmap_spi; 251 int cs530x_probe(struct cs530x_priv *cs530x); 252 253 #endif 254