1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #ifndef AIROHA_ETH_H 8 #define AIROHA_ETH_H 9 10 #include <linux/debugfs.h> 11 #include <linux/etherdevice.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/reset.h> 16 #include <linux/soc/airoha/airoha_offload.h> 17 #include <net/dsa.h> 18 19 #define AIROHA_MAX_NUM_GDM_PORTS 4 20 #define AIROHA_MAX_NUM_GDM_DEVS 2 21 #define AIROHA_MAX_NUM_QDMA 2 22 #define AIROHA_MAX_NUM_IRQ_BANKS 4 23 #define AIROHA_MAX_DSA_PORTS 7 24 #define AIROHA_MAX_NUM_RSTS 3 25 #define AIROHA_MAX_MTU 9220 26 #define AIROHA_MAX_PACKET_SIZE 2048 27 #define AIROHA_NUM_QOS_CHANNELS 4 28 #define AIROHA_NUM_QOS_QUEUES 8 29 #define AIROHA_NUM_TX_RING 32 30 #define AIROHA_NUM_RX_RING 32 31 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \ 32 AIROHA_NUM_QOS_CHANNELS) 33 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64 34 #define AIROHA_FE_MC_MAX_VLAN_PORT 16 35 #define AIROHA_NUM_TX_IRQ 2 36 #define AIROHA_RX_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) 37 #define AIROHA_RX_LEN(_n) ((_n) - AIROHA_RX_HEADROOM) 38 #define HW_DSCP_NUM 2048 39 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048) 40 #define TX_DSCP_NUM 1024 41 #define RX_DSCP_NUM(_n) \ 42 ((_n) == 2 ? 128 : \ 43 (_n) == 11 ? 128 : \ 44 (_n) == 15 ? 128 : \ 45 (_n) == 0 ? 1024 : 16) 46 47 #define PSE_RSV_PAGES 128 48 #define PSE_QUEUE_RSV_PAGES 64 49 50 #define QDMA_METER_IDX(_n) ((_n) & 0xff) 51 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3) 52 53 #define PPE_SRAM_NUM_ENTRIES (8 * 1024) 54 #define PPE_STATS_NUM_ENTRIES (4 * 1024) 55 #define PPE_DRAM_NUM_ENTRIES (16 * 1024) 56 #define PPE_ENTRY_SIZE 80 57 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10)) 58 59 #define MTK_HDR_LEN 4 60 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1 61 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2 62 63 enum { 64 QDMA_INT_REG_IDX0, 65 QDMA_INT_REG_IDX1, 66 QDMA_INT_REG_IDX2, 67 QDMA_INT_REG_IDX3, 68 QDMA_INT_REG_IDX4, 69 QDMA_INT_REG_MAX 70 }; 71 72 enum { 73 HSGMII_LAN_7581_PCIE0_SRCPORT = 0x16, 74 HSGMII_LAN_7581_PCIE1_SRCPORT, 75 HSGMII_LAN_7581_ETH_SRCPORT, 76 HSGMII_LAN_7581_USB_SRCPORT, 77 }; 78 79 enum { 80 HSGMII_LAN_7583_ETH_SRCPORT = 0x16, 81 HSGMII_LAN_7583_PCIE_SRCPORT = 0x18, 82 HSGMII_LAN_7583_USB_SRCPORT, 83 }; 84 85 enum { 86 XSI_PCIE0_VIP_PORT_MASK = BIT(22), 87 XSI_PCIE1_VIP_PORT_MASK = BIT(23), 88 XSI_USB_VIP_PORT_MASK = BIT(25), 89 XSI_ETH_VIP_PORT_MASK = BIT(24), 90 }; 91 92 enum { 93 DEV_STATE_INITIALIZED, 94 DEV_STATE_REGISTERED, 95 }; 96 97 enum { 98 CDM_CRSN_QSEL_Q1 = 1, 99 CDM_CRSN_QSEL_Q5 = 5, 100 CDM_CRSN_QSEL_Q6 = 6, 101 CDM_CRSN_QSEL_Q15 = 15, 102 }; 103 104 enum { 105 CRSN_08 = 0x8, 106 CRSN_21 = 0x15, /* KA */ 107 CRSN_22 = 0x16, /* hit bind and force route to CPU */ 108 CRSN_24 = 0x18, 109 CRSN_25 = 0x19, 110 }; 111 112 enum airoha_gdm_index { 113 AIROHA_GDM1_IDX = 1, 114 AIROHA_GDM2_IDX = 2, 115 AIROHA_GDM3_IDX = 3, 116 AIROHA_GDM4_IDX = 4, 117 }; 118 119 enum { 120 FE_PSE_PORT_CDM1, 121 FE_PSE_PORT_GDM1, 122 FE_PSE_PORT_GDM2, 123 FE_PSE_PORT_GDM3, 124 FE_PSE_PORT_PPE1, 125 FE_PSE_PORT_CDM2, 126 FE_PSE_PORT_CDM3, 127 FE_PSE_PORT_CDM4, 128 FE_PSE_PORT_PPE2, 129 FE_PSE_PORT_GDM4, 130 FE_PSE_PORT_CDM5, 131 FE_PSE_PORT_DROP = 0xf, 132 }; 133 134 enum tx_sched_mode { 135 TC_SCH_WRR8, 136 TC_SCH_SP, 137 TC_SCH_WRR7, 138 TC_SCH_WRR6, 139 TC_SCH_WRR5, 140 TC_SCH_WRR4, 141 TC_SCH_WRR3, 142 TC_SCH_WRR2, 143 }; 144 145 enum trtcm_unit_type { 146 TRTCM_BYTE_UNIT, 147 TRTCM_PACKET_UNIT, 148 }; 149 150 enum trtcm_param_type { 151 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */ 152 TRTCM_TOKEN_RATE_MODE, 153 TRTCM_BUCKETSIZE_SHIFT_MODE, 154 TRTCM_BUCKET_COUNTER_MODE, 155 }; 156 157 enum trtcm_mode_type { 158 TRTCM_COMMIT_MODE, 159 TRTCM_PEAK_MODE, 160 }; 161 162 enum trtcm_param { 163 TRTCM_TICK_SEL = BIT(0), 164 TRTCM_PKT_MODE = BIT(1), 165 TRTCM_METER_MODE = BIT(2), 166 }; 167 168 #define MIN_TOKEN_SIZE 4096 169 #define MAX_TOKEN_SIZE_OFFSET 17 170 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6) 171 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0) 172 173 struct airoha_queue_entry { 174 union { 175 void *buf; 176 struct { 177 struct list_head list; 178 struct sk_buff *skb; 179 }; 180 }; 181 dma_addr_t dma_addr; 182 u16 dma_len; 183 }; 184 185 struct airoha_queue { 186 struct airoha_qdma *qdma; 187 188 /* protect concurrent queue accesses */ 189 spinlock_t lock; 190 struct airoha_queue_entry *entry; 191 struct airoha_qdma_desc *desc; 192 u16 head; 193 u16 tail; 194 195 int queued; 196 int ndesc; 197 int free_thr; 198 int buf_size; 199 bool txq_stopped; 200 201 struct napi_struct napi; 202 struct page_pool *page_pool; 203 struct sk_buff *skb; 204 205 struct list_head tx_list; 206 }; 207 208 struct airoha_tx_irq_queue { 209 struct airoha_qdma *qdma; 210 211 struct napi_struct napi; 212 213 int size; 214 u32 *q; 215 }; 216 217 struct airoha_hw_stats { 218 struct u64_stats_sync syncp; 219 220 /* get_stats64 */ 221 u64 rx_ok_pkts; 222 u64 tx_ok_pkts; 223 u64 rx_ok_bytes; 224 u64 tx_ok_bytes; 225 u64 rx_multicast; 226 u64 rx_errors; 227 u64 rx_drops; 228 u64 tx_drops; 229 u64 rx_crc_error; 230 u64 rx_over_errors; 231 /* ethtool stats */ 232 u64 tx_broadcast; 233 u64 tx_multicast; 234 u64 tx_len[7]; 235 u64 rx_broadcast; 236 u64 rx_fragment; 237 u64 rx_jabber; 238 u64 rx_len[7]; 239 }; 240 241 enum { 242 AIROHA_FOE_STATE_INVALID, 243 AIROHA_FOE_STATE_UNBIND, 244 AIROHA_FOE_STATE_BIND, 245 AIROHA_FOE_STATE_FIN 246 }; 247 248 enum { 249 PPE_PKT_TYPE_IPV4_HNAPT = 0, 250 PPE_PKT_TYPE_IPV4_ROUTE = 1, 251 PPE_PKT_TYPE_BRIDGE = 2, 252 PPE_PKT_TYPE_IPV4_DSLITE = 3, 253 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4, 254 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5, 255 PPE_PKT_TYPE_IPV6_6RD = 7, 256 }; 257 258 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16) 259 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0) 260 261 #define AIROHA_FOE_MAC_WDMA_QOS GENMASK(15, 12) 262 #define AIROHA_FOE_MAC_WDMA_BAND BIT(11) 263 #define AIROHA_FOE_MAC_WDMA_WCID GENMASK(10, 0) 264 265 struct airoha_foe_mac_info_common { 266 u16 vlan1; 267 u16 etype; 268 269 u32 dest_mac_hi; 270 271 u16 vlan2; 272 u16 dest_mac_lo; 273 274 u32 src_mac_hi; 275 }; 276 277 struct airoha_foe_mac_info { 278 struct airoha_foe_mac_info_common common; 279 280 u16 pppoe_id; 281 u16 src_mac_lo; 282 283 u32 meter; 284 }; 285 286 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24) 287 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) 288 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) 289 290 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31) 291 #define AIROHA_FOE_IB1_BIND_UDP BIT(30) 292 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28) 293 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25) 294 #define AIROHA_FOE_IB1_BIND_TTL BIT(24) 295 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) 296 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22) 297 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20) 298 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16) 299 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15) 300 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) 301 302 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24) 303 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13) 304 #define AIROHA_FOE_IB2_PCP BIT(12) 305 #define AIROHA_FOE_IB2_MULTICAST BIT(11) 306 #define AIROHA_FOE_IB2_FAST_PATH BIT(10) 307 #define AIROHA_FOE_IB2_PSE_QOS BIT(9) 308 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5) 309 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0) 310 311 #define AIROHA_FOE_ACTDP GENMASK(31, 24) 312 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16) 313 #define AIROHA_FOE_CHANNEL GENMASK(15, 11) 314 #define AIROHA_FOE_QID GENMASK(10, 8) 315 #define AIROHA_FOE_DPI BIT(7) 316 #define AIROHA_FOE_TUNNEL BIT(6) 317 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0) 318 319 #define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16) 320 #define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9) 321 #define AIROHA_FOE_METER_GRP3 GENMASK(8, 5) 322 #define AIROHA_FOE_METER_GRP2 GENMASK(4, 0) 323 324 struct airoha_foe_bridge { 325 u32 dest_mac_hi; 326 327 u16 src_mac_hi; 328 u16 dest_mac_lo; 329 330 u32 src_mac_lo; 331 332 u32 ib2; 333 334 u32 rsv[5]; 335 336 u32 data; 337 338 struct airoha_foe_mac_info l2; 339 }; 340 341 struct airoha_foe_ipv4_tuple { 342 u32 src_ip; 343 u32 dest_ip; 344 union { 345 struct { 346 u16 dest_port; 347 u16 src_port; 348 }; 349 struct { 350 u8 protocol; 351 u8 _pad[3]; /* fill with 0xa5a5a5 */ 352 }; 353 u32 ports; 354 }; 355 }; 356 357 struct airoha_foe_ipv4 { 358 struct airoha_foe_ipv4_tuple orig_tuple; 359 360 u32 ib2; 361 362 struct airoha_foe_ipv4_tuple new_tuple; 363 364 u32 rsv[2]; 365 366 u32 data; 367 368 struct airoha_foe_mac_info l2; 369 }; 370 371 struct airoha_foe_ipv4_dslite { 372 struct airoha_foe_ipv4_tuple ip4; 373 374 u32 ib2; 375 376 u8 flow_label[3]; 377 u8 priority; 378 379 u32 rsv[4]; 380 381 u32 data; 382 383 struct airoha_foe_mac_info l2; 384 }; 385 386 struct airoha_foe_ipv6 { 387 u32 src_ip[4]; 388 u32 dest_ip[4]; 389 390 union { 391 struct { 392 u16 dest_port; 393 u16 src_port; 394 }; 395 struct { 396 u8 protocol; 397 u8 pad[3]; 398 }; 399 u32 ports; 400 }; 401 402 u32 data; 403 404 u32 ib2; 405 406 struct airoha_foe_mac_info_common l2; 407 408 u32 meter; 409 }; 410 411 struct airoha_foe_entry { 412 union { 413 struct { 414 u32 ib1; 415 union { 416 struct airoha_foe_bridge bridge; 417 struct airoha_foe_ipv4 ipv4; 418 struct airoha_foe_ipv4_dslite dslite; 419 struct airoha_foe_ipv6 ipv6; 420 DECLARE_FLEX_ARRAY(u32, d); 421 }; 422 }; 423 u8 data[PPE_ENTRY_SIZE]; 424 }; 425 }; 426 427 struct airoha_foe_stats { 428 u32 bytes; 429 u32 packets; 430 }; 431 432 struct airoha_foe_stats64 { 433 u64 bytes; 434 u64 packets; 435 }; 436 437 struct airoha_flow_data { 438 struct ethhdr eth; 439 440 union { 441 struct { 442 __be32 src_addr; 443 __be32 dst_addr; 444 } v4; 445 446 struct { 447 struct in6_addr src_addr; 448 struct in6_addr dst_addr; 449 } v6; 450 }; 451 452 __be16 src_port; 453 __be16 dst_port; 454 455 struct { 456 struct { 457 u16 id; 458 __be16 proto; 459 } hdr[2]; 460 u8 num; 461 } vlan; 462 struct { 463 u16 sid; 464 u8 num; 465 } pppoe; 466 }; 467 468 enum airoha_flow_entry_type { 469 FLOW_TYPE_L4, 470 FLOW_TYPE_L2, 471 FLOW_TYPE_L2_SUBFLOW, 472 }; 473 474 struct airoha_flow_table_entry { 475 union { 476 struct hlist_node list; /* PPE L3 flow entry */ 477 struct { 478 struct rhash_head l2_node; /* L2 flow entry */ 479 struct hlist_head l2_flows; /* PPE L2 subflows list */ 480 }; 481 }; 482 483 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */ 484 u32 hash; 485 486 struct airoha_foe_stats64 stats; 487 enum airoha_flow_entry_type type; 488 489 struct rhash_head node; 490 unsigned long cookie; 491 492 /* Must be last --ends in a flexible-array member. */ 493 struct airoha_foe_entry data; 494 }; 495 496 struct airoha_wdma_info { 497 u8 idx; 498 u8 queue; 499 u16 wcid; 500 u8 bss; 501 }; 502 503 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */ 504 #define RX_IRQ0_BANK_PIN_MASK 0x839f 505 #define RX_IRQ1_BANK_PIN_MASK 0x7fe00000 506 #define RX_IRQ2_BANK_PIN_MASK 0x20 507 #define RX_IRQ3_BANK_PIN_MASK 0x40 508 #define RX_IRQ_BANK_PIN_MASK(_n) \ 509 (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \ 510 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \ 511 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \ 512 RX_IRQ0_BANK_PIN_MASK) 513 514 struct airoha_irq_bank { 515 struct airoha_qdma *qdma; 516 517 /* protect concurrent irqmask accesses */ 518 spinlock_t irq_lock; 519 u32 irqmask[QDMA_INT_REG_MAX]; 520 int irq; 521 }; 522 523 struct airoha_qdma { 524 struct airoha_eth *eth; 525 void __iomem *regs; 526 527 int users; 528 529 struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS]; 530 531 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; 532 533 struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; 534 struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; 535 536 DECLARE_BITMAP(qos_channel_map, AIROHA_NUM_QOS_CHANNELS); 537 }; 538 539 enum airoha_priv_flags { 540 AIROHA_PRIV_F_WAN = BIT(0), 541 }; 542 543 struct airoha_gdm_dev { 544 struct airoha_gdm_port *port; 545 struct airoha_qdma *qdma; 546 struct airoha_eth *eth; 547 548 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS); 549 /* qos stats counters */ 550 u64 cpu_tx_packets; 551 u64 fwd_tx_packets; 552 553 u32 flags; 554 int nbq; 555 556 struct airoha_hw_stats stats; 557 }; 558 559 struct airoha_gdm_port { 560 struct airoha_gdm_dev *devs[AIROHA_MAX_NUM_GDM_DEVS]; 561 int id; 562 int users; 563 564 /* protect concurrent hw_stats accesses */ 565 spinlock_t stats_lock; 566 567 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; 568 }; 569 570 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16) 571 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0) 572 573 struct airoha_ppe { 574 struct airoha_ppe_dev dev; 575 struct airoha_eth *eth; 576 577 void *foe; 578 dma_addr_t foe_dma; 579 580 struct rhashtable l2_flows; 581 582 struct hlist_head *foe_flow; 583 u16 *foe_check_time; 584 585 struct airoha_foe_stats *foe_stats; 586 dma_addr_t foe_stats_dma; 587 588 struct dentry *debugfs_dir; 589 }; 590 591 struct airoha_eth_soc_data { 592 u16 version; 593 const char * const *xsi_rsts_names; 594 int num_xsi_rsts; 595 int num_ppe; 596 struct { 597 int (*get_sport)(struct airoha_gdm_port *port, int nbq); 598 u32 (*get_vip_port)(struct airoha_gdm_port *port, int nbq); 599 int (*get_dev_from_sport)(struct airoha_qdma_desc *desc, 600 u16 *port, u16 *dev); 601 } ops; 602 }; 603 604 struct airoha_eth { 605 struct device *dev; 606 607 const struct airoha_eth_soc_data *soc; 608 609 unsigned long state; 610 void __iomem *fe_regs; 611 612 struct airoha_npu __rcu *npu; 613 614 struct airoha_ppe *ppe; 615 struct rhashtable flow_table; 616 617 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS]; 618 struct reset_control_bulk_data *xsi_rsts; 619 620 struct net_device *napi_dev; 621 622 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; 623 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; 624 }; 625 626 u32 airoha_rr(void __iomem *base, u32 offset); 627 void airoha_wr(void __iomem *base, u32 offset, u32 val); 628 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); 629 630 #define airoha_fe_rr(eth, offset) \ 631 airoha_rr((eth)->fe_regs, (offset)) 632 #define airoha_fe_wr(eth, offset, val) \ 633 airoha_wr((eth)->fe_regs, (offset), (val)) 634 #define airoha_fe_rmw(eth, offset, mask, val) \ 635 airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) 636 #define airoha_fe_set(eth, offset, val) \ 637 airoha_rmw((eth)->fe_regs, (offset), 0, (val)) 638 #define airoha_fe_clear(eth, offset, val) \ 639 airoha_rmw((eth)->fe_regs, (offset), (val), 0) 640 #define airoha_fe_get(eth, offset, mask) \ 641 FIELD_GET((mask), airoha_fe_rr((eth), (offset))) 642 643 #define airoha_qdma_rr(qdma, offset) \ 644 airoha_rr((qdma)->regs, (offset)) 645 #define airoha_qdma_wr(qdma, offset, val) \ 646 airoha_wr((qdma)->regs, (offset), (val)) 647 #define airoha_qdma_rmw(qdma, offset, mask, val) \ 648 airoha_rmw((qdma)->regs, (offset), (mask), (val)) 649 #define airoha_qdma_set(qdma, offset, val) \ 650 airoha_rmw((qdma)->regs, (offset), 0, (val)) 651 #define airoha_qdma_clear(qdma, offset, val) \ 652 airoha_rmw((qdma)->regs, (offset), (val), 0) 653 #define airoha_qdma_get(qdma, offset, mask) \ 654 FIELD_GET((mask), airoha_qdma_rr((qdma), (offset))) 655 656 static inline u16 airoha_qdma_get_txq(struct airoha_qdma *qdma, u16 qid) 657 { 658 return qid % ARRAY_SIZE(qdma->q_tx); 659 } 660 661 static inline bool airoha_is_lan_gdm_dev(struct airoha_gdm_dev *dev) 662 { 663 return !(dev->flags & AIROHA_PRIV_F_WAN); 664 } 665 666 static inline bool airoha_is_7581(struct airoha_eth *eth) 667 { 668 return eth->soc->version == 0x7581; 669 } 670 671 static inline bool airoha_is_7583(struct airoha_eth *eth) 672 { 673 return eth->soc->version == 0x7583; 674 } 675 676 int airoha_get_fe_port(struct airoha_gdm_dev *dev); 677 bool airoha_is_valid_gdm_dev(struct airoha_eth *eth, 678 struct airoha_gdm_dev *dev); 679 680 void airoha_ppe_set_cpu_port(struct airoha_gdm_dev *dev, u8 ppe_id, u8 fport); 681 bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index); 682 void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb, 683 u16 hash, bool rx_wlan); 684 int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data); 685 int airoha_ppe_init(struct airoha_eth *eth); 686 void airoha_ppe_deinit(struct airoha_eth *eth); 687 void airoha_ppe_init_upd_mem(struct airoha_gdm_dev *dev, const u8 *addr); 688 u32 airoha_ppe_get_total_num_entries(struct airoha_ppe *ppe); 689 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe, 690 u32 hash); 691 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash, 692 struct airoha_foe_stats64 *stats); 693 694 #ifdef CONFIG_DEBUG_FS 695 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe); 696 #else 697 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe) 698 { 699 return 0; 700 } 701 #endif 702 703 #endif /* AIROHA_ETH_H */ 704