1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Intel IXP4xx PCI host controller 4 * 5 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 6 * 7 * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver 8 * Copyright (C) 2002 Intel Corporation 9 * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org> 10 * Copyright (C) 2003-2004 MontaVista Software, Inc. 11 * Copyright (C) 2005 Deepak Saxena <dsaxena@plexity.net> 12 * Copyright (C) 2005 Alessandro Zummo <a.zummo@towertech.it> 13 * 14 * TODO: 15 * - Test IO-space access 16 * - DMA support 17 */ 18 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/of.h> 23 #include <linux/of_pci.h> 24 #include <linux/pci.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include <linux/bits.h> 28 #include "../pci.h" 29 30 /* Register offsets */ 31 #define IXP4XX_PCI_NP_AD 0x00 32 #define IXP4XX_PCI_NP_CBE 0x04 33 #define IXP4XX_PCI_NP_WDATA 0x08 34 #define IXP4XX_PCI_NP_RDATA 0x0c 35 #define IXP4XX_PCI_CRP_AD_CBE 0x10 36 #define IXP4XX_PCI_CRP_WDATA 0x14 37 #define IXP4XX_PCI_CRP_RDATA 0x18 38 #define IXP4XX_PCI_CSR 0x1c 39 #define IXP4XX_PCI_ISR 0x20 40 #define IXP4XX_PCI_INTEN 0x24 41 #define IXP4XX_PCI_DMACTRL 0x28 42 #define IXP4XX_PCI_AHBMEMBASE 0x2c 43 #define IXP4XX_PCI_AHBIOBASE 0x30 44 #define IXP4XX_PCI_PCIMEMBASE 0x34 45 #define IXP4XX_PCI_AHBDOORBELL 0x38 46 #define IXP4XX_PCI_PCIDOORBELL 0x3c 47 #define IXP4XX_PCI_ATPDMA0_AHBADDR 0x40 48 #define IXP4XX_PCI_ATPDMA0_PCIADDR 0x44 49 #define IXP4XX_PCI_ATPDMA0_LENADDR 0x48 50 #define IXP4XX_PCI_ATPDMA1_AHBADDR 0x4c 51 #define IXP4XX_PCI_ATPDMA1_PCIADDR 0x50 52 #define IXP4XX_PCI_ATPDMA1_LENADDR 0x54 53 54 /* CSR bit definitions */ 55 #define IXP4XX_PCI_CSR_HOST BIT(0) 56 #define IXP4XX_PCI_CSR_ARBEN BIT(1) 57 #define IXP4XX_PCI_CSR_ADS BIT(2) 58 #define IXP4XX_PCI_CSR_PDS BIT(3) 59 #define IXP4XX_PCI_CSR_ABE BIT(4) 60 #define IXP4XX_PCI_CSR_DBT BIT(5) 61 #define IXP4XX_PCI_CSR_ASE BIT(8) 62 #define IXP4XX_PCI_CSR_IC BIT(15) 63 #define IXP4XX_PCI_CSR_PRST BIT(16) 64 65 /* ISR (Interrupt status) Register bit definitions */ 66 #define IXP4XX_PCI_ISR_PSE BIT(0) 67 #define IXP4XX_PCI_ISR_PFE BIT(1) 68 #define IXP4XX_PCI_ISR_PPE BIT(2) 69 #define IXP4XX_PCI_ISR_AHBE BIT(3) 70 #define IXP4XX_PCI_ISR_APDC BIT(4) 71 #define IXP4XX_PCI_ISR_PADC BIT(5) 72 #define IXP4XX_PCI_ISR_ADB BIT(6) 73 #define IXP4XX_PCI_ISR_PDB BIT(7) 74 75 /* INTEN (Interrupt Enable) Register bit definitions */ 76 #define IXP4XX_PCI_INTEN_PSE BIT(0) 77 #define IXP4XX_PCI_INTEN_PFE BIT(1) 78 #define IXP4XX_PCI_INTEN_PPE BIT(2) 79 #define IXP4XX_PCI_INTEN_AHBE BIT(3) 80 #define IXP4XX_PCI_INTEN_APDC BIT(4) 81 #define IXP4XX_PCI_INTEN_PADC BIT(5) 82 #define IXP4XX_PCI_INTEN_ADB BIT(6) 83 #define IXP4XX_PCI_INTEN_PDB BIT(7) 84 85 /* Shift value for byte enable on NP cmd/byte enable register */ 86 #define IXP4XX_PCI_NP_CBE_BESL 4 87 88 /* PCI commands supported by NP access unit */ 89 #define NP_CMD_IOREAD 0x2 90 #define NP_CMD_IOWRITE 0x3 91 #define NP_CMD_CONFIGREAD 0xa 92 #define NP_CMD_CONFIGWRITE 0xb 93 #define NP_CMD_MEMREAD 0x6 94 #define NP_CMD_MEMWRITE 0x7 95 96 /* Constants for CRP access into local config space */ 97 #define CRP_AD_CBE_BESL 20 98 #define CRP_AD_CBE_WRITE 0x00010000 99 100 /* Special PCI configuration space registers for this controller */ 101 #define IXP4XX_PCI_RTOTTO 0x40 102 103 struct ixp4xx_pci { 104 struct device *dev; 105 void __iomem *base; 106 bool errata_hammer; 107 bool host_mode; 108 }; 109 110 /* 111 * The IXP4xx has a peculiar address bus that will change the 112 * byte order on SoC peripherals depending on whether the device 113 * operates in big-endian or little-endian mode. That means that 114 * readl() and writel() that always use little-endian access 115 * will not work for SoC peripherals such as the PCI controller 116 * when used in big-endian mode. The accesses to the individual 117 * PCI devices on the other hand, are always little-endian and 118 * can use readl() and writel(). 119 * 120 * For local AHB bus access we need to use __raw_[readl|writel]() 121 * to make sure that we access the SoC devices in the CPU native 122 * endianness. 123 */ 124 static inline u32 ixp4xx_readl(struct ixp4xx_pci *p, u32 reg) 125 { 126 return __raw_readl(p->base + reg); 127 } 128 129 static inline void ixp4xx_writel(struct ixp4xx_pci *p, u32 reg, u32 val) 130 { 131 __raw_writel(val, p->base + reg); 132 } 133 134 static int ixp4xx_pci_check_master_abort(struct ixp4xx_pci *p) 135 { 136 u32 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); 137 138 if (isr & IXP4XX_PCI_ISR_PFE) { 139 /* Make sure the master abort bit is reset */ 140 ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); 141 dev_dbg(p->dev, "master abort detected\n"); 142 return -EINVAL; 143 } 144 145 return 0; 146 } 147 148 static int ixp4xx_pci_read_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data) 149 { 150 ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); 151 152 if (p->errata_hammer) { 153 int i; 154 155 /* 156 * PCI workaround - only works if NP PCI space reads have 157 * no side effects. Hammer the register and read twice 8 158 * times. last one will be good. 159 */ 160 for (i = 0; i < 8; i++) { 161 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); 162 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); 163 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); 164 } 165 } else { 166 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); 167 *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); 168 } 169 170 return ixp4xx_pci_check_master_abort(p); 171 } 172 173 static int ixp4xx_pci_write_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data) 174 { 175 ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); 176 177 /* Set up the write */ 178 ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); 179 180 /* Execute the write by writing to NP_WDATA */ 181 ixp4xx_writel(p, IXP4XX_PCI_NP_WDATA, data); 182 183 return ixp4xx_pci_check_master_abort(p); 184 } 185 186 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) 187 { 188 /* Root bus is always 0 in this hardware */ 189 if (bus_num == 0) { 190 /* type 0 */ 191 return (PCI_CONF1_ADDRESS(0, 0, PCI_FUNC(devfn), where) & 192 ~PCI_CONF1_ENABLE) | BIT(32-PCI_SLOT(devfn)); 193 } else { 194 /* type 1 */ 195 return (PCI_CONF1_ADDRESS(bus_num, PCI_SLOT(devfn), 196 PCI_FUNC(devfn), where) & 197 ~PCI_CONF1_ENABLE) | 1; 198 } 199 } 200 201 /* 202 * CRP functions are "Controller Configuration Port" accesses 203 * initiated from within this driver itself to read/write PCI 204 * control information in the config space. 205 */ 206 static u32 ixp4xx_crp_byte_lane_enable_bits(u32 n, int size) 207 { 208 if (size == 1) 209 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; 210 if (size == 2) 211 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; 212 if (size == 4) 213 return 0; 214 return 0xffffffff; 215 } 216 217 #ifdef CONFIG_ARM 218 static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size, 219 u32 *value) 220 { 221 u32 n, cmd, val; 222 223 n = where % 4; 224 cmd = where & ~3; 225 226 dev_dbg(p->dev, "%s from %d size %d cmd %08x\n", 227 __func__, where, size, cmd); 228 229 ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); 230 val = ixp4xx_readl(p, IXP4XX_PCI_CRP_RDATA); 231 232 val >>= (8*n); 233 switch (size) { 234 case 1: 235 val &= U8_MAX; 236 dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); 237 break; 238 case 2: 239 val &= U16_MAX; 240 dev_dbg(p->dev, "%s read word %04x\n", __func__, val); 241 break; 242 case 4: 243 val &= U32_MAX; 244 dev_dbg(p->dev, "%s read long %08x\n", __func__, val); 245 break; 246 default: 247 /* Should not happen */ 248 dev_err(p->dev, "%s illegal size\n", __func__); 249 return PCIBIOS_DEVICE_NOT_FOUND; 250 } 251 *value = val; 252 253 return PCIBIOS_SUCCESSFUL; 254 } 255 #endif 256 257 static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size, 258 u32 value) 259 { 260 u32 n, cmd, val; 261 262 n = where % 4; 263 cmd = ixp4xx_crp_byte_lane_enable_bits(n, size); 264 if (cmd == 0xffffffff) 265 return PCIBIOS_BAD_REGISTER_NUMBER; 266 cmd |= where & ~3; 267 cmd |= CRP_AD_CBE_WRITE; 268 269 val = value << (8*n); 270 271 dev_dbg(p->dev, "%s to %d size %d cmd %08x val %08x\n", 272 __func__, where, size, cmd, val); 273 274 ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); 275 ixp4xx_writel(p, IXP4XX_PCI_CRP_WDATA, val); 276 277 return PCIBIOS_SUCCESSFUL; 278 } 279 280 /* 281 * Then follows the functions that read and write from the common PCI 282 * configuration space. 283 */ 284 static u32 ixp4xx_byte_lane_enable_bits(u32 n, int size) 285 { 286 if (size == 1) 287 return (0xf & ~BIT(n)) << 4; 288 if (size == 2) 289 return (0xf & ~(BIT(n) | BIT(n+1))) << 4; 290 if (size == 4) 291 return 0; 292 return 0xffffffff; 293 } 294 295 static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, 296 int where, int size, u32 *value) 297 { 298 struct ixp4xx_pci *p = bus->sysdata; 299 u32 n, addr, val, cmd; 300 u8 bus_num = bus->number; 301 int ret; 302 303 *value = 0xffffffff; 304 n = where % 4; 305 cmd = ixp4xx_byte_lane_enable_bits(n, size); 306 if (cmd == 0xffffffff) 307 return PCIBIOS_BAD_REGISTER_NUMBER; 308 309 addr = ixp4xx_config_addr(bus_num, devfn, where); 310 cmd |= NP_CMD_CONFIGREAD; 311 dev_dbg(p->dev, "read_config from %d size %d dev %d:%d:%d address: %08x cmd: %08x\n", 312 where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); 313 314 ret = ixp4xx_pci_read_indirect(p, addr, cmd, &val); 315 if (ret) 316 return PCIBIOS_DEVICE_NOT_FOUND; 317 318 val >>= (8*n); 319 switch (size) { 320 case 1: 321 val &= U8_MAX; 322 dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); 323 break; 324 case 2: 325 val &= U16_MAX; 326 dev_dbg(p->dev, "%s read word %04x\n", __func__, val); 327 break; 328 case 4: 329 val &= U32_MAX; 330 dev_dbg(p->dev, "%s read long %08x\n", __func__, val); 331 break; 332 default: 333 /* Should not happen */ 334 dev_err(p->dev, "%s illegal size\n", __func__); 335 return PCIBIOS_DEVICE_NOT_FOUND; 336 } 337 *value = val; 338 339 return PCIBIOS_SUCCESSFUL; 340 } 341 342 static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, 343 int where, int size, u32 value) 344 { 345 struct ixp4xx_pci *p = bus->sysdata; 346 u32 n, addr, val, cmd; 347 u8 bus_num = bus->number; 348 int ret; 349 350 n = where % 4; 351 cmd = ixp4xx_byte_lane_enable_bits(n, size); 352 if (cmd == 0xffffffff) 353 return PCIBIOS_BAD_REGISTER_NUMBER; 354 355 addr = ixp4xx_config_addr(bus_num, devfn, where); 356 cmd |= NP_CMD_CONFIGWRITE; 357 val = value << (8*n); 358 359 dev_dbg(p->dev, "write_config_byte %#x to %d size %d dev %d:%d:%d addr: %08x cmd %08x\n", 360 value, where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); 361 362 ret = ixp4xx_pci_write_indirect(p, addr, cmd, val); 363 if (ret) 364 return PCIBIOS_DEVICE_NOT_FOUND; 365 366 return PCIBIOS_SUCCESSFUL; 367 } 368 369 static struct pci_ops ixp4xx_pci_ops = { 370 .read = ixp4xx_pci_read_config, 371 .write = ixp4xx_pci_write_config, 372 }; 373 374 static u32 ixp4xx_pci_addr_to_64mconf(phys_addr_t addr) 375 { 376 u8 base; 377 378 base = ((addr & 0xff000000) >> 24); 379 return (base << 24) | ((base + 1) << 16) 380 | ((base + 2) << 8) | (base + 3); 381 } 382 383 static int ixp4xx_pci_parse_map_ranges(struct ixp4xx_pci *p) 384 { 385 struct device *dev = p->dev; 386 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); 387 struct resource_entry *win; 388 struct resource *res; 389 phys_addr_t addr; 390 391 win = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); 392 if (win) { 393 u32 pcimembase; 394 395 res = win->res; 396 addr = res->start - win->offset; 397 398 if (res->flags & IORESOURCE_PREFETCH) 399 res->name = "IXP4xx PCI PRE-MEM"; 400 else 401 res->name = "IXP4xx PCI NON-PRE-MEM"; 402 403 dev_dbg(dev, "%s window %pR, bus addr %pa\n", 404 res->name, res, &addr); 405 if (resource_size(res) != SZ_64M) { 406 dev_err(dev, "memory range is not 64MB\n"); 407 return -EINVAL; 408 } 409 410 pcimembase = ixp4xx_pci_addr_to_64mconf(addr); 411 /* Commit configuration */ 412 ixp4xx_writel(p, IXP4XX_PCI_PCIMEMBASE, pcimembase); 413 } else { 414 dev_err(dev, "no AHB memory mapping defined\n"); 415 } 416 417 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 418 if (win) { 419 res = win->res; 420 421 addr = pci_pio_to_address(res->start); 422 if (addr & 0xff) { 423 dev_err(dev, "IO mem at uneven address: %pa\n", &addr); 424 return -EINVAL; 425 } 426 427 res->name = "IXP4xx PCI IO MEM"; 428 /* 429 * Setup I/O space location for PCI->AHB access, the 430 * upper 24 bits of the address goes into the lower 431 * 24 bits of this register. 432 */ 433 ixp4xx_writel(p, IXP4XX_PCI_AHBIOBASE, (addr >> 8)); 434 } else { 435 dev_info(dev, "no IO space AHB memory mapping defined\n"); 436 } 437 438 return 0; 439 } 440 441 static int ixp4xx_pci_parse_map_dma_ranges(struct ixp4xx_pci *p) 442 { 443 struct device *dev = p->dev; 444 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); 445 struct resource_entry *win; 446 struct resource *res; 447 phys_addr_t addr; 448 u32 ahbmembase; 449 450 win = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM); 451 if (win) { 452 res = win->res; 453 addr = res->start - win->offset; 454 455 if (resource_size(res) != SZ_64M) { 456 dev_err(dev, "DMA memory range is not 64MB\n"); 457 return -EINVAL; 458 } 459 460 dev_dbg(dev, "DMA MEM BASE: %pa\n", &addr); 461 /* 462 * 4 PCI-to-AHB windows of 16 MB each, write the 8 high bits 463 * into each byte of the PCI_AHBMEMBASE register. 464 */ 465 ahbmembase = ixp4xx_pci_addr_to_64mconf(addr); 466 /* Commit AHB membase */ 467 ixp4xx_writel(p, IXP4XX_PCI_AHBMEMBASE, ahbmembase); 468 } else { 469 dev_err(dev, "no DMA memory range defined\n"); 470 } 471 472 return 0; 473 } 474 475 #ifdef CONFIG_ARM 476 /* Only used to get context for abort handling */ 477 static struct ixp4xx_pci *ixp4xx_pci_abort_singleton; 478 479 static int ixp4xx_pci_abort_handler(unsigned long addr, unsigned int fsr, 480 struct pt_regs *regs) 481 { 482 struct ixp4xx_pci *p = ixp4xx_pci_abort_singleton; 483 u32 isr, status; 484 int ret; 485 486 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); 487 ret = ixp4xx_crp_read_config(p, PCI_STATUS, 2, &status); 488 if (ret) { 489 dev_err(p->dev, "unable to read abort status\n"); 490 return -EINVAL; 491 } 492 493 dev_err(p->dev, 494 "PCI: abort_handler addr = %#lx, isr = %#x, status = %#x\n", 495 addr, isr, status); 496 497 /* Make sure the Master Abort bit is reset */ 498 ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); 499 status |= PCI_STATUS_REC_MASTER_ABORT; 500 ret = ixp4xx_crp_write_config(p, PCI_STATUS, 2, status); 501 if (ret) 502 dev_err(p->dev, "unable to clear abort status bit\n"); 503 504 /* 505 * If it was an imprecise abort, then we need to correct the 506 * return address to be _after_ the instruction. 507 */ 508 if (fsr & (1 << 10)) { 509 dev_err(p->dev, "imprecise abort\n"); 510 regs->ARM_pc += 4; 511 } 512 513 return 0; 514 } 515 #endif 516 517 static int __init ixp4xx_pci_probe(struct platform_device *pdev) 518 { 519 struct device *dev = &pdev->dev; 520 struct device_node *np = dev->of_node; 521 struct ixp4xx_pci *p; 522 struct pci_host_bridge *host; 523 int ret; 524 u32 val; 525 phys_addr_t addr; 526 u32 basereg[4] = { 527 PCI_BASE_ADDRESS_0, 528 PCI_BASE_ADDRESS_1, 529 PCI_BASE_ADDRESS_2, 530 PCI_BASE_ADDRESS_3, 531 }; 532 int i; 533 534 host = devm_pci_alloc_host_bridge(dev, sizeof(*p)); 535 if (!host) 536 return -ENOMEM; 537 538 host->ops = &ixp4xx_pci_ops; 539 p = pci_host_bridge_priv(host); 540 host->sysdata = p; 541 p->dev = dev; 542 dev_set_drvdata(dev, p); 543 544 /* 545 * Set up quirk for erratic behaviour in the 42x variant 546 * when accessing config space. 547 */ 548 if (of_device_is_compatible(np, "intel,ixp42x-pci")) { 549 p->errata_hammer = true; 550 dev_info(dev, "activate hammering errata\n"); 551 } 552 553 p->base = devm_platform_ioremap_resource(pdev, 0); 554 if (IS_ERR(p->base)) 555 return PTR_ERR(p->base); 556 557 val = ixp4xx_readl(p, IXP4XX_PCI_CSR); 558 p->host_mode = !!(val & IXP4XX_PCI_CSR_HOST); 559 dev_info(dev, "controller is in %s mode\n", 560 p->host_mode ? "host" : "option"); 561 562 #ifdef CONFIG_ARM 563 /* Hook in our fault handler for PCI errors */ 564 ixp4xx_pci_abort_singleton = p; 565 hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0, 566 "imprecise external abort"); 567 #endif 568 569 ret = ixp4xx_pci_parse_map_ranges(p); 570 if (ret) 571 return ret; 572 573 ret = ixp4xx_pci_parse_map_dma_ranges(p); 574 if (ret) 575 return ret; 576 577 /* This is only configured in host mode */ 578 if (p->host_mode) { 579 addr = __pa(PAGE_OFFSET); 580 /* This is a noop (0x00) but explains what is going on */ 581 addr |= PCI_BASE_ADDRESS_SPACE_MEMORY; 582 583 for (i = 0; i < 4; i++) { 584 /* Write this directly into the config space */ 585 ret = ixp4xx_crp_write_config(p, basereg[i], 4, addr); 586 if (ret) 587 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_%d\n", i); 588 else 589 dev_info(dev, "set PCI_BASE_ADDR_%d to %pa\n", i, &addr); 590 addr += SZ_16M; 591 } 592 593 /* 594 * Enable CSR window at 64 MiB to allow PCI masters to continue 595 * prefetching past the 64 MiB boundary, if all AHB to PCI 596 * windows are consecutive. 597 */ 598 ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_4, 4, addr); 599 if (ret) 600 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_4\n"); 601 else 602 dev_info(dev, "set PCI_BASE_ADDR_4 to %pa\n", &addr); 603 604 /* 605 * Put the IO memory window at the very end of physical memory 606 * at 0xfffffc00. This is when the system is trying to access IO 607 * memory over AHB. 608 */ 609 addr = 0xfffffc00; 610 addr |= PCI_BASE_ADDRESS_SPACE_IO; 611 ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_5, 4, addr); 612 if (ret) 613 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_5\n"); 614 else 615 dev_info(dev, "set PCI_BASE_ADDR_5 to %pa\n", &addr); 616 617 /* 618 * Retry timeout to 0x80 619 * Transfer ready timeout to 0xff 620 */ 621 ret = ixp4xx_crp_write_config(p, IXP4XX_PCI_RTOTTO, 4, 622 0x000080ff); 623 if (ret) 624 dev_err(dev, "failed to set up TRDY limit\n"); 625 else 626 dev_info(dev, "set TRDY limit to 0x80ff\n"); 627 } 628 629 /* Clear interrupts */ 630 val = IXP4XX_PCI_ISR_PSE | IXP4XX_PCI_ISR_PFE | IXP4XX_PCI_ISR_PPE | IXP4XX_PCI_ISR_AHBE; 631 ixp4xx_writel(p, IXP4XX_PCI_ISR, val); 632 633 /* 634 * Set Initialize Complete in PCI Control Register: allow IXP4XX to 635 * generate PCI configuration cycles. Specify that the AHB bus is 636 * operating in big-endian mode. Set up byte lane swapping between 637 * little-endian PCI and the big-endian AHB bus. 638 */ 639 val = IXP4XX_PCI_CSR_IC | IXP4XX_PCI_CSR_ABE; 640 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 641 val |= (IXP4XX_PCI_CSR_PDS | IXP4XX_PCI_CSR_ADS); 642 ixp4xx_writel(p, IXP4XX_PCI_CSR, val); 643 644 ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); 645 if (ret) 646 dev_err(dev, "unable to initialize master and command memory\n"); 647 else 648 dev_info(dev, "initialized as master\n"); 649 650 pci_host_probe(host); 651 652 return 0; 653 } 654 655 static const struct of_device_id ixp4xx_pci_of_match[] = { 656 { 657 .compatible = "intel,ixp42x-pci", 658 }, 659 { 660 .compatible = "intel,ixp43x-pci", 661 }, 662 {}, 663 }; 664 665 /* 666 * This driver needs to be a builtin module with suppressed bind 667 * attributes since the probe() is initializing a hard exception 668 * handler and this can only be done from __init-tagged code 669 * sections. This module cannot be removed and inserted at all. 670 */ 671 static struct platform_driver ixp4xx_pci_driver = { 672 .driver = { 673 .name = "ixp4xx-pci", 674 .suppress_bind_attrs = true, 675 .of_match_table = ixp4xx_pci_of_match, 676 }, 677 }; 678 builtin_platform_driver_probe(ixp4xx_pci_driver, ixp4xx_pci_probe); 679