1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 4 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 5 */ 6 7 #ifndef _CQ_ENET_DESC_H_ 8 #define _CQ_ENET_DESC_H_ 9 10 #include "cq_desc.h" 11 12 /* Ethernet completion queue descriptor: 16B */ 13 struct cq_enet_wq_desc { 14 __le16 completed_index; 15 __le16 q_number; 16 u8 reserved[11]; 17 u8 type_color; 18 }; 19 20 /* 21 * Defines and Capabilities for CMD_CQ_ENTRY_SIZE_SET 22 */ 23 #define VNIC_RQ_ALL (~0ULL) 24 25 #define VNIC_RQ_CQ_ENTRY_SIZE_16 0 26 #define VNIC_RQ_CQ_ENTRY_SIZE_32 1 27 #define VNIC_RQ_CQ_ENTRY_SIZE_64 2 28 29 #define VNIC_RQ_CQ_ENTRY_SIZE_16_CAPABLE BIT(VNIC_RQ_CQ_ENTRY_SIZE_16) 30 #define VNIC_RQ_CQ_ENTRY_SIZE_32_CAPABLE BIT(VNIC_RQ_CQ_ENTRY_SIZE_32) 31 #define VNIC_RQ_CQ_ENTRY_SIZE_64_CAPABLE BIT(VNIC_RQ_CQ_ENTRY_SIZE_64) 32 33 #define VNIC_RQ_CQ_ENTRY_SIZE_ALL_BIT (VNIC_RQ_CQ_ENTRY_SIZE_16_CAPABLE | \ 34 VNIC_RQ_CQ_ENTRY_SIZE_32_CAPABLE | \ 35 VNIC_RQ_CQ_ENTRY_SIZE_64_CAPABLE) 36 37 /* Completion queue descriptor: Ethernet receive queue, 16B */ 38 struct cq_enet_rq_desc { 39 __le16 completed_index_flags; 40 __le16 q_number_rss_type_flags; 41 __le32 rss_hash; 42 __le16 bytes_written_flags; 43 __le16 vlan; 44 __le16 checksum_fcoe; 45 u8 flags; 46 u8 type_color; 47 }; 48 49 /* Completion queue descriptor: Ethernet receive queue, 32B */ 50 struct cq_enet_rq_desc_32 { 51 __le16 completed_index_flags; 52 __le16 q_number_rss_type_flags; 53 __le32 rss_hash; 54 __le16 bytes_written_flags; 55 __le16 vlan; 56 __le16 checksum_fcoe; 57 u8 flags; 58 u8 fetch_index_flags; 59 __le32 time_stamp; 60 __le16 time_stamp2; 61 __le16 pie_info; 62 __le32 pie_info2; 63 __le16 pie_info3; 64 u8 pie_info4; 65 u8 type_color; 66 }; 67 68 /* Completion queue descriptor: Ethernet receive queue, 64B */ 69 struct cq_enet_rq_desc_64 { 70 __le16 completed_index_flags; 71 __le16 q_number_rss_type_flags; 72 __le32 rss_hash; 73 __le16 bytes_written_flags; 74 __le16 vlan; 75 __le16 checksum_fcoe; 76 u8 flags; 77 u8 fetch_index_flags; 78 __le32 time_stamp; 79 __le16 time_stamp2; 80 __le16 pie_info; 81 __le32 pie_info2; 82 __le16 pie_info3; 83 u8 pie_info4; 84 u8 reserved[32]; 85 u8 type_color; 86 }; 87 88 #define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT (0x1 << 12) 89 #define CQ_ENET_RQ_DESC_FLAGS_FCOE (0x1 << 13) 90 #define CQ_ENET_RQ_DESC_FLAGS_EOP (0x1 << 14) 91 #define CQ_ENET_RQ_DESC_FLAGS_SOP (0x1 << 15) 92 93 #define CQ_ENET_RQ_DESC_RSS_TYPE_BITS 4 94 #define CQ_ENET_RQ_DESC_RSS_TYPE_MASK \ 95 ((1 << CQ_ENET_RQ_DESC_RSS_TYPE_BITS) - 1) 96 #define CQ_ENET_RQ_DESC_RSS_TYPE_NONE 0 97 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv4 1 98 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4 2 99 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6 3 100 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6 4 101 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX 5 102 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX 6 103 104 #define CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC (0x1 << 14) 105 106 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS 14 107 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK \ 108 ((1 << CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS) - 1) 109 #define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED (0x1 << 14) 110 #define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED (0x1 << 15) 111 112 #define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS 12 113 #define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_MASK \ 114 ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS) - 1) 115 #define CQ_ENET_RQ_DESC_VLAN_TCI_CFI_MASK (0x1 << 12) 116 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS 3 117 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_MASK \ 118 ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS) - 1) 119 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_SHIFT 13 120 121 #define CQ_ENET_RQ_DESC_FCOE_SOF_BITS 8 122 #define CQ_ENET_RQ_DESC_FCOE_SOF_MASK \ 123 ((1 << CQ_ENET_RQ_DESC_FCOE_SOF_BITS) - 1) 124 #define CQ_ENET_RQ_DESC_FCOE_EOF_BITS 8 125 #define CQ_ENET_RQ_DESC_FCOE_EOF_MASK \ 126 ((1 << CQ_ENET_RQ_DESC_FCOE_EOF_BITS) - 1) 127 #define CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT 8 128 129 #define CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK (0x1 << 0) 130 #define CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK (0x1 << 0) 131 #define CQ_ENET_RQ_DESC_FLAGS_UDP (0x1 << 1) 132 #define CQ_ENET_RQ_DESC_FCOE_ENC_ERROR (0x1 << 1) 133 #define CQ_ENET_RQ_DESC_FLAGS_TCP (0x1 << 2) 134 #define CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK (0x1 << 3) 135 #define CQ_ENET_RQ_DESC_FLAGS_IPV6 (0x1 << 4) 136 #define CQ_ENET_RQ_DESC_FLAGS_IPV4 (0x1 << 5) 137 #define CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT (0x1 << 6) 138 #define CQ_ENET_RQ_DESC_FLAGS_FCS_OK (0x1 << 7) 139 140 #endif /* _CQ_ENET_DESC_H_ */ 141