1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Driver for Cadence QSPI Controller
4 //
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
8
9 #include <linux/clk.h>
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/iopoll.h>
20 #include <linux/jiffies.h>
21 #include <linux/kernel.h>
22 #include <linux/log2.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/reset.h>
28 #include <linux/sched.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/spi-mem.h>
31 #include <linux/timer.h>
32
33 #define CQSPI_NAME "cadence-qspi"
34 #define CQSPI_MAX_CHIPSELECT 4
35
36 static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX);
37
38 /* Quirks */
39 #define CQSPI_NEEDS_WR_DELAY BIT(0)
40 #define CQSPI_DISABLE_DAC_MODE BIT(1)
41 #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2)
42 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
43 #define CQSPI_SLOW_SRAM BIT(4)
44 #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
45 #define CQSPI_RD_NO_IRQ BIT(6)
46 #define CQSPI_DMA_SET_MASK BIT(7)
47 #define CQSPI_SUPPORT_DEVICE_RESET BIT(8)
48 #define CQSPI_DISABLE_STIG_MODE BIT(9)
49 #define CQSPI_DISABLE_RUNTIME_PM BIT(10)
50
51 /* Capabilities */
52 #define CQSPI_SUPPORTS_OCTAL BIT(0)
53 #define CQSPI_SUPPORTS_QUAD BIT(1)
54
55 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0)
56
57 enum {
58 CLK_QSPI_APB = 0,
59 CLK_QSPI_AHB,
60 CLK_QSPI_NUM,
61 };
62
63 struct cqspi_st;
64
65 struct cqspi_flash_pdata {
66 struct cqspi_st *cqspi;
67 u32 clk_rate;
68 u32 read_delay;
69 u32 tshsl_ns;
70 u32 tsd2d_ns;
71 u32 tchsh_ns;
72 u32 tslch_ns;
73 u8 cs;
74 };
75
76 struct cqspi_st {
77 struct platform_device *pdev;
78 struct spi_controller *host;
79 struct clk *clk;
80 struct clk *clks[CLK_QSPI_NUM];
81 unsigned int sclk;
82
83 void __iomem *iobase;
84 void __iomem *ahb_base;
85 resource_size_t ahb_size;
86 struct completion transfer_complete;
87
88 struct dma_chan *rx_chan;
89 struct completion rx_dma_complete;
90 dma_addr_t mmap_phys_base;
91
92 int current_cs;
93 unsigned long master_ref_clk_hz;
94 bool is_decoded_cs;
95 u32 fifo_depth;
96 u32 fifo_width;
97 u32 num_chipselect;
98 bool rclk_en;
99 u32 trigger_address;
100 u32 wr_delay;
101 bool use_direct_mode;
102 bool use_direct_mode_wr;
103 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
104 bool use_dma_read;
105 u32 pd_dev_id;
106 bool wr_completion;
107 bool slow_sram;
108 bool apb_ahb_hazard;
109
110 bool is_jh7110; /* Flag for StarFive JH7110 SoC */
111 bool disable_stig_mode;
112 refcount_t refcount;
113 refcount_t inflight_ops;
114
115 const struct cqspi_driver_platdata *ddata;
116 };
117
118 struct cqspi_driver_platdata {
119 u32 hwcaps_mask;
120 u16 quirks;
121 int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata,
122 u_char *rxbuf, loff_t from_addr, size_t n_rx);
123 u32 (*get_dma_status)(struct cqspi_st *cqspi);
124 int (*jh7110_clk_init)(struct platform_device *pdev,
125 struct cqspi_st *cqspi);
126 };
127
128 /* Operation timeout value */
129 #define CQSPI_TIMEOUT_MS 500
130 #define CQSPI_READ_TIMEOUT_MS 10
131 #define CQSPI_BUSYWAIT_TIMEOUT_US 500
132
133 /* Runtime_pm autosuspend delay */
134 #define CQSPI_AUTOSUSPEND_TIMEOUT 2000
135
136 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
137 #define CQSPI_DUMMY_BYTES_MAX 4
138 #define CQSPI_DUMMY_CLKS_MAX 31
139
140 #define CQSPI_STIG_DATA_LEN_MAX 8
141
142 /* Register map */
143 #define CQSPI_REG_CONFIG 0x00
144 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
145 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
146 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
147 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
148 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
149 #define CQSPI_REG_CONFIG_BAUD_LSB 19
150 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
151 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
152 #define CQSPI_REG_CONFIG_IDLE_LSB 31
153 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
154 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
155 #define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5)
156 #define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6)
157
158 #define CQSPI_REG_RD_INSTR 0x04
159 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
160 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
161 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
162 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
163 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
164 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
165 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
166 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
167 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
168 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
169
170 #define CQSPI_REG_WR_INSTR 0x08
171 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
172 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
173 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
174
175 #define CQSPI_REG_DELAY 0x0C
176 #define CQSPI_REG_DELAY_TSLCH_LSB 0
177 #define CQSPI_REG_DELAY_TCHSH_LSB 8
178 #define CQSPI_REG_DELAY_TSD2D_LSB 16
179 #define CQSPI_REG_DELAY_TSHSL_LSB 24
180 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
181 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
182 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
183 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
184
185 #define CQSPI_REG_READCAPTURE 0x10
186 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
187 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
188 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
189
190 #define CQSPI_REG_SIZE 0x14
191 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
192 #define CQSPI_REG_SIZE_PAGE_LSB 4
193 #define CQSPI_REG_SIZE_BLOCK_LSB 16
194 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
195 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
196 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
197
198 #define CQSPI_REG_SRAMPARTITION 0x18
199 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
200
201 #define CQSPI_REG_DMA 0x20
202 #define CQSPI_REG_DMA_SINGLE_LSB 0
203 #define CQSPI_REG_DMA_BURST_LSB 8
204 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
205 #define CQSPI_REG_DMA_BURST_MASK 0xFF
206
207 #define CQSPI_REG_REMAP 0x24
208 #define CQSPI_REG_MODE_BIT 0x28
209
210 #define CQSPI_REG_SDRAMLEVEL 0x2C
211 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
212 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
213 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
214 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
215
216 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38
217 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
218
219 #define CQSPI_REG_IRQSTATUS 0x40
220 #define CQSPI_REG_IRQMASK 0x44
221
222 #define CQSPI_REG_INDIRECTRD 0x60
223 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
224 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
225 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
226
227 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
228 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
229 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
230
231 #define CQSPI_REG_CMDCTRL 0x90
232 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
233 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
234 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
235 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
236 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
237 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
238 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
239 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
240 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
241 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
242 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
243 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
244 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
245 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
246
247 #define CQSPI_REG_INDIRECTWR 0x70
248 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
249 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
250 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
251
252 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
253 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
254 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
255
256 #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80
257
258 #define CQSPI_REG_CMDADDRESS 0x94
259 #define CQSPI_REG_CMDREADDATALOWER 0xA0
260 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
261 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
262 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
263
264 #define CQSPI_REG_POLLING_STATUS 0xB0
265 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16
266
267 #define CQSPI_REG_OP_EXT_LOWER 0xE0
268 #define CQSPI_REG_OP_EXT_READ_LSB 24
269 #define CQSPI_REG_OP_EXT_WRITE_LSB 16
270 #define CQSPI_REG_OP_EXT_STIG_LSB 0
271
272 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000
273
274 #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800
275 #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804
276
277 #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C
278
279 #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814
280 #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818
281 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C
282 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1)
283
284 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828
285
286 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00
287 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6
288
289 /* Interrupt status bits */
290 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
291 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
292 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
293 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
294 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
295 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
296 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
297 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
298
299 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
300 CQSPI_REG_IRQ_IND_SRAM_FULL | \
301 CQSPI_REG_IRQ_IND_COMP)
302
303 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
304 CQSPI_REG_IRQ_WATERMARK | \
305 CQSPI_REG_IRQ_UNDERFLOW)
306
307 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
308 #define CQSPI_DMA_UNALIGN 0x3
309
310 #define CQSPI_REG_VERSAL_DMA_VAL 0x602
311
cqspi_wait_for_bit(const struct cqspi_driver_platdata * ddata,void __iomem * reg,const u32 mask,bool clr,bool busywait)312 static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata,
313 void __iomem *reg, const u32 mask, bool clr,
314 bool busywait)
315 {
316 u64 timeout_us = CQSPI_TIMEOUT_MS * USEC_PER_MSEC;
317 u32 val;
318
319 if (busywait) {
320 int ret = readl_relaxed_poll_timeout(reg, val,
321 (((clr ? ~val : val) & mask) == mask),
322 0, CQSPI_BUSYWAIT_TIMEOUT_US);
323
324 if (ret != -ETIMEDOUT)
325 return ret;
326
327 timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US;
328 }
329
330 return readl_relaxed_poll_timeout(reg, val,
331 (((clr ? ~val : val) & mask) == mask),
332 10, timeout_us);
333 }
334
cqspi_is_idle(struct cqspi_st * cqspi)335 static bool cqspi_is_idle(struct cqspi_st *cqspi)
336 {
337 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
338
339 return reg & BIT(CQSPI_REG_CONFIG_IDLE_LSB);
340 }
341
cqspi_get_rd_sram_level(struct cqspi_st * cqspi)342 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
343 {
344 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
345
346 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
347 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
348 }
349
cqspi_get_versal_dma_status(struct cqspi_st * cqspi)350 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
351 {
352 u32 dma_status;
353
354 dma_status = readl(cqspi->iobase +
355 CQSPI_REG_VERSAL_DMA_DST_I_STS);
356 writel(dma_status, cqspi->iobase +
357 CQSPI_REG_VERSAL_DMA_DST_I_STS);
358
359 return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK;
360 }
361
cqspi_irq_handler(int this_irq,void * dev)362 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
363 {
364 struct cqspi_st *cqspi = dev;
365 const struct cqspi_driver_platdata *ddata = cqspi->ddata;
366 unsigned int irq_status;
367
368 /* Read interrupt status */
369 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
370
371 /* Clear interrupt */
372 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
373
374 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
375 if (ddata->get_dma_status(cqspi)) {
376 complete(&cqspi->transfer_complete);
377 return IRQ_HANDLED;
378 }
379 }
380
381 else if (!cqspi->slow_sram)
382 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
383 else
384 irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR;
385
386 if (irq_status)
387 complete(&cqspi->transfer_complete);
388
389 return IRQ_HANDLED;
390 }
391
cqspi_calc_rdreg(const struct spi_mem_op * op)392 static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op)
393 {
394 u32 rdreg = 0;
395
396 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
397 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
398 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
399
400 return rdreg;
401 }
402
cqspi_calc_dummy(const struct spi_mem_op * op)403 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op)
404 {
405 unsigned int dummy_clk;
406
407 if (!op->dummy.nbytes)
408 return 0;
409
410 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
411 if (op->cmd.dtr)
412 dummy_clk /= 2;
413
414 return dummy_clk;
415 }
416
cqspi_wait_idle(struct cqspi_st * cqspi)417 static int cqspi_wait_idle(struct cqspi_st *cqspi)
418 {
419 const unsigned int poll_idle_retry = 3;
420 unsigned int count = 0;
421 unsigned long timeout;
422
423 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
424 while (1) {
425 /*
426 * Read few times in succession to ensure the controller
427 * is indeed idle, that is, the bit does not transition
428 * low again.
429 */
430 if (cqspi_is_idle(cqspi))
431 count++;
432 else
433 count = 0;
434
435 if (count >= poll_idle_retry)
436 return 0;
437
438 if (time_after(jiffies, timeout)) {
439 /* Timeout, in busy mode. */
440 dev_err(&cqspi->pdev->dev,
441 "QSPI is still busy after %dms timeout.\n",
442 CQSPI_TIMEOUT_MS);
443 return -ETIMEDOUT;
444 }
445
446 cpu_relax();
447 }
448 }
449
cqspi_exec_flash_cmd(struct cqspi_st * cqspi,unsigned int reg)450 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
451 {
452 void __iomem *reg_base = cqspi->iobase;
453 int ret;
454
455 /* Write the CMDCTRL without start execution. */
456 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
457 /* Start execute */
458 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
459 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
460
461 /* Polling for completion. */
462 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL,
463 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true);
464 if (ret) {
465 dev_err(&cqspi->pdev->dev,
466 "Flash command execution timed out.\n");
467 return ret;
468 }
469
470 /* Polling QSPI idle status. */
471 return cqspi_wait_idle(cqspi);
472 }
473
cqspi_setup_opcode_ext(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op,unsigned int shift)474 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
475 const struct spi_mem_op *op,
476 unsigned int shift)
477 {
478 struct cqspi_st *cqspi = f_pdata->cqspi;
479 void __iomem *reg_base = cqspi->iobase;
480 unsigned int reg;
481 u8 ext;
482
483 if (op->cmd.nbytes != 2)
484 return -EINVAL;
485
486 /* Opcode extension is the LSB. */
487 ext = op->cmd.opcode & 0xff;
488
489 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
490 reg &= ~(0xff << shift);
491 reg |= ext << shift;
492 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
493
494 return 0;
495 }
496
cqspi_enable_dtr(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op,unsigned int shift)497 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
498 const struct spi_mem_op *op, unsigned int shift)
499 {
500 struct cqspi_st *cqspi = f_pdata->cqspi;
501 void __iomem *reg_base = cqspi->iobase;
502 unsigned int reg;
503 int ret;
504
505 reg = readl(reg_base + CQSPI_REG_CONFIG);
506
507 /*
508 * We enable dual byte opcode here. The callers have to set up the
509 * extension opcode based on which type of operation it is.
510 */
511 if (op->cmd.dtr) {
512 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
513 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
514
515 /* Set up command opcode extension. */
516 ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
517 if (ret)
518 return ret;
519 } else {
520 unsigned int mask = CQSPI_REG_CONFIG_DTR_PROTO | CQSPI_REG_CONFIG_DUAL_OPCODE;
521 /* Shortcut if DTR is already disabled. */
522 if ((reg & mask) == 0)
523 return 0;
524 reg &= ~mask;
525 }
526
527 writel(reg, reg_base + CQSPI_REG_CONFIG);
528
529 return cqspi_wait_idle(cqspi);
530 }
531
cqspi_command_read(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)532 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
533 const struct spi_mem_op *op)
534 {
535 struct cqspi_st *cqspi = f_pdata->cqspi;
536 void __iomem *reg_base = cqspi->iobase;
537 u8 *rxbuf = op->data.buf.in;
538 u8 opcode;
539 size_t n_rx = op->data.nbytes;
540 unsigned int rdreg;
541 unsigned int reg;
542 unsigned int dummy_clk;
543 size_t read_len;
544 int status;
545
546 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
547 if (status)
548 return status;
549
550 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
551 dev_err(&cqspi->pdev->dev,
552 "Invalid input argument, len %zu rxbuf 0x%p\n",
553 n_rx, rxbuf);
554 return -EINVAL;
555 }
556
557 if (op->cmd.dtr)
558 opcode = op->cmd.opcode >> 8;
559 else
560 opcode = op->cmd.opcode;
561
562 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
563
564 rdreg = cqspi_calc_rdreg(op);
565 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
566
567 dummy_clk = cqspi_calc_dummy(op);
568 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
569 return -EOPNOTSUPP;
570
571 if (dummy_clk)
572 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
573 << CQSPI_REG_CMDCTRL_DUMMY_LSB;
574
575 reg |= BIT(CQSPI_REG_CMDCTRL_RD_EN_LSB);
576
577 /* 0 means 1 byte. */
578 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
579 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
580
581 /* setup ADDR BIT field */
582 if (op->addr.nbytes) {
583 reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
584 reg |= ((op->addr.nbytes - 1) &
585 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
586 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
587
588 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
589 }
590
591 status = cqspi_exec_flash_cmd(cqspi, reg);
592 if (status)
593 return status;
594
595 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
596
597 /* Put the read value into rx_buf */
598 read_len = (n_rx > 4) ? 4 : n_rx;
599 memcpy(rxbuf, ®, read_len);
600 rxbuf += read_len;
601
602 if (n_rx > 4) {
603 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
604
605 read_len = n_rx - read_len;
606 memcpy(rxbuf, ®, read_len);
607 }
608
609 /* Reset CMD_CTRL Reg once command read completes */
610 writel(0, reg_base + CQSPI_REG_CMDCTRL);
611
612 return 0;
613 }
614
cqspi_command_write(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)615 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
616 const struct spi_mem_op *op)
617 {
618 struct cqspi_st *cqspi = f_pdata->cqspi;
619 void __iomem *reg_base = cqspi->iobase;
620 u8 opcode;
621 const u8 *txbuf = op->data.buf.out;
622 size_t n_tx = op->data.nbytes;
623 unsigned int reg;
624 unsigned int data;
625 size_t write_len;
626 int ret;
627
628 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
629 if (ret)
630 return ret;
631
632 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
633 dev_err(&cqspi->pdev->dev,
634 "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
635 n_tx, txbuf);
636 return -EINVAL;
637 }
638
639 reg = cqspi_calc_rdreg(op);
640 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
641
642 if (op->cmd.dtr)
643 opcode = op->cmd.opcode >> 8;
644 else
645 opcode = op->cmd.opcode;
646
647 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
648
649 if (op->addr.nbytes) {
650 reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
651 reg |= ((op->addr.nbytes - 1) &
652 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
653 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
654
655 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
656 }
657
658 if (n_tx) {
659 reg |= BIT(CQSPI_REG_CMDCTRL_WR_EN_LSB);
660 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
661 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
662 data = 0;
663 write_len = (n_tx > 4) ? 4 : n_tx;
664 memcpy(&data, txbuf, write_len);
665 txbuf += write_len;
666 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
667
668 if (n_tx > 4) {
669 data = 0;
670 write_len = n_tx - 4;
671 memcpy(&data, txbuf, write_len);
672 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
673 }
674 }
675
676 ret = cqspi_exec_flash_cmd(cqspi, reg);
677
678 /* Reset CMD_CTRL Reg once command write completes */
679 writel(0, reg_base + CQSPI_REG_CMDCTRL);
680
681 return ret;
682 }
683
cqspi_read_setup(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)684 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
685 const struct spi_mem_op *op)
686 {
687 struct cqspi_st *cqspi = f_pdata->cqspi;
688 void __iomem *reg_base = cqspi->iobase;
689 unsigned int dummy_clk = 0;
690 unsigned int reg;
691 int ret;
692 u8 opcode;
693
694 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB);
695 if (ret)
696 return ret;
697
698 if (op->cmd.dtr)
699 opcode = op->cmd.opcode >> 8;
700 else
701 opcode = op->cmd.opcode;
702
703 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
704 reg |= cqspi_calc_rdreg(op);
705
706 /* Setup dummy clock cycles */
707 dummy_clk = cqspi_calc_dummy(op);
708
709 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
710 return -EOPNOTSUPP;
711
712 if (dummy_clk)
713 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
714 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
715
716 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
717
718 /* Set address width */
719 reg = readl(reg_base + CQSPI_REG_SIZE);
720 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
721 reg |= (op->addr.nbytes - 1);
722 writel(reg, reg_base + CQSPI_REG_SIZE);
723 readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
724 return 0;
725 }
726
cqspi_indirect_read_execute(struct cqspi_flash_pdata * f_pdata,u8 * rxbuf,loff_t from_addr,const size_t n_rx)727 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
728 u8 *rxbuf, loff_t from_addr,
729 const size_t n_rx)
730 {
731 struct cqspi_st *cqspi = f_pdata->cqspi;
732 bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ);
733 struct device *dev = &cqspi->pdev->dev;
734 void __iomem *reg_base = cqspi->iobase;
735 void __iomem *ahb_base = cqspi->ahb_base;
736 unsigned int remaining = n_rx;
737 unsigned int mod_bytes = n_rx % 4;
738 unsigned int bytes_to_read = 0;
739 u8 *rxbuf_end = rxbuf + n_rx;
740 int ret = 0;
741
742 if (!refcount_read(&cqspi->refcount))
743 return -ENODEV;
744
745 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
746 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
747
748 /* Clear all interrupts. */
749 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
750
751 /*
752 * On SoCFPGA platform reading the SRAM is slow due to
753 * hardware limitation and causing read interrupt storm to CPU,
754 * so enabling only watermark interrupt to disable all read
755 * interrupts later as we want to run "bytes to read" loop with
756 * all the read interrupts disabled for max performance.
757 */
758
759 if (use_irq && cqspi->slow_sram)
760 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
761 else if (use_irq)
762 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
763 else
764 writel(0, reg_base + CQSPI_REG_IRQMASK);
765
766 reinit_completion(&cqspi->transfer_complete);
767 writel(CQSPI_REG_INDIRECTRD_START_MASK,
768 reg_base + CQSPI_REG_INDIRECTRD);
769 readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */
770
771 while (remaining > 0) {
772 if (use_irq &&
773 !wait_for_completion_timeout(&cqspi->transfer_complete,
774 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
775 ret = -ETIMEDOUT;
776
777 /*
778 * Disable all read interrupts until
779 * we are out of "bytes to read"
780 */
781 if (cqspi->slow_sram)
782 writel(0x0, reg_base + CQSPI_REG_IRQMASK);
783
784 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
785
786 if (ret && bytes_to_read == 0) {
787 dev_err(dev, "Indirect read timeout, no bytes\n");
788 goto failrd;
789 }
790
791 while (bytes_to_read != 0) {
792 unsigned int word_remain = round_down(remaining, 4);
793
794 bytes_to_read *= cqspi->fifo_width;
795 bytes_to_read = bytes_to_read > remaining ?
796 remaining : bytes_to_read;
797 bytes_to_read = round_down(bytes_to_read, 4);
798 /* Read 4 byte word chunks then single bytes */
799 if (bytes_to_read) {
800 ioread32_rep(ahb_base, rxbuf,
801 (bytes_to_read / 4));
802 } else if (!word_remain && mod_bytes) {
803 unsigned int temp = ioread32(ahb_base);
804
805 bytes_to_read = mod_bytes;
806 memcpy(rxbuf, &temp, min((unsigned int)
807 (rxbuf_end - rxbuf),
808 bytes_to_read));
809 }
810 rxbuf += bytes_to_read;
811 remaining -= bytes_to_read;
812 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
813 }
814
815 if (use_irq && remaining > 0) {
816 reinit_completion(&cqspi->transfer_complete);
817 if (cqspi->slow_sram)
818 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
819 }
820 }
821
822 /* Check indirect done status */
823 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD,
824 CQSPI_REG_INDIRECTRD_DONE_MASK, 0, true);
825 if (ret) {
826 dev_err(dev, "Indirect read completion error (%i)\n", ret);
827 goto failrd;
828 }
829
830 /* Disable interrupt */
831 writel(0, reg_base + CQSPI_REG_IRQMASK);
832
833 /* Clear indirect completion status */
834 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
835
836 return 0;
837
838 failrd:
839 /* Disable interrupt */
840 writel(0, reg_base + CQSPI_REG_IRQMASK);
841
842 /* Cancel the indirect read */
843 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
844 reg_base + CQSPI_REG_INDIRECTRD);
845 return ret;
846 }
847
cqspi_device_reset(struct cqspi_st * cqspi)848 static void cqspi_device_reset(struct cqspi_st *cqspi)
849 {
850 u32 reg;
851
852 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
853 reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK;
854 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
855 /*
856 * NOTE: Delay timing implementation is derived from
857 * spi_nor_hw_reset()
858 */
859 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
860 usleep_range(1, 5);
861 writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
862 usleep_range(100, 150);
863 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
864 usleep_range(1000, 1200);
865 }
866
cqspi_controller_enable(struct cqspi_st * cqspi,bool enable)867 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
868 {
869 void __iomem *reg_base = cqspi->iobase;
870 unsigned int reg;
871
872 reg = readl(reg_base + CQSPI_REG_CONFIG);
873
874 if (enable)
875 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
876 else
877 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
878
879 writel(reg, reg_base + CQSPI_REG_CONFIG);
880 }
881
cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata * f_pdata,u_char * rxbuf,loff_t from_addr,size_t n_rx)882 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
883 u_char *rxbuf, loff_t from_addr,
884 size_t n_rx)
885 {
886 struct cqspi_st *cqspi = f_pdata->cqspi;
887 struct device *dev = &cqspi->pdev->dev;
888 void __iomem *reg_base = cqspi->iobase;
889 u32 reg, bytes_to_dma;
890 loff_t addr = from_addr;
891 void *buf = rxbuf;
892 dma_addr_t dma_addr;
893 u8 bytes_rem;
894 int ret = 0;
895
896 bytes_rem = n_rx % 4;
897 bytes_to_dma = (n_rx - bytes_rem);
898
899 if (!bytes_to_dma)
900 goto nondmard;
901
902 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
903 if (ret)
904 return ret;
905
906 cqspi_controller_enable(cqspi, 0);
907
908 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
909 reg |= CQSPI_REG_CONFIG_DMA_MASK;
910 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
911
912 cqspi_controller_enable(cqspi, 1);
913
914 dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE);
915 if (dma_mapping_error(dev, dma_addr)) {
916 dev_err(dev, "dma mapping failed\n");
917 return -ENOMEM;
918 }
919
920 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
921 writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);
922 writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL,
923 reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);
924
925 /* Clear all interrupts. */
926 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
927
928 /* Enable DMA done interrupt */
929 writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK,
930 reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);
931
932 /* Default DMA periph configuration */
933 writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);
934
935 /* Configure DMA Dst address */
936 writel(lower_32_bits(dma_addr),
937 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);
938 writel(upper_32_bits(dma_addr),
939 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);
940
941 /* Configure DMA Src address */
942 writel(cqspi->trigger_address, reg_base +
943 CQSPI_REG_VERSAL_DMA_SRC_ADDR);
944
945 /* Set DMA destination size */
946 writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);
947
948 /* Set DMA destination control */
949 writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL,
950 reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);
951
952 writel(CQSPI_REG_INDIRECTRD_START_MASK,
953 reg_base + CQSPI_REG_INDIRECTRD);
954
955 reinit_completion(&cqspi->transfer_complete);
956
957 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
958 msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) {
959 ret = -ETIMEDOUT;
960 goto failrd;
961 }
962
963 /* Disable DMA interrupt */
964 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
965
966 /* Clear indirect completion status */
967 writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
968 cqspi->iobase + CQSPI_REG_INDIRECTRD);
969 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
970
971 cqspi_controller_enable(cqspi, 0);
972
973 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
974 reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
975 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
976
977 cqspi_controller_enable(cqspi, 1);
978
979 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
980 PM_OSPI_MUX_SEL_LINEAR);
981 if (ret)
982 return ret;
983
984 nondmard:
985 if (bytes_rem) {
986 addr += bytes_to_dma;
987 buf += bytes_to_dma;
988 ret = cqspi_indirect_read_execute(f_pdata, buf, addr,
989 bytes_rem);
990 if (ret)
991 return ret;
992 }
993
994 return 0;
995
996 failrd:
997 /* Disable DMA interrupt */
998 writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
999
1000 /* Cancel the indirect read */
1001 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
1002 reg_base + CQSPI_REG_INDIRECTRD);
1003
1004 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
1005
1006 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1007 reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
1008 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1009
1010 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
1011
1012 return ret;
1013 }
1014
cqspi_write_setup(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)1015 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
1016 const struct spi_mem_op *op)
1017 {
1018 unsigned int reg;
1019 int ret;
1020 struct cqspi_st *cqspi = f_pdata->cqspi;
1021 void __iomem *reg_base = cqspi->iobase;
1022 u8 opcode;
1023
1024 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB);
1025 if (ret)
1026 return ret;
1027
1028 if (op->cmd.dtr)
1029 opcode = op->cmd.opcode >> 8;
1030 else
1031 opcode = op->cmd.opcode;
1032
1033 /* Set opcode. */
1034 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
1035 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
1036 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
1037 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
1038 reg = cqspi_calc_rdreg(op);
1039 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
1040
1041 /*
1042 * SPI NAND flashes require the address of the status register to be
1043 * passed in the Read SR command. Also, some SPI NOR flashes like the
1044 * cypress Semper flash expect a 4-byte dummy address in the Read SR
1045 * command in DTR mode.
1046 *
1047 * But this controller does not support address phase in the Read SR
1048 * command when doing auto-HW polling. So, disable write completion
1049 * polling on the controller's side. spinand and spi-nor will take
1050 * care of polling the status register.
1051 */
1052 if (cqspi->wr_completion) {
1053 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
1054 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
1055 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
1056 /*
1057 * DAC mode require auto polling as flash needs to be polled
1058 * for write completion in case of bubble in SPI transaction
1059 * due to slow CPU/DMA master.
1060 */
1061 cqspi->use_direct_mode_wr = false;
1062 }
1063
1064 reg = readl(reg_base + CQSPI_REG_SIZE);
1065 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
1066 reg |= (op->addr.nbytes - 1);
1067 writel(reg, reg_base + CQSPI_REG_SIZE);
1068 readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
1069 return 0;
1070 }
1071
cqspi_indirect_write_execute(struct cqspi_flash_pdata * f_pdata,loff_t to_addr,const u8 * txbuf,const size_t n_tx)1072 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
1073 loff_t to_addr, const u8 *txbuf,
1074 const size_t n_tx)
1075 {
1076 struct cqspi_st *cqspi = f_pdata->cqspi;
1077 struct device *dev = &cqspi->pdev->dev;
1078 void __iomem *reg_base = cqspi->iobase;
1079 unsigned int remaining = n_tx;
1080 unsigned int write_bytes;
1081 int ret;
1082
1083 if (!refcount_read(&cqspi->refcount))
1084 return -ENODEV;
1085
1086 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
1087 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
1088
1089 /* Clear all interrupts. */
1090 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
1091
1092 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
1093
1094 reinit_completion(&cqspi->transfer_complete);
1095 writel(CQSPI_REG_INDIRECTWR_START_MASK,
1096 reg_base + CQSPI_REG_INDIRECTWR);
1097 readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */
1098
1099 /*
1100 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
1101 * Controller programming sequence, couple of cycles of
1102 * QSPI_REF_CLK delay is required for the above bit to
1103 * be internally synchronized by the QSPI module. Provide 5
1104 * cycles of delay.
1105 */
1106 if (cqspi->wr_delay)
1107 ndelay(cqspi->wr_delay);
1108
1109 /*
1110 * If a hazard exists between the APB and AHB interfaces, perform a
1111 * dummy readback from the controller to ensure synchronization.
1112 */
1113 if (cqspi->apb_ahb_hazard)
1114 readl(reg_base + CQSPI_REG_INDIRECTWR);
1115
1116 while (remaining > 0) {
1117 size_t write_words, mod_bytes;
1118
1119 write_bytes = remaining;
1120 write_words = write_bytes / 4;
1121 mod_bytes = write_bytes % 4;
1122 /* Write 4 bytes at a time then single bytes. */
1123 if (write_words) {
1124 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
1125 txbuf += (write_words * 4);
1126 }
1127 if (mod_bytes) {
1128 unsigned int temp = 0xFFFFFFFF;
1129
1130 memcpy(&temp, txbuf, mod_bytes);
1131 iowrite32(temp, cqspi->ahb_base);
1132 txbuf += mod_bytes;
1133 }
1134
1135 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
1136 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
1137 dev_err(dev, "Indirect write timeout\n");
1138 ret = -ETIMEDOUT;
1139 goto failwr;
1140 }
1141
1142 remaining -= write_bytes;
1143
1144 if (remaining > 0)
1145 reinit_completion(&cqspi->transfer_complete);
1146 }
1147
1148 /* Check indirect done status */
1149 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR,
1150 CQSPI_REG_INDIRECTWR_DONE_MASK, 0, false);
1151 if (ret) {
1152 dev_err(dev, "Indirect write completion error (%i)\n", ret);
1153 goto failwr;
1154 }
1155
1156 /* Disable interrupt. */
1157 writel(0, reg_base + CQSPI_REG_IRQMASK);
1158
1159 /* Clear indirect completion status */
1160 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
1161
1162 cqspi_wait_idle(cqspi);
1163
1164 return 0;
1165
1166 failwr:
1167 /* Disable interrupt. */
1168 writel(0, reg_base + CQSPI_REG_IRQMASK);
1169
1170 /* Cancel the indirect write */
1171 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
1172 reg_base + CQSPI_REG_INDIRECTWR);
1173 return ret;
1174 }
1175
cqspi_chipselect(struct cqspi_flash_pdata * f_pdata)1176 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
1177 {
1178 struct cqspi_st *cqspi = f_pdata->cqspi;
1179 void __iomem *reg_base = cqspi->iobase;
1180 unsigned int chip_select = f_pdata->cs;
1181 unsigned int reg;
1182
1183 reg = readl(reg_base + CQSPI_REG_CONFIG);
1184 if (cqspi->is_decoded_cs) {
1185 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
1186 } else {
1187 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
1188
1189 /* Convert CS if without decoder.
1190 * CS0 to 4b'1110
1191 * CS1 to 4b'1101
1192 * CS2 to 4b'1011
1193 * CS3 to 4b'0111
1194 */
1195 chip_select = 0xF & ~BIT(chip_select);
1196 }
1197
1198 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
1199 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
1200 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
1201 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
1202 writel(reg, reg_base + CQSPI_REG_CONFIG);
1203 }
1204
calculate_ticks_for_ns(const unsigned int ref_clk_hz,const unsigned int ns_val)1205 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
1206 const unsigned int ns_val)
1207 {
1208 unsigned int ticks;
1209
1210 ticks = ref_clk_hz / 1000; /* kHz */
1211 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
1212
1213 return ticks;
1214 }
1215
cqspi_delay(struct cqspi_flash_pdata * f_pdata)1216 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
1217 {
1218 struct cqspi_st *cqspi = f_pdata->cqspi;
1219 void __iomem *iobase = cqspi->iobase;
1220 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1221 unsigned int tshsl, tchsh, tslch, tsd2d;
1222 unsigned int reg;
1223 unsigned int tsclk;
1224
1225 /* calculate the number of ref ticks for one sclk tick */
1226 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
1227
1228 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
1229 /* this particular value must be at least one sclk */
1230 if (tshsl < tsclk)
1231 tshsl = tsclk;
1232
1233 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
1234 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
1235 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
1236
1237 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
1238 << CQSPI_REG_DELAY_TSHSL_LSB;
1239 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
1240 << CQSPI_REG_DELAY_TCHSH_LSB;
1241 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
1242 << CQSPI_REG_DELAY_TSLCH_LSB;
1243 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
1244 << CQSPI_REG_DELAY_TSD2D_LSB;
1245 writel(reg, iobase + CQSPI_REG_DELAY);
1246 }
1247
cqspi_config_baudrate_div(struct cqspi_st * cqspi)1248 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
1249 {
1250 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1251 void __iomem *reg_base = cqspi->iobase;
1252 u32 reg, div;
1253
1254 /* Recalculate the baudrate divisor based on QSPI specification. */
1255 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1256
1257 /* Maximum baud divisor */
1258 if (div > CQSPI_REG_CONFIG_BAUD_MASK) {
1259 div = CQSPI_REG_CONFIG_BAUD_MASK;
1260 dev_warn(&cqspi->pdev->dev,
1261 "Unable to adjust clock <= %d hz. Reduced to %d hz\n",
1262 cqspi->sclk, ref_clk_hz/((div+1)*2));
1263 }
1264
1265 reg = readl(reg_base + CQSPI_REG_CONFIG);
1266 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
1267 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
1268 writel(reg, reg_base + CQSPI_REG_CONFIG);
1269 }
1270
cqspi_readdata_capture(struct cqspi_st * cqspi,const bool bypass,const unsigned int delay)1271 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
1272 const bool bypass,
1273 const unsigned int delay)
1274 {
1275 void __iomem *reg_base = cqspi->iobase;
1276 unsigned int reg;
1277
1278 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1279
1280 if (bypass)
1281 reg |= BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB);
1282 else
1283 reg &= ~BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB);
1284
1285 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1286 << CQSPI_REG_READCAPTURE_DELAY_LSB);
1287
1288 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
1289 << CQSPI_REG_READCAPTURE_DELAY_LSB;
1290
1291 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
1292 }
1293
cqspi_configure(struct cqspi_flash_pdata * f_pdata,unsigned long sclk)1294 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
1295 unsigned long sclk)
1296 {
1297 struct cqspi_st *cqspi = f_pdata->cqspi;
1298 int switch_cs = (cqspi->current_cs != f_pdata->cs);
1299 int switch_ck = (cqspi->sclk != sclk);
1300
1301 if (switch_cs || switch_ck)
1302 cqspi_controller_enable(cqspi, 0);
1303
1304 /* Switch chip select. */
1305 if (switch_cs) {
1306 cqspi->current_cs = f_pdata->cs;
1307 cqspi_chipselect(f_pdata);
1308 }
1309
1310 /* Setup baudrate divisor and delays */
1311 if (switch_ck) {
1312 cqspi->sclk = sclk;
1313 cqspi_config_baudrate_div(cqspi);
1314 cqspi_delay(f_pdata);
1315 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1316 f_pdata->read_delay);
1317 }
1318
1319 if (switch_cs || switch_ck)
1320 cqspi_controller_enable(cqspi, 1);
1321 }
1322
cqspi_write(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)1323 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
1324 const struct spi_mem_op *op)
1325 {
1326 struct cqspi_st *cqspi = f_pdata->cqspi;
1327 loff_t to = op->addr.val;
1328 size_t len = op->data.nbytes;
1329 const u_char *buf = op->data.buf.out;
1330 int ret;
1331
1332 ret = cqspi_write_setup(f_pdata, op);
1333 if (ret)
1334 return ret;
1335
1336 /*
1337 * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1338 * address (all 0s) with the read status register command in DTR mode.
1339 * But this controller does not support sending dummy address bytes to
1340 * the flash when it is polling the write completion register in DTR
1341 * mode. So, we can not use direct mode when in DTR mode for writing
1342 * data.
1343 */
1344 if (!op->cmd.dtr && cqspi->use_direct_mode &&
1345 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
1346 memcpy_toio(cqspi->ahb_base + to, buf, len);
1347 return cqspi_wait_idle(cqspi);
1348 }
1349
1350 return cqspi_indirect_write_execute(f_pdata, to, buf, len);
1351 }
1352
cqspi_rx_dma_callback(void * param)1353 static void cqspi_rx_dma_callback(void *param)
1354 {
1355 struct cqspi_st *cqspi = param;
1356
1357 complete(&cqspi->rx_dma_complete);
1358 }
1359
cqspi_direct_read_execute(struct cqspi_flash_pdata * f_pdata,u_char * buf,loff_t from,size_t len)1360 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
1361 u_char *buf, loff_t from, size_t len)
1362 {
1363 struct cqspi_st *cqspi = f_pdata->cqspi;
1364 struct device *dev = &cqspi->pdev->dev;
1365 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
1366 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1367 int ret = 0;
1368 struct dma_async_tx_descriptor *tx;
1369 dma_cookie_t cookie;
1370 dma_addr_t dma_dst;
1371 struct device *ddev;
1372
1373 if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1374 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1375 return 0;
1376 }
1377
1378 ddev = cqspi->rx_chan->device->dev;
1379 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
1380 if (dma_mapping_error(ddev, dma_dst)) {
1381 dev_err(dev, "dma mapping failed\n");
1382 return -ENOMEM;
1383 }
1384 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1385 len, flags);
1386 if (!tx) {
1387 dev_err(dev, "device_prep_dma_memcpy error\n");
1388 ret = -EIO;
1389 goto err_unmap;
1390 }
1391
1392 tx->callback = cqspi_rx_dma_callback;
1393 tx->callback_param = cqspi;
1394 cookie = tx->tx_submit(tx);
1395 reinit_completion(&cqspi->rx_dma_complete);
1396
1397 ret = dma_submit_error(cookie);
1398 if (ret) {
1399 dev_err(dev, "dma_submit_error %d\n", cookie);
1400 ret = -EIO;
1401 goto err_unmap;
1402 }
1403
1404 dma_async_issue_pending(cqspi->rx_chan);
1405 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1406 msecs_to_jiffies(max_t(size_t, len, 500)))) {
1407 dmaengine_terminate_sync(cqspi->rx_chan);
1408 dev_err(dev, "DMA wait_for_completion_timeout\n");
1409 ret = -ETIMEDOUT;
1410 goto err_unmap;
1411 }
1412
1413 err_unmap:
1414 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
1415
1416 return ret;
1417 }
1418
cqspi_read(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)1419 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
1420 const struct spi_mem_op *op)
1421 {
1422 struct cqspi_st *cqspi = f_pdata->cqspi;
1423 const struct cqspi_driver_platdata *ddata = cqspi->ddata;
1424 loff_t from = op->addr.val;
1425 size_t len = op->data.nbytes;
1426 u_char *buf = op->data.buf.in;
1427 u64 dma_align = (u64)(uintptr_t)buf;
1428 int ret;
1429
1430 ret = cqspi_read_setup(f_pdata, op);
1431 if (ret)
1432 return ret;
1433
1434 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1435 return cqspi_direct_read_execute(f_pdata, buf, from, len);
1436
1437 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
1438 virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0))
1439 return ddata->indirect_read_dma(f_pdata, buf, from, len);
1440
1441 return cqspi_indirect_read_execute(f_pdata, buf, from, len);
1442 }
1443
cqspi_mem_process(struct spi_mem * mem,const struct spi_mem_op * op)1444 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
1445 {
1446 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1447 struct cqspi_flash_pdata *f_pdata;
1448
1449 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];
1450 cqspi_configure(f_pdata, op->max_freq);
1451
1452 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1453 /*
1454 * Performing reads in DAC mode forces to read minimum 4 bytes
1455 * which is unsupported on some flash devices during register
1456 * reads, prefer STIG mode for such small reads.
1457 */
1458 if (!op->addr.nbytes ||
1459 (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX &&
1460 !cqspi->disable_stig_mode))
1461 return cqspi_command_read(f_pdata, op);
1462
1463 return cqspi_read(f_pdata, op);
1464 }
1465
1466 if (!op->addr.nbytes || !op->data.buf.out)
1467 return cqspi_command_write(f_pdata, op);
1468
1469 return cqspi_write(f_pdata, op);
1470 }
1471
cqspi_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)1472 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1473 {
1474 int ret;
1475 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1476 struct device *dev = &cqspi->pdev->dev;
1477 const struct cqspi_driver_platdata *ddata = of_device_get_match_data(dev);
1478
1479 if (refcount_read(&cqspi->inflight_ops) == 0)
1480 return -ENODEV;
1481
1482 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
1483 ret = pm_runtime_resume_and_get(dev);
1484 if (ret) {
1485 dev_err(&mem->spi->dev, "resume failed with %d\n", ret);
1486 return ret;
1487 }
1488 }
1489
1490 if (!refcount_read(&cqspi->refcount))
1491 return -EBUSY;
1492
1493 refcount_inc(&cqspi->inflight_ops);
1494
1495 if (!refcount_read(&cqspi->refcount)) {
1496 if (refcount_read(&cqspi->inflight_ops))
1497 refcount_dec(&cqspi->inflight_ops);
1498 return -EBUSY;
1499 }
1500
1501 ret = cqspi_mem_process(mem, op);
1502
1503 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
1504 pm_runtime_put_autosuspend(dev);
1505
1506 if (ret)
1507 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1508
1509 if (refcount_read(&cqspi->inflight_ops) > 1)
1510 refcount_dec(&cqspi->inflight_ops);
1511
1512 return ret;
1513 }
1514
cqspi_supports_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)1515 static bool cqspi_supports_mem_op(struct spi_mem *mem,
1516 const struct spi_mem_op *op)
1517 {
1518 bool all_true, all_false;
1519
1520 /*
1521 * op->dummy.dtr is required for converting nbytes into ncycles.
1522 * Also, don't check the dtr field of the op phase having zero nbytes.
1523 */
1524 all_true = op->cmd.dtr &&
1525 (!op->addr.nbytes || op->addr.dtr) &&
1526 (!op->dummy.nbytes || op->dummy.dtr) &&
1527 (!op->data.nbytes || op->data.dtr);
1528
1529 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1530 !op->data.dtr;
1531
1532 if (all_true) {
1533 /* Right now we only support 8-8-8 DTR mode. */
1534 if (op->cmd.nbytes && op->cmd.buswidth != 8)
1535 return false;
1536 if (op->addr.nbytes && op->addr.buswidth != 8)
1537 return false;
1538 if (op->data.nbytes && op->data.buswidth != 8)
1539 return false;
1540 } else if (!all_false) {
1541 /* Mixed DTR modes are not supported. */
1542 return false;
1543 }
1544
1545 return spi_mem_default_supports_op(mem, op);
1546 }
1547
cqspi_of_get_flash_pdata(struct platform_device * pdev,struct cqspi_flash_pdata * f_pdata,struct device_node * np)1548 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1549 struct cqspi_flash_pdata *f_pdata,
1550 struct device_node *np)
1551 {
1552 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1553 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1554 return -ENXIO;
1555 }
1556
1557 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1558 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1559 return -ENXIO;
1560 }
1561
1562 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1563 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1564 return -ENXIO;
1565 }
1566
1567 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1568 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1569 return -ENXIO;
1570 }
1571
1572 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1573 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1574 return -ENXIO;
1575 }
1576
1577 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1578 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1579 return -ENXIO;
1580 }
1581
1582 return 0;
1583 }
1584
cqspi_of_get_pdata(struct cqspi_st * cqspi)1585 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1586 {
1587 struct device *dev = &cqspi->pdev->dev;
1588 struct device_node *np = dev->of_node;
1589 u32 id[2];
1590
1591 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1592
1593 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1594 /* Zero signals FIFO depth should be runtime detected. */
1595 cqspi->fifo_depth = 0;
1596 }
1597
1598 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1599 dev_err(dev, "couldn't determine fifo-width\n");
1600 return -ENXIO;
1601 }
1602
1603 if (of_property_read_u32(np, "cdns,trigger-address",
1604 &cqspi->trigger_address)) {
1605 dev_err(dev, "couldn't determine trigger-address\n");
1606 return -ENXIO;
1607 }
1608
1609 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1610 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1611
1612 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1613
1614 if (!of_property_read_u32_array(np, "power-domains", id,
1615 ARRAY_SIZE(id)))
1616 cqspi->pd_dev_id = id[1];
1617
1618 return 0;
1619 }
1620
cqspi_controller_init(struct cqspi_st * cqspi)1621 static void cqspi_controller_init(struct cqspi_st *cqspi)
1622 {
1623 u32 reg;
1624
1625 /* Configure the remap address register, no remap */
1626 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1627
1628 /* Disable all interrupts. */
1629 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1630
1631 /* Configure the SRAM split to 1:1 . */
1632 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1633
1634 /* Load indirect trigger address. */
1635 writel(cqspi->trigger_address,
1636 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1637
1638 /* Program read watermark -- 1/2 of the FIFO. */
1639 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1640 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1641 /* Program write watermark -- 1/8 of the FIFO. */
1642 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1643 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1644
1645 /* Disable direct access controller */
1646 if (!cqspi->use_direct_mode) {
1647 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1648 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1649 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1650 }
1651
1652 /* Enable DMA interface */
1653 if (cqspi->use_dma_read) {
1654 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1655 reg |= CQSPI_REG_CONFIG_DMA_MASK;
1656 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1657 }
1658 }
1659
cqspi_controller_detect_fifo_depth(struct cqspi_st * cqspi)1660 static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi)
1661 {
1662 struct device *dev = &cqspi->pdev->dev;
1663 u32 reg, fifo_depth;
1664
1665 /*
1666 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N
1667 * the FIFO depth.
1668 */
1669 writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1670 reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1671 fifo_depth = reg + 1;
1672
1673 /* FIFO depth of zero means no value from devicetree was provided. */
1674 if (cqspi->fifo_depth == 0) {
1675 cqspi->fifo_depth = fifo_depth;
1676 dev_dbg(dev, "using FIFO depth of %u\n", fifo_depth);
1677 } else if (fifo_depth != cqspi->fifo_depth) {
1678 dev_warn(dev, "detected FIFO depth (%u) different from config (%u)\n",
1679 fifo_depth, cqspi->fifo_depth);
1680 }
1681 }
1682
cqspi_request_mmap_dma(struct cqspi_st * cqspi)1683 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1684 {
1685 dma_cap_mask_t mask;
1686
1687 dma_cap_zero(mask);
1688 dma_cap_set(DMA_MEMCPY, mask);
1689
1690 cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1691 if (IS_ERR(cqspi->rx_chan)) {
1692 int ret = PTR_ERR(cqspi->rx_chan);
1693
1694 cqspi->rx_chan = NULL;
1695 if (ret == -ENODEV) {
1696 /* DMA support is not mandatory */
1697 dev_info(&cqspi->pdev->dev, "No Rx DMA available\n");
1698 return 0;
1699 }
1700
1701 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1702 }
1703 init_completion(&cqspi->rx_dma_complete);
1704
1705 return 0;
1706 }
1707
cqspi_get_name(struct spi_mem * mem)1708 static const char *cqspi_get_name(struct spi_mem *mem)
1709 {
1710 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1711 struct device *dev = &cqspi->pdev->dev;
1712
1713 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
1714 spi_get_chipselect(mem->spi, 0));
1715 }
1716
1717 static const struct spi_controller_mem_ops cqspi_mem_ops = {
1718 .exec_op = cqspi_exec_mem_op,
1719 .get_name = cqspi_get_name,
1720 .supports_op = cqspi_supports_mem_op,
1721 };
1722
1723 static const struct spi_controller_mem_caps cqspi_mem_caps = {
1724 .dtr = true,
1725 .per_op_freq = true,
1726 };
1727
cqspi_setup_flash(struct cqspi_st * cqspi)1728 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1729 {
1730 struct platform_device *pdev = cqspi->pdev;
1731 struct device *dev = &pdev->dev;
1732 struct cqspi_flash_pdata *f_pdata;
1733 int ret, cs, max_cs = -1;
1734
1735 /* Get flash device data */
1736 for_each_available_child_of_node_scoped(dev->of_node, np) {
1737 ret = of_property_read_u32(np, "reg", &cs);
1738 if (ret) {
1739 dev_err(dev, "Couldn't determine chip select.\n");
1740 return ret;
1741 }
1742
1743 if (cs >= cqspi->num_chipselect) {
1744 dev_err(dev, "Chip select %d out of range.\n", cs);
1745 return -EINVAL;
1746 }
1747
1748 max_cs = max_t(int, cs, max_cs);
1749
1750 f_pdata = &cqspi->f_pdata[cs];
1751 f_pdata->cqspi = cqspi;
1752 f_pdata->cs = cs;
1753
1754 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1755 if (ret)
1756 return ret;
1757 }
1758
1759 if (max_cs < 0) {
1760 dev_err(dev, "No flash device declared\n");
1761 return -ENODEV;
1762 }
1763
1764 cqspi->num_chipselect = max_cs + 1;
1765 return 0;
1766 }
1767
cqspi_jh7110_clk_init(struct platform_device * pdev,struct cqspi_st * cqspi)1768 static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi)
1769 {
1770 static struct clk_bulk_data qspiclk[] = {
1771 { .id = "apb" },
1772 { .id = "ahb" },
1773 };
1774
1775 int ret = 0;
1776
1777 ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk);
1778 if (ret) {
1779 dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__);
1780 return ret;
1781 }
1782
1783 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk;
1784 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk;
1785
1786 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]);
1787 if (ret) {
1788 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__);
1789 return ret;
1790 }
1791
1792 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]);
1793 if (ret) {
1794 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__);
1795 goto disable_apb_clk;
1796 }
1797
1798 cqspi->is_jh7110 = true;
1799
1800 return 0;
1801
1802 disable_apb_clk:
1803 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1804
1805 return ret;
1806 }
1807
cqspi_jh7110_disable_clk(struct platform_device * pdev,struct cqspi_st * cqspi)1808 static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi)
1809 {
1810 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]);
1811 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1812 }
cqspi_probe(struct platform_device * pdev)1813 static int cqspi_probe(struct platform_device *pdev)
1814 {
1815 const struct cqspi_driver_platdata *ddata;
1816 struct reset_control *rstc, *rstc_ocp, *rstc_ref;
1817 struct device *dev = &pdev->dev;
1818 struct spi_controller *host;
1819 struct resource *res_ahb;
1820 struct cqspi_st *cqspi;
1821 int ret;
1822 int irq;
1823
1824 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));
1825 if (!host)
1826 return -ENOMEM;
1827
1828 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1829 host->mem_ops = &cqspi_mem_ops;
1830 host->mem_caps = &cqspi_mem_caps;
1831 host->dev.of_node = pdev->dev.of_node;
1832
1833 cqspi = spi_controller_get_devdata(host);
1834
1835 cqspi->pdev = pdev;
1836 cqspi->host = host;
1837 cqspi->is_jh7110 = false;
1838 cqspi->ddata = ddata = of_device_get_match_data(dev);
1839 platform_set_drvdata(pdev, cqspi);
1840
1841 /* Obtain configuration from OF. */
1842 ret = cqspi_of_get_pdata(cqspi);
1843 if (ret) {
1844 dev_err(dev, "Cannot get mandatory OF data.\n");
1845 return -ENODEV;
1846 }
1847
1848 /* Obtain QSPI clock. */
1849 cqspi->clk = devm_clk_get(dev, NULL);
1850 if (IS_ERR(cqspi->clk)) {
1851 dev_err(dev, "Cannot claim QSPI clock.\n");
1852 ret = PTR_ERR(cqspi->clk);
1853 return ret;
1854 }
1855
1856 /* Obtain and remap controller address. */
1857 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
1858 if (IS_ERR(cqspi->iobase)) {
1859 dev_err(dev, "Cannot remap controller address.\n");
1860 ret = PTR_ERR(cqspi->iobase);
1861 return ret;
1862 }
1863
1864 /* Obtain and remap AHB address. */
1865 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);
1866 if (IS_ERR(cqspi->ahb_base)) {
1867 dev_err(dev, "Cannot remap AHB address.\n");
1868 ret = PTR_ERR(cqspi->ahb_base);
1869 return ret;
1870 }
1871 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1872 cqspi->ahb_size = resource_size(res_ahb);
1873
1874 init_completion(&cqspi->transfer_complete);
1875
1876 /* Obtain IRQ line. */
1877 irq = platform_get_irq(pdev, 0);
1878 if (irq < 0)
1879 return -ENXIO;
1880
1881 ret = pm_runtime_set_active(dev);
1882 if (ret)
1883 return ret;
1884
1885
1886 ret = clk_prepare_enable(cqspi->clk);
1887 if (ret) {
1888 dev_err(dev, "Cannot enable QSPI clock.\n");
1889 goto probe_clk_failed;
1890 }
1891
1892 /* Obtain QSPI reset control */
1893 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1894 if (IS_ERR(rstc)) {
1895 ret = PTR_ERR(rstc);
1896 dev_err(dev, "Cannot get QSPI reset.\n");
1897 goto probe_reset_failed;
1898 }
1899
1900 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1901 if (IS_ERR(rstc_ocp)) {
1902 ret = PTR_ERR(rstc_ocp);
1903 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1904 goto probe_reset_failed;
1905 }
1906
1907 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
1908 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
1909 if (IS_ERR(rstc_ref)) {
1910 ret = PTR_ERR(rstc_ref);
1911 dev_err(dev, "Cannot get QSPI REF reset.\n");
1912 goto probe_reset_failed;
1913 }
1914 reset_control_assert(rstc_ref);
1915 reset_control_deassert(rstc_ref);
1916 }
1917
1918 reset_control_assert(rstc);
1919 reset_control_deassert(rstc);
1920
1921 reset_control_assert(rstc_ocp);
1922 reset_control_deassert(rstc_ocp);
1923
1924 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1925 host->max_speed_hz = cqspi->master_ref_clk_hz;
1926
1927 /* write completion is supported by default */
1928 cqspi->wr_completion = true;
1929
1930 if (ddata) {
1931 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1932 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1933 cqspi->master_ref_clk_hz);
1934 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1935 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1936 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_QUAD)
1937 host->mode_bits |= SPI_TX_QUAD;
1938 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {
1939 cqspi->use_direct_mode = true;
1940 cqspi->use_direct_mode_wr = true;
1941 }
1942 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
1943 cqspi->use_dma_read = true;
1944 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
1945 cqspi->wr_completion = false;
1946 if (ddata->quirks & CQSPI_SLOW_SRAM)
1947 cqspi->slow_sram = true;
1948 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)
1949 cqspi->apb_ahb_hazard = true;
1950
1951 if (ddata->jh7110_clk_init) {
1952 ret = cqspi_jh7110_clk_init(pdev, cqspi);
1953 if (ret)
1954 goto probe_reset_failed;
1955 }
1956 if (ddata->quirks & CQSPI_DISABLE_STIG_MODE)
1957 cqspi->disable_stig_mode = true;
1958
1959 if (ddata->quirks & CQSPI_DMA_SET_MASK) {
1960 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1961 if (ret)
1962 goto probe_reset_failed;
1963 }
1964 }
1965
1966 refcount_set(&cqspi->refcount, 1);
1967 refcount_set(&cqspi->inflight_ops, 1);
1968
1969 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1970 pdev->name, cqspi);
1971 if (ret) {
1972 dev_err(dev, "Cannot request IRQ.\n");
1973 goto probe_reset_failed;
1974 }
1975
1976 cqspi_wait_idle(cqspi);
1977 cqspi_controller_enable(cqspi, 0);
1978 cqspi_controller_detect_fifo_depth(cqspi);
1979 cqspi_controller_init(cqspi);
1980 cqspi_controller_enable(cqspi, 1);
1981 cqspi->current_cs = -1;
1982 cqspi->sclk = 0;
1983
1984 ret = cqspi_setup_flash(cqspi);
1985 if (ret) {
1986 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1987 goto probe_setup_failed;
1988 }
1989
1990 host->num_chipselect = cqspi->num_chipselect;
1991
1992 if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET))
1993 cqspi_device_reset(cqspi);
1994
1995 if (cqspi->use_direct_mode) {
1996 ret = cqspi_request_mmap_dma(cqspi);
1997 if (ret == -EPROBE_DEFER)
1998 goto probe_setup_failed;
1999 }
2000
2001 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
2002 pm_runtime_enable(dev);
2003 pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT);
2004 pm_runtime_use_autosuspend(dev);
2005 pm_runtime_get_noresume(dev);
2006 }
2007
2008 ret = spi_register_controller(host);
2009 if (ret) {
2010 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
2011 goto probe_setup_failed;
2012 }
2013
2014 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
2015 pm_runtime_put_autosuspend(dev);
2016 pm_runtime_mark_last_busy(dev);
2017 pm_runtime_put_autosuspend(dev);
2018 }
2019
2020 return 0;
2021 probe_setup_failed:
2022 cqspi_controller_enable(cqspi, 0);
2023 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2024 pm_runtime_disable(dev);
2025 probe_reset_failed:
2026 if (cqspi->is_jh7110)
2027 cqspi_jh7110_disable_clk(pdev, cqspi);
2028 clk_disable_unprepare(cqspi->clk);
2029 probe_clk_failed:
2030 return ret;
2031 }
2032
cqspi_remove(struct platform_device * pdev)2033 static void cqspi_remove(struct platform_device *pdev)
2034 {
2035 const struct cqspi_driver_platdata *ddata;
2036 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
2037 struct device *dev = &pdev->dev;
2038
2039 ddata = of_device_get_match_data(dev);
2040
2041 refcount_set(&cqspi->refcount, 0);
2042
2043 if (!refcount_dec_and_test(&cqspi->inflight_ops))
2044 cqspi_wait_idle(cqspi);
2045
2046 spi_unregister_controller(cqspi->host);
2047 cqspi_controller_enable(cqspi, 0);
2048
2049 if (cqspi->rx_chan)
2050 dma_release_channel(cqspi->rx_chan);
2051
2052 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2053 if (pm_runtime_get_sync(&pdev->dev) >= 0)
2054 clk_disable(cqspi->clk);
2055
2056 if (cqspi->is_jh7110)
2057 cqspi_jh7110_disable_clk(pdev, cqspi);
2058
2059 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
2060 pm_runtime_put_sync(&pdev->dev);
2061 pm_runtime_disable(&pdev->dev);
2062 }
2063 }
2064
cqspi_runtime_suspend(struct device * dev)2065 static int cqspi_runtime_suspend(struct device *dev)
2066 {
2067 struct cqspi_st *cqspi = dev_get_drvdata(dev);
2068
2069 cqspi_controller_enable(cqspi, 0);
2070 clk_disable_unprepare(cqspi->clk);
2071 return 0;
2072 }
2073
cqspi_runtime_resume(struct device * dev)2074 static int cqspi_runtime_resume(struct device *dev)
2075 {
2076 struct cqspi_st *cqspi = dev_get_drvdata(dev);
2077
2078 clk_prepare_enable(cqspi->clk);
2079 cqspi_wait_idle(cqspi);
2080 cqspi_controller_enable(cqspi, 0);
2081 cqspi_controller_init(cqspi);
2082 cqspi_controller_enable(cqspi, 1);
2083
2084 cqspi->current_cs = -1;
2085 cqspi->sclk = 0;
2086 return 0;
2087 }
2088
cqspi_suspend(struct device * dev)2089 static int cqspi_suspend(struct device *dev)
2090 {
2091 struct cqspi_st *cqspi = dev_get_drvdata(dev);
2092 int ret;
2093
2094 ret = spi_controller_suspend(cqspi->host);
2095 if (ret)
2096 return ret;
2097
2098 return pm_runtime_force_suspend(dev);
2099 }
2100
cqspi_resume(struct device * dev)2101 static int cqspi_resume(struct device *dev)
2102 {
2103 struct cqspi_st *cqspi = dev_get_drvdata(dev);
2104 int ret;
2105
2106 ret = pm_runtime_force_resume(dev);
2107 if (ret) {
2108 dev_err(dev, "pm_runtime_force_resume failed on resume\n");
2109 return ret;
2110 }
2111
2112 return spi_controller_resume(cqspi->host);
2113 }
2114
2115 static const struct dev_pm_ops cqspi_dev_pm_ops = {
2116 RUNTIME_PM_OPS(cqspi_runtime_suspend, cqspi_runtime_resume, NULL)
2117 SYSTEM_SLEEP_PM_OPS(cqspi_suspend, cqspi_resume)
2118 };
2119
2120 static const struct cqspi_driver_platdata cdns_qspi = {
2121 .quirks = CQSPI_DISABLE_DAC_MODE,
2122 };
2123
2124 static const struct cqspi_driver_platdata k2g_qspi = {
2125 .quirks = CQSPI_NEEDS_WR_DELAY,
2126 };
2127
2128 static const struct cqspi_driver_platdata am654_ospi = {
2129 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD,
2130 .quirks = CQSPI_NEEDS_WR_DELAY,
2131 };
2132
2133 static const struct cqspi_driver_platdata intel_lgm_qspi = {
2134 .quirks = CQSPI_DISABLE_DAC_MODE,
2135 };
2136
2137 static const struct cqspi_driver_platdata socfpga_qspi = {
2138 .quirks = CQSPI_DISABLE_DAC_MODE
2139 | CQSPI_NO_SUPPORT_WR_COMPLETION
2140 | CQSPI_SLOW_SRAM
2141 | CQSPI_DISABLE_STIG_MODE
2142 | CQSPI_DISABLE_RUNTIME_PM,
2143 };
2144
2145 static const struct cqspi_driver_platdata versal_ospi = {
2146 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
2147 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA
2148 | CQSPI_DMA_SET_MASK,
2149 .indirect_read_dma = cqspi_versal_indirect_read_dma,
2150 .get_dma_status = cqspi_get_versal_dma_status,
2151 };
2152
2153 static const struct cqspi_driver_platdata versal2_ospi = {
2154 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
2155 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA
2156 | CQSPI_DMA_SET_MASK
2157 | CQSPI_SUPPORT_DEVICE_RESET,
2158 .indirect_read_dma = cqspi_versal_indirect_read_dma,
2159 .get_dma_status = cqspi_get_versal_dma_status,
2160 };
2161
2162 static const struct cqspi_driver_platdata jh7110_qspi = {
2163 .quirks = CQSPI_DISABLE_DAC_MODE,
2164 .jh7110_clk_init = cqspi_jh7110_clk_init,
2165 };
2166
2167 static const struct cqspi_driver_platdata pensando_cdns_qspi = {
2168 .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE,
2169 };
2170
2171 static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = {
2172 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
2173 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION |
2174 CQSPI_RD_NO_IRQ,
2175 };
2176
2177 static const struct of_device_id cqspi_dt_ids[] = {
2178 {
2179 .compatible = "cdns,qspi-nor",
2180 .data = &cdns_qspi,
2181 },
2182 {
2183 .compatible = "ti,k2g-qspi",
2184 .data = &k2g_qspi,
2185 },
2186 {
2187 .compatible = "ti,am654-ospi",
2188 .data = &am654_ospi,
2189 },
2190 {
2191 .compatible = "intel,lgm-qspi",
2192 .data = &intel_lgm_qspi,
2193 },
2194 {
2195 .compatible = "xlnx,versal-ospi-1.0",
2196 .data = &versal_ospi,
2197 },
2198 {
2199 .compatible = "intel,socfpga-qspi",
2200 .data = &socfpga_qspi,
2201 },
2202 {
2203 .compatible = "starfive,jh7110-qspi",
2204 .data = &jh7110_qspi,
2205 },
2206 {
2207 .compatible = "amd,pensando-elba-qspi",
2208 .data = &pensando_cdns_qspi,
2209 },
2210 {
2211 .compatible = "mobileye,eyeq5-ospi",
2212 .data = &mobileye_eyeq5_ospi,
2213 },
2214 {
2215 .compatible = "amd,versal2-ospi",
2216 .data = &versal2_ospi,
2217 },
2218 { /* end of table */ }
2219 };
2220
2221 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
2222
2223 static struct platform_driver cqspi_platform_driver = {
2224 .probe = cqspi_probe,
2225 .remove = cqspi_remove,
2226 .driver = {
2227 .name = CQSPI_NAME,
2228 .pm = pm_ptr(&cqspi_dev_pm_ops),
2229 .of_match_table = cqspi_dt_ids,
2230 },
2231 };
2232
2233 module_platform_driver(cqspi_platform_driver);
2234
2235 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
2236 MODULE_LICENSE("GPL v2");
2237 MODULE_ALIAS("platform:" CQSPI_NAME);
2238 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
2239 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
2240 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
2241 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
2242 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");
2243