1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* cp header registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP), 111 /* SE status registers */ 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 113 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 115 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 116 }; 117 118 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 119 /* compute queue registers */ 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 157 }; 158 159 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 160 161 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 162 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 163 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 164 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 165 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 166 struct amdgpu_cu_info *cu_info); 167 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 168 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 169 170 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 171 uint64_t queue_mask) 172 { 173 struct amdgpu_device *adev = kiq_ring->adev; 174 u64 shader_mc_addr; 175 176 /* Cleaner shader MC address */ 177 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 178 179 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 180 amdgpu_ring_write(kiq_ring, 181 PACKET3_SET_RESOURCES_VMID_MASK(0) | 182 /* vmid_mask:0* queue_type:0 (KIQ) */ 183 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 184 amdgpu_ring_write(kiq_ring, 185 lower_32_bits(queue_mask)); /* queue mask lo */ 186 amdgpu_ring_write(kiq_ring, 187 upper_32_bits(queue_mask)); /* queue mask hi */ 188 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 189 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 190 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 191 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 192 } 193 194 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 195 struct amdgpu_ring *ring) 196 { 197 struct amdgpu_device *adev = kiq_ring->adev; 198 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 199 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 200 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 201 202 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 203 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 204 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 205 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 206 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 207 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 208 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 209 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 210 /*queue_type: normal compute queue */ 211 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 212 /* alloc format: all_on_one_pipe */ 213 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 214 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 215 /* num_queues: must be 1 */ 216 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 217 amdgpu_ring_write(kiq_ring, 218 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 219 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 220 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 221 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 222 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 223 } 224 225 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 226 struct amdgpu_ring *ring, 227 enum amdgpu_unmap_queues_action action, 228 u64 gpu_addr, u64 seq) 229 { 230 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 231 232 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 233 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 234 PACKET3_UNMAP_QUEUES_ACTION(action) | 235 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 236 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 237 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 238 amdgpu_ring_write(kiq_ring, 239 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 240 241 if (action == PREEMPT_QUEUES_NO_UNMAP) { 242 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 243 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 244 amdgpu_ring_write(kiq_ring, seq); 245 } else { 246 amdgpu_ring_write(kiq_ring, 0); 247 amdgpu_ring_write(kiq_ring, 0); 248 amdgpu_ring_write(kiq_ring, 0); 249 } 250 } 251 252 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 253 struct amdgpu_ring *ring, 254 u64 addr, 255 u64 seq) 256 { 257 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 258 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 260 amdgpu_ring_write(kiq_ring, 261 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 262 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 263 PACKET3_QUERY_STATUS_COMMAND(2)); 264 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 267 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 268 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 269 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 270 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 271 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 272 } 273 274 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 275 uint16_t pasid, uint32_t flush_type, 276 bool all_hub) 277 { 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 279 amdgpu_ring_write(kiq_ring, 280 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 281 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 282 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 283 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 284 } 285 286 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 287 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 288 uint32_t xcc_id, uint32_t vmid) 289 { 290 struct amdgpu_device *adev = kiq_ring->adev; 291 unsigned i; 292 293 /* enter save mode */ 294 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 295 mutex_lock(&adev->srbm_mutex); 296 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 297 298 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 301 /* wait till dequeue take effects */ 302 for (i = 0; i < adev->usec_timeout; i++) { 303 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 304 break; 305 udelay(1); 306 } 307 if (i >= adev->usec_timeout) 308 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 309 } else { 310 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 311 } 312 313 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 314 mutex_unlock(&adev->srbm_mutex); 315 /* exit safe mode */ 316 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 317 } 318 319 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 320 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 321 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 322 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 323 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 324 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 325 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 326 .set_resources_size = 8, 327 .map_queues_size = 7, 328 .unmap_queues_size = 6, 329 .query_status_size = 7, 330 .invalidate_tlbs_size = 2, 331 }; 332 333 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 334 { 335 int i, num_xcc; 336 337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 338 for (i = 0; i < num_xcc; i++) 339 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 340 } 341 342 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 343 { 344 int i, num_xcc, dev_inst; 345 346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 347 for (i = 0; i < num_xcc; i++) { 348 dev_inst = GET_INST(GC, i); 349 350 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 351 GOLDEN_GB_ADDR_CONFIG); 352 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 353 } 354 } 355 356 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 357 { 358 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 359 360 /* If it is an XCC reg, normalize the reg to keep 361 lower 16 bits in local xcc */ 362 363 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 364 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 365 return normalized_reg; 366 else 367 return reg; 368 } 369 370 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 371 bool wc, uint32_t reg, uint32_t val) 372 { 373 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 374 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 375 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 376 WRITE_DATA_DST_SEL(0) | 377 (wc ? WR_CONFIRM : 0)); 378 amdgpu_ring_write(ring, reg); 379 amdgpu_ring_write(ring, 0); 380 amdgpu_ring_write(ring, val); 381 } 382 383 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 384 int mem_space, int opt, uint32_t addr0, 385 uint32_t addr1, uint32_t ref, uint32_t mask, 386 uint32_t inv) 387 { 388 /* Only do the normalization on regspace */ 389 if (mem_space == 0) { 390 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 391 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 392 } 393 394 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 395 amdgpu_ring_write(ring, 396 /* memory (1) or register (0) */ 397 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 398 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 399 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 400 WAIT_REG_MEM_ENGINE(eng_sel))); 401 402 if (mem_space) 403 BUG_ON(addr0 & 0x3); /* Dword align */ 404 amdgpu_ring_write(ring, addr0); 405 amdgpu_ring_write(ring, addr1); 406 amdgpu_ring_write(ring, ref); 407 amdgpu_ring_write(ring, mask); 408 amdgpu_ring_write(ring, inv); /* poll interval */ 409 } 410 411 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 412 { 413 uint32_t scratch_reg0_offset, xcc_offset; 414 struct amdgpu_device *adev = ring->adev; 415 uint32_t tmp = 0; 416 unsigned i; 417 int r; 418 419 /* Use register offset which is local to XCC in the packet */ 420 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 421 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 422 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 423 tmp = RREG32(scratch_reg0_offset); 424 425 r = amdgpu_ring_alloc(ring, 3); 426 if (r) 427 return r; 428 429 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 430 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 431 amdgpu_ring_write(ring, 0xDEADBEEF); 432 amdgpu_ring_commit(ring); 433 434 for (i = 0; i < adev->usec_timeout; i++) { 435 tmp = RREG32(scratch_reg0_offset); 436 if (tmp == 0xDEADBEEF) 437 break; 438 udelay(1); 439 } 440 441 if (i >= adev->usec_timeout) 442 r = -ETIMEDOUT; 443 return r; 444 } 445 446 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 447 { 448 struct amdgpu_device *adev = ring->adev; 449 struct amdgpu_ib ib; 450 struct dma_fence *f = NULL; 451 452 unsigned index; 453 uint64_t gpu_addr; 454 uint32_t tmp; 455 long r; 456 457 r = amdgpu_device_wb_get(adev, &index); 458 if (r) 459 return r; 460 461 gpu_addr = adev->wb.gpu_addr + (index * 4); 462 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 463 memset(&ib, 0, sizeof(ib)); 464 465 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 466 if (r) 467 goto err1; 468 469 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 470 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 471 ib.ptr[2] = lower_32_bits(gpu_addr); 472 ib.ptr[3] = upper_32_bits(gpu_addr); 473 ib.ptr[4] = 0xDEADBEEF; 474 ib.length_dw = 5; 475 476 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 477 if (r) 478 goto err2; 479 480 r = dma_fence_wait_timeout(f, false, timeout); 481 if (r == 0) { 482 r = -ETIMEDOUT; 483 goto err2; 484 } else if (r < 0) { 485 goto err2; 486 } 487 488 tmp = adev->wb.wb[index]; 489 if (tmp == 0xDEADBEEF) 490 r = 0; 491 else 492 r = -EINVAL; 493 494 err2: 495 amdgpu_ib_free(&ib, NULL); 496 dma_fence_put(f); 497 err1: 498 amdgpu_device_wb_free(adev, index); 499 return r; 500 } 501 502 503 /* This value might differs per partition */ 504 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 505 { 506 uint64_t clock; 507 508 mutex_lock(&adev->gfx.gpu_clock_mutex); 509 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 510 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 511 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 512 mutex_unlock(&adev->gfx.gpu_clock_mutex); 513 514 return clock; 515 } 516 517 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 518 { 519 amdgpu_ucode_release(&adev->gfx.pfp_fw); 520 amdgpu_ucode_release(&adev->gfx.me_fw); 521 amdgpu_ucode_release(&adev->gfx.ce_fw); 522 amdgpu_ucode_release(&adev->gfx.rlc_fw); 523 amdgpu_ucode_release(&adev->gfx.mec_fw); 524 amdgpu_ucode_release(&adev->gfx.mec2_fw); 525 526 kfree(adev->gfx.rlc.register_list_format); 527 } 528 529 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 530 const char *chip_name) 531 { 532 int err; 533 const struct rlc_firmware_header_v2_0 *rlc_hdr; 534 uint16_t version_major; 535 uint16_t version_minor; 536 537 538 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 539 AMDGPU_UCODE_REQUIRED, 540 "amdgpu/%s_rlc.bin", chip_name); 541 if (err) 542 goto out; 543 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 544 545 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 546 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 547 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 548 out: 549 if (err) 550 amdgpu_ucode_release(&adev->gfx.rlc_fw); 551 552 return err; 553 } 554 555 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 556 const char *chip_name) 557 { 558 int err; 559 560 if (amdgpu_sriov_vf(adev)) { 561 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 562 AMDGPU_UCODE_REQUIRED, 563 "amdgpu/%s_sjt_mec.bin", chip_name); 564 565 if (err) 566 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 567 AMDGPU_UCODE_REQUIRED, 568 "amdgpu/%s_mec.bin", chip_name); 569 } else 570 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 571 AMDGPU_UCODE_REQUIRED, 572 "amdgpu/%s_mec.bin", chip_name); 573 if (err) 574 goto out; 575 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 576 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 577 578 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 579 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 580 581 out: 582 if (err) 583 amdgpu_ucode_release(&adev->gfx.mec_fw); 584 return err; 585 } 586 587 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 588 { 589 char ucode_prefix[15]; 590 int r; 591 592 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 593 594 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 595 if (r) 596 return r; 597 598 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 599 if (r) 600 return r; 601 602 return r; 603 } 604 605 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 606 { 607 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 608 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 609 } 610 611 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 612 { 613 int r, i, num_xcc; 614 u32 *hpd; 615 const __le32 *fw_data; 616 unsigned fw_size; 617 u32 *fw; 618 size_t mec_hpd_size; 619 620 const struct gfx_firmware_header_v1_0 *mec_hdr; 621 622 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 623 for (i = 0; i < num_xcc; i++) 624 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 625 AMDGPU_MAX_COMPUTE_QUEUES); 626 627 /* take ownership of the relevant compute queues */ 628 amdgpu_gfx_compute_queue_acquire(adev); 629 mec_hpd_size = 630 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 631 if (mec_hpd_size) { 632 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 633 AMDGPU_GEM_DOMAIN_VRAM | 634 AMDGPU_GEM_DOMAIN_GTT, 635 &adev->gfx.mec.hpd_eop_obj, 636 &adev->gfx.mec.hpd_eop_gpu_addr, 637 (void **)&hpd); 638 if (r) { 639 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 640 gfx_v9_4_3_mec_fini(adev); 641 return r; 642 } 643 644 if (amdgpu_emu_mode == 1) { 645 for (i = 0; i < mec_hpd_size / 4; i++) { 646 memset((void *)(hpd + i), 0, 4); 647 if (i % 50 == 0) 648 msleep(1); 649 } 650 } else { 651 memset(hpd, 0, mec_hpd_size); 652 } 653 654 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 655 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 656 } 657 658 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 659 660 fw_data = (const __le32 *) 661 (adev->gfx.mec_fw->data + 662 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 663 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 664 665 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 666 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 667 &adev->gfx.mec.mec_fw_obj, 668 &adev->gfx.mec.mec_fw_gpu_addr, 669 (void **)&fw); 670 if (r) { 671 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 672 gfx_v9_4_3_mec_fini(adev); 673 return r; 674 } 675 676 memcpy(fw, fw_data, fw_size); 677 678 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 679 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 680 681 return 0; 682 } 683 684 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 685 u32 sh_num, u32 instance, int xcc_id) 686 { 687 u32 data; 688 689 if (instance == 0xffffffff) 690 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 691 INSTANCE_BROADCAST_WRITES, 1); 692 else 693 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 694 INSTANCE_INDEX, instance); 695 696 if (se_num == 0xffffffff) 697 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 698 SE_BROADCAST_WRITES, 1); 699 else 700 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 701 702 if (sh_num == 0xffffffff) 703 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 704 SH_BROADCAST_WRITES, 1); 705 else 706 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 707 708 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 709 } 710 711 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 712 { 713 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 714 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 715 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 716 (address << SQ_IND_INDEX__INDEX__SHIFT) | 717 (SQ_IND_INDEX__FORCE_READ_MASK)); 718 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 719 } 720 721 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 722 uint32_t wave, uint32_t thread, 723 uint32_t regno, uint32_t num, uint32_t *out) 724 { 725 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 726 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 727 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 728 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 729 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 730 (SQ_IND_INDEX__FORCE_READ_MASK) | 731 (SQ_IND_INDEX__AUTO_INCR_MASK)); 732 while (num--) 733 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 734 } 735 736 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 737 uint32_t xcc_id, uint32_t simd, uint32_t wave, 738 uint32_t *dst, int *no_fields) 739 { 740 /* type 1 wave data */ 741 dst[(*no_fields)++] = 1; 742 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 743 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 744 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 745 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 746 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 757 } 758 759 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 760 uint32_t wave, uint32_t start, 761 uint32_t size, uint32_t *dst) 762 { 763 wave_read_regs(adev, xcc_id, simd, wave, 0, 764 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 765 } 766 767 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 768 uint32_t wave, uint32_t thread, 769 uint32_t start, uint32_t size, 770 uint32_t *dst) 771 { 772 wave_read_regs(adev, xcc_id, simd, wave, thread, 773 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 774 } 775 776 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 777 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 778 { 779 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 780 } 781 782 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 783 { 784 u32 xcp_ctl; 785 786 /* Value is expected to be the same on all, fetch from first instance */ 787 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 788 789 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 790 } 791 792 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 793 int num_xccs_per_xcp) 794 { 795 int ret, i, num_xcc; 796 u32 tmp = 0; 797 798 if (adev->psp.funcs) { 799 ret = psp_spatial_partition(&adev->psp, 800 NUM_XCC(adev->gfx.xcc_mask) / 801 num_xccs_per_xcp); 802 if (ret) 803 return ret; 804 } else { 805 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 806 807 for (i = 0; i < num_xcc; i++) { 808 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 809 num_xccs_per_xcp); 810 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 811 i % num_xccs_per_xcp); 812 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 813 tmp); 814 } 815 ret = 0; 816 } 817 818 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 819 820 return ret; 821 } 822 823 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 824 { 825 int xcc; 826 827 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 828 if (!xcc) { 829 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 830 return -EINVAL; 831 } 832 833 return xcc - 1; 834 } 835 836 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 837 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 838 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 839 .read_wave_data = &gfx_v9_4_3_read_wave_data, 840 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 841 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 842 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 843 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 844 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 845 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 846 }; 847 848 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 849 struct aca_bank *bank, enum aca_smu_type type, 850 void *data) 851 { 852 struct aca_bank_info info; 853 u64 misc0; 854 u32 instlo; 855 int ret; 856 857 ret = aca_bank_info_decode(bank, &info); 858 if (ret) 859 return ret; 860 861 /* NOTE: overwrite info.die_id with xcd id for gfx */ 862 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 863 instlo &= GENMASK(31, 1); 864 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 865 866 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 867 868 switch (type) { 869 case ACA_SMU_TYPE_UE: 870 bank->aca_err_type = ACA_BANK_ERR_UE_DE_DECODE(bank); 871 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL); 872 break; 873 case ACA_SMU_TYPE_CE: 874 bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank); 875 ret = aca_error_cache_log_bank_error(handle, &info, 876 bank->aca_err_type, 877 ACA_REG__MISC0__ERRCNT(misc0)); 878 break; 879 default: 880 return -EINVAL; 881 } 882 883 return ret; 884 } 885 886 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 887 enum aca_smu_type type, void *data) 888 { 889 u32 instlo; 890 891 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 892 instlo &= GENMASK(31, 1); 893 switch (instlo) { 894 case mmSMNAID_XCD0_MCA_SMU: 895 case mmSMNAID_XCD1_MCA_SMU: 896 case mmSMNXCD_XCD0_MCA_SMU: 897 return true; 898 default: 899 break; 900 } 901 902 return false; 903 } 904 905 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 906 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 907 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 908 }; 909 910 static const struct aca_info gfx_v9_4_3_aca_info = { 911 .hwip = ACA_HWIP_TYPE_SMU, 912 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 913 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 914 }; 915 916 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 917 { 918 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 919 adev->gfx.ras = &gfx_v9_4_3_ras; 920 921 adev->gfx.config.max_hw_contexts = 8; 922 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 923 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 924 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 925 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 926 adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG; 927 928 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 929 REG_GET_FIELD( 930 adev->gfx.config.gb_addr_config, 931 GB_ADDR_CONFIG, 932 NUM_PIPES); 933 934 adev->gfx.config.max_tile_pipes = 935 adev->gfx.config.gb_addr_config_fields.num_pipes; 936 937 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 938 REG_GET_FIELD( 939 adev->gfx.config.gb_addr_config, 940 GB_ADDR_CONFIG, 941 NUM_BANKS); 942 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 943 REG_GET_FIELD( 944 adev->gfx.config.gb_addr_config, 945 GB_ADDR_CONFIG, 946 MAX_COMPRESSED_FRAGS); 947 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 948 REG_GET_FIELD( 949 adev->gfx.config.gb_addr_config, 950 GB_ADDR_CONFIG, 951 NUM_RB_PER_SE); 952 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 953 REG_GET_FIELD( 954 adev->gfx.config.gb_addr_config, 955 GB_ADDR_CONFIG, 956 NUM_SHADER_ENGINES); 957 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 958 REG_GET_FIELD( 959 adev->gfx.config.gb_addr_config, 960 GB_ADDR_CONFIG, 961 PIPE_INTERLEAVE_SIZE)); 962 963 return 0; 964 } 965 966 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 967 int xcc_id, int mec, int pipe, int queue) 968 { 969 unsigned irq_type; 970 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 971 unsigned int hw_prio; 972 uint32_t xcc_doorbell_start; 973 974 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 975 ring_id]; 976 977 /* mec0 is me1 */ 978 ring->xcc_id = xcc_id; 979 ring->me = mec + 1; 980 ring->pipe = pipe; 981 ring->queue = queue; 982 983 ring->ring_obj = NULL; 984 ring->use_doorbell = true; 985 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 986 xcc_id * adev->doorbell_index.xcc_doorbell_range; 987 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 988 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 989 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 990 GFX9_MEC_HPD_SIZE; 991 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 992 sprintf(ring->name, "comp_%d.%d.%d.%d", 993 ring->xcc_id, ring->me, ring->pipe, ring->queue); 994 995 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 996 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 997 + ring->pipe; 998 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 999 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1000 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1001 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1002 hw_prio, NULL); 1003 } 1004 1005 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1006 { 1007 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1008 uint32_t *ptr, num_xcc, inst; 1009 1010 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1011 1012 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1013 if (!ptr) { 1014 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1015 adev->gfx.ip_dump_core = NULL; 1016 } else { 1017 adev->gfx.ip_dump_core = ptr; 1018 } 1019 1020 /* Allocate memory for compute queue registers for all the instances */ 1021 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1022 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1023 adev->gfx.mec.num_queue_per_pipe; 1024 1025 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1026 if (!ptr) { 1027 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1028 adev->gfx.ip_dump_compute_queues = NULL; 1029 } else { 1030 adev->gfx.ip_dump_compute_queues = ptr; 1031 } 1032 } 1033 1034 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1035 { 1036 int i, j, k, r, ring_id, xcc_id, num_xcc; 1037 struct amdgpu_device *adev = ip_block->adev; 1038 1039 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1040 case IP_VERSION(9, 4, 3): 1041 case IP_VERSION(9, 4, 4): 1042 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1043 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1044 if (adev->gfx.mec_fw_version >= 153) { 1045 adev->gfx.enable_cleaner_shader = true; 1046 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1047 if (r) { 1048 adev->gfx.enable_cleaner_shader = false; 1049 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1050 } 1051 } 1052 break; 1053 default: 1054 adev->gfx.enable_cleaner_shader = false; 1055 break; 1056 } 1057 1058 adev->gfx.mec.num_mec = 2; 1059 adev->gfx.mec.num_pipe_per_mec = 4; 1060 adev->gfx.mec.num_queue_per_pipe = 8; 1061 1062 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1063 1064 /* EOP Event */ 1065 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1066 if (r) 1067 return r; 1068 1069 /* Bad opcode Event */ 1070 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1071 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1072 &adev->gfx.bad_op_irq); 1073 if (r) 1074 return r; 1075 1076 /* Privileged reg */ 1077 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1078 &adev->gfx.priv_reg_irq); 1079 if (r) 1080 return r; 1081 1082 /* Privileged inst */ 1083 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1084 &adev->gfx.priv_inst_irq); 1085 if (r) 1086 return r; 1087 1088 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1089 1090 r = adev->gfx.rlc.funcs->init(adev); 1091 if (r) { 1092 DRM_ERROR("Failed to init rlc BOs!\n"); 1093 return r; 1094 } 1095 1096 r = gfx_v9_4_3_mec_init(adev); 1097 if (r) { 1098 DRM_ERROR("Failed to init MEC BOs!\n"); 1099 return r; 1100 } 1101 1102 /* set up the compute queues - allocate horizontally across pipes */ 1103 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1104 ring_id = 0; 1105 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1106 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1107 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1108 k++) { 1109 if (!amdgpu_gfx_is_mec_queue_enabled( 1110 adev, xcc_id, i, k, j)) 1111 continue; 1112 1113 r = gfx_v9_4_3_compute_ring_init(adev, 1114 ring_id, 1115 xcc_id, 1116 i, k, j); 1117 if (r) 1118 return r; 1119 1120 ring_id++; 1121 } 1122 } 1123 } 1124 1125 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1126 if (r) { 1127 DRM_ERROR("Failed to init KIQ BOs!\n"); 1128 return r; 1129 } 1130 1131 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1132 if (r) 1133 return r; 1134 1135 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1136 r = amdgpu_gfx_mqd_sw_init(adev, 1137 sizeof(struct v9_mqd_allocation), xcc_id); 1138 if (r) 1139 return r; 1140 } 1141 1142 adev->gfx.compute_supported_reset = 1143 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1144 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1145 case IP_VERSION(9, 4, 3): 1146 case IP_VERSION(9, 4, 4): 1147 if (adev->gfx.mec_fw_version >= 155) { 1148 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1149 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1150 } 1151 break; 1152 default: 1153 break; 1154 } 1155 r = gfx_v9_4_3_gpu_early_init(adev); 1156 if (r) 1157 return r; 1158 1159 r = amdgpu_gfx_ras_sw_init(adev); 1160 if (r) 1161 return r; 1162 1163 r = amdgpu_gfx_sysfs_init(adev); 1164 if (r) 1165 return r; 1166 1167 gfx_v9_4_3_alloc_ip_dump(adev); 1168 1169 return 0; 1170 } 1171 1172 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1173 { 1174 int i, num_xcc; 1175 struct amdgpu_device *adev = ip_block->adev; 1176 1177 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1178 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1179 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1180 1181 for (i = 0; i < num_xcc; i++) { 1182 amdgpu_gfx_mqd_sw_fini(adev, i); 1183 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1184 amdgpu_gfx_kiq_fini(adev, i); 1185 } 1186 1187 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1188 1189 gfx_v9_4_3_mec_fini(adev); 1190 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1191 gfx_v9_4_3_free_microcode(adev); 1192 amdgpu_gfx_sysfs_fini(adev); 1193 1194 kfree(adev->gfx.ip_dump_core); 1195 kfree(adev->gfx.ip_dump_compute_queues); 1196 1197 return 0; 1198 } 1199 1200 #define DEFAULT_SH_MEM_BASES (0x6000) 1201 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1202 int xcc_id) 1203 { 1204 int i; 1205 uint32_t sh_mem_config; 1206 uint32_t sh_mem_bases; 1207 uint32_t data; 1208 1209 /* 1210 * Configure apertures: 1211 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1212 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1213 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1214 */ 1215 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1216 1217 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1218 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1219 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1220 1221 mutex_lock(&adev->srbm_mutex); 1222 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1223 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1224 /* CP and shaders */ 1225 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1226 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1227 1228 /* Enable trap for each kfd vmid. */ 1229 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1230 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1231 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1232 } 1233 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1234 mutex_unlock(&adev->srbm_mutex); 1235 1236 /* 1237 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1238 * access. These should be enabled by FW for target VMIDs. 1239 */ 1240 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1241 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1242 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1243 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1244 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1245 } 1246 } 1247 1248 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1249 { 1250 int vmid; 1251 1252 /* 1253 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1254 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1255 * the driver can enable them for graphics. VMID0 should maintain 1256 * access so that HWS firmware can save/restore entries. 1257 */ 1258 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1259 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1260 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1261 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1262 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1263 } 1264 } 1265 1266 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1267 int xcc_id) 1268 { 1269 u32 tmp; 1270 int i; 1271 1272 /* XXX SH_MEM regs */ 1273 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1274 mutex_lock(&adev->srbm_mutex); 1275 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1276 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1277 /* CP and shaders */ 1278 if (i == 0) { 1279 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1280 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1281 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1282 !!adev->gmc.noretry); 1283 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1284 regSH_MEM_CONFIG, tmp); 1285 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1286 regSH_MEM_BASES, 0); 1287 } else { 1288 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1289 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1290 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1291 !!adev->gmc.noretry); 1292 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1293 regSH_MEM_CONFIG, tmp); 1294 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1295 (adev->gmc.private_aperture_start >> 1296 48)); 1297 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1298 (adev->gmc.shared_aperture_start >> 1299 48)); 1300 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1301 regSH_MEM_BASES, tmp); 1302 } 1303 } 1304 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1305 1306 mutex_unlock(&adev->srbm_mutex); 1307 1308 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1309 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1310 } 1311 1312 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1313 { 1314 int i, num_xcc; 1315 1316 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1317 1318 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1319 adev->gfx.config.db_debug2 = 1320 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1321 1322 for (i = 0; i < num_xcc; i++) 1323 gfx_v9_4_3_xcc_constants_init(adev, i); 1324 } 1325 1326 static void 1327 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1328 int xcc_id) 1329 { 1330 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1331 } 1332 1333 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1334 { 1335 /* 1336 * Rlc save restore list is workable since v2_1. 1337 */ 1338 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1339 } 1340 1341 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1342 { 1343 uint32_t data; 1344 1345 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1346 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1347 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1348 } 1349 1350 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1351 { 1352 uint32_t rlc_setting; 1353 1354 /* if RLC is not enabled, do nothing */ 1355 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1356 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1357 return false; 1358 1359 return true; 1360 } 1361 1362 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1363 { 1364 uint32_t data; 1365 unsigned i; 1366 1367 data = RLC_SAFE_MODE__CMD_MASK; 1368 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1369 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1370 1371 /* wait for RLC_SAFE_MODE */ 1372 for (i = 0; i < adev->usec_timeout; i++) { 1373 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1374 break; 1375 udelay(1); 1376 } 1377 } 1378 1379 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1380 int xcc_id) 1381 { 1382 uint32_t data; 1383 1384 data = RLC_SAFE_MODE__CMD_MASK; 1385 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1386 } 1387 1388 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1389 { 1390 int xcc_id, num_xcc; 1391 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1392 1393 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1394 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1395 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1396 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1397 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1398 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1399 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1400 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1401 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1402 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1403 } 1404 adev->gfx.rlc.rlcg_reg_access_supported = true; 1405 } 1406 1407 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1408 { 1409 /* init spm vmid with 0xf */ 1410 if (adev->gfx.rlc.funcs->update_spm_vmid) 1411 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1412 1413 return 0; 1414 } 1415 1416 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1417 int xcc_id) 1418 { 1419 u32 i, j, k; 1420 u32 mask; 1421 1422 mutex_lock(&adev->grbm_idx_mutex); 1423 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1424 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1425 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1426 xcc_id); 1427 for (k = 0; k < adev->usec_timeout; k++) { 1428 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1429 break; 1430 udelay(1); 1431 } 1432 if (k == adev->usec_timeout) { 1433 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1434 0xffffffff, 1435 0xffffffff, xcc_id); 1436 mutex_unlock(&adev->grbm_idx_mutex); 1437 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1438 i, j); 1439 return; 1440 } 1441 } 1442 } 1443 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1444 xcc_id); 1445 mutex_unlock(&adev->grbm_idx_mutex); 1446 1447 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1448 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1449 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1450 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1451 for (k = 0; k < adev->usec_timeout; k++) { 1452 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1453 break; 1454 udelay(1); 1455 } 1456 } 1457 1458 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1459 bool enable, int xcc_id) 1460 { 1461 u32 tmp; 1462 1463 /* These interrupts should be enabled to drive DS clock */ 1464 1465 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1466 1467 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1468 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1469 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1470 1471 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1472 } 1473 1474 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1475 { 1476 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1477 RLC_ENABLE_F32, 0); 1478 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1479 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1480 } 1481 1482 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1483 { 1484 int i, num_xcc; 1485 1486 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1487 for (i = 0; i < num_xcc; i++) 1488 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1489 } 1490 1491 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1492 { 1493 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1494 SOFT_RESET_RLC, 1); 1495 udelay(50); 1496 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1497 SOFT_RESET_RLC, 0); 1498 udelay(50); 1499 } 1500 1501 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1502 { 1503 int i, num_xcc; 1504 1505 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1506 for (i = 0; i < num_xcc; i++) 1507 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1508 } 1509 1510 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1511 { 1512 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1513 RLC_ENABLE_F32, 1); 1514 udelay(50); 1515 1516 /* carrizo do enable cp interrupt after cp inited */ 1517 if (!(adev->flags & AMD_IS_APU)) { 1518 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1519 udelay(50); 1520 } 1521 } 1522 1523 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1524 { 1525 #ifdef AMDGPU_RLC_DEBUG_RETRY 1526 u32 rlc_ucode_ver; 1527 #endif 1528 int i, num_xcc; 1529 1530 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1531 for (i = 0; i < num_xcc; i++) { 1532 gfx_v9_4_3_xcc_rlc_start(adev, i); 1533 #ifdef AMDGPU_RLC_DEBUG_RETRY 1534 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1535 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1536 if (rlc_ucode_ver == 0x108) { 1537 dev_info(adev->dev, 1538 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1539 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1540 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1541 * default is 0x9C4 to create a 100us interval */ 1542 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1543 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1544 * to disable the page fault retry interrupts, default is 1545 * 0x100 (256) */ 1546 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1547 } 1548 #endif 1549 } 1550 } 1551 1552 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1553 int xcc_id) 1554 { 1555 const struct rlc_firmware_header_v2_0 *hdr; 1556 const __le32 *fw_data; 1557 unsigned i, fw_size; 1558 1559 if (!adev->gfx.rlc_fw) 1560 return -EINVAL; 1561 1562 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1563 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1564 1565 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1566 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1567 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1568 1569 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1570 RLCG_UCODE_LOADING_START_ADDRESS); 1571 for (i = 0; i < fw_size; i++) { 1572 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1573 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1574 msleep(1); 1575 } 1576 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1577 } 1578 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1579 1580 return 0; 1581 } 1582 1583 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1584 { 1585 int r; 1586 1587 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1588 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1589 /* legacy rlc firmware loading */ 1590 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1591 if (r) 1592 return r; 1593 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1594 } 1595 1596 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1597 /* disable CG */ 1598 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1599 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1600 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1601 1602 return 0; 1603 } 1604 1605 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1606 { 1607 int r, i, num_xcc; 1608 1609 if (amdgpu_sriov_vf(adev)) 1610 return 0; 1611 1612 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1613 for (i = 0; i < num_xcc; i++) { 1614 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1615 if (r) 1616 return r; 1617 } 1618 1619 return 0; 1620 } 1621 1622 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1623 unsigned vmid) 1624 { 1625 u32 reg, pre_data, data; 1626 1627 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1628 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1629 pre_data = RREG32_NO_KIQ(reg); 1630 else 1631 pre_data = RREG32(reg); 1632 1633 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1634 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1635 1636 if (pre_data != data) { 1637 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1638 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1639 } else 1640 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1641 } 1642 } 1643 1644 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1645 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1646 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1647 }; 1648 1649 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1650 uint32_t offset, 1651 struct soc15_reg_rlcg *entries, int arr_size) 1652 { 1653 int i, inst; 1654 uint32_t reg; 1655 1656 if (!entries) 1657 return false; 1658 1659 for (i = 0; i < arr_size; i++) { 1660 const struct soc15_reg_rlcg *entry; 1661 1662 entry = &entries[i]; 1663 inst = adev->ip_map.logical_to_dev_inst ? 1664 adev->ip_map.logical_to_dev_inst( 1665 adev, entry->hwip, entry->instance) : 1666 entry->instance; 1667 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1668 entry->reg; 1669 if (offset == reg) 1670 return true; 1671 } 1672 1673 return false; 1674 } 1675 1676 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1677 { 1678 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1679 (void *)rlcg_access_gc_9_4_3, 1680 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1681 } 1682 1683 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1684 bool enable, int xcc_id) 1685 { 1686 if (enable) { 1687 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1688 } else { 1689 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1690 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1691 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1692 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1693 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1694 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1695 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1696 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1697 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1698 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1699 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1700 } 1701 udelay(50); 1702 } 1703 1704 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1705 int xcc_id) 1706 { 1707 const struct gfx_firmware_header_v1_0 *mec_hdr; 1708 const __le32 *fw_data; 1709 unsigned i; 1710 u32 tmp; 1711 u32 mec_ucode_addr_offset; 1712 u32 mec_ucode_data_offset; 1713 1714 if (!adev->gfx.mec_fw) 1715 return -EINVAL; 1716 1717 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1718 1719 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1720 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1721 1722 fw_data = (const __le32 *) 1723 (adev->gfx.mec_fw->data + 1724 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1725 tmp = 0; 1726 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1727 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1728 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1729 1730 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1731 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1732 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1733 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1734 1735 mec_ucode_addr_offset = 1736 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1737 mec_ucode_data_offset = 1738 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1739 1740 /* MEC1 */ 1741 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1742 for (i = 0; i < mec_hdr->jt_size; i++) 1743 WREG32(mec_ucode_data_offset, 1744 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1745 1746 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1747 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1748 1749 return 0; 1750 } 1751 1752 /* KIQ functions */ 1753 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1754 { 1755 uint32_t tmp; 1756 struct amdgpu_device *adev = ring->adev; 1757 1758 /* tell RLC which is KIQ queue */ 1759 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1760 tmp &= 0xffffff00; 1761 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1762 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1763 } 1764 1765 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1766 { 1767 struct amdgpu_device *adev = ring->adev; 1768 1769 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1770 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1771 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1772 mqd->cp_hqd_queue_priority = 1773 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1774 } 1775 } 1776 } 1777 1778 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1779 { 1780 struct amdgpu_device *adev = ring->adev; 1781 struct v9_mqd *mqd = ring->mqd_ptr; 1782 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1783 uint32_t tmp; 1784 1785 mqd->header = 0xC0310800; 1786 mqd->compute_pipelinestat_enable = 0x00000001; 1787 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1788 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1789 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1790 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1791 mqd->compute_misc_reserved = 0x00000003; 1792 1793 mqd->dynamic_cu_mask_addr_lo = 1794 lower_32_bits(ring->mqd_gpu_addr 1795 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1796 mqd->dynamic_cu_mask_addr_hi = 1797 upper_32_bits(ring->mqd_gpu_addr 1798 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1799 1800 eop_base_addr = ring->eop_gpu_addr >> 8; 1801 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1802 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1803 1804 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1805 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1806 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1807 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1808 1809 mqd->cp_hqd_eop_control = tmp; 1810 1811 /* enable doorbell? */ 1812 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1813 1814 if (ring->use_doorbell) { 1815 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1816 DOORBELL_OFFSET, ring->doorbell_index); 1817 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1818 DOORBELL_EN, 1); 1819 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1820 DOORBELL_SOURCE, 0); 1821 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1822 DOORBELL_HIT, 0); 1823 if (amdgpu_sriov_multi_vf_mode(adev)) 1824 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1825 DOORBELL_MODE, 1); 1826 } else { 1827 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1828 DOORBELL_EN, 0); 1829 } 1830 1831 mqd->cp_hqd_pq_doorbell_control = tmp; 1832 1833 /* disable the queue if it's active */ 1834 ring->wptr = 0; 1835 mqd->cp_hqd_dequeue_request = 0; 1836 mqd->cp_hqd_pq_rptr = 0; 1837 mqd->cp_hqd_pq_wptr_lo = 0; 1838 mqd->cp_hqd_pq_wptr_hi = 0; 1839 1840 /* set the pointer to the MQD */ 1841 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1842 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1843 1844 /* set MQD vmid to 0 */ 1845 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1846 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1847 mqd->cp_mqd_control = tmp; 1848 1849 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1850 hqd_gpu_addr = ring->gpu_addr >> 8; 1851 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1852 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1853 1854 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1855 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1856 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1857 (order_base_2(ring->ring_size / 4) - 1)); 1858 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1859 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1860 #ifdef __BIG_ENDIAN 1861 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1862 #endif 1863 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1864 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1866 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1867 mqd->cp_hqd_pq_control = tmp; 1868 1869 /* set the wb address whether it's enabled or not */ 1870 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1871 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1872 mqd->cp_hqd_pq_rptr_report_addr_hi = 1873 upper_32_bits(wb_gpu_addr) & 0xffff; 1874 1875 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1876 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1877 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1878 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1879 1880 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1881 ring->wptr = 0; 1882 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1883 1884 /* set the vmid for the queue */ 1885 mqd->cp_hqd_vmid = 0; 1886 1887 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1888 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1889 mqd->cp_hqd_persistent_state = tmp; 1890 1891 /* set MIN_IB_AVAIL_SIZE */ 1892 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1893 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1894 mqd->cp_hqd_ib_control = tmp; 1895 1896 /* set static priority for a queue/ring */ 1897 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1898 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1899 1900 /* map_queues packet doesn't need activate the queue, 1901 * so only kiq need set this field. 1902 */ 1903 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1904 mqd->cp_hqd_active = 1; 1905 1906 return 0; 1907 } 1908 1909 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1910 int xcc_id) 1911 { 1912 struct amdgpu_device *adev = ring->adev; 1913 struct v9_mqd *mqd = ring->mqd_ptr; 1914 int j; 1915 1916 /* disable wptr polling */ 1917 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1918 1919 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1920 mqd->cp_hqd_eop_base_addr_lo); 1921 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1922 mqd->cp_hqd_eop_base_addr_hi); 1923 1924 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1925 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1926 mqd->cp_hqd_eop_control); 1927 1928 /* enable doorbell? */ 1929 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1930 mqd->cp_hqd_pq_doorbell_control); 1931 1932 /* disable the queue if it's active */ 1933 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1934 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1935 for (j = 0; j < adev->usec_timeout; j++) { 1936 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1937 break; 1938 udelay(1); 1939 } 1940 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1941 mqd->cp_hqd_dequeue_request); 1942 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1943 mqd->cp_hqd_pq_rptr); 1944 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1945 mqd->cp_hqd_pq_wptr_lo); 1946 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1947 mqd->cp_hqd_pq_wptr_hi); 1948 } 1949 1950 /* set the pointer to the MQD */ 1951 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1952 mqd->cp_mqd_base_addr_lo); 1953 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1954 mqd->cp_mqd_base_addr_hi); 1955 1956 /* set MQD vmid to 0 */ 1957 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1958 mqd->cp_mqd_control); 1959 1960 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1961 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1962 mqd->cp_hqd_pq_base_lo); 1963 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1964 mqd->cp_hqd_pq_base_hi); 1965 1966 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1967 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1968 mqd->cp_hqd_pq_control); 1969 1970 /* set the wb address whether it's enabled or not */ 1971 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1972 mqd->cp_hqd_pq_rptr_report_addr_lo); 1973 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1974 mqd->cp_hqd_pq_rptr_report_addr_hi); 1975 1976 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1977 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1978 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1979 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1980 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1981 1982 /* enable the doorbell if requested */ 1983 if (ring->use_doorbell) { 1984 WREG32_SOC15( 1985 GC, GET_INST(GC, xcc_id), 1986 regCP_MEC_DOORBELL_RANGE_LOWER, 1987 ((adev->doorbell_index.kiq + 1988 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1989 2) << 2); 1990 WREG32_SOC15( 1991 GC, GET_INST(GC, xcc_id), 1992 regCP_MEC_DOORBELL_RANGE_UPPER, 1993 ((adev->doorbell_index.userqueue_end + 1994 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1995 2) << 2); 1996 } 1997 1998 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1999 mqd->cp_hqd_pq_doorbell_control); 2000 2001 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2002 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2003 mqd->cp_hqd_pq_wptr_lo); 2004 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2005 mqd->cp_hqd_pq_wptr_hi); 2006 2007 /* set the vmid for the queue */ 2008 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2009 2010 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2011 mqd->cp_hqd_persistent_state); 2012 2013 /* activate the queue */ 2014 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2015 mqd->cp_hqd_active); 2016 2017 if (ring->use_doorbell) 2018 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2019 2020 return 0; 2021 } 2022 2023 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2024 int xcc_id) 2025 { 2026 struct amdgpu_device *adev = ring->adev; 2027 int j; 2028 2029 /* disable the queue if it's active */ 2030 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2031 2032 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2033 2034 for (j = 0; j < adev->usec_timeout; j++) { 2035 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2036 break; 2037 udelay(1); 2038 } 2039 2040 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2041 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2042 2043 /* Manual disable if dequeue request times out */ 2044 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2045 } 2046 2047 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2048 0); 2049 } 2050 2051 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2052 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2053 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2054 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2055 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2056 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2057 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2058 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2059 2060 return 0; 2061 } 2062 2063 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2064 { 2065 struct amdgpu_device *adev = ring->adev; 2066 struct v9_mqd *mqd = ring->mqd_ptr; 2067 struct v9_mqd *tmp_mqd; 2068 2069 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2070 2071 /* GPU could be in bad state during probe, driver trigger the reset 2072 * after load the SMU, in this case , the mqd is not be initialized. 2073 * driver need to re-init the mqd. 2074 * check mqd->cp_hqd_pq_control since this value should not be 0 2075 */ 2076 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2077 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2078 /* for GPU_RESET case , reset MQD to a clean status */ 2079 if (adev->gfx.kiq[xcc_id].mqd_backup) 2080 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2081 2082 /* reset ring buffer */ 2083 ring->wptr = 0; 2084 amdgpu_ring_clear_ring(ring); 2085 mutex_lock(&adev->srbm_mutex); 2086 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2087 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2088 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2089 mutex_unlock(&adev->srbm_mutex); 2090 } else { 2091 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2092 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2093 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2094 mutex_lock(&adev->srbm_mutex); 2095 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2096 amdgpu_ring_clear_ring(ring); 2097 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2098 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2099 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2100 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2101 mutex_unlock(&adev->srbm_mutex); 2102 2103 if (adev->gfx.kiq[xcc_id].mqd_backup) 2104 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2105 } 2106 2107 return 0; 2108 } 2109 2110 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) 2111 { 2112 struct amdgpu_device *adev = ring->adev; 2113 struct v9_mqd *mqd = ring->mqd_ptr; 2114 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2115 struct v9_mqd *tmp_mqd; 2116 2117 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2118 * is not be initialized before 2119 */ 2120 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2121 2122 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2123 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2124 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2125 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2126 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2127 mutex_lock(&adev->srbm_mutex); 2128 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2129 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2130 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2131 mutex_unlock(&adev->srbm_mutex); 2132 2133 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2134 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2135 } else { 2136 /* restore MQD to a clean status */ 2137 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2138 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2139 /* reset ring buffer */ 2140 ring->wptr = 0; 2141 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2142 amdgpu_ring_clear_ring(ring); 2143 } 2144 2145 return 0; 2146 } 2147 2148 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2149 { 2150 struct amdgpu_ring *ring; 2151 int j; 2152 2153 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2154 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2155 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2156 mutex_lock(&adev->srbm_mutex); 2157 soc15_grbm_select(adev, ring->me, 2158 ring->pipe, 2159 ring->queue, 0, GET_INST(GC, xcc_id)); 2160 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2161 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2162 mutex_unlock(&adev->srbm_mutex); 2163 } 2164 } 2165 2166 return 0; 2167 } 2168 2169 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2170 { 2171 struct amdgpu_ring *ring; 2172 int r; 2173 2174 ring = &adev->gfx.kiq[xcc_id].ring; 2175 2176 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2177 if (unlikely(r != 0)) 2178 return r; 2179 2180 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2181 if (unlikely(r != 0)) { 2182 amdgpu_bo_unreserve(ring->mqd_obj); 2183 return r; 2184 } 2185 2186 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 2187 amdgpu_bo_kunmap(ring->mqd_obj); 2188 ring->mqd_ptr = NULL; 2189 amdgpu_bo_unreserve(ring->mqd_obj); 2190 return 0; 2191 } 2192 2193 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2194 { 2195 struct amdgpu_ring *ring = NULL; 2196 int r = 0, i; 2197 2198 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2199 2200 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2201 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2202 2203 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2204 if (unlikely(r != 0)) 2205 goto done; 2206 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2207 if (!r) { 2208 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2209 amdgpu_bo_kunmap(ring->mqd_obj); 2210 ring->mqd_ptr = NULL; 2211 } 2212 amdgpu_bo_unreserve(ring->mqd_obj); 2213 if (r) 2214 goto done; 2215 } 2216 2217 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2218 done: 2219 return r; 2220 } 2221 2222 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2223 { 2224 struct amdgpu_ring *ring; 2225 int r, j; 2226 2227 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2228 2229 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2230 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2231 2232 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2233 if (r) 2234 return r; 2235 } else { 2236 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2237 } 2238 2239 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2240 if (r) 2241 return r; 2242 2243 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2244 if (r) 2245 return r; 2246 2247 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2248 ring = &adev->gfx.compute_ring 2249 [j + xcc_id * adev->gfx.num_compute_rings]; 2250 r = amdgpu_ring_test_helper(ring); 2251 if (r) 2252 return r; 2253 } 2254 2255 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2256 2257 return 0; 2258 } 2259 2260 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2261 { 2262 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2263 2264 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2265 if (amdgpu_sriov_vf(adev)) { 2266 enum amdgpu_gfx_partition mode; 2267 2268 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2269 AMDGPU_XCP_FL_NONE); 2270 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2271 return -EINVAL; 2272 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2273 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2274 num_xcp = num_xcc / num_xcc_per_xcp; 2275 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2276 2277 } else { 2278 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2279 AMDGPU_XCP_FL_NONE) == 2280 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2281 r = amdgpu_xcp_switch_partition_mode( 2282 adev->xcp_mgr, amdgpu_user_partt_mode); 2283 } 2284 if (r) 2285 return r; 2286 2287 for (i = 0; i < num_xcc; i++) { 2288 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2289 if (r) 2290 return r; 2291 } 2292 2293 return 0; 2294 } 2295 2296 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2297 { 2298 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2299 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2300 2301 if (amdgpu_sriov_vf(adev)) { 2302 /* must disable polling for SRIOV when hw finished, otherwise 2303 * CPC engine may still keep fetching WB address which is already 2304 * invalid after sw finished and trigger DMAR reading error in 2305 * hypervisor side. 2306 */ 2307 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2308 return; 2309 } 2310 2311 /* Use deinitialize sequence from CAIL when unbinding device 2312 * from driver, otherwise KIQ is hanging when binding back 2313 */ 2314 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2315 mutex_lock(&adev->srbm_mutex); 2316 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2317 adev->gfx.kiq[xcc_id].ring.pipe, 2318 adev->gfx.kiq[xcc_id].ring.queue, 0, 2319 GET_INST(GC, xcc_id)); 2320 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2321 xcc_id); 2322 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2323 mutex_unlock(&adev->srbm_mutex); 2324 } 2325 2326 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2327 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2328 } 2329 2330 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2331 { 2332 int r; 2333 struct amdgpu_device *adev = ip_block->adev; 2334 2335 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2336 adev->gfx.cleaner_shader_ptr); 2337 2338 if (!amdgpu_sriov_vf(adev)) 2339 gfx_v9_4_3_init_golden_registers(adev); 2340 2341 gfx_v9_4_3_constants_init(adev); 2342 2343 r = adev->gfx.rlc.funcs->resume(adev); 2344 if (r) 2345 return r; 2346 2347 r = gfx_v9_4_3_cp_resume(adev); 2348 if (r) 2349 return r; 2350 2351 return r; 2352 } 2353 2354 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2355 { 2356 struct amdgpu_device *adev = ip_block->adev; 2357 int i, num_xcc; 2358 2359 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2360 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2361 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2362 2363 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2364 for (i = 0; i < num_xcc; i++) { 2365 gfx_v9_4_3_xcc_fini(adev, i); 2366 } 2367 2368 return 0; 2369 } 2370 2371 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2372 { 2373 return gfx_v9_4_3_hw_fini(ip_block); 2374 } 2375 2376 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2377 { 2378 return gfx_v9_4_3_hw_init(ip_block); 2379 } 2380 2381 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2382 { 2383 struct amdgpu_device *adev = ip_block->adev; 2384 int i, num_xcc; 2385 2386 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2387 for (i = 0; i < num_xcc; i++) { 2388 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2389 GRBM_STATUS, GUI_ACTIVE)) 2390 return false; 2391 } 2392 return true; 2393 } 2394 2395 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2396 { 2397 unsigned i; 2398 struct amdgpu_device *adev = ip_block->adev; 2399 2400 for (i = 0; i < adev->usec_timeout; i++) { 2401 if (gfx_v9_4_3_is_idle(ip_block)) 2402 return 0; 2403 udelay(1); 2404 } 2405 return -ETIMEDOUT; 2406 } 2407 2408 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2409 { 2410 u32 grbm_soft_reset = 0; 2411 u32 tmp; 2412 struct amdgpu_device *adev = ip_block->adev; 2413 2414 /* GRBM_STATUS */ 2415 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2416 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2417 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2418 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2419 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2420 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2421 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2422 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2423 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2424 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2425 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2426 } 2427 2428 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2429 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2430 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2431 } 2432 2433 /* GRBM_STATUS2 */ 2434 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2435 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2436 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2437 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2438 2439 2440 if (grbm_soft_reset) { 2441 /* stop the rlc */ 2442 adev->gfx.rlc.funcs->stop(adev); 2443 2444 /* Disable MEC parsing/prefetching */ 2445 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2446 2447 if (grbm_soft_reset) { 2448 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2449 tmp |= grbm_soft_reset; 2450 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2451 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2452 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2453 2454 udelay(50); 2455 2456 tmp &= ~grbm_soft_reset; 2457 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2458 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2459 } 2460 2461 /* Wait a little for things to settle down */ 2462 udelay(50); 2463 } 2464 return 0; 2465 } 2466 2467 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2468 uint32_t vmid, 2469 uint32_t gds_base, uint32_t gds_size, 2470 uint32_t gws_base, uint32_t gws_size, 2471 uint32_t oa_base, uint32_t oa_size) 2472 { 2473 struct amdgpu_device *adev = ring->adev; 2474 2475 /* GDS Base */ 2476 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2477 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2478 gds_base); 2479 2480 /* GDS Size */ 2481 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2482 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2483 gds_size); 2484 2485 /* GWS */ 2486 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2487 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2488 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2489 2490 /* OA */ 2491 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2492 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2493 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2494 } 2495 2496 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2497 { 2498 struct amdgpu_device *adev = ip_block->adev; 2499 2500 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2501 AMDGPU_MAX_COMPUTE_RINGS); 2502 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2503 gfx_v9_4_3_set_ring_funcs(adev); 2504 gfx_v9_4_3_set_irq_funcs(adev); 2505 gfx_v9_4_3_set_gds_init(adev); 2506 gfx_v9_4_3_set_rlc_funcs(adev); 2507 2508 /* init rlcg reg access ctrl */ 2509 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2510 2511 return gfx_v9_4_3_init_microcode(adev); 2512 } 2513 2514 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2515 { 2516 struct amdgpu_device *adev = ip_block->adev; 2517 int r; 2518 2519 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2520 if (r) 2521 return r; 2522 2523 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2524 if (r) 2525 return r; 2526 2527 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2528 if (r) 2529 return r; 2530 2531 if (adev->gfx.ras && 2532 adev->gfx.ras->enable_watchdog_timer) 2533 adev->gfx.ras->enable_watchdog_timer(adev); 2534 2535 return 0; 2536 } 2537 2538 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2539 bool enable, int xcc_id) 2540 { 2541 uint32_t def, data; 2542 2543 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2544 return; 2545 2546 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2547 regRLC_CGTT_MGCG_OVERRIDE); 2548 2549 if (enable) 2550 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2551 else 2552 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2553 2554 if (def != data) 2555 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2556 regRLC_CGTT_MGCG_OVERRIDE, data); 2557 2558 } 2559 2560 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2561 bool enable, int xcc_id) 2562 { 2563 uint32_t def, data; 2564 2565 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2566 return; 2567 2568 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2569 regRLC_CGTT_MGCG_OVERRIDE); 2570 2571 if (enable) 2572 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2573 else 2574 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2575 2576 if (def != data) 2577 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2578 regRLC_CGTT_MGCG_OVERRIDE, data); 2579 } 2580 2581 static void 2582 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2583 bool enable, int xcc_id) 2584 { 2585 uint32_t data, def; 2586 2587 /* It is disabled by HW by default */ 2588 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2589 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2590 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2591 2592 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2593 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2594 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2595 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2596 2597 if (def != data) 2598 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2599 2600 /* MGLS is a global flag to control all MGLS in GFX */ 2601 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2602 /* 2 - RLC memory Light sleep */ 2603 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2604 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2605 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2606 if (def != data) 2607 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2608 } 2609 /* 3 - CP memory Light sleep */ 2610 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2611 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2612 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2613 if (def != data) 2614 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2615 } 2616 } 2617 } else { 2618 /* 1 - MGCG_OVERRIDE */ 2619 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2620 2621 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2622 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2623 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2624 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2625 2626 if (def != data) 2627 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2628 2629 /* 2 - disable MGLS in RLC */ 2630 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2631 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2632 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2633 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2634 } 2635 2636 /* 3 - disable MGLS in CP */ 2637 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2638 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2639 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2640 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2641 } 2642 } 2643 2644 } 2645 2646 static void 2647 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2648 bool enable, int xcc_id) 2649 { 2650 uint32_t def, data; 2651 2652 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2653 2654 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2655 /* unset CGCG override */ 2656 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2657 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2658 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2659 else 2660 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2661 /* update CGCG and CGLS override bits */ 2662 if (def != data) 2663 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2664 2665 /* CGCG Hysteresis: 400us */ 2666 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2667 2668 data = (0x2710 2669 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2670 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2671 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2672 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2673 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2674 if (def != data) 2675 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2676 2677 /* set IDLE_POLL_COUNT(0x33450100)*/ 2678 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2679 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2680 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2681 if (def != data) 2682 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2683 } else { 2684 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2685 /* reset CGCG/CGLS bits */ 2686 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2687 /* disable cgcg and cgls in FSM */ 2688 if (def != data) 2689 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2690 } 2691 2692 } 2693 2694 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2695 bool enable, int xcc_id) 2696 { 2697 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2698 2699 if (enable) { 2700 /* FGCG */ 2701 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2702 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2703 2704 /* CGCG/CGLS should be enabled after MGCG/MGLS 2705 * === MGCG + MGLS === 2706 */ 2707 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2708 xcc_id); 2709 /* === CGCG + CGLS === */ 2710 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2711 xcc_id); 2712 } else { 2713 /* CGCG/CGLS should be disabled before MGCG/MGLS 2714 * === CGCG + CGLS === 2715 */ 2716 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2717 xcc_id); 2718 /* === MGCG + MGLS === */ 2719 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2720 xcc_id); 2721 2722 /* FGCG */ 2723 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2724 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2725 } 2726 2727 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2728 2729 return 0; 2730 } 2731 2732 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2733 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2734 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2735 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2736 .init = gfx_v9_4_3_rlc_init, 2737 .resume = gfx_v9_4_3_rlc_resume, 2738 .stop = gfx_v9_4_3_rlc_stop, 2739 .reset = gfx_v9_4_3_rlc_reset, 2740 .start = gfx_v9_4_3_rlc_start, 2741 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2742 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2743 }; 2744 2745 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2746 enum amd_powergating_state state) 2747 { 2748 return 0; 2749 } 2750 2751 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2752 enum amd_clockgating_state state) 2753 { 2754 struct amdgpu_device *adev = ip_block->adev; 2755 int i, num_xcc; 2756 2757 if (amdgpu_sriov_vf(adev)) 2758 return 0; 2759 2760 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2761 for (i = 0; i < num_xcc; i++) 2762 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2763 adev, state == AMD_CG_STATE_GATE, i); 2764 2765 return 0; 2766 } 2767 2768 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2769 { 2770 struct amdgpu_device *adev = ip_block->adev; 2771 int data; 2772 2773 if (amdgpu_sriov_vf(adev)) 2774 *flags = 0; 2775 2776 /* AMD_CG_SUPPORT_GFX_MGCG */ 2777 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2778 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2779 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2780 2781 /* AMD_CG_SUPPORT_GFX_CGCG */ 2782 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2783 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2784 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2785 2786 /* AMD_CG_SUPPORT_GFX_CGLS */ 2787 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2788 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2789 2790 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2791 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2792 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2793 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2794 2795 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2796 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2797 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2798 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2799 } 2800 2801 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2802 { 2803 struct amdgpu_device *adev = ring->adev; 2804 u32 ref_and_mask, reg_mem_engine; 2805 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2806 2807 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2808 switch (ring->me) { 2809 case 1: 2810 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2811 break; 2812 case 2: 2813 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2814 break; 2815 default: 2816 return; 2817 } 2818 reg_mem_engine = 0; 2819 } else { 2820 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2821 reg_mem_engine = 1; /* pfp */ 2822 } 2823 2824 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2825 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2826 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2827 ref_and_mask, ref_and_mask, 0x20); 2828 } 2829 2830 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2831 struct amdgpu_job *job, 2832 struct amdgpu_ib *ib, 2833 uint32_t flags) 2834 { 2835 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2836 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2837 2838 /* Currently, there is a high possibility to get wave ID mismatch 2839 * between ME and GDS, leading to a hw deadlock, because ME generates 2840 * different wave IDs than the GDS expects. This situation happens 2841 * randomly when at least 5 compute pipes use GDS ordered append. 2842 * The wave IDs generated by ME are also wrong after suspend/resume. 2843 * Those are probably bugs somewhere else in the kernel driver. 2844 * 2845 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2846 * GDS to 0 for this ring (me/pipe). 2847 */ 2848 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2849 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2850 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2851 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2852 } 2853 2854 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2855 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2856 amdgpu_ring_write(ring, 2857 #ifdef __BIG_ENDIAN 2858 (2 << 0) | 2859 #endif 2860 lower_32_bits(ib->gpu_addr)); 2861 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2862 amdgpu_ring_write(ring, control); 2863 } 2864 2865 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2866 u64 seq, unsigned flags) 2867 { 2868 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2869 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2870 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2871 2872 /* RELEASE_MEM - flush caches, send int */ 2873 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2874 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2875 EOP_TC_NC_ACTION_EN) : 2876 (EOP_TCL1_ACTION_EN | 2877 EOP_TC_ACTION_EN | 2878 EOP_TC_WB_ACTION_EN | 2879 EOP_TC_MD_ACTION_EN)) | 2880 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2881 EVENT_INDEX(5))); 2882 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2883 2884 /* 2885 * the address should be Qword aligned if 64bit write, Dword 2886 * aligned if only send 32bit data low (discard data high) 2887 */ 2888 if (write64bit) 2889 BUG_ON(addr & 0x7); 2890 else 2891 BUG_ON(addr & 0x3); 2892 amdgpu_ring_write(ring, lower_32_bits(addr)); 2893 amdgpu_ring_write(ring, upper_32_bits(addr)); 2894 amdgpu_ring_write(ring, lower_32_bits(seq)); 2895 amdgpu_ring_write(ring, upper_32_bits(seq)); 2896 amdgpu_ring_write(ring, 0); 2897 } 2898 2899 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2900 { 2901 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2902 uint32_t seq = ring->fence_drv.sync_seq; 2903 uint64_t addr = ring->fence_drv.gpu_addr; 2904 2905 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2906 lower_32_bits(addr), upper_32_bits(addr), 2907 seq, 0xffffffff, 4); 2908 } 2909 2910 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2911 unsigned vmid, uint64_t pd_addr) 2912 { 2913 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2914 } 2915 2916 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2917 { 2918 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2919 } 2920 2921 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2922 { 2923 u64 wptr; 2924 2925 /* XXX check if swapping is necessary on BE */ 2926 if (ring->use_doorbell) 2927 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2928 else 2929 BUG(); 2930 return wptr; 2931 } 2932 2933 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2934 { 2935 struct amdgpu_device *adev = ring->adev; 2936 2937 /* XXX check if swapping is necessary on BE */ 2938 if (ring->use_doorbell) { 2939 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2940 WDOORBELL64(ring->doorbell_index, ring->wptr); 2941 } else { 2942 BUG(); /* only DOORBELL method supported on gfx9 now */ 2943 } 2944 } 2945 2946 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2947 u64 seq, unsigned int flags) 2948 { 2949 struct amdgpu_device *adev = ring->adev; 2950 2951 /* we only allocate 32bit for each seq wb address */ 2952 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2953 2954 /* write fence seq to the "addr" */ 2955 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2956 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2957 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2958 amdgpu_ring_write(ring, lower_32_bits(addr)); 2959 amdgpu_ring_write(ring, upper_32_bits(addr)); 2960 amdgpu_ring_write(ring, lower_32_bits(seq)); 2961 2962 if (flags & AMDGPU_FENCE_FLAG_INT) { 2963 /* set register to trigger INT */ 2964 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2965 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2966 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2967 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2968 amdgpu_ring_write(ring, 0); 2969 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2970 } 2971 } 2972 2973 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2974 uint32_t reg_val_offs) 2975 { 2976 struct amdgpu_device *adev = ring->adev; 2977 2978 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2979 2980 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2981 amdgpu_ring_write(ring, 0 | /* src: register*/ 2982 (5 << 8) | /* dst: memory */ 2983 (1 << 20)); /* write confirm */ 2984 amdgpu_ring_write(ring, reg); 2985 amdgpu_ring_write(ring, 0); 2986 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2987 reg_val_offs * 4)); 2988 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2989 reg_val_offs * 4)); 2990 } 2991 2992 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2993 uint32_t val) 2994 { 2995 uint32_t cmd = 0; 2996 2997 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2998 2999 switch (ring->funcs->type) { 3000 case AMDGPU_RING_TYPE_GFX: 3001 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3002 break; 3003 case AMDGPU_RING_TYPE_KIQ: 3004 cmd = (1 << 16); /* no inc addr */ 3005 break; 3006 default: 3007 cmd = WR_CONFIRM; 3008 break; 3009 } 3010 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3011 amdgpu_ring_write(ring, cmd); 3012 amdgpu_ring_write(ring, reg); 3013 amdgpu_ring_write(ring, 0); 3014 amdgpu_ring_write(ring, val); 3015 } 3016 3017 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3018 uint32_t val, uint32_t mask) 3019 { 3020 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3021 } 3022 3023 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3024 uint32_t reg0, uint32_t reg1, 3025 uint32_t ref, uint32_t mask) 3026 { 3027 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3028 ref, mask); 3029 } 3030 3031 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3032 unsigned vmid) 3033 { 3034 struct amdgpu_device *adev = ring->adev; 3035 uint32_t value = 0; 3036 3037 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3038 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3039 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3040 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3041 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3042 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3043 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3044 } 3045 3046 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3047 struct amdgpu_device *adev, int me, int pipe, 3048 enum amdgpu_interrupt_state state, int xcc_id) 3049 { 3050 u32 mec_int_cntl, mec_int_cntl_reg; 3051 3052 /* 3053 * amdgpu controls only the first MEC. That's why this function only 3054 * handles the setting of interrupts for this specific MEC. All other 3055 * pipes' interrupts are set by amdkfd. 3056 */ 3057 3058 if (me == 1) { 3059 switch (pipe) { 3060 case 0: 3061 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3062 break; 3063 case 1: 3064 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3065 break; 3066 case 2: 3067 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3068 break; 3069 case 3: 3070 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3071 break; 3072 default: 3073 DRM_DEBUG("invalid pipe %d\n", pipe); 3074 return; 3075 } 3076 } else { 3077 DRM_DEBUG("invalid me %d\n", me); 3078 return; 3079 } 3080 3081 switch (state) { 3082 case AMDGPU_IRQ_STATE_DISABLE: 3083 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3084 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3085 TIME_STAMP_INT_ENABLE, 0); 3086 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3087 break; 3088 case AMDGPU_IRQ_STATE_ENABLE: 3089 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3090 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3091 TIME_STAMP_INT_ENABLE, 1); 3092 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3093 break; 3094 default: 3095 break; 3096 } 3097 } 3098 3099 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3100 int xcc_id, int me, int pipe) 3101 { 3102 /* 3103 * amdgpu controls only the first MEC. That's why this function only 3104 * handles the setting of interrupts for this specific MEC. All other 3105 * pipes' interrupts are set by amdkfd. 3106 */ 3107 if (me != 1) 3108 return 0; 3109 3110 switch (pipe) { 3111 case 0: 3112 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3113 case 1: 3114 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3115 case 2: 3116 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3117 case 3: 3118 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3119 default: 3120 return 0; 3121 } 3122 } 3123 3124 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3125 struct amdgpu_irq_src *source, 3126 unsigned type, 3127 enum amdgpu_interrupt_state state) 3128 { 3129 u32 mec_int_cntl_reg, mec_int_cntl; 3130 int i, j, k, num_xcc; 3131 3132 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3133 switch (state) { 3134 case AMDGPU_IRQ_STATE_DISABLE: 3135 case AMDGPU_IRQ_STATE_ENABLE: 3136 for (i = 0; i < num_xcc; i++) { 3137 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3138 PRIV_REG_INT_ENABLE, 3139 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3140 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3141 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3142 /* MECs start at 1 */ 3143 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3144 3145 if (mec_int_cntl_reg) { 3146 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3147 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3148 PRIV_REG_INT_ENABLE, 3149 state == AMDGPU_IRQ_STATE_ENABLE ? 3150 1 : 0); 3151 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3152 } 3153 } 3154 } 3155 } 3156 break; 3157 default: 3158 break; 3159 } 3160 3161 return 0; 3162 } 3163 3164 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3165 struct amdgpu_irq_src *source, 3166 unsigned type, 3167 enum amdgpu_interrupt_state state) 3168 { 3169 u32 mec_int_cntl_reg, mec_int_cntl; 3170 int i, j, k, num_xcc; 3171 3172 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3173 switch (state) { 3174 case AMDGPU_IRQ_STATE_DISABLE: 3175 case AMDGPU_IRQ_STATE_ENABLE: 3176 for (i = 0; i < num_xcc; i++) { 3177 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3178 OPCODE_ERROR_INT_ENABLE, 3179 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3180 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3181 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3182 /* MECs start at 1 */ 3183 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3184 3185 if (mec_int_cntl_reg) { 3186 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3187 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3188 OPCODE_ERROR_INT_ENABLE, 3189 state == AMDGPU_IRQ_STATE_ENABLE ? 3190 1 : 0); 3191 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3192 } 3193 } 3194 } 3195 } 3196 break; 3197 default: 3198 break; 3199 } 3200 3201 return 0; 3202 } 3203 3204 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3205 struct amdgpu_irq_src *source, 3206 unsigned type, 3207 enum amdgpu_interrupt_state state) 3208 { 3209 int i, num_xcc; 3210 3211 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3212 switch (state) { 3213 case AMDGPU_IRQ_STATE_DISABLE: 3214 case AMDGPU_IRQ_STATE_ENABLE: 3215 for (i = 0; i < num_xcc; i++) 3216 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3217 PRIV_INSTR_INT_ENABLE, 3218 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3219 break; 3220 default: 3221 break; 3222 } 3223 3224 return 0; 3225 } 3226 3227 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3228 struct amdgpu_irq_src *src, 3229 unsigned type, 3230 enum amdgpu_interrupt_state state) 3231 { 3232 int i, num_xcc; 3233 3234 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3235 for (i = 0; i < num_xcc; i++) { 3236 switch (type) { 3237 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3238 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3239 adev, 1, 0, state, i); 3240 break; 3241 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3242 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3243 adev, 1, 1, state, i); 3244 break; 3245 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3246 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3247 adev, 1, 2, state, i); 3248 break; 3249 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3250 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3251 adev, 1, 3, state, i); 3252 break; 3253 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3254 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3255 adev, 2, 0, state, i); 3256 break; 3257 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3258 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3259 adev, 2, 1, state, i); 3260 break; 3261 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3262 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3263 adev, 2, 2, state, i); 3264 break; 3265 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3266 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3267 adev, 2, 3, state, i); 3268 break; 3269 default: 3270 break; 3271 } 3272 } 3273 3274 return 0; 3275 } 3276 3277 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3278 struct amdgpu_irq_src *source, 3279 struct amdgpu_iv_entry *entry) 3280 { 3281 int i, xcc_id; 3282 u8 me_id, pipe_id, queue_id; 3283 struct amdgpu_ring *ring; 3284 3285 DRM_DEBUG("IH: CP EOP\n"); 3286 me_id = (entry->ring_id & 0x0c) >> 2; 3287 pipe_id = (entry->ring_id & 0x03) >> 0; 3288 queue_id = (entry->ring_id & 0x70) >> 4; 3289 3290 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3291 3292 if (xcc_id == -EINVAL) 3293 return -EINVAL; 3294 3295 switch (me_id) { 3296 case 0: 3297 case 1: 3298 case 2: 3299 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3300 ring = &adev->gfx.compute_ring 3301 [i + 3302 xcc_id * adev->gfx.num_compute_rings]; 3303 /* Per-queue interrupt is supported for MEC starting from VI. 3304 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3305 */ 3306 3307 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3308 amdgpu_fence_process(ring); 3309 } 3310 break; 3311 } 3312 return 0; 3313 } 3314 3315 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3316 struct amdgpu_iv_entry *entry) 3317 { 3318 u8 me_id, pipe_id, queue_id; 3319 struct amdgpu_ring *ring; 3320 int i, xcc_id; 3321 3322 me_id = (entry->ring_id & 0x0c) >> 2; 3323 pipe_id = (entry->ring_id & 0x03) >> 0; 3324 queue_id = (entry->ring_id & 0x70) >> 4; 3325 3326 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3327 3328 if (xcc_id == -EINVAL) 3329 return; 3330 3331 switch (me_id) { 3332 case 0: 3333 case 1: 3334 case 2: 3335 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3336 ring = &adev->gfx.compute_ring 3337 [i + 3338 xcc_id * adev->gfx.num_compute_rings]; 3339 if (ring->me == me_id && ring->pipe == pipe_id && 3340 ring->queue == queue_id) 3341 drm_sched_fault(&ring->sched); 3342 } 3343 break; 3344 } 3345 } 3346 3347 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3348 struct amdgpu_irq_src *source, 3349 struct amdgpu_iv_entry *entry) 3350 { 3351 DRM_ERROR("Illegal register access in command stream\n"); 3352 gfx_v9_4_3_fault(adev, entry); 3353 return 0; 3354 } 3355 3356 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3357 struct amdgpu_irq_src *source, 3358 struct amdgpu_iv_entry *entry) 3359 { 3360 DRM_ERROR("Illegal opcode in command stream\n"); 3361 gfx_v9_4_3_fault(adev, entry); 3362 return 0; 3363 } 3364 3365 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3366 struct amdgpu_irq_src *source, 3367 struct amdgpu_iv_entry *entry) 3368 { 3369 DRM_ERROR("Illegal instruction in command stream\n"); 3370 gfx_v9_4_3_fault(adev, entry); 3371 return 0; 3372 } 3373 3374 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3375 { 3376 const unsigned int cp_coher_cntl = 3377 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3378 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3379 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3380 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3381 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3382 3383 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3384 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3385 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3386 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3387 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3388 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3389 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3390 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3391 } 3392 3393 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3394 uint32_t pipe, bool enable) 3395 { 3396 struct amdgpu_device *adev = ring->adev; 3397 uint32_t val; 3398 uint32_t wcl_cs_reg; 3399 3400 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3401 val = enable ? 0x1 : 0x7f; 3402 3403 switch (pipe) { 3404 case 0: 3405 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3406 break; 3407 case 1: 3408 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3409 break; 3410 case 2: 3411 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3412 break; 3413 case 3: 3414 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3415 break; 3416 default: 3417 DRM_DEBUG("invalid pipe %d\n", pipe); 3418 return; 3419 } 3420 3421 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3422 3423 } 3424 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3425 { 3426 struct amdgpu_device *adev = ring->adev; 3427 uint32_t val; 3428 int i; 3429 3430 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3431 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3432 * around 25% of gpu resources. 3433 */ 3434 val = enable ? 0x1f : 0x07ffffff; 3435 amdgpu_ring_emit_wreg(ring, 3436 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3437 val); 3438 3439 /* Restrict waves for normal/low priority compute queues as well 3440 * to get best QoS for high priority compute jobs. 3441 * 3442 * amdgpu controls only 1st ME(0-3 CS pipes). 3443 */ 3444 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3445 if (i != ring->pipe) 3446 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3447 3448 } 3449 } 3450 3451 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3452 uint32_t pipe, uint32_t queue, 3453 uint32_t xcc_id) 3454 { 3455 int i, r; 3456 /* make sure dequeue is complete*/ 3457 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3458 mutex_lock(&adev->srbm_mutex); 3459 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3460 for (i = 0; i < adev->usec_timeout; i++) { 3461 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3462 break; 3463 udelay(1); 3464 } 3465 if (i >= adev->usec_timeout) 3466 r = -ETIMEDOUT; 3467 else 3468 r = 0; 3469 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3470 mutex_unlock(&adev->srbm_mutex); 3471 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3472 3473 return r; 3474 3475 } 3476 3477 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3478 { 3479 /*TODO: Need check gfx9.4.4 mec fw whether supports pipe reset as well.*/ 3480 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 3481 adev->gfx.mec_fw_version >= 0x0000009b) 3482 return true; 3483 else 3484 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3485 3486 return false; 3487 } 3488 3489 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3490 { 3491 struct amdgpu_device *adev = ring->adev; 3492 uint32_t reset_pipe, clean_pipe; 3493 int r; 3494 3495 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3496 return -EINVAL; 3497 3498 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3499 mutex_lock(&adev->srbm_mutex); 3500 3501 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3502 clean_pipe = reset_pipe; 3503 3504 if (ring->me == 1) { 3505 switch (ring->pipe) { 3506 case 0: 3507 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3508 MEC_ME1_PIPE0_RESET, 1); 3509 break; 3510 case 1: 3511 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3512 MEC_ME1_PIPE1_RESET, 1); 3513 break; 3514 case 2: 3515 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3516 MEC_ME1_PIPE2_RESET, 1); 3517 break; 3518 case 3: 3519 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3520 MEC_ME1_PIPE3_RESET, 1); 3521 break; 3522 default: 3523 break; 3524 } 3525 } else { 3526 if (ring->pipe) 3527 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3528 MEC_ME2_PIPE1_RESET, 1); 3529 else 3530 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3531 MEC_ME2_PIPE0_RESET, 1); 3532 } 3533 3534 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3535 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3536 mutex_unlock(&adev->srbm_mutex); 3537 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3538 3539 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3540 return r; 3541 } 3542 3543 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3544 unsigned int vmid) 3545 { 3546 struct amdgpu_device *adev = ring->adev; 3547 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3548 struct amdgpu_ring *kiq_ring = &kiq->ring; 3549 unsigned long flags; 3550 int r; 3551 3552 if (amdgpu_sriov_vf(adev)) 3553 return -EINVAL; 3554 3555 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3556 return -EINVAL; 3557 3558 spin_lock_irqsave(&kiq->ring_lock, flags); 3559 3560 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3561 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3562 return -ENOMEM; 3563 } 3564 3565 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3566 0, 0); 3567 amdgpu_ring_commit(kiq_ring); 3568 3569 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3570 3571 r = amdgpu_ring_test_ring(kiq_ring); 3572 if (r) { 3573 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3574 ring->name); 3575 goto pipe_reset; 3576 } 3577 3578 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3579 if (r) 3580 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3581 3582 pipe_reset: 3583 if(r) { 3584 r = gfx_v9_4_3_reset_hw_pipe(ring); 3585 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3586 r ? "failed" : "successfully"); 3587 if (r) 3588 return r; 3589 } 3590 3591 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3592 if (unlikely(r != 0)){ 3593 dev_err(adev->dev, "fail to resv mqd_obj\n"); 3594 return r; 3595 } 3596 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3597 if (!r) { 3598 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3599 amdgpu_bo_kunmap(ring->mqd_obj); 3600 ring->mqd_ptr = NULL; 3601 } 3602 amdgpu_bo_unreserve(ring->mqd_obj); 3603 if (r) { 3604 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 3605 return r; 3606 } 3607 spin_lock_irqsave(&kiq->ring_lock, flags); 3608 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3609 if (r) { 3610 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3611 return -ENOMEM; 3612 } 3613 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3614 amdgpu_ring_commit(kiq_ring); 3615 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3616 3617 r = amdgpu_ring_test_ring(kiq_ring); 3618 if (r) { 3619 dev_err(adev->dev, "fail to remap queue\n"); 3620 return r; 3621 } 3622 return amdgpu_ring_test_ring(ring); 3623 } 3624 3625 enum amdgpu_gfx_cp_ras_mem_id { 3626 AMDGPU_GFX_CP_MEM1 = 1, 3627 AMDGPU_GFX_CP_MEM2, 3628 AMDGPU_GFX_CP_MEM3, 3629 AMDGPU_GFX_CP_MEM4, 3630 AMDGPU_GFX_CP_MEM5, 3631 }; 3632 3633 enum amdgpu_gfx_gcea_ras_mem_id { 3634 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3635 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3636 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3637 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3638 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3639 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3640 AMDGPU_GFX_GCEA_MAM_DMEM0, 3641 AMDGPU_GFX_GCEA_MAM_DMEM1, 3642 AMDGPU_GFX_GCEA_MAM_DMEM2, 3643 AMDGPU_GFX_GCEA_MAM_DMEM3, 3644 AMDGPU_GFX_GCEA_MAM_AMEM0, 3645 AMDGPU_GFX_GCEA_MAM_AMEM1, 3646 AMDGPU_GFX_GCEA_MAM_AMEM2, 3647 AMDGPU_GFX_GCEA_MAM_AMEM3, 3648 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3649 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3650 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3651 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3652 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3653 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3654 }; 3655 3656 enum amdgpu_gfx_gc_cane_ras_mem_id { 3657 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3658 }; 3659 3660 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3661 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3662 }; 3663 3664 enum amdgpu_gfx_gds_ras_mem_id { 3665 AMDGPU_GFX_GDS_MEM0 = 0, 3666 }; 3667 3668 enum amdgpu_gfx_lds_ras_mem_id { 3669 AMDGPU_GFX_LDS_BANK0 = 0, 3670 AMDGPU_GFX_LDS_BANK1, 3671 AMDGPU_GFX_LDS_BANK2, 3672 AMDGPU_GFX_LDS_BANK3, 3673 AMDGPU_GFX_LDS_BANK4, 3674 AMDGPU_GFX_LDS_BANK5, 3675 AMDGPU_GFX_LDS_BANK6, 3676 AMDGPU_GFX_LDS_BANK7, 3677 AMDGPU_GFX_LDS_BANK8, 3678 AMDGPU_GFX_LDS_BANK9, 3679 AMDGPU_GFX_LDS_BANK10, 3680 AMDGPU_GFX_LDS_BANK11, 3681 AMDGPU_GFX_LDS_BANK12, 3682 AMDGPU_GFX_LDS_BANK13, 3683 AMDGPU_GFX_LDS_BANK14, 3684 AMDGPU_GFX_LDS_BANK15, 3685 AMDGPU_GFX_LDS_BANK16, 3686 AMDGPU_GFX_LDS_BANK17, 3687 AMDGPU_GFX_LDS_BANK18, 3688 AMDGPU_GFX_LDS_BANK19, 3689 AMDGPU_GFX_LDS_BANK20, 3690 AMDGPU_GFX_LDS_BANK21, 3691 AMDGPU_GFX_LDS_BANK22, 3692 AMDGPU_GFX_LDS_BANK23, 3693 AMDGPU_GFX_LDS_BANK24, 3694 AMDGPU_GFX_LDS_BANK25, 3695 AMDGPU_GFX_LDS_BANK26, 3696 AMDGPU_GFX_LDS_BANK27, 3697 AMDGPU_GFX_LDS_BANK28, 3698 AMDGPU_GFX_LDS_BANK29, 3699 AMDGPU_GFX_LDS_BANK30, 3700 AMDGPU_GFX_LDS_BANK31, 3701 AMDGPU_GFX_LDS_SP_BUFFER_A, 3702 AMDGPU_GFX_LDS_SP_BUFFER_B, 3703 }; 3704 3705 enum amdgpu_gfx_rlc_ras_mem_id { 3706 AMDGPU_GFX_RLC_GPMF32 = 1, 3707 AMDGPU_GFX_RLC_RLCVF32, 3708 AMDGPU_GFX_RLC_SCRATCH, 3709 AMDGPU_GFX_RLC_SRM_ARAM, 3710 AMDGPU_GFX_RLC_SRM_DRAM, 3711 AMDGPU_GFX_RLC_TCTAG, 3712 AMDGPU_GFX_RLC_SPM_SE, 3713 AMDGPU_GFX_RLC_SPM_GRBMT, 3714 }; 3715 3716 enum amdgpu_gfx_sp_ras_mem_id { 3717 AMDGPU_GFX_SP_SIMDID0 = 0, 3718 }; 3719 3720 enum amdgpu_gfx_spi_ras_mem_id { 3721 AMDGPU_GFX_SPI_MEM0 = 0, 3722 AMDGPU_GFX_SPI_MEM1, 3723 AMDGPU_GFX_SPI_MEM2, 3724 AMDGPU_GFX_SPI_MEM3, 3725 }; 3726 3727 enum amdgpu_gfx_sqc_ras_mem_id { 3728 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3729 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3730 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3731 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3732 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3733 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3734 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3735 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3736 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3737 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3738 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3739 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3740 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3741 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3742 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3743 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3744 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3745 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3746 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3747 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3748 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3749 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3750 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3751 }; 3752 3753 enum amdgpu_gfx_sq_ras_mem_id { 3754 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3755 AMDGPU_GFX_SQ_SGPR_MEM1, 3756 AMDGPU_GFX_SQ_SGPR_MEM2, 3757 AMDGPU_GFX_SQ_SGPR_MEM3, 3758 }; 3759 3760 enum amdgpu_gfx_ta_ras_mem_id { 3761 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3762 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3763 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3764 AMDGPU_GFX_TA_FSX_LFIFO, 3765 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3766 }; 3767 3768 enum amdgpu_gfx_tcc_ras_mem_id { 3769 AMDGPU_GFX_TCC_MEM1 = 1, 3770 }; 3771 3772 enum amdgpu_gfx_tca_ras_mem_id { 3773 AMDGPU_GFX_TCA_MEM1 = 1, 3774 }; 3775 3776 enum amdgpu_gfx_tci_ras_mem_id { 3777 AMDGPU_GFX_TCIW_MEM = 1, 3778 }; 3779 3780 enum amdgpu_gfx_tcp_ras_mem_id { 3781 AMDGPU_GFX_TCP_LFIFO0 = 1, 3782 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3783 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3784 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3785 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3786 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3787 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3788 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3789 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3790 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3791 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3792 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3793 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3794 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3795 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3796 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3797 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3798 AMDGPU_GFX_TCP_VM_FIFO, 3799 AMDGPU_GFX_TCP_DB_TAGRAM0, 3800 AMDGPU_GFX_TCP_DB_TAGRAM1, 3801 AMDGPU_GFX_TCP_DB_TAGRAM2, 3802 AMDGPU_GFX_TCP_DB_TAGRAM3, 3803 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3804 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3805 AMDGPU_GFX_TCP_CMD_FIFO, 3806 }; 3807 3808 enum amdgpu_gfx_td_ras_mem_id { 3809 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3810 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3811 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3812 }; 3813 3814 enum amdgpu_gfx_tcx_ras_mem_id { 3815 AMDGPU_GFX_TCX_FIFOD0 = 0, 3816 AMDGPU_GFX_TCX_FIFOD1, 3817 AMDGPU_GFX_TCX_FIFOD2, 3818 AMDGPU_GFX_TCX_FIFOD3, 3819 AMDGPU_GFX_TCX_FIFOD4, 3820 AMDGPU_GFX_TCX_FIFOD5, 3821 AMDGPU_GFX_TCX_FIFOD6, 3822 AMDGPU_GFX_TCX_FIFOD7, 3823 AMDGPU_GFX_TCX_FIFOB0, 3824 AMDGPU_GFX_TCX_FIFOB1, 3825 AMDGPU_GFX_TCX_FIFOB2, 3826 AMDGPU_GFX_TCX_FIFOB3, 3827 AMDGPU_GFX_TCX_FIFOB4, 3828 AMDGPU_GFX_TCX_FIFOB5, 3829 AMDGPU_GFX_TCX_FIFOB6, 3830 AMDGPU_GFX_TCX_FIFOB7, 3831 AMDGPU_GFX_TCX_FIFOA0, 3832 AMDGPU_GFX_TCX_FIFOA1, 3833 AMDGPU_GFX_TCX_FIFOA2, 3834 AMDGPU_GFX_TCX_FIFOA3, 3835 AMDGPU_GFX_TCX_FIFOA4, 3836 AMDGPU_GFX_TCX_FIFOA5, 3837 AMDGPU_GFX_TCX_FIFOA6, 3838 AMDGPU_GFX_TCX_FIFOA7, 3839 AMDGPU_GFX_TCX_CFIFO0, 3840 AMDGPU_GFX_TCX_CFIFO1, 3841 AMDGPU_GFX_TCX_CFIFO2, 3842 AMDGPU_GFX_TCX_CFIFO3, 3843 AMDGPU_GFX_TCX_CFIFO4, 3844 AMDGPU_GFX_TCX_CFIFO5, 3845 AMDGPU_GFX_TCX_CFIFO6, 3846 AMDGPU_GFX_TCX_CFIFO7, 3847 AMDGPU_GFX_TCX_FIFO_ACKB0, 3848 AMDGPU_GFX_TCX_FIFO_ACKB1, 3849 AMDGPU_GFX_TCX_FIFO_ACKB2, 3850 AMDGPU_GFX_TCX_FIFO_ACKB3, 3851 AMDGPU_GFX_TCX_FIFO_ACKB4, 3852 AMDGPU_GFX_TCX_FIFO_ACKB5, 3853 AMDGPU_GFX_TCX_FIFO_ACKB6, 3854 AMDGPU_GFX_TCX_FIFO_ACKB7, 3855 AMDGPU_GFX_TCX_FIFO_ACKD0, 3856 AMDGPU_GFX_TCX_FIFO_ACKD1, 3857 AMDGPU_GFX_TCX_FIFO_ACKD2, 3858 AMDGPU_GFX_TCX_FIFO_ACKD3, 3859 AMDGPU_GFX_TCX_FIFO_ACKD4, 3860 AMDGPU_GFX_TCX_FIFO_ACKD5, 3861 AMDGPU_GFX_TCX_FIFO_ACKD6, 3862 AMDGPU_GFX_TCX_FIFO_ACKD7, 3863 AMDGPU_GFX_TCX_DST_FIFOA0, 3864 AMDGPU_GFX_TCX_DST_FIFOA1, 3865 AMDGPU_GFX_TCX_DST_FIFOA2, 3866 AMDGPU_GFX_TCX_DST_FIFOA3, 3867 AMDGPU_GFX_TCX_DST_FIFOA4, 3868 AMDGPU_GFX_TCX_DST_FIFOA5, 3869 AMDGPU_GFX_TCX_DST_FIFOA6, 3870 AMDGPU_GFX_TCX_DST_FIFOA7, 3871 AMDGPU_GFX_TCX_DST_FIFOB0, 3872 AMDGPU_GFX_TCX_DST_FIFOB1, 3873 AMDGPU_GFX_TCX_DST_FIFOB2, 3874 AMDGPU_GFX_TCX_DST_FIFOB3, 3875 AMDGPU_GFX_TCX_DST_FIFOB4, 3876 AMDGPU_GFX_TCX_DST_FIFOB5, 3877 AMDGPU_GFX_TCX_DST_FIFOB6, 3878 AMDGPU_GFX_TCX_DST_FIFOB7, 3879 AMDGPU_GFX_TCX_DST_FIFOD0, 3880 AMDGPU_GFX_TCX_DST_FIFOD1, 3881 AMDGPU_GFX_TCX_DST_FIFOD2, 3882 AMDGPU_GFX_TCX_DST_FIFOD3, 3883 AMDGPU_GFX_TCX_DST_FIFOD4, 3884 AMDGPU_GFX_TCX_DST_FIFOD5, 3885 AMDGPU_GFX_TCX_DST_FIFOD6, 3886 AMDGPU_GFX_TCX_DST_FIFOD7, 3887 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3888 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3889 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3890 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3891 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3892 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3893 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3894 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3895 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3896 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3897 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3898 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3899 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3900 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3901 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3902 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3903 }; 3904 3905 enum amdgpu_gfx_atc_l2_ras_mem_id { 3906 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3907 }; 3908 3909 enum amdgpu_gfx_utcl2_ras_mem_id { 3910 AMDGPU_GFX_UTCL2_MEM0 = 0, 3911 }; 3912 3913 enum amdgpu_gfx_vml2_ras_mem_id { 3914 AMDGPU_GFX_VML2_MEM0 = 0, 3915 }; 3916 3917 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3918 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3919 }; 3920 3921 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3922 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3923 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3924 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3925 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3926 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3927 }; 3928 3929 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3930 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3931 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3932 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3933 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3934 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3935 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3936 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3937 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3938 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3939 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3940 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3941 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3942 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3943 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3944 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3945 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3946 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3947 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3948 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3949 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3950 }; 3951 3952 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3953 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3954 }; 3955 3956 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3957 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3958 }; 3959 3960 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3961 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3962 }; 3963 3964 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3965 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3966 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3967 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3968 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3969 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3970 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3971 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3972 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3973 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3974 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3975 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3976 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3977 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3978 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3979 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3980 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3981 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3982 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3983 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3984 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3985 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3986 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3987 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3988 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3989 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3990 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3991 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3992 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3993 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3994 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3995 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3996 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3997 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3998 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3999 }; 4000 4001 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4002 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4003 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4004 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4005 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4006 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4007 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4008 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4009 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4010 }; 4011 4012 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4013 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4014 }; 4015 4016 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4017 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4018 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4019 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4020 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4021 }; 4022 4023 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4024 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4025 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4026 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4027 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4028 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4029 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4030 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4031 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4032 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4033 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4034 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4035 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4036 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4037 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4038 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4039 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4040 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4041 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4042 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4043 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4044 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4045 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4046 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4047 }; 4048 4049 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4050 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4051 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4052 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4053 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4054 }; 4055 4056 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4057 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4058 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4059 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4060 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4061 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4062 }; 4063 4064 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4065 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4066 }; 4067 4068 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4069 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4070 }; 4071 4072 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4073 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4074 }; 4075 4076 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4077 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4078 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4079 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4080 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4081 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4082 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4083 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4084 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4085 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4086 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4087 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4088 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4089 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4090 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4091 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4092 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4093 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4094 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4095 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4096 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4097 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4098 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4099 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4100 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4101 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4102 }; 4103 4104 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4105 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4106 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4107 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4108 }; 4109 4110 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4111 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4112 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4113 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4114 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4115 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4116 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4117 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4118 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4119 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4120 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4121 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4122 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4123 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4124 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4125 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4126 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4127 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4128 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4129 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4130 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4131 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4132 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4133 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4134 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4135 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4136 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4137 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4138 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4139 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4140 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4141 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4142 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4143 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4144 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4145 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4146 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4147 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4148 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4149 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4150 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4151 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4152 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4153 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4154 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4155 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4156 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4157 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4158 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4159 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4160 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4161 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4162 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4163 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4164 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4165 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4166 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4167 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4168 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4169 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4170 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4171 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4172 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4173 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4174 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4175 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4176 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4177 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4178 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4179 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4180 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4181 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4182 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4183 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4184 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4185 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4186 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4187 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4188 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4189 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4190 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4191 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4192 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4193 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4194 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4195 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4196 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4197 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4198 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4199 }; 4200 4201 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4202 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4203 }; 4204 4205 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4206 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4207 }; 4208 4209 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4210 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4211 }; 4212 4213 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4214 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4215 }; 4216 4217 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4218 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4219 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4220 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4221 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4222 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4223 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4224 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4225 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4226 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4227 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4228 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4229 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4230 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4231 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4232 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4233 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4234 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4235 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4236 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4237 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4238 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4239 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4240 }; 4241 4242 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4243 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4244 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4245 AMDGPU_GFX_RLC_MEM, 1}, 4246 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4247 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4248 AMDGPU_GFX_CP_MEM, 1}, 4249 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4250 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4251 AMDGPU_GFX_CP_MEM, 1}, 4252 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4253 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4254 AMDGPU_GFX_CP_MEM, 1}, 4255 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4256 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4257 AMDGPU_GFX_GDS_MEM, 1}, 4258 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4259 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4260 AMDGPU_GFX_GC_CANE_MEM, 1}, 4261 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4262 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4263 AMDGPU_GFX_SPI_MEM, 1}, 4264 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4265 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4266 AMDGPU_GFX_SP_MEM, 4}, 4267 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4268 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4269 AMDGPU_GFX_SP_MEM, 4}, 4270 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4271 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4272 AMDGPU_GFX_SQ_MEM, 4}, 4273 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4274 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4275 AMDGPU_GFX_SQC_MEM, 4}, 4276 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4277 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4278 AMDGPU_GFX_TCX_MEM, 1}, 4279 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4280 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4281 AMDGPU_GFX_TCC_MEM, 1}, 4282 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4283 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4284 AMDGPU_GFX_TA_MEM, 4}, 4285 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4286 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4287 AMDGPU_GFX_TCI_MEM, 1}, 4288 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4289 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4290 AMDGPU_GFX_TCP_MEM, 4}, 4291 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4292 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4293 AMDGPU_GFX_TD_MEM, 4}, 4294 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4295 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4296 AMDGPU_GFX_GCEA_MEM, 1}, 4297 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4298 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4299 AMDGPU_GFX_LDS_MEM, 4}, 4300 }; 4301 4302 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4303 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4304 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4305 AMDGPU_GFX_RLC_MEM, 1}, 4306 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4307 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4308 AMDGPU_GFX_CP_MEM, 1}, 4309 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4310 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4311 AMDGPU_GFX_CP_MEM, 1}, 4312 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4313 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4314 AMDGPU_GFX_CP_MEM, 1}, 4315 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4316 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4317 AMDGPU_GFX_GDS_MEM, 1}, 4318 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4319 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4320 AMDGPU_GFX_GC_CANE_MEM, 1}, 4321 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4322 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4323 AMDGPU_GFX_SPI_MEM, 1}, 4324 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4325 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4326 AMDGPU_GFX_SP_MEM, 4}, 4327 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4328 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4329 AMDGPU_GFX_SP_MEM, 4}, 4330 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4331 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4332 AMDGPU_GFX_SQ_MEM, 4}, 4333 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4334 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4335 AMDGPU_GFX_SQC_MEM, 4}, 4336 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4337 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4338 AMDGPU_GFX_TCX_MEM, 1}, 4339 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4340 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4341 AMDGPU_GFX_TCC_MEM, 1}, 4342 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4343 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4344 AMDGPU_GFX_TA_MEM, 4}, 4345 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4346 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4347 AMDGPU_GFX_TCI_MEM, 1}, 4348 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4349 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4350 AMDGPU_GFX_TCP_MEM, 4}, 4351 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4352 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4353 AMDGPU_GFX_TD_MEM, 4}, 4354 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4355 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4356 AMDGPU_GFX_TCA_MEM, 1}, 4357 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4358 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4359 AMDGPU_GFX_GCEA_MEM, 1}, 4360 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4361 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4362 AMDGPU_GFX_LDS_MEM, 4}, 4363 }; 4364 4365 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4366 void *ras_error_status, int xcc_id) 4367 { 4368 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4369 unsigned long ce_count = 0, ue_count = 0; 4370 uint32_t i, j, k; 4371 4372 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4373 struct amdgpu_smuio_mcm_config_info mcm_info = { 4374 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4375 .die_id = xcc_id & 0x01 ? 1 : 0, 4376 }; 4377 4378 mutex_lock(&adev->grbm_idx_mutex); 4379 4380 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4381 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4382 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4383 /* no need to select if instance number is 1 */ 4384 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4385 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4386 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4387 4388 amdgpu_ras_inst_query_ras_error_count(adev, 4389 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4390 1, 4391 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4392 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4393 GET_INST(GC, xcc_id), 4394 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4395 &ce_count); 4396 4397 amdgpu_ras_inst_query_ras_error_count(adev, 4398 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4399 1, 4400 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4401 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4402 GET_INST(GC, xcc_id), 4403 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4404 &ue_count); 4405 } 4406 } 4407 } 4408 4409 /* handle extra register entries of UE */ 4410 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4411 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4412 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4413 /* no need to select if instance number is 1 */ 4414 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4415 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4416 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4417 4418 amdgpu_ras_inst_query_ras_error_count(adev, 4419 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4420 1, 4421 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4422 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4423 GET_INST(GC, xcc_id), 4424 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4425 &ue_count); 4426 } 4427 } 4428 } 4429 4430 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4431 xcc_id); 4432 mutex_unlock(&adev->grbm_idx_mutex); 4433 4434 /* the caller should make sure initialize value of 4435 * err_data->ue_count and err_data->ce_count 4436 */ 4437 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4438 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4439 } 4440 4441 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4442 void *ras_error_status, int xcc_id) 4443 { 4444 uint32_t i, j, k; 4445 4446 mutex_lock(&adev->grbm_idx_mutex); 4447 4448 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4449 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4450 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4451 /* no need to select if instance number is 1 */ 4452 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4453 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4454 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4455 4456 amdgpu_ras_inst_reset_ras_error_count(adev, 4457 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4458 1, 4459 GET_INST(GC, xcc_id)); 4460 4461 amdgpu_ras_inst_reset_ras_error_count(adev, 4462 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4463 1, 4464 GET_INST(GC, xcc_id)); 4465 } 4466 } 4467 } 4468 4469 /* handle extra register entries of UE */ 4470 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4471 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4472 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4473 /* no need to select if instance number is 1 */ 4474 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4475 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4476 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4477 4478 amdgpu_ras_inst_reset_ras_error_count(adev, 4479 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4480 1, 4481 GET_INST(GC, xcc_id)); 4482 } 4483 } 4484 } 4485 4486 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4487 xcc_id); 4488 mutex_unlock(&adev->grbm_idx_mutex); 4489 } 4490 4491 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4492 void *ras_error_status, int xcc_id) 4493 { 4494 uint32_t i; 4495 uint32_t data; 4496 4497 if (amdgpu_sriov_vf(adev)) 4498 return; 4499 4500 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4501 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4502 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4503 4504 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4505 (amdgpu_watchdog_timer.period < 1 || 4506 amdgpu_watchdog_timer.period > 0x23)) { 4507 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4508 amdgpu_watchdog_timer.period = 0x23; 4509 } 4510 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4511 amdgpu_watchdog_timer.period); 4512 4513 mutex_lock(&adev->grbm_idx_mutex); 4514 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4515 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4516 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4517 } 4518 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4519 xcc_id); 4520 mutex_unlock(&adev->grbm_idx_mutex); 4521 } 4522 4523 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4524 void *ras_error_status) 4525 { 4526 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4527 gfx_v9_4_3_inst_query_ras_err_count); 4528 } 4529 4530 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4531 { 4532 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4533 } 4534 4535 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4536 { 4537 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4538 } 4539 4540 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4541 { 4542 /* Header itself is a NOP packet */ 4543 if (num_nop == 1) { 4544 amdgpu_ring_write(ring, ring->funcs->nop); 4545 return; 4546 } 4547 4548 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4549 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4550 4551 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4552 amdgpu_ring_insert_nop(ring, num_nop - 1); 4553 } 4554 4555 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4556 { 4557 struct amdgpu_device *adev = ip_block->adev; 4558 uint32_t i, j, k; 4559 uint32_t xcc_id, xcc_offset, inst_offset; 4560 uint32_t num_xcc, reg, num_inst; 4561 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4562 4563 if (!adev->gfx.ip_dump_core) 4564 return; 4565 4566 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4567 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4568 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4569 xcc_offset = xcc_id * reg_count; 4570 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4571 for (i = 0; i < reg_count; i++) 4572 drm_printf(p, "%-50s \t 0x%08x\n", 4573 gc_reg_list_9_4_3[i].reg_name, 4574 adev->gfx.ip_dump_core[xcc_offset + i]); 4575 } 4576 4577 /* print compute queue registers for all instances */ 4578 if (!adev->gfx.ip_dump_compute_queues) 4579 return; 4580 4581 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4582 adev->gfx.mec.num_queue_per_pipe; 4583 4584 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4585 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4586 num_xcc, 4587 adev->gfx.mec.num_mec, 4588 adev->gfx.mec.num_pipe_per_mec, 4589 adev->gfx.mec.num_queue_per_pipe); 4590 4591 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4592 xcc_offset = xcc_id * reg_count * num_inst; 4593 inst_offset = 0; 4594 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4595 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4596 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4597 drm_printf(p, 4598 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4599 xcc_id, i, j, k); 4600 for (reg = 0; reg < reg_count; reg++) { 4601 drm_printf(p, 4602 "%-50s \t 0x%08x\n", 4603 gc_cp_reg_list_9_4_3[reg].reg_name, 4604 adev->gfx.ip_dump_compute_queues 4605 [xcc_offset + inst_offset + 4606 reg]); 4607 } 4608 inst_offset += reg_count; 4609 } 4610 } 4611 } 4612 } 4613 } 4614 4615 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4616 { 4617 struct amdgpu_device *adev = ip_block->adev; 4618 uint32_t i, j, k; 4619 uint32_t num_xcc, reg, num_inst; 4620 uint32_t xcc_id, xcc_offset, inst_offset; 4621 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4622 4623 if (!adev->gfx.ip_dump_core) 4624 return; 4625 4626 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4627 4628 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4629 xcc_offset = xcc_id * reg_count; 4630 for (i = 0; i < reg_count; i++) 4631 adev->gfx.ip_dump_core[xcc_offset + i] = 4632 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4633 GET_INST(GC, xcc_id))); 4634 } 4635 4636 /* dump compute queue registers for all instances */ 4637 if (!adev->gfx.ip_dump_compute_queues) 4638 return; 4639 4640 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4641 adev->gfx.mec.num_queue_per_pipe; 4642 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4643 mutex_lock(&adev->srbm_mutex); 4644 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4645 xcc_offset = xcc_id * reg_count * num_inst; 4646 inst_offset = 0; 4647 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4648 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4649 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4650 /* ME0 is for GFX so start from 1 for CP */ 4651 soc15_grbm_select(adev, 1 + i, j, k, 0, 4652 GET_INST(GC, xcc_id)); 4653 4654 for (reg = 0; reg < reg_count; reg++) { 4655 adev->gfx.ip_dump_compute_queues 4656 [xcc_offset + 4657 inst_offset + reg] = 4658 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4659 gc_cp_reg_list_9_4_3[reg], 4660 GET_INST(GC, xcc_id))); 4661 } 4662 inst_offset += reg_count; 4663 } 4664 } 4665 } 4666 } 4667 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4668 mutex_unlock(&adev->srbm_mutex); 4669 } 4670 4671 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4672 { 4673 /* Emit the cleaner shader */ 4674 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4675 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4676 } 4677 4678 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4679 .name = "gfx_v9_4_3", 4680 .early_init = gfx_v9_4_3_early_init, 4681 .late_init = gfx_v9_4_3_late_init, 4682 .sw_init = gfx_v9_4_3_sw_init, 4683 .sw_fini = gfx_v9_4_3_sw_fini, 4684 .hw_init = gfx_v9_4_3_hw_init, 4685 .hw_fini = gfx_v9_4_3_hw_fini, 4686 .suspend = gfx_v9_4_3_suspend, 4687 .resume = gfx_v9_4_3_resume, 4688 .is_idle = gfx_v9_4_3_is_idle, 4689 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4690 .soft_reset = gfx_v9_4_3_soft_reset, 4691 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4692 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4693 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4694 .dump_ip_state = gfx_v9_4_3_ip_dump, 4695 .print_ip_state = gfx_v9_4_3_ip_print, 4696 }; 4697 4698 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4699 .type = AMDGPU_RING_TYPE_COMPUTE, 4700 .align_mask = 0xff, 4701 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4702 .support_64bit_ptrs = true, 4703 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4704 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4705 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4706 .emit_frame_size = 4707 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4708 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4709 5 + /* hdp invalidate */ 4710 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4711 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4712 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4713 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4714 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4715 7 + /* gfx_v9_4_3_emit_mem_sync */ 4716 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4717 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4718 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4719 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4720 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4721 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4722 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4723 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4724 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4725 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4726 .test_ring = gfx_v9_4_3_ring_test_ring, 4727 .test_ib = gfx_v9_4_3_ring_test_ib, 4728 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4729 .pad_ib = amdgpu_ring_generic_pad_ib, 4730 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4731 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4732 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4733 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4734 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4735 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4736 .reset = gfx_v9_4_3_reset_kcq, 4737 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4738 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4739 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4740 }; 4741 4742 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4743 .type = AMDGPU_RING_TYPE_KIQ, 4744 .align_mask = 0xff, 4745 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4746 .support_64bit_ptrs = true, 4747 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4748 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4749 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4750 .emit_frame_size = 4751 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4752 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4753 5 + /* hdp invalidate */ 4754 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4755 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4756 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4757 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4758 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4759 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4760 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4761 .test_ring = gfx_v9_4_3_ring_test_ring, 4762 .insert_nop = amdgpu_ring_insert_nop, 4763 .pad_ib = amdgpu_ring_generic_pad_ib, 4764 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4765 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4766 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4767 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4768 }; 4769 4770 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4771 { 4772 int i, j, num_xcc; 4773 4774 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4775 for (i = 0; i < num_xcc; i++) { 4776 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4777 4778 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4779 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4780 = &gfx_v9_4_3_ring_funcs_compute; 4781 } 4782 } 4783 4784 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4785 .set = gfx_v9_4_3_set_eop_interrupt_state, 4786 .process = gfx_v9_4_3_eop_irq, 4787 }; 4788 4789 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4790 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4791 .process = gfx_v9_4_3_priv_reg_irq, 4792 }; 4793 4794 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4795 .set = gfx_v9_4_3_set_bad_op_fault_state, 4796 .process = gfx_v9_4_3_bad_op_irq, 4797 }; 4798 4799 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4800 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4801 .process = gfx_v9_4_3_priv_inst_irq, 4802 }; 4803 4804 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4805 { 4806 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4807 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4808 4809 adev->gfx.priv_reg_irq.num_types = 1; 4810 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4811 4812 adev->gfx.bad_op_irq.num_types = 1; 4813 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4814 4815 adev->gfx.priv_inst_irq.num_types = 1; 4816 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4817 } 4818 4819 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4820 { 4821 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4822 } 4823 4824 4825 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4826 { 4827 /* 9.4.3 variants removed all the GDS internal memory, 4828 * only support GWS opcode in kernel, like barrier 4829 * semaphore.etc */ 4830 4831 /* init asic gds info */ 4832 adev->gds.gds_size = 0; 4833 adev->gds.gds_compute_max_wave_id = 0; 4834 adev->gds.gws_size = 64; 4835 adev->gds.oa_size = 16; 4836 } 4837 4838 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4839 u32 bitmap, int xcc_id) 4840 { 4841 u32 data; 4842 4843 if (!bitmap) 4844 return; 4845 4846 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4847 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4848 4849 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4850 } 4851 4852 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4853 { 4854 u32 data, mask; 4855 4856 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4857 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4858 4859 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4860 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4861 4862 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4863 4864 return (~data) & mask; 4865 } 4866 4867 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4868 struct amdgpu_cu_info *cu_info) 4869 { 4870 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4871 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4872 unsigned disable_masks[4 * 4]; 4873 bool is_symmetric_cus; 4874 4875 if (!adev || !cu_info) 4876 return -EINVAL; 4877 4878 /* 4879 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4880 */ 4881 if (adev->gfx.config.max_shader_engines * 4882 adev->gfx.config.max_sh_per_se > 16) 4883 return -EINVAL; 4884 4885 amdgpu_gfx_parse_disable_cu(disable_masks, 4886 adev->gfx.config.max_shader_engines, 4887 adev->gfx.config.max_sh_per_se); 4888 4889 mutex_lock(&adev->grbm_idx_mutex); 4890 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4891 is_symmetric_cus = true; 4892 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4893 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4894 mask = 1; 4895 ao_bitmap = 0; 4896 counter = 0; 4897 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4898 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4899 adev, 4900 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4901 xcc_id); 4902 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4903 4904 cu_info->bitmap[xcc_id][i][j] = bitmap; 4905 4906 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4907 if (bitmap & mask) { 4908 if (counter < adev->gfx.config.max_cu_per_sh) 4909 ao_bitmap |= mask; 4910 counter++; 4911 } 4912 mask <<= 1; 4913 } 4914 active_cu_number += counter; 4915 if (i < 2 && j < 2) 4916 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4917 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4918 } 4919 if (i && is_symmetric_cus && prev_counter != counter) 4920 is_symmetric_cus = false; 4921 prev_counter = counter; 4922 } 4923 if (is_symmetric_cus) { 4924 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4925 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4926 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4927 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4928 } 4929 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4930 xcc_id); 4931 } 4932 mutex_unlock(&adev->grbm_idx_mutex); 4933 4934 cu_info->number = active_cu_number; 4935 cu_info->ao_cu_mask = ao_cu_mask; 4936 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4937 4938 return 0; 4939 } 4940 4941 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4942 .type = AMD_IP_BLOCK_TYPE_GFX, 4943 .major = 9, 4944 .minor = 4, 4945 .rev = 3, 4946 .funcs = &gfx_v9_4_3_ip_funcs, 4947 }; 4948 4949 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4950 { 4951 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4952 uint32_t tmp_mask; 4953 int i, r; 4954 4955 /* TODO : Initialize golden regs */ 4956 /* gfx_v9_4_3_init_golden_registers(adev); */ 4957 4958 tmp_mask = inst_mask; 4959 for_each_inst(i, tmp_mask) 4960 gfx_v9_4_3_xcc_constants_init(adev, i); 4961 4962 if (!amdgpu_sriov_vf(adev)) { 4963 tmp_mask = inst_mask; 4964 for_each_inst(i, tmp_mask) { 4965 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4966 if (r) 4967 return r; 4968 } 4969 } 4970 4971 tmp_mask = inst_mask; 4972 for_each_inst(i, tmp_mask) { 4973 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4974 if (r) 4975 return r; 4976 } 4977 4978 return 0; 4979 } 4980 4981 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4982 { 4983 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4984 int i; 4985 4986 for_each_inst(i, inst_mask) 4987 gfx_v9_4_3_xcc_fini(adev, i); 4988 4989 return 0; 4990 } 4991 4992 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4993 .suspend = &gfx_v9_4_3_xcp_suspend, 4994 .resume = &gfx_v9_4_3_xcp_resume 4995 }; 4996 4997 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4998 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4999 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5000 }; 5001 5002 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5003 { 5004 int r; 5005 5006 r = amdgpu_ras_block_late_init(adev, ras_block); 5007 if (r) 5008 return r; 5009 5010 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5011 &gfx_v9_4_3_aca_info, 5012 NULL); 5013 if (r) 5014 goto late_fini; 5015 5016 return 0; 5017 5018 late_fini: 5019 amdgpu_ras_block_late_fini(adev, ras_block); 5020 5021 return r; 5022 } 5023 5024 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5025 .ras_block = { 5026 .hw_ops = &gfx_v9_4_3_ras_ops, 5027 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5028 }, 5029 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5030 }; 5031