1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Copyright (c) 2021 BayLibre, SAS 5 * Copyright (c) 2024 Collabora Ltd. 6 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 7 */ 8 9 #ifndef _MTK_HDMI_REGS_H 10 #define _MTK_HDMI_REGS_H 11 12 /* HDMI_TOP Config */ 13 #define TOP_CFG00 0x000 14 #define HDMI2_ON BIT(2) 15 #define HDMI_MODE_HDMI BIT(3) 16 #define SCR_ON BIT(4) 17 #define TMDS_PACK_MODE GENMASK(9, 8) 18 #define TMDS_PACK_MODE_8BPP 0 19 #define TMDS_PACK_MODE_10BPP 1 20 #define TMDS_PACK_MODE_12BPP 2 21 #define TMDS_PACK_MODE_16BPP 3 22 #define DEEPCOLOR_PKT_EN BIT(12) 23 #define HDMI_ABIST_VIDEO_FORMAT GENMASK(21, 16) 24 #define HDMI_ABIST_ENABLE BIT(31) 25 #define TOP_CFG01 0x004 26 #define CP_SET_MUTE_EN BIT(0) 27 #define CP_CLR_MUTE_EN BIT(1) 28 #define NULL_PKT_EN BIT(2) 29 #define NULL_PKT_VSYNC_HIGH_EN BIT(3) 30 31 /* HDMI_TOP Audio: Channel Mapping */ 32 #define TOP_AUD_MAP 0x00c 33 #define SD0_MAP GENMASK(2, 0) 34 #define SD1_MAP GENMASK(6, 4) 35 #define SD2_MAP GENMASK(10, 8) 36 #define SD3_MAP GENMASK(14, 12) 37 #define SD4_MAP GENMASK(18, 16) 38 #define SD5_MAP GENMASK(22, 20) 39 #define SD6_MAP GENMASK(26, 24) 40 #define SD7_MAP GENMASK(30, 28) 41 42 /* Auxiliary Video Information (AVI) Infoframe */ 43 #define TOP_AVI_HEADER 0x024 44 #define TOP_AVI_PKT00 0x028 45 #define TOP_AVI_PKT01 0x02C 46 #define TOP_AVI_PKT02 0x030 47 #define TOP_AVI_PKT03 0x034 48 #define TOP_AVI_PKT04 0x038 49 #define TOP_AVI_PKT05 0x03C 50 51 /* Audio Interface Infoframe */ 52 #define TOP_AIF_HEADER 0x040 53 #define TOP_AIF_PKT00 0x044 54 #define TOP_AIF_PKT01 0x048 55 #define TOP_AIF_PKT02 0x04c 56 #define TOP_AIF_PKT03 0x050 57 58 /* Audio SPDIF Infoframe */ 59 #define TOP_SPDIF_HEADER 0x054 60 #define TOP_SPDIF_PKT00 0x058 61 #define TOP_SPDIF_PKT01 0x05c 62 #define TOP_SPDIF_PKT02 0x060 63 #define TOP_SPDIF_PKT03 0x064 64 #define TOP_SPDIF_PKT04 0x068 65 #define TOP_SPDIF_PKT05 0x06c 66 #define TOP_SPDIF_PKT06 0x070 67 #define TOP_SPDIF_PKT07 0x074 68 69 /* Infoframes Configuration */ 70 #define TOP_INFO_EN 0x01c 71 #define AVI_EN BIT(0) 72 #define SPD_EN BIT(1) 73 #define AUD_EN BIT(2) 74 #define CP_EN BIT(5) 75 #define VSIF_EN BIT(11) 76 #define AVI_EN_WR BIT(16) 77 #define SPD_EN_WR BIT(17) 78 #define AUD_EN_WR BIT(18) 79 #define CP_EN_WR BIT(21) 80 #define VSIF_EN_WR BIT(27) 81 #define TOP_INFO_RPT 0x020 82 #define AVI_RPT_EN BIT(0) 83 #define SPD_RPT_EN BIT(1) 84 #define AUD_RPT_EN BIT(2) 85 #define CP_RPT_EN BIT(5) 86 #define VSIF_RPT_EN BIT(11) 87 88 /* Vendor Specific Infoframe */ 89 #define TOP_VSIF_HEADER 0x174 90 #define TOP_VSIF_PKT00 0x178 91 #define TOP_VSIF_PKT01 0x17c 92 #define TOP_VSIF_PKT02 0x180 93 #define TOP_VSIF_PKT03 0x184 94 #define TOP_VSIF_PKT04 0x188 95 #define TOP_VSIF_PKT05 0x18c 96 #define TOP_VSIF_PKT06 0x190 97 #define TOP_VSIF_PKT07 0x194 98 99 /* HDMI_TOP Misc */ 100 #define TOP_MISC_CTLR 0x1a4 101 #define DEEP_COLOR_ADD BIT(4) 102 103 /* Hardware interrupts */ 104 #define TOP_INT_STA00 0x1a8 105 #define TOP_INT_ENABLE00 0x1b0 106 #define HTPLG_R_INT BIT(0) 107 #define HTPLG_F_INT BIT(1) 108 #define PORD_R_INT BIT(2) 109 #define PORD_F_INT BIT(3) 110 #define HDMI_VSYNC_INT BIT(4) 111 #define HDMI_AUDIO_INT BIT(5) 112 #define HDCP2X_RX_REAUTH_REQ_DDCM_INT BIT(25) 113 #define TOP_INT_ENABLE01 0x1b4 114 #define TOP_INT_CLR00 0x1b8 115 #define TOP_INT_CLR01 0x1bc 116 117 118 /* Video Mute */ 119 #define TOP_VMUTE_CFG1 0x1c8 120 #define REG_VMUTE_EN BIT(16) 121 122 /* HDMI Audio IP */ 123 #define AIP_CTRL 0x400 124 #define CTS_SW_SEL BIT(0) 125 #define CTS_REQ_EN BIT(1) 126 #define MCLK_EN BIT(2) 127 #define NO_MCLK_CTSGEN_SEL BIT(3) 128 #define AUD_IN_EN BIT(8) 129 #define AUD_SEL_OWRT BIT(9) 130 #define SPDIF_EN BIT(13) 131 #define HBRA_ON BIT(14) 132 #define DSD_EN BIT(15) 133 #define I2S_EN GENMASK(19, 16) 134 #define HBR_FROM_SPDIF BIT(20) 135 #define CTS_CAL_N4 BIT(23) 136 #define SPDIF_INTERNAL_MODULE BIT(24) 137 #define AIP_N_VAL 0x404 138 #define AIP_CTS_SVAL 0x408 139 #define AIP_SPDIF_CTRL 0x40c 140 #define WR_1UI_LOCK BIT(0) 141 #define FS_OVERRIDE_WRITE BIT(1) 142 #define WR_2UI_LOCK BIT(2) 143 #define MAX_1UI_WRITE GENMASK(15, 8) 144 #define MAX_2UI_SPDIF_WRITE GENMASK(23, 16) 145 #define MAX_2UI_I2S_HI_WRITE GENMASK(23, 20) 146 #define MAX_2UI_I2S_LFE_CC_SWAP BIT(1) 147 #define MAX_2UI_I2S_LO_WRITE GENMASK(19, 16) 148 #define AUD_ERR_THRESH GENMASK(29, 24) 149 #define I2S2DSD_EN BIT(30) 150 #define AIP_I2S_CTRL 0x410 151 #define FIFO0_MAP GENMASK(1, 0) 152 #define FIFO1_MAP GENMASK(3, 2) 153 #define FIFO2_MAP GENMASK(5, 4) 154 #define FIFO3_MAP GENMASK(7, 6) 155 #define I2S_1ST_BIT_NOSHIFT BIT(8) 156 #define I2S_DATA_DIR_LSB BIT(9) 157 #define JUSTIFY_RIGHT BIT(10) 158 #define WS_HIGH BIT(11) 159 #define VBIT_COMPRESSED BIT(12) 160 #define CBIT_ORDER_SAME BIT(13) 161 #define SCK_EDGE_RISE BIT(14) 162 #define AIP_I2S_CHST0 0x414 163 #define AIP_I2S_CHST1 0x418 164 #define AIP_TXCTRL 0x424 165 #define RST4AUDIO BIT(0) 166 #define RST4AUDIO_FIFO BIT(1) 167 #define RST4AUDIO_ACR BIT(2) 168 #define AUD_LAYOUT_1 BIT(4) 169 #define AUD_MUTE_FIFO_EN BIT(5) 170 #define AUD_PACKET_DROP BIT(6) 171 #define DSD_MUTE_EN BIT(7) 172 #define AIP_TPI_CTRL 0x428 173 #define TPI_AUDIO_LOOKUP_EN BIT(2) 174 175 /* Video downsampling configuration */ 176 #define VID_DOWNSAMPLE_CONFIG 0x8d0 177 #define C444_C422_CONFIG_ENABLE BIT(0) 178 #define C422_C420_CONFIG_ENABLE BIT(4) 179 #define C422_C420_CONFIG_BYPASS BIT(5) 180 #define C422_C420_CONFIG_OUT_CB_OR_CR BIT(6) 181 #define VID_OUT_FORMAT 0x8fc 182 #define OUTPUT_FORMAT_DEMUX_420_ENABLE BIT(10) 183 184 /* HDCP registers */ 185 #define HDCP_TOP_CTRL 0xc00 186 #define HDCP2X_CTRL_0 0xc20 187 #define HDCP2X_EN BIT(0) 188 #define HDCP2X_ENCRYPT_EN BIT(7) 189 #define HDCP2X_HPD_OVR BIT(10) 190 #define HDCP2X_HPD_SW BIT(11) 191 #define HDCP2X_POL_CTRL 0xc54 192 #define HDCP2X_DIS_POLL_EN BIT(16) 193 #define HDCP1X_CTRL 0xcd0 194 #define HDCP1X_ENC_EN BIT(6) 195 196 /* HDMI DDC registers */ 197 #define HPD_DDC_CTRL 0xc08 198 #define HPD_DDC_DELAY_CNT GENMASK(31, 16) 199 #define HPD_DDC_HPD_DBNC_EN BIT(2) 200 #define HPD_DDC_PORD_DBNC_EN BIT(3) 201 #define DDC_CTRL 0xc10 202 #define DDC_CTRL_ADDR GENMASK(7, 1) 203 #define DDC_CTRL_OFFSET GENMASK(15, 8) 204 #define DDC_CTRL_DIN_CNT GENMASK(25, 16) 205 #define DDC_CTRL_CMD GENMASK(31, 28) 206 #define SCDC_CTRL 0xc18 207 #define SCDC_DDC_SEGMENT GENMASK(15, 8) 208 #define HPD_DDC_STATUS 0xc60 209 #define HPD_STATE GENMASK(1, 0) 210 #define HPD_STATE_CONNECTED 2 211 #define HPD_PIN_STA BIT(4) 212 #define PORD_PIN_STA BIT(5) 213 #define DDC_I2C_IN_PROG BIT(13) 214 #define DDC_DATA_OUT GENMASK(23, 16) 215 #define SI2C_CTRL 0xcac 216 #define SI2C_WR BIT(0) 217 #define SI2C_RD BIT(1) 218 #define SI2C_CONFIRM_READ BIT(2) 219 #define SI2C_WDATA GENMASK(15, 8) 220 #define SI2C_ADDR GENMASK(23, 16) 221 222 /* HDCP DDC registers */ 223 #define HDCP2X_DDCM_STATUS 0xc68 224 #define DDC_I2C_NO_ACK BIT(10) 225 #define DDC_I2C_BUS_LOW BIT(11) 226 227 /* HDMI TX registers */ 228 #define HDMITX_CONFIG_MT8188 0xea0 229 #define HDMITX_CONFIG_MT8195 0x900 230 #define HDMI_YUV420_MODE BIT(10) 231 #define HDMITX_SW_HPD BIT(29) 232 #define HDMITX_SW_RSTB BIT(31) 233 234 /** 235 * enum mtk_hdmi_ddc_v2_cmds - DDC_CMD register commands 236 * @DDC_CMD_READ_NOACK: Current address read with no ACK on last byte 237 * @DDC_CMD_READ: Current address read with ACK on last byte 238 * @DDC_CMD_SEQ_READ_NOACK: Sequential read with no ACK on last byte 239 * @DDC_CMD_SEQ_READ: Sequential read with ACK on last byte 240 * @DDC_CMD_ENH_READ_NOACK: Enhanced read with no ACK on last byte 241 * @DDC_CMD_ENH_READ: Enhanced read with ACK on last byte 242 * @DDC_CMD_SEQ_WRITE_NOACK: Sequential write ignoring ACK on last byte 243 * @DDC_CMD_SEQ_WRITE: Sequential write requiring ACK on last byte 244 * @DDC_CMD_RSVD: Reserved for future use 245 * @DDC_CMD_CLEAR_FIFO: Clear DDC I2C FIFO 246 * @DDC_CMD_CLOCK_SCL: Start clocking DDC I2C SCL 247 * @DDC_CMD_ABORT_XFER: Abort DDC I2C transaction 248 */ 249 enum mtk_hdmi_ddc_v2_cmds { 250 DDC_CMD_READ_NOACK = 0x0, 251 DDC_CMD_READ, 252 DDC_CMD_SEQ_READ_NOACK, 253 DDC_CMD_SEQ_READ, 254 DDC_CMD_ENH_READ_NOACK, 255 DDC_CMD_ENH_READ, 256 DDC_CMD_SEQ_WRITE_NOACK, 257 DDC_CMD_SEQ_WRITE = 0x07, 258 DDC_CMD_CLEAR_FIFO = 0x09, 259 DDC_CMD_CLOCK_SCL = 0x0a, 260 DDC_CMD_ABORT_XFER = 0x0f 261 }; 262 263 #endif /* _MTK_HDMI_REGS_H */ 264