1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R-Car Gen3 Clock Pulse Generator
4 *
5 * Copyright (C) 2015-2018 Glider bvba
6 * Copyright (C) 2019 Renesas Electronics Corp.
7 *
8 * Based on clk-rcar-gen3.c
9 *
10 * Copyright (C) 2015 Renesas Electronics Corp.
11 */
12
13 #include <linux/bug.h>
14 #include <linux/bitfield.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/device.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/pm.h>
22 #include <linux/slab.h>
23 #include <linux/sys_soc.h>
24
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
28
29 #define CPG_PLLECR 0x00d0 /* PLL Enable Control Register */
30
31 #define CPG_PLLECR_PLLST(n) BIT(8 + (n)) /* PLLn Circuit Status */
32
33 #define CPG_PLL0CR 0x00d8 /* PLLn Control Registers */
34 #define CPG_PLL2CR 0x002c
35 #define CPG_PLL4CR 0x01f4
36
37 #define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */
38
39 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
40
41 /* PLL Clocks */
42 struct cpg_pll_clk {
43 struct clk_hw hw;
44 void __iomem *pllcr_reg;
45 void __iomem *pllecr_reg;
46 unsigned int fixed_mult;
47 u32 pllecr_pllst_mask;
48 };
49
50 #define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw)
51
cpg_pll_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)52 static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
53 unsigned long parent_rate)
54 {
55 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
56 unsigned int mult;
57
58 mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1;
59
60 return parent_rate * mult * pll_clk->fixed_mult;
61 }
62
cpg_pll_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)63 static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
64 struct clk_rate_request *req)
65 {
66 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
67 unsigned int min_mult, max_mult, mult;
68 unsigned long prate;
69
70 prate = req->best_parent_rate * pll_clk->fixed_mult;
71 min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
72 max_mult = min(div64_ul(req->max_rate, prate), 128ULL);
73 if (max_mult < min_mult)
74 return -EINVAL;
75
76 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
77 mult = clamp(mult, min_mult, max_mult);
78
79 req->rate = prate * mult;
80 return 0;
81 }
82
cpg_pll_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)83 static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
84 unsigned long parent_rate)
85 {
86 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
87 unsigned int mult, i;
88 u32 val;
89
90 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
91 mult = clamp(mult, 1U, 128U);
92
93 val = readl(pll_clk->pllcr_reg);
94 val &= ~CPG_PLLnCR_STC_MASK;
95 val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1);
96 writel(val, pll_clk->pllcr_reg);
97
98 for (i = 1000; i; i--) {
99 if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)
100 return 0;
101
102 cpu_relax();
103 }
104
105 return -ETIMEDOUT;
106 }
107
108 static const struct clk_ops cpg_pll_clk_ops = {
109 .recalc_rate = cpg_pll_clk_recalc_rate,
110 .determine_rate = cpg_pll_clk_determine_rate,
111 .set_rate = cpg_pll_clk_set_rate,
112 };
113
cpg_pll_clk_register(const char * name,const char * parent_name,void __iomem * base,unsigned int mult,unsigned int offset,unsigned int index)114 static struct clk * __init cpg_pll_clk_register(const char *name,
115 const char *parent_name,
116 void __iomem *base,
117 unsigned int mult,
118 unsigned int offset,
119 unsigned int index)
120
121 {
122 struct cpg_pll_clk *pll_clk;
123 struct clk_init_data init = {};
124 struct clk *clk;
125
126 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
127 if (!pll_clk)
128 return ERR_PTR(-ENOMEM);
129
130 init.name = name;
131 init.ops = &cpg_pll_clk_ops;
132 init.parent_names = &parent_name;
133 init.num_parents = 1;
134
135 pll_clk->hw.init = &init;
136 pll_clk->pllcr_reg = base + offset;
137 pll_clk->pllecr_reg = base + CPG_PLLECR;
138 pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */
139 pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
140
141 clk = clk_register(NULL, &pll_clk->hw);
142 if (IS_ERR(clk))
143 kfree(pll_clk);
144
145 return clk;
146 }
147
148 /*
149 * Z Clock & Z2 Clock
150 *
151 * Traits of this clock:
152 * prepare - clk_prepare only ensures that parents are prepared
153 * enable - clk_enable only ensures that parents are enabled
154 * rate - rate is adjustable.
155 * clk->rate = (parent->rate * mult / 32 ) / fixed_div
156 * parent - fixed parent. No clk_set_parent support
157 */
158 #define CPG_FRQCRB 0x00000004
159 #define CPG_FRQCRB_KICK BIT(31)
160 #define CPG_FRQCRC 0x000000e0
161
162 struct cpg_z_clk {
163 struct clk_hw hw;
164 void __iomem *reg;
165 void __iomem *kick_reg;
166 unsigned long max_rate; /* Maximum rate for normal mode */
167 unsigned int fixed_div;
168 u32 mask;
169 };
170
171 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
172
cpg_z_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)173 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
174 unsigned long parent_rate)
175 {
176 struct cpg_z_clk *zclk = to_z_clk(hw);
177 unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg));
178
179 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
180 32 * zclk->fixed_div);
181 }
182
cpg_z_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)183 static int cpg_z_clk_determine_rate(struct clk_hw *hw,
184 struct clk_rate_request *req)
185 {
186 struct cpg_z_clk *zclk = to_z_clk(hw);
187 unsigned int min_mult, max_mult, mult;
188 unsigned long rate, prate;
189
190 rate = min(req->rate, req->max_rate);
191 if (rate <= zclk->max_rate) {
192 /* Set parent rate to initial value for normal modes */
193 prate = zclk->max_rate;
194 } else {
195 /* Set increased parent rate for boost modes */
196 prate = rate;
197 }
198 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
199 prate * zclk->fixed_div);
200
201 prate = req->best_parent_rate / zclk->fixed_div;
202 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
203 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
204 if (max_mult < min_mult)
205 return -EINVAL;
206
207 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
208 mult = clamp(mult, min_mult, max_mult);
209
210 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
211 return 0;
212 }
213
cpg_z_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)214 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
215 unsigned long parent_rate)
216 {
217 struct cpg_z_clk *zclk = to_z_clk(hw);
218 unsigned int mult;
219 unsigned int i;
220
221 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
222 parent_rate);
223 mult = clamp(mult, 1U, 32U);
224
225 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
226 return -EBUSY;
227
228 cpg_reg_modify(zclk->reg, zclk->mask,
229 field_prep(zclk->mask, 32 - mult));
230
231 /*
232 * Set KICK bit in FRQCRB to update hardware setting and wait for
233 * clock change completion.
234 */
235 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
236
237 /*
238 * Note: There is no HW information about the worst case latency.
239 *
240 * Using experimental measurements, it seems that no more than
241 * ~10 iterations are needed, independently of the CPU rate.
242 * Since this value might be dependent on external xtal rate, pll1
243 * rate or even the other emulation clocks rate, use 1000 as a
244 * "super" safe value.
245 */
246 for (i = 1000; i; i--) {
247 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
248 return 0;
249
250 cpu_relax();
251 }
252
253 return -ETIMEDOUT;
254 }
255
256 static const struct clk_ops cpg_z_clk_ops = {
257 .recalc_rate = cpg_z_clk_recalc_rate,
258 .determine_rate = cpg_z_clk_determine_rate,
259 .set_rate = cpg_z_clk_set_rate,
260 };
261
__cpg_z_clk_register(const char * name,const char * parent_name,void __iomem * reg,unsigned int div,unsigned int offset,unsigned int fcr,unsigned int flags)262 static struct clk * __init __cpg_z_clk_register(const char *name,
263 const char *parent_name,
264 void __iomem *reg,
265 unsigned int div,
266 unsigned int offset,
267 unsigned int fcr,
268 unsigned int flags)
269 {
270 struct clk_init_data init = {};
271 struct cpg_z_clk *zclk;
272 struct clk *clk;
273
274 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
275 if (!zclk)
276 return ERR_PTR(-ENOMEM);
277
278 init.name = name;
279 init.ops = &cpg_z_clk_ops;
280 init.flags = flags;
281 init.parent_names = &parent_name;
282 init.num_parents = 1;
283
284 zclk->reg = reg + fcr;
285 zclk->kick_reg = reg + CPG_FRQCRB;
286 zclk->hw.init = &init;
287 zclk->mask = GENMASK(offset + 4, offset);
288 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
289
290 clk = clk_register(NULL, &zclk->hw);
291 if (IS_ERR(clk)) {
292 kfree(zclk);
293 return clk;
294 }
295
296 zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
297 zclk->fixed_div;
298 return clk;
299 }
300
cpg_z_clk_register(const char * name,const char * parent_name,void __iomem * reg,unsigned int div,unsigned int offset)301 static struct clk * __init cpg_z_clk_register(const char *name,
302 const char *parent_name,
303 void __iomem *reg,
304 unsigned int div,
305 unsigned int offset)
306 {
307 return __cpg_z_clk_register(name, parent_name, reg, div, offset,
308 CPG_FRQCRC, CLK_SET_RATE_PARENT);
309 }
310
cpg_zg_clk_register(const char * name,const char * parent_name,void __iomem * reg,unsigned int div,unsigned int offset)311 static struct clk * __init cpg_zg_clk_register(const char *name,
312 const char *parent_name,
313 void __iomem *reg,
314 unsigned int div,
315 unsigned int offset)
316 {
317 return __cpg_z_clk_register(name, parent_name, reg, div, offset,
318 CPG_FRQCRB, 0);
319
320 }
321
322 static const struct clk_div_table cpg_rpcsrc_div_table[] = {
323 { 2, 5 }, { 3, 6 }, { 0, 0 },
324 };
325
326 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
327 static unsigned int cpg_clk_extalr __initdata;
328 static u32 cpg_mode __initdata;
329 static u32 cpg_quirks __initdata;
330
331 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
332
333 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
334 {
335 .soc_id = "r8a7796", .revision = "ES1.0",
336 .data = (void *)(RCKCR_CKSEL),
337 },
338 { /* sentinel */ }
339 };
340
rcar_gen3_cpg_clk_register(struct device * dev,const struct cpg_core_clk * core,const struct cpg_mssr_info * info,struct cpg_mssr_pub * pub)341 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
342 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
343 struct cpg_mssr_pub *pub)
344 {
345 struct raw_notifier_head *notifiers = &pub->notifiers;
346 void __iomem *base = pub->base0;
347 struct clk **clks = pub->clks;
348 const struct clk *parent;
349 unsigned int mult = 1;
350 unsigned int div = 1;
351 u32 value;
352
353 parent = clks[core->parent & 0xffff]; /* some types use high bits */
354 if (IS_ERR(parent))
355 return ERR_CAST(parent);
356
357 switch (core->type) {
358 case CLK_TYPE_GEN3_MAIN:
359 div = cpg_pll_config->extal_div;
360 break;
361
362 case CLK_TYPE_GEN3_PLL0:
363 /*
364 * PLL0 is implemented as a custom clock, to change the
365 * multiplier when cpufreq changes between normal and boost
366 * modes.
367 */
368 return cpg_pll_clk_register(core->name, __clk_get_name(parent),
369 base, 2, CPG_PLL0CR, 0);
370
371 case CLK_TYPE_GEN3_PLL1:
372 mult = cpg_pll_config->pll1_mult;
373 div = cpg_pll_config->pll1_div;
374 break;
375
376 case CLK_TYPE_GEN3_PLL2:
377 /*
378 * PLL2 is implemented as a custom clock, to change the
379 * multiplier when cpufreq changes between normal and boost
380 * modes.
381 */
382 return cpg_pll_clk_register(core->name, __clk_get_name(parent),
383 base, 2, CPG_PLL2CR, 2);
384
385 case CLK_TYPE_GEN3_PLL3:
386 mult = cpg_pll_config->pll3_mult;
387 div = cpg_pll_config->pll3_div;
388 break;
389
390 case CLK_TYPE_GEN3_PLL4:
391 /*
392 * PLL4 is a configurable multiplier clock. Register it as a
393 * fixed factor clock for now as there's no generic multiplier
394 * clock implementation and we currently have no need to change
395 * the multiplier value.
396 */
397 value = readl(base + CPG_PLL4CR);
398 mult = (((value >> 24) & 0x7f) + 1) * 2;
399 break;
400
401 case CLK_TYPE_GEN3_SDH:
402 return cpg_sdh_clk_register(core->name, base + core->offset,
403 __clk_get_name(parent), notifiers);
404
405 case CLK_TYPE_GEN3_SD:
406 return cpg_sd_clk_register(core->name, base + core->offset,
407 __clk_get_name(parent));
408
409 case CLK_TYPE_GEN3_R:
410 if (cpg_quirks & RCKCR_CKSEL) {
411 struct cpg_simple_notifier *csn;
412
413 csn = kzalloc(sizeof(*csn), GFP_KERNEL);
414 if (!csn)
415 return ERR_PTR(-ENOMEM);
416
417 csn->reg = base + CPG_RCKCR;
418
419 /*
420 * RINT is default.
421 * Only if EXTALR is populated, we switch to it.
422 */
423 value = readl(csn->reg) & 0x3f;
424
425 if (clk_get_rate(clks[cpg_clk_extalr])) {
426 parent = clks[cpg_clk_extalr];
427 value |= CPG_RCKCR_CKSEL;
428 }
429
430 writel(value, csn->reg);
431 cpg_simple_notifier_register(notifiers, csn);
432 break;
433 }
434
435 /* Select parent clock of RCLK by MD28 */
436 if (cpg_mode & BIT(28))
437 parent = clks[cpg_clk_extalr];
438 break;
439
440 case CLK_TYPE_GEN3_MDSEL:
441 /*
442 * Clock selectable between two parents and two fixed dividers
443 * using a mode pin
444 */
445 if (cpg_mode & BIT(core->offset)) {
446 div = core->div & 0xffff;
447 } else {
448 parent = clks[core->parent >> 16];
449 if (IS_ERR(parent))
450 return ERR_CAST(parent);
451 div = core->div >> 16;
452 }
453 mult = 1;
454 break;
455
456 case CLK_TYPE_GEN3_Z:
457 return cpg_z_clk_register(core->name, __clk_get_name(parent),
458 base, core->div, core->offset);
459
460 case CLK_TYPE_GEN3_ZG:
461 return cpg_zg_clk_register(core->name, __clk_get_name(parent),
462 base, core->div, core->offset);
463
464 case CLK_TYPE_GEN3_OSC:
465 /*
466 * Clock combining OSC EXTAL predivider and a fixed divider
467 */
468 div = cpg_pll_config->osc_prediv * core->div;
469 break;
470
471 case CLK_TYPE_GEN3_RCKSEL:
472 /*
473 * Clock selectable between two parents and two fixed dividers
474 * using RCKCR.CKSEL
475 */
476 if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
477 div = core->div & 0xffff;
478 } else {
479 parent = clks[core->parent >> 16];
480 if (IS_ERR(parent))
481 return ERR_CAST(parent);
482 div = core->div >> 16;
483 }
484 break;
485
486 case CLK_TYPE_GEN3_RPCSRC:
487 return clk_register_divider_table(NULL, core->name,
488 __clk_get_name(parent), 0,
489 base + CPG_RPCCKCR, 3, 2, 0,
490 cpg_rpcsrc_div_table,
491 &cpg_lock);
492
493 case CLK_TYPE_GEN3_E3_RPCSRC:
494 /*
495 * Register RPCSRC as fixed factor clock based on the
496 * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
497 * which has been set prior to booting the kernel.
498 */
499 value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
500
501 switch (value) {
502 case 0:
503 div = 5;
504 break;
505 case 1:
506 div = 3;
507 break;
508 case 2:
509 parent = clks[core->parent >> 16];
510 if (IS_ERR(parent))
511 return ERR_CAST(parent);
512 div = core->div;
513 break;
514 case 3:
515 default:
516 div = 2;
517 break;
518 }
519 break;
520
521 case CLK_TYPE_GEN3_RPC:
522 return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
523 __clk_get_name(parent), notifiers);
524
525 case CLK_TYPE_GEN3_RPCD2:
526 return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
527 __clk_get_name(parent));
528
529 default:
530 return ERR_PTR(-EINVAL);
531 }
532
533 return clk_register_fixed_factor(NULL, core->name,
534 __clk_get_name(parent), 0, mult, div);
535 }
536
rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config * config,unsigned int clk_extalr,u32 mode)537 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
538 unsigned int clk_extalr, u32 mode)
539 {
540 const struct soc_device_attribute *attr;
541
542 cpg_pll_config = config;
543 cpg_clk_extalr = clk_extalr;
544 cpg_mode = mode;
545 attr = soc_device_match(cpg_quirks_match);
546 if (attr)
547 cpg_quirks = (uintptr_t)attr->data;
548 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
549
550 return 0;
551 }
552