1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * UEFI Common Platform Error Record
4 *
5 * Copyright (C) 2010, Intel Corp.
6 * Author: Huang Ying <ying.huang@intel.com>
7 */
8
9 #ifndef LINUX_CPER_H
10 #define LINUX_CPER_H
11
12 #include <linux/uuid.h>
13 #include <linux/trace_seq.h>
14
15 /* CPER record signature and the size */
16 #define CPER_SIG_RECORD "CPER"
17 #define CPER_SIG_SIZE 4
18 /* Used in signature_end field in struct cper_record_header */
19 #define CPER_SIG_END 0xffffffff
20
21 /*
22 * CPER record header revision, used in revision field in struct
23 * cper_record_header
24 */
25 #define CPER_RECORD_REV 0x0100
26
27 /*
28 * CPER record length contains the CPER fields which are relevant for further
29 * handling of a memory error in userspace (we don't carry all the fields
30 * defined in the UEFI spec because some of them don't make any sense.)
31 * Currently, a length of 256 should be more than enough.
32 */
33 #define CPER_REC_LEN 256
34 /*
35 * Severity definition for error_severity in struct cper_record_header
36 * and section_severity in struct cper_section_descriptor
37 */
38 enum {
39 CPER_SEV_RECOVERABLE,
40 CPER_SEV_FATAL,
41 CPER_SEV_CORRECTED,
42 CPER_SEV_INFORMATIONAL,
43 };
44
45 /*
46 * Validation bits definition for validation_bits in struct
47 * cper_record_header. If set, corresponding fields in struct
48 * cper_record_header contain valid information.
49 */
50 #define CPER_VALID_PLATFORM_ID 0x0001
51 #define CPER_VALID_TIMESTAMP 0x0002
52 #define CPER_VALID_PARTITION_ID 0x0004
53
54 /*
55 * Notification type used to generate error record, used in
56 * notification_type in struct cper_record_header. These UUIDs are defined
57 * in the UEFI spec v2.7, sec N.2.1.
58 */
59
60 /* Corrected Machine Check */
61 #define CPER_NOTIFY_CMC \
62 GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
63 0xEB, 0xD4, 0xF8, 0x90)
64 /* Corrected Platform Error */
65 #define CPER_NOTIFY_CPE \
66 GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \
67 0xF2, 0x7E, 0xBE, 0xEE)
68 /* Machine Check Exception */
69 #define CPER_NOTIFY_MCE \
70 GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
71 0xE1, 0x49, 0x13, 0xBB)
72 /* PCI Express Error */
73 #define CPER_NOTIFY_PCIE \
74 GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \
75 0xAF, 0x67, 0xC1, 0x04)
76 /* INIT Record (for IPF) */
77 #define CPER_NOTIFY_INIT \
78 GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \
79 0xD3, 0x9B, 0xC9, 0x8E)
80 /* Non-Maskable Interrupt */
81 #define CPER_NOTIFY_NMI \
82 GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \
83 0x85, 0xD6, 0xE9, 0x8A)
84 /* BOOT Error Record */
85 #define CPER_NOTIFY_BOOT \
86 GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
87 0xD4, 0x64, 0xB3, 0x8F)
88 /* DMA Remapping Error */
89 #define CPER_NOTIFY_DMAR \
90 GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \
91 0x72, 0x2D, 0xEB, 0x41)
92 /* CXL Protocol Error Section */
93 #define CPER_SEC_CXL_PROT_ERR \
94 GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78, \
95 0x4B, 0x77, 0x10, 0x48)
96
97 /* CXL Event record UUIDs are formatted as GUIDs and reported in section type */
98 /*
99 * General Media Event Record
100 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
101 */
102 #define CPER_SEC_CXL_GEN_MEDIA_GUID \
103 GUID_INIT(0xfbcd0a77, 0xc260, 0x417f, \
104 0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6)
105 /*
106 * DRAM Event Record
107 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
108 */
109 #define CPER_SEC_CXL_DRAM_GUID \
110 GUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, \
111 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24)
112 /*
113 * Memory Module Event Record
114 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
115 */
116 #define CPER_SEC_CXL_MEM_MODULE_GUID \
117 GUID_INIT(0xfe927475, 0xdd59, 0x4339, \
118 0xa5, 0x86, 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74)
119
120 /*
121 * Flags bits definitions for flags in struct cper_record_header
122 * If set, the error has been recovered
123 */
124 #define CPER_HW_ERROR_FLAGS_RECOVERED 0x1
125 /* If set, the error is for previous boot */
126 #define CPER_HW_ERROR_FLAGS_PREVERR 0x2
127 /* If set, the error is injected for testing */
128 #define CPER_HW_ERROR_FLAGS_SIMULATED 0x4
129
130 /*
131 * CPER section header revision, used in revision field in struct
132 * cper_section_descriptor
133 */
134 #define CPER_SEC_REV 0x0100
135
136 /*
137 * Validation bits definition for validation_bits in struct
138 * cper_section_descriptor. If set, corresponding fields in struct
139 * cper_section_descriptor contain valid information.
140 */
141 #define CPER_SEC_VALID_FRU_ID 0x1
142 #define CPER_SEC_VALID_FRU_TEXT 0x2
143
144 /*
145 * Flags bits definitions for flags in struct cper_section_descriptor
146 *
147 * If set, the section is associated with the error condition
148 * directly, and should be focused on
149 */
150 #define CPER_SEC_PRIMARY 0x0001
151 /*
152 * If set, the error was not contained within the processor or memory
153 * hierarchy and the error may have propagated to persistent storage
154 * or network
155 */
156 #define CPER_SEC_CONTAINMENT_WARNING 0x0002
157 /* If set, the component must be re-initialized or re-enabled prior to use */
158 #define CPER_SEC_RESET 0x0004
159 /* If set, Linux may choose to discontinue use of the resource */
160 #define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008
161 /*
162 * If set, resource could not be queried for error information due to
163 * conflicts with other system software or resources. Some fields of
164 * the section will be invalid
165 */
166 #define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010
167 /*
168 * If set, action has been taken to ensure error containment (such as
169 * poisoning data), but the error has not been fully corrected and the
170 * data has not been consumed. Linux may choose to take further
171 * corrective action before the data is consumed
172 */
173 #define CPER_SEC_LATENT_ERROR 0x0020
174
175 /*
176 * Section type definitions, used in section_type field in struct
177 * cper_section_descriptor. These UUIDs are defined in the UEFI spec
178 * v2.7, sec N.2.2.
179 */
180
181 /* Processor Generic */
182 #define CPER_SEC_PROC_GENERIC \
183 GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
184 0x93, 0xC4, 0xF3, 0xDB)
185 /* Processor Specific: X86/X86_64 */
186 #define CPER_SEC_PROC_IA \
187 GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
188 0x24, 0x2B, 0x6E, 0x1D)
189 /* Processor Specific: IA64 */
190 #define CPER_SEC_PROC_IPF \
191 GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \
192 0x80, 0xC7, 0x3C, 0x88, 0x81)
193 /* Processor Specific: ARM */
194 #define CPER_SEC_PROC_ARM \
195 GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05, \
196 0x1D, 0x5D, 0x46, 0xB0)
197 /* Platform Memory */
198 #define CPER_SEC_PLATFORM_MEM \
199 GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
200 0xED, 0x7C, 0x83, 0xB1)
201 #define CPER_SEC_PCIE \
202 GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \
203 0xCB, 0x3C, 0x6F, 0x35)
204 /* Firmware Error Record Reference */
205 #define CPER_SEC_FW_ERR_REC_REF \
206 GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \
207 0x9C, 0x8E, 0x69, 0xED)
208 /* PCI/PCI-X Bus */
209 #define CPER_SEC_PCI_X_BUS \
210 GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \
211 0xD3, 0xF9, 0xC9, 0xDD)
212 /* PCI Component/Device */
213 #define CPER_SEC_PCI_DEV \
214 GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \
215 0x8B, 0x00, 0x13, 0x26)
216 #define CPER_SEC_DMAR_GENERIC \
217 GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \
218 0xDE, 0x3E, 0x2C, 0x64)
219 /* Intel VT for Directed I/O specific DMAr */
220 #define CPER_SEC_DMAR_VT \
221 GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \
222 0xDD, 0x93, 0xE8, 0xCF)
223 /* IOMMU specific DMAr */
224 #define CPER_SEC_DMAR_IOMMU \
225 GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \
226 0xDF, 0xAA, 0x84, 0xEC)
227
228 #define CPER_PROC_VALID_TYPE 0x0001
229 #define CPER_PROC_VALID_ISA 0x0002
230 #define CPER_PROC_VALID_ERROR_TYPE 0x0004
231 #define CPER_PROC_VALID_OPERATION 0x0008
232 #define CPER_PROC_VALID_FLAGS 0x0010
233 #define CPER_PROC_VALID_LEVEL 0x0020
234 #define CPER_PROC_VALID_VERSION 0x0040
235 #define CPER_PROC_VALID_BRAND_INFO 0x0080
236 #define CPER_PROC_VALID_ID 0x0100
237 #define CPER_PROC_VALID_TARGET_ADDRESS 0x0200
238 #define CPER_PROC_VALID_REQUESTOR_ID 0x0400
239 #define CPER_PROC_VALID_RESPONDER_ID 0x0800
240 #define CPER_PROC_VALID_IP 0x1000
241
242 #define CPER_MEM_VALID_ERROR_STATUS 0x0001
243 #define CPER_MEM_VALID_PA 0x0002
244 #define CPER_MEM_VALID_PA_MASK 0x0004
245 #define CPER_MEM_VALID_NODE 0x0008
246 #define CPER_MEM_VALID_CARD 0x0010
247 #define CPER_MEM_VALID_MODULE 0x0020
248 #define CPER_MEM_VALID_BANK 0x0040
249 #define CPER_MEM_VALID_DEVICE 0x0080
250 #define CPER_MEM_VALID_ROW 0x0100
251 #define CPER_MEM_VALID_COLUMN 0x0200
252 #define CPER_MEM_VALID_BIT_POSITION 0x0400
253 #define CPER_MEM_VALID_REQUESTOR_ID 0x0800
254 #define CPER_MEM_VALID_RESPONDER_ID 0x1000
255 #define CPER_MEM_VALID_TARGET_ID 0x2000
256 #define CPER_MEM_VALID_ERROR_TYPE 0x4000
257 #define CPER_MEM_VALID_RANK_NUMBER 0x8000
258 #define CPER_MEM_VALID_CARD_HANDLE 0x10000
259 #define CPER_MEM_VALID_MODULE_HANDLE 0x20000
260 #define CPER_MEM_VALID_ROW_EXT 0x40000
261 #define CPER_MEM_VALID_BANK_GROUP 0x80000
262 #define CPER_MEM_VALID_BANK_ADDRESS 0x100000
263 #define CPER_MEM_VALID_CHIP_ID 0x200000
264
265 #define CPER_MEM_EXT_ROW_MASK 0x3
266 #define CPER_MEM_EXT_ROW_SHIFT 16
267
268 #define CPER_MEM_BANK_ADDRESS_MASK 0xff
269 #define CPER_MEM_BANK_GROUP_SHIFT 8
270
271 #define CPER_MEM_CHIP_ID_SHIFT 5
272
273 #define CPER_PCIE_VALID_PORT_TYPE 0x0001
274 #define CPER_PCIE_VALID_VERSION 0x0002
275 #define CPER_PCIE_VALID_COMMAND_STATUS 0x0004
276 #define CPER_PCIE_VALID_DEVICE_ID 0x0008
277 #define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010
278 #define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020
279 #define CPER_PCIE_VALID_CAPABILITY 0x0040
280 #define CPER_PCIE_VALID_AER_INFO 0x0080
281
282 #define CPER_PCIE_SLOT_SHIFT 3
283
284 #define CPER_ARM_VALID_MPIDR BIT(0)
285 #define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1)
286 #define CPER_ARM_VALID_RUNNING_STATE BIT(2)
287 #define CPER_ARM_VALID_VENDOR_INFO BIT(3)
288
289 #define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0)
290 #define CPER_ARM_INFO_VALID_FLAGS BIT(1)
291 #define CPER_ARM_INFO_VALID_ERR_INFO BIT(2)
292 #define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3)
293 #define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4)
294
295 #define CPER_ARM_INFO_FLAGS_FIRST BIT(0)
296 #define CPER_ARM_INFO_FLAGS_LAST BIT(1)
297 #define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2)
298 #define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3)
299
300 #define CPER_ARM_CACHE_ERROR 0
301 #define CPER_ARM_TLB_ERROR 1
302 #define CPER_ARM_BUS_ERROR 2
303 #define CPER_ARM_VENDOR_ERROR 3
304 #define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR
305
306 #define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0)
307 #define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1)
308 #define CPER_ARM_ERR_VALID_LEVEL BIT(2)
309 #define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3)
310 #define CPER_ARM_ERR_VALID_CORRECTED BIT(4)
311 #define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5)
312 #define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6)
313 #define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7)
314 #define CPER_ARM_ERR_VALID_TIME_OUT BIT(8)
315 #define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9)
316 #define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10)
317 #define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11)
318
319 #define CPER_ARM_ERR_TRANSACTION_SHIFT 16
320 #define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)
321 #define CPER_ARM_ERR_OPERATION_SHIFT 18
322 #define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)
323 #define CPER_ARM_ERR_LEVEL_SHIFT 22
324 #define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)
325 #define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25
326 #define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)
327 #define CPER_ARM_ERR_CORRECTED_SHIFT 26
328 #define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)
329 #define CPER_ARM_ERR_PRECISE_PC_SHIFT 27
330 #define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)
331 #define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28
332 #define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)
333 #define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29
334 #define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)
335 #define CPER_ARM_ERR_TIME_OUT_SHIFT 31
336 #define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)
337 #define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32
338 #define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)
339 #define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34
340 #define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0)
341 #define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43
342 #define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)
343
344 /*
345 * All tables and structs must be byte-packed to match CPER
346 * specification, since the tables are provided by the system BIOS
347 */
348 #pragma pack(1)
349
350 /* Record Header, UEFI v2.7 sec N.2.1 */
351 struct cper_record_header {
352 char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */
353 u16 revision; /* must be CPER_RECORD_REV */
354 u32 signature_end; /* must be CPER_SIG_END */
355 u16 section_count;
356 u32 error_severity;
357 u32 validation_bits;
358 u32 record_length;
359 u64 timestamp;
360 guid_t platform_id;
361 guid_t partition_id;
362 guid_t creator_id;
363 guid_t notification_type;
364 u64 record_id;
365 u32 flags;
366 u64 persistence_information;
367 u8 reserved[12]; /* must be zero */
368 };
369
370 /* Section Descriptor, UEFI v2.7 sec N.2.2 */
371 struct cper_section_descriptor {
372 u32 section_offset; /* Offset in bytes of the
373 * section body from the base
374 * of the record header */
375 u32 section_length;
376 u16 revision; /* must be CPER_RECORD_REV */
377 u8 validation_bits;
378 u8 reserved; /* must be zero */
379 u32 flags;
380 guid_t section_type;
381 guid_t fru_id;
382 u32 section_severity;
383 u8 fru_text[20];
384 };
385
386 /* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
387 struct cper_sec_proc_generic {
388 u64 validation_bits;
389 u8 proc_type;
390 u8 proc_isa;
391 u8 proc_error_type;
392 u8 operation;
393 u8 flags;
394 u8 level;
395 u16 reserved;
396 u64 cpu_version;
397 char cpu_brand[128];
398 u64 proc_id;
399 u64 target_addr;
400 u64 requestor_id;
401 u64 responder_id;
402 u64 ip;
403 };
404
405 /* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
406 struct cper_sec_proc_ia {
407 u64 validation_bits;
408 u64 lapic_id;
409 u8 cpuid[48];
410 };
411
412 /* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
413 struct cper_ia_err_info {
414 guid_t err_type;
415 u64 validation_bits;
416 u64 check_info;
417 u64 target_id;
418 u64 requestor_id;
419 u64 responder_id;
420 u64 ip;
421 };
422
423 /* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
424 struct cper_ia_proc_ctx {
425 u16 reg_ctx_type;
426 u16 reg_arr_size;
427 u32 msr_addr;
428 u64 mm_reg_addr;
429 };
430
431 /* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
432 struct cper_sec_proc_arm {
433 u32 validation_bits;
434 u16 err_info_num; /* Number of Processor Error Info */
435 u16 context_info_num; /* Number of Processor Context Info Records*/
436 u32 section_length;
437 u8 affinity_level;
438 u8 reserved[3]; /* must be zero */
439 u64 mpidr;
440 u64 midr;
441 u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
442 u32 psci_state;
443 };
444
445 /* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
446 struct cper_arm_err_info {
447 u8 version;
448 u8 length;
449 u16 validation_bits;
450 u8 type;
451 u16 multiple_error;
452 u8 flags;
453 u64 error_info;
454 u64 virt_fault_addr;
455 u64 physical_fault_addr;
456 };
457
458 /* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
459 struct cper_arm_ctx_info {
460 u16 version;
461 u16 type;
462 u32 size;
463 };
464
465 /* Old Memory Error Section, UEFI v2.1, v2.2 */
466 struct cper_sec_mem_err_old {
467 u64 validation_bits;
468 u64 error_status;
469 u64 physical_addr;
470 u64 physical_addr_mask;
471 u16 node;
472 u16 card;
473 u16 module;
474 u16 bank;
475 u16 device;
476 u16 row;
477 u16 column;
478 u16 bit_pos;
479 u64 requestor_id;
480 u64 responder_id;
481 u64 target_id;
482 u8 error_type;
483 };
484
485 /* Memory Error Section (UEFI >= v2.3), UEFI v2.8 sec N.2.5 */
486 struct cper_sec_mem_err {
487 u64 validation_bits;
488 u64 error_status;
489 u64 physical_addr;
490 u64 physical_addr_mask;
491 u16 node;
492 u16 card;
493 u16 module;
494 u16 bank;
495 u16 device;
496 u16 row;
497 u16 column;
498 u16 bit_pos;
499 u64 requestor_id;
500 u64 responder_id;
501 u64 target_id;
502 u8 error_type;
503 u8 extended;
504 u16 rank;
505 u16 mem_array_handle; /* "card handle" in UEFI 2.4 */
506 u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */
507 };
508
509 struct cper_mem_err_compact {
510 u64 validation_bits;
511 u16 node;
512 u16 card;
513 u16 module;
514 u16 bank;
515 u16 device;
516 u16 row;
517 u16 column;
518 u16 bit_pos;
519 u64 requestor_id;
520 u64 responder_id;
521 u64 target_id;
522 u16 rank;
523 u16 mem_array_handle;
524 u16 mem_dev_handle;
525 u8 extended;
526 };
527
cper_get_mem_extension(u64 mem_valid,u8 mem_extended)528 static inline u32 cper_get_mem_extension(u64 mem_valid, u8 mem_extended)
529 {
530 if (!(mem_valid & CPER_MEM_VALID_ROW_EXT))
531 return 0;
532 return (mem_extended & CPER_MEM_EXT_ROW_MASK) << CPER_MEM_EXT_ROW_SHIFT;
533 }
534
535 /* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
536 struct cper_sec_pcie {
537 u64 validation_bits;
538 u32 port_type;
539 struct {
540 u8 minor;
541 u8 major;
542 u8 reserved[2];
543 } version;
544 u16 command;
545 u16 status;
546 u32 reserved;
547 struct {
548 u16 vendor_id;
549 u16 device_id;
550 u8 class_code[3];
551 u8 function;
552 u8 device;
553 u16 segment;
554 u8 bus;
555 u8 secondary_bus;
556 u16 slot;
557 u8 reserved;
558 } device_id;
559 struct {
560 u32 lower;
561 u32 upper;
562 } serial_number;
563 struct {
564 u16 secondary_status;
565 u16 control;
566 } bridge;
567 u8 capability[60];
568 u8 aer_info[96];
569 };
570
571 /* Firmware Error Record Reference, UEFI v2.7 sec N.2.10 */
572 struct cper_sec_fw_err_rec_ref {
573 u8 record_type;
574 u8 revision;
575 u8 reserved[6];
576 u64 record_identifier;
577 guid_t record_identifier_guid;
578 };
579
580 /* Reset to default packing */
581 #pragma pack()
582
583 extern const char *const cper_proc_error_type_strs[4];
584
585 u64 cper_next_record_id(void);
586 const char *cper_severity_str(unsigned int);
587 const char *cper_mem_err_type_str(unsigned int);
588 const char *cper_mem_err_status_str(u64 status);
589 void cper_print_bits(const char *prefix, unsigned int bits,
590 const char * const strs[], unsigned int strs_size);
591 void cper_mem_err_pack(const struct cper_sec_mem_err *,
592 struct cper_mem_err_compact *);
593 const char *cper_mem_err_unpack(struct trace_seq *,
594 struct cper_mem_err_compact *);
595 void cper_print_proc_arm(const char *pfx,
596 const struct cper_sec_proc_arm *proc);
597 void cper_print_proc_ia(const char *pfx,
598 const struct cper_sec_proc_ia *proc);
599 int cper_mem_err_location(struct cper_mem_err_compact *mem, char *msg);
600 int cper_dimm_err_location(struct cper_mem_err_compact *mem, char *msg);
601
602 struct acpi_hest_generic_status;
603 void cper_estatus_print(const char *pfx,
604 const struct acpi_hest_generic_status *estatus);
605 int cper_estatus_check_header(const struct acpi_hest_generic_status *estatus);
606 int cper_estatus_check(const struct acpi_hest_generic_status *estatus);
607
608 struct cxl_cper_sec_prot_err;
609 void cxl_cper_print_prot_err(const char *pfx,
610 const struct cxl_cper_sec_prot_err *prot_err);
611
612 #endif
613