1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * DMA support for Internal DMAC with SDHI SD/SDIO controller
4 *
5 * Copyright (C) 2016-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
8 */
9
10 #include <linux/bitops.h>
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/io-64-nonatomic-hi-lo.h>
14 #include <linux/mmc/host.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/pagemap.h>
18 #include <linux/platform_data/tmio.h>
19 #include <linux/platform_device.h>
20 #include <linux/scatterlist.h>
21 #include <linux/sys_soc.h>
22
23 #include "renesas_sdhi.h"
24 #include "tmio_mmc.h"
25
26 #define DM_CM_DTRAN_MODE 0x820
27 #define DM_CM_DTRAN_CTRL 0x828
28 #define DM_CM_RST 0x830
29 #define DM_CM_INFO1 0x840
30 #define DM_CM_INFO1_MASK 0x848
31 #define DM_CM_INFO2 0x850
32 #define DM_CM_INFO2_MASK 0x858
33 #define DM_DTRAN_ADDR 0x880
34
35 /* DM_CM_DTRAN_MODE */
36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */
38 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4))
39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */
40
41 /* DM_CM_DTRAN_CTRL */
42 #define DTRAN_CTRL_DM_START BIT(0)
43
44 /* DM_CM_RST */
45 #define RST_DTRANRST1 BIT(9)
46 #define RST_DTRANRST0 BIT(8)
47 #define RST_RESERVED_BITS GENMASK_ULL(31, 0)
48
49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
50 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0)
51 #define INFO1_DTRANEND1 BIT(20)
52 #define INFO1_DTRANEND1_OLD BIT(17)
53 #define INFO1_DTRANEND0 BIT(16)
54
55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
56 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0)
57 #define INFO2_DTRANERR1 BIT(17)
58 #define INFO2_DTRANERR0 BIT(16)
59
60 enum renesas_sdhi_dma_cookie {
61 COOKIE_UNMAPPED,
62 COOKIE_PRE_MAPPED,
63 COOKIE_MAPPED,
64 };
65
66 /*
67 * Specification of this driver:
68 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
69 * - Since this SDHI DMAC register set has 16 but 32-bit width, we
70 * need a custom accessor.
71 */
72
73 static unsigned long global_flags;
74 /*
75 * Workaround for avoiding to use RX DMAC by multiple channels. On R-Car M3-W
76 * ES1.0, when multiple SDHI channels use RX DMAC simultaneously, sometimes
77 * hundreds of data bytes are not stored into the system memory even if the
78 * DMAC interrupt happened. So, this driver then uses one RX DMAC channel only.
79 */
80 #define SDHI_INTERNAL_DMAC_RX_IN_USE 0
81
82 /* Definitions for sampling clocks */
83 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
84 {
85 .clk_rate = 0,
86 .tap = 0x00000300,
87 .tap_hs400_4tap = 0x00000100,
88 },
89 };
90
91 static const struct renesas_sdhi_of_data of_data_rza2 = {
92 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
93 TMIO_MMC_HAVE_CBSY,
94 .tmio_ocr_mask = MMC_VDD_32_33,
95 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
96 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
97 .bus_shift = 2,
98 .scc_offset = 0 - 0x1000,
99 .taps = rcar_gen3_scc_taps,
100 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
101 /* DMAC can handle 32bit blk count but only 1 segment */
102 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
103 .max_segs = 1,
104 };
105
106 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = {
107 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
108 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
109 TMIO_MMC_64BIT_DATA_PORT,
110 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
111 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
112 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
113 .bus_shift = 2,
114 .scc_offset = 0x1000,
115 .taps = rcar_gen3_scc_taps,
116 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
117 /* DMAC can handle 32bit blk count but only 1 segment */
118 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
119 .max_segs = 1,
120 .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK,
121 };
122
123 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = {
124 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
125 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
126 TMIO_MMC_64BIT_DATA_PORT,
127 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
128 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
129 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
130 .bus_shift = 2,
131 .scc_offset = 0x1000,
132 .taps = rcar_gen3_scc_taps,
133 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
134 /* DMAC can handle 32bit blk count but only 1 segment */
135 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
136 .max_segs = 1,
137 };
138
139 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
140 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
141 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
142 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
143 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
144 };
145
146 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
147 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
148 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
149 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
150 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
151 };
152
153 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
154 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
156 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
157 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
158 };
159
160 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
161 .hs400_disabled = true,
162 .hs400_4taps = true,
163 };
164
165 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = {
166 .hs400_disabled = true,
167 .hs400_4taps = true,
168 .dma_one_rx_only = true,
169 .old_info1_layout = true,
170 };
171
172 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
173 .hs400_4taps = true,
174 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
175 .manual_tap_correction = true,
176 };
177
178 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
179 .hs400_disabled = true,
180 };
181
182 static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = {
183 .fixed_addr_mode = true,
184 };
185
186 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
187 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
188 .manual_tap_correction = true,
189 };
190
191 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
192 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
193 .manual_tap_correction = true,
194 };
195
196 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
197 .hs400_4taps = true,
198 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
199 .hs400_calib_table = r8a7796_es13_calib_table,
200 .manual_tap_correction = true,
201 };
202
203 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
204 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
205 .hs400_calib_table = r8a77965_calib_table,
206 .manual_tap_correction = true,
207 };
208
209 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
210 .hs400_calib_table = r8a77990_calib_table,
211 .manual_tap_correction = true,
212 };
213
214 static const struct renesas_sdhi_quirks sdhi_quirks_rzg2l = {
215 .fixed_addr_mode = true,
216 .hs400_disabled = true,
217 };
218
219 /*
220 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
221 * So, we want to treat them equally and only have a match for ES1.2 to enforce
222 * this if there ever will be a way to distinguish ES1.2.
223 */
224 static const struct soc_device_attribute sdhi_quirks_match[] = {
225 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
226 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
227 { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_one_rx },
228 { .soc_id = "r8a7796", .revision = "ES1.[12]", .data = &sdhi_quirks_4tap_nohs400 },
229 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
230 { .soc_id = "r8a77980", .revision = "ES1.*", .data = &sdhi_quirks_nohs400 },
231 { /* Sentinel. */ }
232 };
233
234 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = {
235 .of_data = &of_data_rcar_gen3,
236 .quirks = &sdhi_quirks_bad_taps2367,
237 };
238
239 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = {
240 .of_data = &of_data_rcar_gen3,
241 .quirks = &sdhi_quirks_bad_taps1357,
242 };
243
244 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = {
245 .of_data = &of_data_rcar_gen3,
246 .quirks = &sdhi_quirks_r8a77965,
247 };
248
249 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = {
250 .of_data = &of_data_rcar_gen3_no_sdh_fallback,
251 .quirks = &sdhi_quirks_nohs400,
252 };
253
254 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = {
255 .of_data = &of_data_rcar_gen3,
256 .quirks = &sdhi_quirks_r8a77990,
257 };
258
259 static const struct renesas_sdhi_of_data_with_quirks of_rzg2l_compatible = {
260 .of_data = &of_data_rcar_gen3,
261 .quirks = &sdhi_quirks_rzg2l,
262 };
263
264 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = {
265 .of_data = &of_data_rcar_gen3,
266 };
267
268 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = {
269 .of_data = &of_data_rcar_gen3,
270 .quirks = &sdhi_quirks_nohs400,
271 };
272
273 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = {
274 .of_data = &of_data_rza2,
275 .quirks = &sdhi_quirks_fixed_addr,
276 };
277
278 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
279 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
280 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
281 { .compatible = "renesas,sdhi-r8a774b1", .data = &of_r8a77965_compatible, },
282 { .compatible = "renesas,sdhi-r8a774c0", .data = &of_r8a77990_compatible, },
283 { .compatible = "renesas,sdhi-r8a774e1", .data = &of_r8a7795_compatible, },
284 { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, },
285 { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, },
286 { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, },
287 { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, },
288 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, },
289 { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, },
290 { .compatible = "renesas,sdhi-r8a779md", .data = &of_rcar_gen3_nohs400_compatible, },
291 { .compatible = "renesas,sdhi-r9a09g011", .data = &of_rzg2l_compatible, },
292 { .compatible = "renesas,sdhi-r9a09g057", .data = &of_rzg2l_compatible, },
293 { .compatible = "renesas,rzg2l-sdhi", .data = &of_rzg2l_compatible, },
294 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
295 { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, },
296 {},
297 };
298 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
299
300 static void
renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host * host,bool enable)301 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
302 {
303 struct renesas_sdhi *priv = host_to_priv(host);
304 u32 dma_irqs = INFO1_DTRANEND0 |
305 (sdhi_has_quirk(priv, old_info1_layout) ?
306 INFO1_DTRANEND1_OLD : INFO1_DTRANEND1);
307
308 if (!host->chan_tx || !host->chan_rx)
309 return;
310
311 writel(enable ? ~dma_irqs : INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK);
312
313 if (priv->dma_priv.enable)
314 priv->dma_priv.enable(host, enable);
315 }
316
317 static void
renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host * host)318 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host)
319 {
320 u64 val = RST_DTRANRST1 | RST_DTRANRST0;
321
322 renesas_sdhi_internal_dmac_enable_dma(host, false);
323
324 writel(RST_RESERVED_BITS & ~val, host->ctl + DM_CM_RST);
325 writel(RST_RESERVED_BITS | val, host->ctl + DM_CM_RST);
326
327 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
328
329 renesas_sdhi_internal_dmac_enable_dma(host, true);
330 }
331
renesas_sdhi_internal_dmac_dma_irq(struct tmio_mmc_host * host)332 static bool renesas_sdhi_internal_dmac_dma_irq(struct tmio_mmc_host *host)
333 {
334 struct renesas_sdhi *priv = host_to_priv(host);
335 struct renesas_sdhi_dma *dma_priv = &priv->dma_priv;
336
337 u32 dma_irqs = INFO1_DTRANEND0 |
338 (sdhi_has_quirk(priv, old_info1_layout) ?
339 INFO1_DTRANEND1_OLD : INFO1_DTRANEND1);
340 u32 status = readl(host->ctl + DM_CM_INFO1);
341
342 if (status & dma_irqs) {
343 writel(status ^ dma_irqs, host->ctl + DM_CM_INFO1);
344 set_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags);
345 if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags))
346 queue_work(system_bh_wq, &dma_priv->dma_complete);
347 }
348
349 return status & dma_irqs;
350 }
351
352 static void
renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host * host)353 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host)
354 {
355 struct renesas_sdhi *priv = host_to_priv(host);
356 struct renesas_sdhi_dma *dma_priv = &priv->dma_priv;
357
358 set_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags);
359 if (test_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags) ||
360 host->data->error)
361 queue_work(system_bh_wq, &dma_priv->dma_complete);
362 }
363
364 /*
365 * renesas_sdhi_internal_dmac_map() will be called with two different
366 * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single
367 * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg
368 * pointer in a mmc_data instead of host->sg_ptr.
369 */
370 static void
renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host * host,struct mmc_data * data,enum renesas_sdhi_dma_cookie cookie)371 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host,
372 struct mmc_data *data,
373 enum renesas_sdhi_dma_cookie cookie)
374 {
375 bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) :
376 (data->host_cookie == cookie);
377
378 if (unmap) {
379 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
380 mmc_get_dma_dir(data));
381 data->host_cookie = COOKIE_UNMAPPED;
382 }
383 }
384
385 static bool
renesas_sdhi_internal_dmac_map(struct tmio_mmc_host * host,struct mmc_data * data,enum renesas_sdhi_dma_cookie cookie)386 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host,
387 struct mmc_data *data,
388 enum renesas_sdhi_dma_cookie cookie)
389 {
390 if (data->host_cookie == COOKIE_PRE_MAPPED)
391 return true;
392
393 if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
394 mmc_get_dma_dir(data)))
395 return false;
396
397 data->host_cookie = cookie;
398
399 /* This DMAC needs buffers to be 128-byte aligned */
400 if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) {
401 renesas_sdhi_internal_dmac_unmap(host, data, cookie);
402 return false;
403 }
404
405 return true;
406 }
407
408 static void
renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host * host,struct mmc_data * data)409 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
410 struct mmc_data *data)
411 {
412 struct renesas_sdhi *priv = host_to_priv(host);
413 struct scatterlist *sg = host->sg_ptr;
414 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
415
416 if (!sdhi_has_quirk(priv, fixed_addr_mode))
417 dtran_mode |= DTRAN_MODE_ADDR_MODE;
418
419 if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED))
420 goto force_pio;
421
422 if (data->flags & MMC_DATA_READ) {
423 dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
424 if (sdhi_has_quirk(priv, dma_one_rx_only) &&
425 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
426 goto force_pio_with_unmap;
427 } else {
428 dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
429 }
430
431 priv->dma_priv.end_flags = 0;
432 renesas_sdhi_internal_dmac_enable_dma(host, true);
433
434 /* set dma parameters */
435 writel(dtran_mode, host->ctl + DM_CM_DTRAN_MODE);
436 writel(sg_dma_address(sg), host->ctl + DM_DTRAN_ADDR);
437
438 host->dma_on = true;
439
440 return;
441
442 force_pio_with_unmap:
443 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
444
445 force_pio:
446 renesas_sdhi_internal_dmac_enable_dma(host, false);
447 }
448
renesas_sdhi_internal_dmac_issue_work_fn(struct work_struct * work)449 static void renesas_sdhi_internal_dmac_issue_work_fn(struct work_struct *work)
450 {
451 struct tmio_mmc_host *host = from_work(host, work, dma_issue);
452 struct renesas_sdhi *priv = host_to_priv(host);
453
454 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
455
456 if (!host->cmd->error) {
457 /* start the DMAC */
458 writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL);
459 } else {
460 /* on CMD errors, simulate DMA end immediately */
461 set_bit(SDHI_DMA_END_FLAG_DMA, &priv->dma_priv.end_flags);
462 if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &priv->dma_priv.end_flags))
463 queue_work(system_bh_wq, &priv->dma_priv.dma_complete);
464 }
465 }
466
renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host * host)467 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host)
468 {
469 enum dma_data_direction dir;
470
471 if (!host->dma_on)
472 return false;
473
474 if (!host->data)
475 return false;
476
477 if (host->data->flags & MMC_DATA_READ)
478 dir = DMA_FROM_DEVICE;
479 else
480 dir = DMA_TO_DEVICE;
481
482 renesas_sdhi_internal_dmac_enable_dma(host, false);
483 renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED);
484
485 if (dir == DMA_FROM_DEVICE)
486 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
487
488 host->dma_on = false;
489
490 return true;
491 }
492
renesas_sdhi_internal_dmac_complete_work_fn(struct work_struct * work)493 static void renesas_sdhi_internal_dmac_complete_work_fn(struct work_struct *work)
494 {
495 struct renesas_sdhi_dma *dma_priv = from_work(dma_priv, work, dma_complete);
496 struct renesas_sdhi *priv = container_of(dma_priv, typeof(*priv), dma_priv);
497 struct tmio_mmc_host *host = priv->host;
498
499 spin_lock_irq(&host->lock);
500 if (!renesas_sdhi_internal_dmac_complete(host))
501 goto out;
502
503 tmio_mmc_do_data_irq(host);
504 out:
505 spin_unlock_irq(&host->lock);
506 }
507
renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host * host)508 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host)
509 {
510 if (host->data)
511 renesas_sdhi_internal_dmac_complete(host);
512 }
513
renesas_sdhi_internal_dmac_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)514 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc,
515 struct mmc_request *mrq,
516 int err)
517 {
518 struct tmio_mmc_host *host = mmc_priv(mmc);
519 struct mmc_data *data = mrq->data;
520
521 if (!data)
522 return;
523
524 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
525 }
526
renesas_sdhi_internal_dmac_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)527 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc,
528 struct mmc_request *mrq)
529 {
530 struct tmio_mmc_host *host = mmc_priv(mmc);
531 struct mmc_data *data = mrq->data;
532
533 if (!data)
534 return;
535
536 data->host_cookie = COOKIE_UNMAPPED;
537 renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED);
538 }
539
540 static void
renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host * host,struct tmio_mmc_data * pdata)541 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
542 struct tmio_mmc_data *pdata)
543 {
544 struct renesas_sdhi *priv = host_to_priv(host);
545
546 /* Disable DMAC interrupts initially */
547 writel(INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK);
548 writel(INFO2_MASK_CLEAR, host->ctl + DM_CM_INFO2_MASK);
549 writel(0, host->ctl + DM_CM_INFO1);
550 writel(0, host->ctl + DM_CM_INFO2);
551
552 /* Each value is set to non-zero to assume "enabling" each DMA */
553 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
554
555 INIT_WORK(&priv->dma_priv.dma_complete,
556 renesas_sdhi_internal_dmac_complete_work_fn);
557 INIT_WORK(&host->dma_issue,
558 renesas_sdhi_internal_dmac_issue_work_fn);
559
560 /* Add pre_req and post_req */
561 host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req;
562 host->ops.post_req = renesas_sdhi_internal_dmac_post_req;
563 }
564
565 static void
renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host * host)566 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
567 {
568 /* Each value is set to zero to assume "disabling" each DMA */
569 host->chan_rx = host->chan_tx = NULL;
570 }
571
572 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
573 .start = renesas_sdhi_internal_dmac_start_dma,
574 .enable = renesas_sdhi_internal_dmac_enable_dma,
575 .request = renesas_sdhi_internal_dmac_request_dma,
576 .release = renesas_sdhi_internal_dmac_release_dma,
577 .abort = renesas_sdhi_internal_dmac_abort_dma,
578 .dataend = renesas_sdhi_internal_dmac_dataend_dma,
579 .end = renesas_sdhi_internal_dmac_end_dma,
580 .dma_irq = renesas_sdhi_internal_dmac_dma_irq,
581 };
582
renesas_sdhi_internal_dmac_probe(struct platform_device * pdev)583 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
584 {
585 const struct soc_device_attribute *attr;
586 const struct renesas_sdhi_of_data_with_quirks *of_data_quirks;
587 const struct renesas_sdhi_quirks *quirks;
588 struct device *dev = &pdev->dev;
589
590 of_data_quirks = of_device_get_match_data(&pdev->dev);
591 quirks = of_data_quirks->quirks;
592
593 attr = soc_device_match(sdhi_quirks_match);
594 if (attr)
595 quirks = attr->data;
596
597 /* value is max of SD_SECCNT. Confirmed by HW engineers */
598 dma_set_max_seg_size(dev, 0xffffffff);
599
600 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops,
601 of_data_quirks->of_data, quirks);
602 }
603
604 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
605 SYSTEM_SLEEP_PM_OPS(renesas_sdhi_suspend, renesas_sdhi_resume)
606 RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
607 tmio_mmc_host_runtime_resume,
608 NULL)
609 };
610
611 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
612 .driver = {
613 .name = "renesas_sdhi_internal_dmac",
614 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
615 .pm = pm_ptr(&renesas_sdhi_internal_dmac_dev_pm_ops),
616 .of_match_table = renesas_sdhi_internal_dmac_of_match,
617 },
618 .probe = renesas_sdhi_internal_dmac_probe,
619 .remove = renesas_sdhi_remove,
620 };
621
622 module_platform_driver(renesas_internal_dmac_sdhi_driver);
623
624 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
625 MODULE_AUTHOR("Yoshihiro Shimoda");
626 MODULE_LICENSE("GPL v2");
627