1# SPDX-License-Identifier: GPL-2.0 2# common clock support for SOPHGO SoC family. 3 4config CLK_SOPHGO_CV1800 5 tristate "Support for the Sophgo CV1800 series SoCs clock controller" 6 depends on ARCH_SOPHGO || COMPILE_TEST 7 help 8 This driver supports clock controller of Sophgo CV18XX series SoC. 9 The driver require a 25MHz Oscillator to function generate clock. 10 It includes PLLs, common clock function and some vendor clock for 11 IPs of CV18XX series SoC 12 13config CLK_SOPHGO_SG2042_PLL 14 tristate "Sophgo SG2042 PLL clock support" 15 depends on ARCH_SOPHGO || COMPILE_TEST 16 help 17 This driver supports the PLL clock controller on the 18 Sophgo SG2042 SoC. This clock IP uses three oscillators with 19 frequency of 25 MHz as input, which are used for Main/Fixed 20 PLL, DDR PLL 0 and DDR PLL 1 respectively. 21 22config CLK_SOPHGO_SG2042_CLKGEN 23 tristate "Sophgo SG2042 Clock Generator support" 24 depends on CLK_SOPHGO_SG2042_PLL 25 help 26 This driver supports the Clock Generator on the 27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock 28 because it uses PLL clocks as input. 29 This driver provides clock function such as DIV/Mux/Gate. 30 31config CLK_SOPHGO_SG2042_RPGATE 32 tristate "Sophgo SG2042 RP subsystem clock controller support" 33 depends on CLK_SOPHGO_SG2042_CLKGEN 34 help 35 This driver supports the RP((Riscv Processors)) subsystem clock 36 controller on the Sophgo SG2042 SoC. 37 This clock IP depends on SG2042 Clock Generator because it uses 38 clock from Clock Generator IP as input. 39 This driver provides Gate function for RP. 40